1 // SPDX-License-Identifier: GPL-2.0-only
3 * Local APIC handling, local APIC timers
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
15 * Mikael Pettersson : PM converted to driver model.
18 #include <linux/perf_event.h>
19 #include <linux/kernel_stat.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/acpi_pmtmr.h>
22 #include <linux/clockchips.h>
23 #include <linux/interrupt.h>
24 #include <linux/memblock.h>
25 #include <linux/ftrace.h>
26 #include <linux/ioport.h>
27 #include <linux/export.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/delay.h>
30 #include <linux/timex.h>
31 #include <linux/i8253.h>
32 #include <linux/dmar.h>
33 #include <linux/init.h>
34 #include <linux/cpu.h>
35 #include <linux/dmi.h>
36 #include <linux/smp.h>
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
47 #include <asm/traps.h>
49 #include <asm/io_apic.h>
57 #include <asm/hypervisor.h>
58 #include <asm/cpu_device_id.h>
59 #include <asm/intel-family.h>
60 #include <asm/irq_regs.h>
62 unsigned int num_processors;
64 unsigned disabled_cpus;
66 /* Processor that is doing the boot up */
67 unsigned int boot_cpu_physical_apicid __ro_after_init = -1U;
68 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
70 u8 boot_cpu_apic_version __ro_after_init;
73 * The highest APIC ID seen during enumeration.
75 static unsigned int max_physical_apicid;
78 * Bitmask of physically existing CPUs:
80 physid_mask_t phys_cpu_present_map;
83 * Processor to be disabled specified by kernel parameter
84 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
85 * avoid undefined behaviour caused by sending INIT from AP to BSP.
87 static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID;
90 * This variable controls which CPUs receive external NMIs. By default,
91 * external NMIs are delivered only to the BSP.
93 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP;
96 * Map cpu index to physical APIC ID
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
108 * On x86_32, the mapping between cpu and logical apicid may vary
109 * depending on apic in use. The following early percpu variable is
110 * used for the mapping. This is where the behaviors of x86_64 and 32
111 * actually diverge. Let's keep it ugly for now.
113 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase __ro_after_init;
119 * Handle interrupt mode configuration register (IMCR).
120 * This register controls whether the interrupt signals
121 * that reach the BSP come from the master PIC or from the
122 * local APIC. Before entering Symmetric I/O Mode, either
123 * the BIOS or the operating system must switch out of
124 * PIC Mode by changing the IMCR.
126 static inline void imcr_pic_to_apic(void)
128 /* select IMCR register */
130 /* NMI and 8259 INTR go through APIC */
134 static inline void imcr_apic_to_pic(void)
136 /* select IMCR register */
138 /* NMI and 8259 INTR go directly to BSP */
144 * Knob to control our willingness to enable the local APIC.
148 static int force_enable_local_apic __initdata;
151 * APIC command line parameters
153 static int __init parse_lapic(char *arg)
155 if (IS_ENABLED(CONFIG_X86_32) && !arg)
156 force_enable_local_apic = 1;
157 else if (arg && !strncmp(arg, "notscdeadline", 13))
158 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
161 early_param("lapic", parse_lapic);
164 static int apic_calibrate_pmtmr __initdata;
165 static __init int setup_apicpmtimer(char *s)
167 apic_calibrate_pmtmr = 1;
171 __setup("apicpmtimer", setup_apicpmtimer);
174 unsigned long mp_lapic_addr __ro_after_init;
175 int disable_apic __ro_after_init;
176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
177 static int disable_apic_timer __initdata;
178 /* Local APIC timer works in C2 */
179 int local_apic_timer_c2_ok __ro_after_init;
180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
183 * Debug level, exported for io_apic.c
185 int apic_verbosity __ro_after_init;
187 int pic_mode __ro_after_init;
189 /* Have we found an MP table */
190 int smp_found_config __ro_after_init;
192 static struct resource lapic_resource = {
193 .name = "Local APIC",
194 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
197 unsigned int lapic_timer_period = 0;
199 static void apic_pm_activate(void);
201 static unsigned long apic_phys __ro_after_init;
204 * Get the LAPIC version
206 static inline int lapic_get_version(void)
208 return GET_APIC_VERSION(apic_read(APIC_LVR));
212 * Check, if the APIC is integrated or a separate chip
214 static inline int lapic_is_integrated(void)
216 return APIC_INTEGRATED(lapic_get_version());
220 * Check, whether this is a modern or a first generation APIC
222 static int modern_apic(void)
224 /* AMD systems use old APIC versions, so check the CPU */
225 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
226 boot_cpu_data.x86 >= 0xf)
229 /* Hygon systems use modern APIC */
230 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
233 return lapic_get_version() >= 0x14;
237 * right after this call apic become NOOP driven
238 * so apic->write/read doesn't do anything
240 static void __init apic_disable(void)
242 pr_info("APIC: switched to apic NOOP\n");
246 void native_apic_wait_icr_idle(void)
248 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
252 u32 native_safe_apic_wait_icr_idle(void)
259 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
262 inc_irq_stat(icr_read_retry_count);
264 } while (timeout++ < 1000);
269 void native_apic_icr_write(u32 low, u32 id)
273 local_irq_save(flags);
274 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
275 apic_write(APIC_ICR, low);
276 local_irq_restore(flags);
279 u64 native_apic_icr_read(void)
283 icr2 = apic_read(APIC_ICR2);
284 icr1 = apic_read(APIC_ICR);
286 return icr1 | ((u64)icr2 << 32);
291 * get_physical_broadcast - Get number of physical broadcast IDs
293 int get_physical_broadcast(void)
295 return modern_apic() ? 0xff : 0xf;
300 * lapic_get_maxlvt - get the maximum number of local vector table entries
302 int lapic_get_maxlvt(void)
305 * - we always have APIC integrated on 64bit mode
306 * - 82489DXs do not report # of LVT entries
308 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
316 #define APIC_DIVISOR 16
317 #define TSC_DIVISOR 8
320 * This function sets up the local APIC timer, with a timeout of
321 * 'clocks' APIC bus clock. During calibration we actually call
322 * this function twice on the boot CPU, once with a bogus timeout
323 * value, second time for real. The other (noncalibrating) CPUs
324 * call this function only once, with the real, calibrated value.
326 * We do reads before writes even if unnecessary, to get around the
327 * P5 APIC double write bug.
329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
331 unsigned int lvtt_value, tmp_value;
333 lvtt_value = LOCAL_TIMER_VECTOR;
335 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
339 if (!lapic_is_integrated())
340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
343 lvtt_value |= APIC_LVT_MASKED;
345 apic_write(APIC_LVTT, lvtt_value);
347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
351 * According to Intel, MFENCE can do the serialization here.
353 asm volatile("mfence" : : : "memory");
360 tmp_value = apic_read(APIC_TDCR);
361 apic_write(APIC_TDCR,
362 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
366 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
370 * Setup extended LVT, AMD specific
372 * Software should use the LVT offsets the BIOS provides. The offsets
373 * are determined by the subsystems using it like those for MCE
374 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
375 * are supported. Beginning with family 10h at least 4 offsets are
378 * Since the offsets must be consistent for all cores, we keep track
379 * of the LVT offsets in software and reserve the offset for the same
380 * vector also to be used on other cores. An offset is freed by
381 * setting the entry to APIC_EILVT_MASKED.
383 * If the BIOS is right, there should be no conflicts. Otherwise a
384 * "[Firmware Bug]: ..." error message is generated. However, if
385 * software does not properly determines the offsets, it is not
386 * necessarily a BIOS bug.
389 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
391 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
393 return (old & APIC_EILVT_MASKED)
394 || (new == APIC_EILVT_MASKED)
395 || ((new & ~APIC_EILVT_MASKED) == old);
398 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
400 unsigned int rsvd, vector;
402 if (offset >= APIC_EILVT_NR_MAX)
405 rsvd = atomic_read(&eilvt_offsets[offset]);
407 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
408 if (vector && !eilvt_entry_is_changeable(vector, new))
409 /* may not change if vectors are different */
411 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
412 } while (rsvd != new);
414 rsvd &= ~APIC_EILVT_MASKED;
415 if (rsvd && rsvd != vector)
416 pr_info("LVT offset %d assigned for vector 0x%02x\n",
423 * If mask=1, the LVT entry does not generate interrupts while mask=0
424 * enables the vector. See also the BKDGs. Must be called with
425 * preemption disabled.
428 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
430 unsigned long reg = APIC_EILVTn(offset);
431 unsigned int new, old, reserved;
433 new = (mask << 16) | (msg_type << 8) | vector;
434 old = apic_read(reg);
435 reserved = reserve_eilvt_offset(offset, new);
437 if (reserved != new) {
438 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
439 "vector 0x%x, but the register is already in use for "
440 "vector 0x%x on another cpu\n",
441 smp_processor_id(), reg, offset, new, reserved);
445 if (!eilvt_entry_is_changeable(old, new)) {
446 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
447 "vector 0x%x, but the register is already in use for "
448 "vector 0x%x on this cpu\n",
449 smp_processor_id(), reg, offset, new, old);
453 apic_write(reg, new);
457 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
460 * Program the next event, relative to now
462 static int lapic_next_event(unsigned long delta,
463 struct clock_event_device *evt)
465 apic_write(APIC_TMICT, delta);
469 static int lapic_next_deadline(unsigned long delta,
470 struct clock_event_device *evt)
475 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
479 static int lapic_timer_shutdown(struct clock_event_device *evt)
483 /* Lapic used as dummy for broadcast ? */
484 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
487 v = apic_read(APIC_LVTT);
488 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
489 apic_write(APIC_LVTT, v);
490 apic_write(APIC_TMICT, 0);
495 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
497 /* Lapic used as dummy for broadcast ? */
498 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
501 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
505 static int lapic_timer_set_periodic(struct clock_event_device *evt)
507 return lapic_timer_set_periodic_oneshot(evt, false);
510 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
512 return lapic_timer_set_periodic_oneshot(evt, true);
516 * Local APIC timer broadcast function
518 static void lapic_timer_broadcast(const struct cpumask *mask)
521 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
527 * The local apic timer can be used for any function which is CPU local.
529 static struct clock_event_device lapic_clockevent = {
531 .features = CLOCK_EVT_FEAT_PERIODIC |
532 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
533 | CLOCK_EVT_FEAT_DUMMY,
535 .set_state_shutdown = lapic_timer_shutdown,
536 .set_state_periodic = lapic_timer_set_periodic,
537 .set_state_oneshot = lapic_timer_set_oneshot,
538 .set_state_oneshot_stopped = lapic_timer_shutdown,
539 .set_next_event = lapic_next_event,
540 .broadcast = lapic_timer_broadcast,
544 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
546 static const struct x86_cpu_id deadline_match[] __initconst = {
547 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */
548 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */
550 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020),
552 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011),
553 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e),
554 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c),
555 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003),
557 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136),
558 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014),
559 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0),
561 X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22),
562 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20),
563 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17),
565 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25),
566 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17),
568 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2),
569 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2),
571 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52),
572 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52),
577 static __init bool apic_validate_deadline_timer(void)
579 const struct x86_cpu_id *m;
582 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
584 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
587 m = x86_match_cpu(deadline_match);
591 rev = (u32)m->driver_data;
593 if (boot_cpu_data.microcode >= rev)
596 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
597 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
598 "please update microcode to version: 0x%x (or later)\n", rev);
603 * Setup the local APIC timer for this CPU. Copy the initialized values
604 * of the boot CPU and register the clock event in the framework.
606 static void setup_APIC_timer(void)
608 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
610 if (this_cpu_has(X86_FEATURE_ARAT)) {
611 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
612 /* Make LAPIC timer preferrable over percpu HPET */
613 lapic_clockevent.rating = 150;
616 memcpy(levt, &lapic_clockevent, sizeof(*levt));
617 levt->cpumask = cpumask_of(smp_processor_id());
619 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
620 levt->name = "lapic-deadline";
621 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
622 CLOCK_EVT_FEAT_DUMMY);
623 levt->set_next_event = lapic_next_deadline;
624 clockevents_config_and_register(levt,
625 tsc_khz * (1000 / TSC_DIVISOR),
628 clockevents_register_device(levt);
632 * Install the updated TSC frequency from recalibration at the TSC
633 * deadline clockevent devices.
635 static void __lapic_update_tsc_freq(void *info)
637 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
639 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
642 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
645 void lapic_update_tsc_freq(void)
648 * The clockevent device's ->mult and ->shift can both be
649 * changed. In order to avoid races, schedule the frequency
650 * update code on each CPU.
652 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
656 * In this functions we calibrate APIC bus clocks to the external timer.
658 * We want to do the calibration only once since we want to have local timer
659 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
662 * This was previously done by reading the PIT/HPET and waiting for a wrap
663 * around to find out, that a tick has elapsed. I have a box, where the PIT
664 * readout is broken, so it never gets out of the wait loop again. This was
665 * also reported by others.
667 * Monitoring the jiffies value is inaccurate and the clockevents
668 * infrastructure allows us to do a simple substitution of the interrupt
671 * The calibration routine also uses the pm_timer when possible, as the PIT
672 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
673 * back to normal later in the boot process).
676 #define LAPIC_CAL_LOOPS (HZ/10)
678 static __initdata int lapic_cal_loops = -1;
679 static __initdata long lapic_cal_t1, lapic_cal_t2;
680 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
681 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
682 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
685 * Temporary interrupt handler and polled calibration function.
687 static void __init lapic_cal_handler(struct clock_event_device *dev)
689 unsigned long long tsc = 0;
690 long tapic = apic_read(APIC_TMCCT);
691 unsigned long pm = acpi_pm_read_early();
693 if (boot_cpu_has(X86_FEATURE_TSC))
696 switch (lapic_cal_loops++) {
698 lapic_cal_t1 = tapic;
699 lapic_cal_tsc1 = tsc;
701 lapic_cal_j1 = jiffies;
704 case LAPIC_CAL_LOOPS:
705 lapic_cal_t2 = tapic;
706 lapic_cal_tsc2 = tsc;
707 if (pm < lapic_cal_pm1)
708 pm += ACPI_PM_OVRRUN;
710 lapic_cal_j2 = jiffies;
716 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
718 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
719 const long pm_thresh = pm_100ms / 100;
723 #ifndef CONFIG_X86_PM_TIMER
727 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
729 /* Check, if the PM timer is available */
733 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
735 if (deltapm > (pm_100ms - pm_thresh) &&
736 deltapm < (pm_100ms + pm_thresh)) {
737 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
741 res = (((u64)deltapm) * mult) >> 22;
742 do_div(res, 1000000);
743 pr_warn("APIC calibration not consistent "
744 "with PM-Timer: %ldms instead of 100ms\n", (long)res);
746 /* Correct the lapic counter value */
747 res = (((u64)(*delta)) * pm_100ms);
748 do_div(res, deltapm);
749 pr_info("APIC delta adjusted to PM-Timer: "
750 "%lu (%ld)\n", (unsigned long)res, *delta);
753 /* Correct the tsc counter value */
754 if (boot_cpu_has(X86_FEATURE_TSC)) {
755 res = (((u64)(*deltatsc)) * pm_100ms);
756 do_div(res, deltapm);
757 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
758 "PM-Timer: %lu (%ld)\n",
759 (unsigned long)res, *deltatsc);
760 *deltatsc = (long)res;
766 static int __init lapic_init_clockevent(void)
768 if (!lapic_timer_period)
771 /* Calculate the scaled math multiplication factor */
772 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
773 TICK_NSEC, lapic_clockevent.shift);
774 lapic_clockevent.max_delta_ns =
775 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
776 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
777 lapic_clockevent.min_delta_ns =
778 clockevent_delta2ns(0xF, &lapic_clockevent);
779 lapic_clockevent.min_delta_ticks = 0xF;
784 bool __init apic_needs_pit(void)
787 * If the frequencies are not known, PIT is required for both TSC
788 * and apic timer calibration.
790 if (!tsc_khz || !cpu_khz)
793 /* Is there an APIC at all or is it disabled? */
794 if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic)
798 * If interrupt delivery mode is legacy PIC or virtual wire without
799 * configuration, the local APIC timer wont be set up. Make sure
800 * that the PIT is initialized.
802 if (apic_intr_mode == APIC_PIC ||
803 apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG)
806 /* Virt guests may lack ARAT, but still have DEADLINE */
807 if (!boot_cpu_has(X86_FEATURE_ARAT))
810 /* Deadline timer is based on TSC so no further PIT action required */
811 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
814 /* APIC timer disabled? */
815 if (disable_apic_timer)
818 * The APIC timer frequency is known already, no PIT calibration
819 * required. If unknown, let the PIT be initialized.
821 return lapic_timer_period == 0;
824 static int __init calibrate_APIC_clock(void)
826 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
827 u64 tsc_perj = 0, tsc_start = 0;
828 unsigned long jif_start;
829 unsigned long deltaj;
830 long delta, deltatsc;
831 int pm_referenced = 0;
833 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
837 * Check if lapic timer has already been calibrated by platform
838 * specific routine, such as tsc calibration code. If so just fill
839 * in the clockevent structure and return.
841 if (!lapic_init_clockevent()) {
842 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
845 * Direct calibration methods must have an always running
846 * local APIC timer, no need for broadcast timer.
848 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
852 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
853 "calibrating APIC timer ...\n");
856 * There are platforms w/o global clockevent devices. Instead of
857 * making the calibration conditional on that, use a polling based
858 * approach everywhere.
863 * Setup the APIC counter to maximum. There is no way the lapic
864 * can underflow in the 100ms detection time frame
866 __setup_APIC_LVTT(0xffffffff, 0, 0);
869 * Methods to terminate the calibration loop:
870 * 1) Global clockevent if available (jiffies)
871 * 2) TSC if available and frequency is known
873 jif_start = READ_ONCE(jiffies);
877 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
881 * Enable interrupts so the tick can fire, if a global
882 * clockevent device is available
886 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
887 /* Wait for a tick to elapse */
890 u64 tsc_now = rdtsc();
891 if ((tsc_now - tsc_start) >= tsc_perj) {
892 tsc_start += tsc_perj;
896 unsigned long jif_now = READ_ONCE(jiffies);
898 if (time_after(jif_now, jif_start)) {
906 /* Invoke the calibration routine */
908 lapic_cal_handler(NULL);
914 /* Build delta t1-t2 as apic timer counts down */
915 delta = lapic_cal_t1 - lapic_cal_t2;
916 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
918 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
920 /* we trust the PM based calibration if possible */
921 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
924 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
925 lapic_init_clockevent();
927 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
928 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
929 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
932 if (boot_cpu_has(X86_FEATURE_TSC)) {
933 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
935 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
936 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
939 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
941 lapic_timer_period / (1000000 / HZ),
942 lapic_timer_period % (1000000 / HZ));
945 * Do a sanity check on the APIC calibration result
947 if (lapic_timer_period < (1000000 / HZ)) {
949 pr_warn("APIC frequency too slow, disabling apic timer\n");
953 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
956 * PM timer calibration failed or not turned on so lets try APIC
957 * timer based calibration, if a global clockevent device is
960 if (!pm_referenced && global_clock_event) {
961 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
964 * Setup the apic timer manually
966 levt->event_handler = lapic_cal_handler;
967 lapic_timer_set_periodic(levt);
968 lapic_cal_loops = -1;
970 /* Let the interrupts run */
973 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
976 /* Stop the lapic timer */
978 lapic_timer_shutdown(levt);
981 deltaj = lapic_cal_j2 - lapic_cal_j1;
982 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
984 /* Check, if the jiffies result is consistent */
985 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
986 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
988 levt->features |= CLOCK_EVT_FEAT_DUMMY;
992 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
993 pr_warn("APIC timer disabled due to verification failure\n");
1001 * Setup the boot APIC
1003 * Calibrate and verify the result.
1005 void __init setup_boot_APIC_clock(void)
1008 * The local apic timer can be disabled via the kernel
1009 * commandline or from the CPU detection code. Register the lapic
1010 * timer as a dummy clock event source on SMP systems, so the
1011 * broadcast mechanism is used. On UP systems simply ignore it.
1013 if (disable_apic_timer) {
1014 pr_info("Disabling APIC timer\n");
1015 /* No broadcast on UP ! */
1016 if (num_possible_cpus() > 1) {
1017 lapic_clockevent.mult = 1;
1023 if (calibrate_APIC_clock()) {
1024 /* No broadcast on UP ! */
1025 if (num_possible_cpus() > 1)
1031 * If nmi_watchdog is set to IO_APIC, we need the
1032 * PIT/HPET going. Otherwise register lapic as a dummy
1035 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1037 /* Setup the lapic or request the broadcast */
1039 amd_e400_c1e_apic_setup();
1042 void setup_secondary_APIC_clock(void)
1045 amd_e400_c1e_apic_setup();
1049 * The guts of the apic timer interrupt
1051 static void local_apic_timer_interrupt(void)
1053 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1056 * Normally we should not be here till LAPIC has been initialized but
1057 * in some cases like kdump, its possible that there is a pending LAPIC
1058 * timer interrupt from previous kernel's context and is delivered in
1059 * new kernel the moment interrupts are enabled.
1061 * Interrupts are enabled early and LAPIC is setup much later, hence
1062 * its possible that when we get here evt->event_handler is NULL.
1063 * Check for event_handler being NULL and discard the interrupt as
1066 if (!evt->event_handler) {
1067 pr_warn("Spurious LAPIC timer interrupt on cpu %d\n",
1068 smp_processor_id());
1070 lapic_timer_shutdown(evt);
1075 * the NMI deadlock-detector uses this.
1077 inc_irq_stat(apic_timer_irqs);
1079 evt->event_handler(evt);
1083 * Local APIC timer interrupt. This is the most natural way for doing
1084 * local interrupts, but local timer interrupts can be emulated by
1085 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1087 * [ if a single-CPU system runs an SMP kernel then we call the local
1088 * interrupt as well. Thus we cannot inline the local irq ... ]
1090 DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt)
1092 struct pt_regs *old_regs = set_irq_regs(regs);
1095 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1096 local_apic_timer_interrupt();
1097 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1099 set_irq_regs(old_regs);
1102 int setup_profiling_timer(unsigned int multiplier)
1108 * Local APIC start and shutdown
1112 * clear_local_APIC - shutdown the local APIC
1114 * This is called, when a CPU is disabled and before rebooting, so the state of
1115 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1116 * leftovers during boot.
1118 void clear_local_APIC(void)
1123 /* APIC hasn't been mapped yet */
1124 if (!x2apic_mode && !apic_phys)
1127 maxlvt = lapic_get_maxlvt();
1129 * Masking an LVT entry can trigger a local APIC error
1130 * if the vector is zero. Mask LVTERR first to prevent this.
1133 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1134 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1137 * Careful: we have to set masks only first to deassert
1138 * any level-triggered sources.
1140 v = apic_read(APIC_LVTT);
1141 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1142 v = apic_read(APIC_LVT0);
1143 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1144 v = apic_read(APIC_LVT1);
1145 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1147 v = apic_read(APIC_LVTPC);
1148 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1151 /* lets not touch this if we didn't frob it */
1152 #ifdef CONFIG_X86_THERMAL_VECTOR
1154 v = apic_read(APIC_LVTTHMR);
1155 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1158 #ifdef CONFIG_X86_MCE_INTEL
1160 v = apic_read(APIC_LVTCMCI);
1161 if (!(v & APIC_LVT_MASKED))
1162 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1167 * Clean APIC state for other OSs:
1169 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1170 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1171 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1173 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1175 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1177 /* Integrated APIC (!82489DX) ? */
1178 if (lapic_is_integrated()) {
1180 /* Clear ESR due to Pentium errata 3AP and 11AP */
1181 apic_write(APIC_ESR, 0);
1182 apic_read(APIC_ESR);
1187 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1189 * Contrary to disable_local_APIC() this does not touch the enable bit in
1190 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1191 * bus would require a hardware reset as the APIC would lose track of bus
1192 * arbitration. On systems with FSB delivery APICBASE could be disabled,
1193 * but it has to be guaranteed that no interrupt is sent to the APIC while
1194 * in that state and it's not clear from the SDM whether it still responds
1195 * to INIT/SIPI messages. Stay on the safe side and use software disable.
1197 void apic_soft_disable(void)
1203 /* Soft disable APIC (implies clearing of registers for 82489DX!). */
1204 value = apic_read(APIC_SPIV);
1205 value &= ~APIC_SPIV_APIC_ENABLED;
1206 apic_write(APIC_SPIV, value);
1210 * disable_local_APIC - clear and disable the local APIC
1212 void disable_local_APIC(void)
1214 /* APIC hasn't been mapped yet */
1215 if (!x2apic_mode && !apic_phys)
1218 apic_soft_disable();
1220 #ifdef CONFIG_X86_32
1222 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1223 * restore the disabled state.
1225 if (enabled_via_apicbase) {
1228 rdmsr(MSR_IA32_APICBASE, l, h);
1229 l &= ~MSR_IA32_APICBASE_ENABLE;
1230 wrmsr(MSR_IA32_APICBASE, l, h);
1236 * If Linux enabled the LAPIC against the BIOS default disable it down before
1237 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1238 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1239 * for the case where Linux didn't enable the LAPIC.
1241 void lapic_shutdown(void)
1243 unsigned long flags;
1245 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1248 local_irq_save(flags);
1250 #ifdef CONFIG_X86_32
1251 if (!enabled_via_apicbase)
1255 disable_local_APIC();
1258 local_irq_restore(flags);
1262 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1264 void __init sync_Arb_IDs(void)
1267 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1270 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1276 apic_wait_icr_idle();
1278 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1279 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1280 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1283 enum apic_intr_mode_id apic_intr_mode __ro_after_init;
1285 static int __init __apic_intr_mode_select(void)
1287 /* Check kernel option */
1289 pr_info("APIC disabled via kernel command line\n");
1294 #ifdef CONFIG_X86_64
1295 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1296 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1298 pr_info("APIC disabled by BIOS\n");
1302 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1304 /* Neither 82489DX nor integrated APIC ? */
1305 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1310 /* If the BIOS pretends there is an integrated APIC ? */
1311 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1312 APIC_INTEGRATED(boot_cpu_apic_version)) {
1314 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1315 boot_cpu_physical_apicid);
1320 /* Check MP table or ACPI MADT configuration */
1321 if (!smp_found_config) {
1322 disable_ioapic_support();
1324 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1325 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1327 return APIC_VIRTUAL_WIRE;
1331 /* If SMP should be disabled, then really disable it! */
1332 if (!setup_max_cpus) {
1333 pr_info("APIC: SMP mode deactivated\n");
1334 return APIC_SYMMETRIC_IO_NO_ROUTING;
1337 if (read_apic_id() != boot_cpu_physical_apicid) {
1338 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1339 read_apic_id(), boot_cpu_physical_apicid);
1340 /* Or can we switch back to PIC here? */
1344 return APIC_SYMMETRIC_IO;
1347 /* Select the interrupt delivery mode for the BSP */
1348 void __init apic_intr_mode_select(void)
1350 apic_intr_mode = __apic_intr_mode_select();
1354 * An initial setup of the virtual wire mode.
1356 void __init init_bsp_APIC(void)
1361 * Don't do the setup now if we have a SMP BIOS as the
1362 * through-I/O-APIC virtual wire mode might be active.
1364 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1368 * Do not trust the local APIC being empty at bootup.
1375 value = apic_read(APIC_SPIV);
1376 value &= ~APIC_VECTOR_MASK;
1377 value |= APIC_SPIV_APIC_ENABLED;
1379 #ifdef CONFIG_X86_32
1380 /* This bit is reserved on P4/Xeon and should be cleared */
1381 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1382 (boot_cpu_data.x86 == 15))
1383 value &= ~APIC_SPIV_FOCUS_DISABLED;
1386 value |= APIC_SPIV_FOCUS_DISABLED;
1387 value |= SPURIOUS_APIC_VECTOR;
1388 apic_write(APIC_SPIV, value);
1391 * Set up the virtual wire mode.
1393 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1394 value = APIC_DM_NMI;
1395 if (!lapic_is_integrated()) /* 82489DX */
1396 value |= APIC_LVT_LEVEL_TRIGGER;
1397 if (apic_extnmi == APIC_EXTNMI_NONE)
1398 value |= APIC_LVT_MASKED;
1399 apic_write(APIC_LVT1, value);
1402 static void __init apic_bsp_setup(bool upmode);
1404 /* Init the interrupt delivery mode for the BSP */
1405 void __init apic_intr_mode_init(void)
1407 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1409 switch (apic_intr_mode) {
1411 pr_info("APIC: Keep in PIC mode(8259)\n");
1413 case APIC_VIRTUAL_WIRE:
1414 pr_info("APIC: Switch to virtual wire mode setup\n");
1415 default_setup_apic_routing();
1417 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1418 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1420 default_setup_apic_routing();
1422 case APIC_SYMMETRIC_IO:
1423 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1424 default_setup_apic_routing();
1426 case APIC_SYMMETRIC_IO_NO_ROUTING:
1427 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1431 apic_bsp_setup(upmode);
1434 static void lapic_setup_esr(void)
1436 unsigned int oldvalue, value, maxlvt;
1438 if (!lapic_is_integrated()) {
1439 pr_info("No ESR for 82489DX.\n");
1443 if (apic->disable_esr) {
1445 * Something untraceable is creating bad interrupts on
1446 * secondary quads ... for the moment, just leave the
1447 * ESR disabled - we can't do anything useful with the
1448 * errors anyway - mbligh
1450 pr_info("Leaving ESR disabled.\n");
1454 maxlvt = lapic_get_maxlvt();
1455 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1456 apic_write(APIC_ESR, 0);
1457 oldvalue = apic_read(APIC_ESR);
1459 /* enables sending errors */
1460 value = ERROR_APIC_VECTOR;
1461 apic_write(APIC_LVTERR, value);
1464 * spec says clear errors after enabling vector.
1467 apic_write(APIC_ESR, 0);
1468 value = apic_read(APIC_ESR);
1469 if (value != oldvalue)
1470 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1471 "vector: 0x%08x after: 0x%08x\n",
1475 #define APIC_IR_REGS APIC_ISR_NR
1476 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1477 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1480 unsigned long map[APIC_IR_MAPSIZE];
1481 u32 regs[APIC_IR_REGS];
1484 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1489 for (i = 0; i < APIC_IR_REGS; i++)
1490 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1493 for (i = 0; i < APIC_IR_REGS; i++)
1494 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1497 * If the ISR map is not empty. ACK the APIC and run another round
1498 * to verify whether a pending IRR has been unblocked and turned
1501 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1503 * There can be multiple ISR bits set when a high priority
1504 * interrupt preempted a lower priority one. Issue an ACK
1507 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1512 return !bitmap_empty(irr->map, APIC_IR_BITS);
1516 * After a crash, we no longer service the interrupts and a pending
1517 * interrupt from previous kernel might still have ISR bit set.
1519 * Most probably by now the CPU has serviced that pending interrupt and it
1520 * might not have done the ack_APIC_irq() because it thought, interrupt
1521 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1522 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1523 * a vector might get locked. It was noticed for timer irq (vector
1524 * 0x31). Issue an extra EOI to clear ISR.
1526 * If there are pending IRR bits they turn into ISR bits after a higher
1527 * priority ISR bit has been acked.
1529 static void apic_pending_intr_clear(void)
1531 union apic_ir irr, isr;
1534 /* 512 loops are way oversized and give the APIC a chance to obey. */
1535 for (i = 0; i < 512; i++) {
1536 if (!apic_check_and_ack(&irr, &isr))
1539 /* Dump the IRR/ISR content if that failed */
1540 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1544 * setup_local_APIC - setup the local APIC
1546 * Used to setup local APIC while initializing BSP or bringing up APs.
1547 * Always called with preemption disabled.
1549 static void setup_local_APIC(void)
1551 int cpu = smp_processor_id();
1555 disable_ioapic_support();
1560 * If this comes from kexec/kcrash the APIC might be enabled in
1561 * SPIV. Soft disable it before doing further initialization.
1563 value = apic_read(APIC_SPIV);
1564 value &= ~APIC_SPIV_APIC_ENABLED;
1565 apic_write(APIC_SPIV, value);
1567 #ifdef CONFIG_X86_32
1568 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1569 if (lapic_is_integrated() && apic->disable_esr) {
1570 apic_write(APIC_ESR, 0);
1571 apic_write(APIC_ESR, 0);
1572 apic_write(APIC_ESR, 0);
1573 apic_write(APIC_ESR, 0);
1577 * Double-check whether this APIC is really registered.
1578 * This is meaningless in clustered apic mode, so we skip it.
1580 BUG_ON(!apic->apic_id_registered());
1583 * Intel recommends to set DFR, LDR and TPR before enabling
1584 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1585 * document number 292116). So here it goes...
1587 apic->init_apic_ldr();
1589 #ifdef CONFIG_X86_32
1590 if (apic->dest_logical) {
1591 int logical_apicid, ldr_apicid;
1594 * APIC LDR is initialized. If logical_apicid mapping was
1595 * initialized during get_smp_config(), make sure it matches
1598 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1599 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1600 if (logical_apicid != BAD_APICID)
1601 WARN_ON(logical_apicid != ldr_apicid);
1602 /* Always use the value from LDR. */
1603 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1608 * Set Task Priority to 'accept all except vectors 0-31'. An APIC
1609 * vector in the 16-31 range could be delivered if TPR == 0, but we
1610 * would think it's an exception and terrible things will happen. We
1611 * never change this later on.
1613 value = apic_read(APIC_TASKPRI);
1614 value &= ~APIC_TPRI_MASK;
1616 apic_write(APIC_TASKPRI, value);
1618 /* Clear eventually stale ISR/IRR bits */
1619 apic_pending_intr_clear();
1622 * Now that we are all set up, enable the APIC
1624 value = apic_read(APIC_SPIV);
1625 value &= ~APIC_VECTOR_MASK;
1629 value |= APIC_SPIV_APIC_ENABLED;
1631 #ifdef CONFIG_X86_32
1633 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1634 * certain networking cards. If high frequency interrupts are
1635 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1636 * entry is masked/unmasked at a high rate as well then sooner or
1637 * later IOAPIC line gets 'stuck', no more interrupts are received
1638 * from the device. If focus CPU is disabled then the hang goes
1641 * [ This bug can be reproduced easily with a level-triggered
1642 * PCI Ne2000 networking cards and PII/PIII processors, dual
1646 * Actually disabling the focus CPU check just makes the hang less
1647 * frequent as it makes the interrupt distributon model be more
1648 * like LRU than MRU (the short-term load is more even across CPUs).
1652 * - enable focus processor (bit==0)
1653 * - 64bit mode always use processor focus
1654 * so no need to set it
1656 value &= ~APIC_SPIV_FOCUS_DISABLED;
1660 * Set spurious IRQ vector
1662 value |= SPURIOUS_APIC_VECTOR;
1663 apic_write(APIC_SPIV, value);
1665 perf_events_lapic_init();
1668 * Set up LVT0, LVT1:
1670 * set up through-local-APIC on the boot CPU's LINT0. This is not
1671 * strictly necessary in pure symmetric-IO mode, but sometimes
1672 * we delegate interrupts to the 8259A.
1675 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1677 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1678 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1679 value = APIC_DM_EXTINT;
1680 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1682 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1683 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1685 apic_write(APIC_LVT0, value);
1688 * Only the BSP sees the LINT1 NMI signal by default. This can be
1689 * modified by apic_extnmi= boot option.
1691 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1692 apic_extnmi == APIC_EXTNMI_ALL)
1693 value = APIC_DM_NMI;
1695 value = APIC_DM_NMI | APIC_LVT_MASKED;
1698 if (!lapic_is_integrated())
1699 value |= APIC_LVT_LEVEL_TRIGGER;
1700 apic_write(APIC_LVT1, value);
1702 #ifdef CONFIG_X86_MCE_INTEL
1703 /* Recheck CMCI information after local APIC is up on CPU #0 */
1709 static void end_local_APIC_setup(void)
1713 #ifdef CONFIG_X86_32
1716 /* Disable the local apic timer */
1717 value = apic_read(APIC_LVTT);
1718 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1719 apic_write(APIC_LVTT, value);
1727 * APIC setup function for application processors. Called from smpboot.c
1729 void apic_ap_setup(void)
1732 end_local_APIC_setup();
1735 #ifdef CONFIG_X86_X2APIC
1743 static int x2apic_state;
1745 static void __x2apic_disable(void)
1749 if (!boot_cpu_has(X86_FEATURE_APIC))
1752 rdmsrl(MSR_IA32_APICBASE, msr);
1753 if (!(msr & X2APIC_ENABLE))
1755 /* Disable xapic and x2apic first and then reenable xapic mode */
1756 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1757 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1758 printk_once(KERN_INFO "x2apic disabled\n");
1761 static void __x2apic_enable(void)
1765 rdmsrl(MSR_IA32_APICBASE, msr);
1766 if (msr & X2APIC_ENABLE)
1768 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1769 printk_once(KERN_INFO "x2apic enabled\n");
1772 static int __init setup_nox2apic(char *str)
1774 if (x2apic_enabled()) {
1775 int apicid = native_apic_msr_read(APIC_ID);
1777 if (apicid >= 255) {
1778 pr_warn("Apicid: %08x, cannot enforce nox2apic\n",
1782 pr_warn("x2apic already enabled.\n");
1785 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1786 x2apic_state = X2APIC_DISABLED;
1790 early_param("nox2apic", setup_nox2apic);
1792 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1793 void x2apic_setup(void)
1796 * If x2apic is not in ON state, disable it if already enabled
1799 if (x2apic_state != X2APIC_ON) {
1806 static __init void x2apic_disable(void)
1808 u32 x2apic_id, state = x2apic_state;
1811 x2apic_state = X2APIC_DISABLED;
1813 if (state != X2APIC_ON)
1816 x2apic_id = read_apic_id();
1817 if (x2apic_id >= 255)
1818 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1821 register_lapic_address(mp_lapic_addr);
1824 static __init void x2apic_enable(void)
1826 if (x2apic_state != X2APIC_OFF)
1830 x2apic_state = X2APIC_ON;
1834 static __init void try_to_enable_x2apic(int remap_mode)
1836 if (x2apic_state == X2APIC_DISABLED)
1839 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1840 /* IR is required if there is APIC ID > 255 even when running
1843 if (max_physical_apicid > 255 ||
1844 !x86_init.hyper.x2apic_available()) {
1845 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1851 * without IR all CPUs can be addressed by IOAPIC/MSI
1852 * only in physical mode
1859 void __init check_x2apic(void)
1861 if (x2apic_enabled()) {
1862 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1864 x2apic_state = X2APIC_ON;
1865 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1866 x2apic_state = X2APIC_DISABLED;
1869 #else /* CONFIG_X86_X2APIC */
1870 static int __init validate_x2apic(void)
1872 if (!apic_is_x2apic_enabled())
1875 * Checkme: Can we simply turn off x2apic here instead of panic?
1877 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1879 early_initcall(validate_x2apic);
1881 static inline void try_to_enable_x2apic(int remap_mode) { }
1882 static inline void __x2apic_enable(void) { }
1883 #endif /* !CONFIG_X86_X2APIC */
1885 void __init enable_IR_x2apic(void)
1887 unsigned long flags;
1890 if (skip_ioapic_setup) {
1891 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1895 ir_stat = irq_remapping_prepare();
1896 if (ir_stat < 0 && !x2apic_supported())
1899 ret = save_ioapic_entries();
1901 pr_info("Saving IO-APIC state failed: %d\n", ret);
1905 local_irq_save(flags);
1906 legacy_pic->mask_all();
1907 mask_ioapic_entries();
1909 /* If irq_remapping_prepare() succeeded, try to enable it */
1911 ir_stat = irq_remapping_enable();
1912 /* ir_stat contains the remap mode or an error code */
1913 try_to_enable_x2apic(ir_stat);
1916 restore_ioapic_entries();
1917 legacy_pic->restore_mask();
1918 local_irq_restore(flags);
1921 #ifdef CONFIG_X86_64
1923 * Detect and enable local APICs on non-SMP boards.
1924 * Original code written by Keir Fraser.
1925 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1926 * not correctly set up (usually the APIC timer won't work etc.)
1928 static int __init detect_init_APIC(void)
1930 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1931 pr_info("No local APIC present\n");
1935 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1940 static int __init apic_verify(void)
1945 * The APIC feature bit should now be enabled
1948 features = cpuid_edx(1);
1949 if (!(features & (1 << X86_FEATURE_APIC))) {
1950 pr_warn("Could not enable APIC!\n");
1953 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1954 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1956 /* The BIOS may have set up the APIC at some other address */
1957 if (boot_cpu_data.x86 >= 6) {
1958 rdmsr(MSR_IA32_APICBASE, l, h);
1959 if (l & MSR_IA32_APICBASE_ENABLE)
1960 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1963 pr_info("Found and enabled local APIC!\n");
1967 int __init apic_force_enable(unsigned long addr)
1975 * Some BIOSes disable the local APIC in the APIC_BASE
1976 * MSR. This can only be done in software for Intel P6 or later
1977 * and AMD K7 (Model > 1) or later.
1979 if (boot_cpu_data.x86 >= 6) {
1980 rdmsr(MSR_IA32_APICBASE, l, h);
1981 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1982 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1983 l &= ~MSR_IA32_APICBASE_BASE;
1984 l |= MSR_IA32_APICBASE_ENABLE | addr;
1985 wrmsr(MSR_IA32_APICBASE, l, h);
1986 enabled_via_apicbase = 1;
1989 return apic_verify();
1993 * Detect and initialize APIC
1995 static int __init detect_init_APIC(void)
1997 /* Disabled by kernel option? */
2001 switch (boot_cpu_data.x86_vendor) {
2002 case X86_VENDOR_AMD:
2003 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
2004 (boot_cpu_data.x86 >= 15))
2007 case X86_VENDOR_HYGON:
2009 case X86_VENDOR_INTEL:
2010 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2011 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2018 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2020 * Over-ride BIOS and try to enable the local APIC only if
2021 * "lapic" specified.
2023 if (!force_enable_local_apic) {
2024 pr_info("Local APIC disabled by BIOS -- "
2025 "you can enable it with \"lapic\"\n");
2028 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2040 pr_info("No local APIC present or hardware disabled\n");
2046 * init_apic_mappings - initialize APIC mappings
2048 void __init init_apic_mappings(void)
2050 unsigned int new_apicid;
2052 if (apic_validate_deadline_timer())
2053 pr_info("TSC deadline timer available\n");
2056 boot_cpu_physical_apicid = read_apic_id();
2060 /* If no local APIC can be found return early */
2061 if (!smp_found_config && detect_init_APIC()) {
2062 /* lets NOP'ify apic operations */
2063 pr_info("APIC: disable apic facility\n");
2066 apic_phys = mp_lapic_addr;
2069 * If the system has ACPI MADT tables or MP info, the LAPIC
2070 * address is already registered.
2072 if (!acpi_lapic && !smp_found_config)
2073 register_lapic_address(apic_phys);
2077 * Fetch the APIC ID of the BSP in case we have a
2078 * default configuration (or the MP table is broken).
2080 new_apicid = read_apic_id();
2081 if (boot_cpu_physical_apicid != new_apicid) {
2082 boot_cpu_physical_apicid = new_apicid;
2084 * yeah -- we lie about apic_version
2085 * in case if apic was disabled via boot option
2086 * but it's not a problem for SMP compiled kernel
2087 * since apic_intr_mode_select is prepared for such
2088 * a case and disable smp mode
2090 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2094 void __init register_lapic_address(unsigned long address)
2096 mp_lapic_addr = address;
2099 set_fixmap_nocache(FIX_APIC_BASE, address);
2100 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2101 APIC_BASE, address);
2103 if (boot_cpu_physical_apicid == -1U) {
2104 boot_cpu_physical_apicid = read_apic_id();
2105 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2110 * Local APIC interrupts
2114 * spurious_interrupt - Catch all for interrupts raised on unused vectors
2115 * @regs: Pointer to pt_regs on stack
2116 * @vector: The vector number
2118 * This is invoked from ASM entry code to catch all interrupts which
2119 * trigger on an entry which is routed to the common_spurious idtentry
2122 * Also called from sysvec_spurious_apic_interrupt().
2124 DEFINE_IDTENTRY_IRQ(spurious_interrupt)
2128 trace_spurious_apic_entry(vector);
2130 inc_irq_stat(irq_spurious_count);
2133 * If this is a spurious interrupt then do not acknowledge
2135 if (vector == SPURIOUS_APIC_VECTOR) {
2137 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2138 smp_processor_id());
2143 * If it is a vectored one, verify it's set in the ISR. If set,
2146 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2147 if (v & (1 << (vector & 0x1f))) {
2148 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2149 vector, smp_processor_id());
2152 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2153 vector, smp_processor_id());
2156 trace_spurious_apic_exit(vector);
2159 DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt)
2161 __spurious_interrupt(regs, SPURIOUS_APIC_VECTOR);
2165 * This interrupt should never happen with our APIC/SMP architecture
2167 DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt)
2169 static const char * const error_interrupt_reason[] = {
2170 "Send CS error", /* APIC Error Bit 0 */
2171 "Receive CS error", /* APIC Error Bit 1 */
2172 "Send accept error", /* APIC Error Bit 2 */
2173 "Receive accept error", /* APIC Error Bit 3 */
2174 "Redirectable IPI", /* APIC Error Bit 4 */
2175 "Send illegal vector", /* APIC Error Bit 5 */
2176 "Received illegal vector", /* APIC Error Bit 6 */
2177 "Illegal register address", /* APIC Error Bit 7 */
2181 trace_error_apic_entry(ERROR_APIC_VECTOR);
2183 /* First tickle the hardware, only then report what went on. -- REW */
2184 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2185 apic_write(APIC_ESR, 0);
2186 v = apic_read(APIC_ESR);
2188 atomic_inc(&irq_err_count);
2190 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2191 smp_processor_id(), v);
2196 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2201 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2203 trace_error_apic_exit(ERROR_APIC_VECTOR);
2207 * connect_bsp_APIC - attach the APIC to the interrupt system
2209 static void __init connect_bsp_APIC(void)
2211 #ifdef CONFIG_X86_32
2214 * Do not trust the local APIC being empty at bootup.
2218 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2219 * local APIC to INT and NMI lines.
2221 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2222 "enabling APIC mode.\n");
2229 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2230 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2232 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2235 void disconnect_bsp_APIC(int virt_wire_setup)
2239 #ifdef CONFIG_X86_32
2242 * Put the board back into PIC mode (has an effect only on
2243 * certain older boards). Note that APIC interrupts, including
2244 * IPIs, won't work beyond this point! The only exception are
2247 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2248 "entering PIC mode.\n");
2254 /* Go back to Virtual Wire compatibility mode */
2256 /* For the spurious interrupt use vector F, and enable it */
2257 value = apic_read(APIC_SPIV);
2258 value &= ~APIC_VECTOR_MASK;
2259 value |= APIC_SPIV_APIC_ENABLED;
2261 apic_write(APIC_SPIV, value);
2263 if (!virt_wire_setup) {
2265 * For LVT0 make it edge triggered, active high,
2266 * external and enabled
2268 value = apic_read(APIC_LVT0);
2269 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2270 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2271 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2272 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2273 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2274 apic_write(APIC_LVT0, value);
2277 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2281 * For LVT1 make it edge triggered, active high,
2284 value = apic_read(APIC_LVT1);
2285 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2286 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2287 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2288 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2289 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2290 apic_write(APIC_LVT1, value);
2294 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2295 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2296 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2297 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2299 * NOTE: Reserve 0 for BSP.
2301 static int nr_logical_cpuids = 1;
2304 * Used to store mapping between logical CPU IDs and APIC IDs.
2306 static int cpuid_to_apicid[] = {
2307 [0 ... NR_CPUS - 1] = -1,
2312 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2313 * @apicid: APIC ID to check
2315 bool apic_id_is_primary_thread(unsigned int apicid)
2319 if (smp_num_siblings == 1)
2321 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2322 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2323 return !(apicid & mask);
2328 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2329 * and cpuid_to_apicid[] synchronized.
2331 static int allocate_logical_cpuid(int apicid)
2336 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2337 * check if the kernel has allocated a cpuid for it.
2339 for (i = 0; i < nr_logical_cpuids; i++) {
2340 if (cpuid_to_apicid[i] == apicid)
2344 /* Allocate a new cpuid. */
2345 if (nr_logical_cpuids >= nr_cpu_ids) {
2346 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2347 "Processor %d/0x%x and the rest are ignored.\n",
2348 nr_cpu_ids, nr_logical_cpuids, apicid);
2352 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2353 return nr_logical_cpuids++;
2356 int generic_processor_info(int apicid, int version)
2358 int cpu, max = nr_cpu_ids;
2359 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2360 phys_cpu_present_map);
2363 * boot_cpu_physical_apicid is designed to have the apicid
2364 * returned by read_apic_id(), i.e, the apicid of the
2365 * currently booting-up processor. However, on some platforms,
2366 * it is temporarily modified by the apicid reported as BSP
2367 * through MP table. Concretely:
2369 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2370 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2372 * This function is executed with the modified
2373 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2374 * parameter doesn't work to disable APs on kdump 2nd kernel.
2376 * Since fixing handling of boot_cpu_physical_apicid requires
2377 * another discussion and tests on each platform, we leave it
2378 * for now and here we use read_apic_id() directly in this
2379 * function, generic_processor_info().
2381 if (disabled_cpu_apicid != BAD_APICID &&
2382 disabled_cpu_apicid != read_apic_id() &&
2383 disabled_cpu_apicid == apicid) {
2384 int thiscpu = num_processors + disabled_cpus;
2386 pr_warn("APIC: Disabling requested cpu."
2387 " Processor %d/0x%x ignored.\n", thiscpu, apicid);
2394 * If boot cpu has not been detected yet, then only allow upto
2395 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2397 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2398 apicid != boot_cpu_physical_apicid) {
2399 int thiscpu = max + disabled_cpus - 1;
2401 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost"
2402 " reached. Keeping one slot for boot cpu."
2403 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2409 if (num_processors >= nr_cpu_ids) {
2410 int thiscpu = max + disabled_cpus;
2412 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. "
2413 "Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2419 if (apicid == boot_cpu_physical_apicid) {
2421 * x86_bios_cpu_apicid is required to have processors listed
2422 * in same order as logical cpu numbers. Hence the first
2423 * entry is BSP, and so on.
2424 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2429 /* Logical cpuid 0 is reserved for BSP. */
2430 cpuid_to_apicid[0] = apicid;
2432 cpu = allocate_logical_cpuid(apicid);
2442 if (version == 0x0) {
2443 pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2448 if (version != boot_cpu_apic_version) {
2449 pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2450 boot_cpu_apic_version, cpu, version);
2453 if (apicid > max_physical_apicid)
2454 max_physical_apicid = apicid;
2456 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2457 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2458 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2460 #ifdef CONFIG_X86_32
2461 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2462 apic->x86_32_early_logical_apicid(cpu);
2464 set_cpu_possible(cpu, true);
2465 physid_set(apicid, phys_cpu_present_map);
2466 set_cpu_present(cpu, true);
2472 int hard_smp_processor_id(void)
2474 return read_apic_id();
2478 * Override the generic EOI implementation with an optimized version.
2479 * Only called during early boot when only one CPU is active and with
2480 * interrupts disabled, so we know this does not race with actual APIC driver
2483 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2487 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2488 /* Should happen once for each apic */
2489 WARN_ON((*drv)->eoi_write == eoi_write);
2490 (*drv)->native_eoi_write = (*drv)->eoi_write;
2491 (*drv)->eoi_write = eoi_write;
2495 static void __init apic_bsp_up_setup(void)
2497 #ifdef CONFIG_X86_64
2498 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2501 * Hack: In case of kdump, after a crash, kernel might be booting
2502 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2503 * might be zero if read from MP tables. Get it from LAPIC.
2505 # ifdef CONFIG_CRASH_DUMP
2506 boot_cpu_physical_apicid = read_apic_id();
2509 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2513 * apic_bsp_setup - Setup function for local apic and io-apic
2514 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2516 static void __init apic_bsp_setup(bool upmode)
2520 apic_bsp_up_setup();
2524 end_local_APIC_setup();
2525 irq_remap_enable_fault_handling();
2529 #ifdef CONFIG_UP_LATE_INIT
2530 void __init up_late_init(void)
2532 if (apic_intr_mode == APIC_PIC)
2535 /* Setup local timer */
2536 x86_init.timers.setup_percpu_clockev();
2547 * 'active' is true if the local APIC was enabled by us and
2548 * not the BIOS; this signifies that we are also responsible
2549 * for disabling it before entering apm/acpi suspend
2552 /* r/w apic fields */
2553 unsigned int apic_id;
2554 unsigned int apic_taskpri;
2555 unsigned int apic_ldr;
2556 unsigned int apic_dfr;
2557 unsigned int apic_spiv;
2558 unsigned int apic_lvtt;
2559 unsigned int apic_lvtpc;
2560 unsigned int apic_lvt0;
2561 unsigned int apic_lvt1;
2562 unsigned int apic_lvterr;
2563 unsigned int apic_tmict;
2564 unsigned int apic_tdcr;
2565 unsigned int apic_thmr;
2566 unsigned int apic_cmci;
2569 static int lapic_suspend(void)
2571 unsigned long flags;
2574 if (!apic_pm_state.active)
2577 maxlvt = lapic_get_maxlvt();
2579 apic_pm_state.apic_id = apic_read(APIC_ID);
2580 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2581 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2582 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2583 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2584 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2586 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2587 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2588 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2589 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2590 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2591 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2592 #ifdef CONFIG_X86_THERMAL_VECTOR
2594 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2596 #ifdef CONFIG_X86_MCE_INTEL
2598 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2601 local_irq_save(flags);
2604 * Mask IOAPIC before disabling the local APIC to prevent stale IRR
2605 * entries on some implementations.
2607 mask_ioapic_entries();
2609 disable_local_APIC();
2611 irq_remapping_disable();
2613 local_irq_restore(flags);
2617 static void lapic_resume(void)
2620 unsigned long flags;
2623 if (!apic_pm_state.active)
2626 local_irq_save(flags);
2629 * IO-APIC and PIC have their own resume routines.
2630 * We just mask them here to make sure the interrupt
2631 * subsystem is completely quiet while we enable x2apic
2632 * and interrupt-remapping.
2634 mask_ioapic_entries();
2635 legacy_pic->mask_all();
2641 * Make sure the APICBASE points to the right address
2643 * FIXME! This will be wrong if we ever support suspend on
2644 * SMP! We'll need to do this as part of the CPU restore!
2646 if (boot_cpu_data.x86 >= 6) {
2647 rdmsr(MSR_IA32_APICBASE, l, h);
2648 l &= ~MSR_IA32_APICBASE_BASE;
2649 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2650 wrmsr(MSR_IA32_APICBASE, l, h);
2654 maxlvt = lapic_get_maxlvt();
2655 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2656 apic_write(APIC_ID, apic_pm_state.apic_id);
2657 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2658 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2659 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2660 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2661 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2662 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2663 #ifdef CONFIG_X86_THERMAL_VECTOR
2665 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2667 #ifdef CONFIG_X86_MCE_INTEL
2669 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2672 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2673 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2674 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2675 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2676 apic_write(APIC_ESR, 0);
2677 apic_read(APIC_ESR);
2678 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2679 apic_write(APIC_ESR, 0);
2680 apic_read(APIC_ESR);
2682 irq_remapping_reenable(x2apic_mode);
2684 local_irq_restore(flags);
2688 * This device has no shutdown method - fully functioning local APICs
2689 * are needed on every CPU up until machine_halt/restart/poweroff.
2692 static struct syscore_ops lapic_syscore_ops = {
2693 .resume = lapic_resume,
2694 .suspend = lapic_suspend,
2697 static void apic_pm_activate(void)
2699 apic_pm_state.active = 1;
2702 static int __init init_lapic_sysfs(void)
2704 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2705 if (boot_cpu_has(X86_FEATURE_APIC))
2706 register_syscore_ops(&lapic_syscore_ops);
2711 /* local apic needs to resume before other devices access its registers. */
2712 core_initcall(init_lapic_sysfs);
2714 #else /* CONFIG_PM */
2716 static void apic_pm_activate(void) { }
2718 #endif /* CONFIG_PM */
2720 #ifdef CONFIG_X86_64
2722 static int multi_checked;
2725 static int set_multi(const struct dmi_system_id *d)
2729 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2734 static const struct dmi_system_id multi_dmi_table[] = {
2736 .callback = set_multi,
2737 .ident = "IBM System Summit2",
2739 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2740 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2746 static void dmi_check_multi(void)
2751 dmi_check_system(multi_dmi_table);
2756 * apic_is_clustered_box() -- Check if we can expect good TSC
2758 * Thus far, the major user of this is IBM's Summit2 series:
2759 * Clustered boxes may have unsynced TSC problems if they are
2761 * Use DMI to check them
2763 int apic_is_clustered_box(void)
2771 * APIC command line parameters
2773 static int __init setup_disableapic(char *arg)
2776 setup_clear_cpu_cap(X86_FEATURE_APIC);
2779 early_param("disableapic", setup_disableapic);
2781 /* same as disableapic, for compatibility */
2782 static int __init setup_nolapic(char *arg)
2784 return setup_disableapic(arg);
2786 early_param("nolapic", setup_nolapic);
2788 static int __init parse_lapic_timer_c2_ok(char *arg)
2790 local_apic_timer_c2_ok = 1;
2793 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2795 static int __init parse_disable_apic_timer(char *arg)
2797 disable_apic_timer = 1;
2800 early_param("noapictimer", parse_disable_apic_timer);
2802 static int __init parse_nolapic_timer(char *arg)
2804 disable_apic_timer = 1;
2807 early_param("nolapic_timer", parse_nolapic_timer);
2809 static int __init apic_set_verbosity(char *arg)
2812 #ifdef CONFIG_X86_64
2813 skip_ioapic_setup = 0;
2819 if (strcmp("debug", arg) == 0)
2820 apic_verbosity = APIC_DEBUG;
2821 else if (strcmp("verbose", arg) == 0)
2822 apic_verbosity = APIC_VERBOSE;
2823 #ifdef CONFIG_X86_64
2825 pr_warn("APIC Verbosity level %s not recognised"
2826 " use apic=verbose or apic=debug\n", arg);
2833 early_param("apic", apic_set_verbosity);
2835 static int __init lapic_insert_resource(void)
2840 /* Put local APIC into the resource map. */
2841 lapic_resource.start = apic_phys;
2842 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2843 insert_resource(&iomem_resource, &lapic_resource);
2849 * need call insert after e820__reserve_resources()
2850 * that is using request_resource
2852 late_initcall(lapic_insert_resource);
2854 static int __init apic_set_disabled_cpu_apicid(char *arg)
2856 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2861 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2863 static int __init apic_set_extnmi(char *arg)
2868 if (!strncmp("all", arg, 3))
2869 apic_extnmi = APIC_EXTNMI_ALL;
2870 else if (!strncmp("none", arg, 4))
2871 apic_extnmi = APIC_EXTNMI_NONE;
2872 else if (!strncmp("bsp", arg, 3))
2873 apic_extnmi = APIC_EXTNMI_BSP;
2875 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2881 early_param("apic_extnmi", apic_set_extnmi);