1 // SPDX-License-Identifier: GPL-2.0-only
3 * Shared support code for AMD K8 northbridges and derivatives.
4 * Copyright 2006 Andi Kleen, SUSE Labs.
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/types.h>
10 #include <linux/slab.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/export.h>
14 #include <linux/spinlock.h>
15 #include <linux/pci_ids.h>
16 #include <asm/amd_nb.h>
18 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
22 #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
23 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
24 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
25 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
26 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
27 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
28 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
30 /* Protect the PCI config register pairs used for SMN and DF indirect access. */
31 static DEFINE_MUTEX(smn_mutex);
33 static u32 *flush_words;
35 static const struct pci_device_id amd_root_ids[] = {
36 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
37 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
38 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
39 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
43 #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
45 static const struct pci_device_id amd_nb_misc_ids[] = {
46 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
47 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
48 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
49 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
50 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
51 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
52 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
53 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
54 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
55 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
56 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
57 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
58 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
59 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
60 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
65 static const struct pci_device_id amd_nb_link_ids[] = {
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
67 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
68 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
69 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
70 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
71 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
72 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
73 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
74 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
75 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
76 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
77 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
78 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
82 static const struct pci_device_id hygon_root_ids[] = {
83 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
87 static const struct pci_device_id hygon_nb_misc_ids[] = {
88 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
92 static const struct pci_device_id hygon_nb_link_ids[] = {
93 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
97 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
100 { 0xfe, 0x00, 0x20 },
104 static struct amd_northbridge_info amd_northbridges;
108 return amd_northbridges.num;
110 EXPORT_SYMBOL_GPL(amd_nb_num);
112 bool amd_nb_has_feature(unsigned int feature)
114 return ((amd_northbridges.flags & feature) == feature);
116 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
118 struct amd_northbridge *node_to_amd_nb(int node)
120 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
122 EXPORT_SYMBOL_GPL(node_to_amd_nb);
124 static struct pci_dev *next_northbridge(struct pci_dev *dev,
125 const struct pci_device_id *ids)
128 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
131 } while (!pci_match_id(ids, dev));
135 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
137 struct pci_dev *root;
140 if (node >= amd_northbridges.num)
143 root = node_to_amd_nb(node)->root;
147 mutex_lock(&smn_mutex);
149 err = pci_write_config_dword(root, 0x60, address);
151 pr_warn("Error programming SMN address 0x%x.\n", address);
155 err = (write ? pci_write_config_dword(root, 0x64, *value)
156 : pci_read_config_dword(root, 0x64, value));
158 pr_warn("Error %s SMN address 0x%x.\n",
159 (write ? "writing to" : "reading from"), address);
162 mutex_unlock(&smn_mutex);
168 int amd_smn_read(u16 node, u32 address, u32 *value)
170 return __amd_smn_rw(node, address, value, false);
172 EXPORT_SYMBOL_GPL(amd_smn_read);
174 int amd_smn_write(u16 node, u32 address, u32 value)
176 return __amd_smn_rw(node, address, &value, true);
178 EXPORT_SYMBOL_GPL(amd_smn_write);
181 * Data Fabric Indirect Access uses FICAA/FICAD.
183 * Fabric Indirect Configuration Access Address (FICAA): Constructed based
184 * on the device's Instance Id and the PCI function and register offset of
185 * the desired register.
187 * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
188 * and FICAD HI registers but so far we only need the LO register.
190 int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
196 if (node >= amd_northbridges.num)
199 F4 = node_to_amd_nb(node)->link;
204 ficaa |= reg & 0x3FC;
205 ficaa |= (func & 0x7) << 11;
206 ficaa |= instance_id << 16;
208 mutex_lock(&smn_mutex);
210 err = pci_write_config_dword(F4, 0x5C, ficaa);
212 pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
216 err = pci_read_config_dword(F4, 0x98, lo);
218 pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
221 mutex_unlock(&smn_mutex);
226 EXPORT_SYMBOL_GPL(amd_df_indirect_read);
228 int amd_cache_northbridges(void)
230 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
231 const struct pci_device_id *link_ids = amd_nb_link_ids;
232 const struct pci_device_id *root_ids = amd_root_ids;
233 struct pci_dev *root, *misc, *link;
234 struct amd_northbridge *nb;
235 u16 roots_per_misc = 0;
240 if (amd_northbridges.num)
243 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
244 root_ids = hygon_root_ids;
245 misc_ids = hygon_nb_misc_ids;
246 link_ids = hygon_nb_link_ids;
250 while ((misc = next_northbridge(misc, misc_ids)) != NULL)
257 while ((root = next_northbridge(root, root_ids)) != NULL)
261 roots_per_misc = root_count / misc_count;
264 * There should be _exactly_ N roots for each DF/SMN
267 if (!roots_per_misc || (root_count % roots_per_misc)) {
268 pr_info("Unsupported AMD DF/PCI configuration found\n");
273 nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
277 amd_northbridges.nb = nb;
278 amd_northbridges.num = misc_count;
280 link = misc = root = NULL;
281 for (i = 0; i < amd_northbridges.num; i++) {
282 node_to_amd_nb(i)->root = root =
283 next_northbridge(root, root_ids);
284 node_to_amd_nb(i)->misc = misc =
285 next_northbridge(misc, misc_ids);
286 node_to_amd_nb(i)->link = link =
287 next_northbridge(link, link_ids);
290 * If there are more PCI root devices than data fabric/
291 * system management network interfaces, then the (N)
292 * PCI roots per DF/SMN interface are functionally the
293 * same (for DF/SMN access) and N-1 are redundant. N-1
294 * PCI roots should be skipped per DF/SMN interface so
295 * the following DF/SMN interfaces get mapped to
298 for (j = 1; j < roots_per_misc; j++)
299 root = next_northbridge(root, root_ids);
302 if (amd_gart_present())
303 amd_northbridges.flags |= AMD_NB_GART;
306 * Check for L3 cache presence.
308 if (!cpuid_edx(0x80000006))
312 * Some CPU families support L3 Cache Index Disable. There are some
313 * limitations because of E382 and E388 on family 0x10.
315 if (boot_cpu_data.x86 == 0x10 &&
316 boot_cpu_data.x86_model >= 0x8 &&
317 (boot_cpu_data.x86_model > 0x9 ||
318 boot_cpu_data.x86_stepping >= 0x1))
319 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
321 if (boot_cpu_data.x86 == 0x15)
322 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
324 /* L3 cache partitioning is supported on family 0x15 */
325 if (boot_cpu_data.x86 == 0x15)
326 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
330 EXPORT_SYMBOL_GPL(amd_cache_northbridges);
333 * Ignores subdevice/subvendor but as far as I can figure out
334 * they're useless anyways
336 bool __init early_is_amd_nb(u32 device)
338 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
339 const struct pci_device_id *id;
340 u32 vendor = device & 0xffff;
342 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
343 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
346 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
347 misc_ids = hygon_nb_misc_ids;
350 for (id = misc_ids; id->vendor; id++)
351 if (vendor == id->vendor && device == id->device)
356 struct resource *amd_get_mmconfig_range(struct resource *res)
360 unsigned int segn_busn_bits;
362 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
363 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
366 /* assume all cpus from fam10h have mmconfig */
367 if (boot_cpu_data.x86 < 0x10)
370 address = MSR_FAM10H_MMIO_CONF_BASE;
371 rdmsrl(address, msr);
373 /* mmconfig is not enabled */
374 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
377 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
379 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
380 FAM10H_MMIO_CONF_BUSRANGE_MASK;
382 res->flags = IORESOURCE_MEM;
384 res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
388 int amd_get_subcaches(int cpu)
390 struct pci_dev *link = node_to_amd_nb(topology_die_id(cpu))->link;
393 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
396 pci_read_config_dword(link, 0x1d4, &mask);
398 return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
401 int amd_set_subcaches(int cpu, unsigned long mask)
403 static unsigned int reset, ban;
404 struct amd_northbridge *nb = node_to_amd_nb(topology_die_id(cpu));
408 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
411 /* if necessary, collect reset state of L3 partitioning and BAN mode */
413 pci_read_config_dword(nb->link, 0x1d4, &reset);
414 pci_read_config_dword(nb->misc, 0x1b8, &ban);
418 /* deactivate BAN mode if any subcaches are to be disabled */
420 pci_read_config_dword(nb->misc, 0x1b8, ®);
421 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
424 cuid = cpu_data(cpu).cpu_core_id;
426 mask |= (0xf ^ (1 << cuid)) << 26;
428 pci_write_config_dword(nb->link, 0x1d4, mask);
430 /* reset BAN mode if L3 partitioning returned to reset state */
431 pci_read_config_dword(nb->link, 0x1d4, ®);
433 pci_read_config_dword(nb->misc, 0x1b8, ®);
435 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
441 static void amd_cache_gart(void)
445 if (!amd_nb_has_feature(AMD_NB_GART))
448 flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
450 amd_northbridges.flags &= ~AMD_NB_GART;
451 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
455 for (i = 0; i != amd_northbridges.num; i++)
456 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
459 void amd_flush_garts(void)
463 static DEFINE_SPINLOCK(gart_lock);
465 if (!amd_nb_has_feature(AMD_NB_GART))
469 * Avoid races between AGP and IOMMU. In theory it's not needed
470 * but I'm not sure if the hardware won't lose flush requests
471 * when another is pending. This whole thing is so expensive anyways
472 * that it doesn't matter to serialize more. -AK
474 spin_lock_irqsave(&gart_lock, flags);
476 for (i = 0; i < amd_northbridges.num; i++) {
477 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
481 for (i = 0; i < amd_northbridges.num; i++) {
483 /* Make sure the hardware actually executed the flush*/
485 pci_read_config_dword(node_to_amd_nb(i)->misc,
492 spin_unlock_irqrestore(&gart_lock, flags);
494 pr_notice("nothing to flush?\n");
496 EXPORT_SYMBOL_GPL(amd_flush_garts);
498 static void __fix_erratum_688(void *info)
500 #define MSR_AMD64_IC_CFG 0xC0011021
502 msr_set_bit(MSR_AMD64_IC_CFG, 3);
503 msr_set_bit(MSR_AMD64_IC_CFG, 14);
506 /* Apply erratum 688 fix so machines without a BIOS fix work. */
507 static __init void fix_erratum_688(void)
512 if (boot_cpu_data.x86 != 0x14)
515 if (!amd_northbridges.num)
518 F4 = node_to_amd_nb(0)->link;
522 if (pci_read_config_dword(F4, 0x164, &val))
528 on_each_cpu(__fix_erratum_688, NULL, 0);
530 pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
533 static __init int init_amd_nbs(void)
535 amd_cache_northbridges();
543 /* This has to go after the PCI subsystem */
544 fs_initcall(init_amd_nbs);