1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
9 * 32-bit intercept words in the VMCB Control Area, starting
10 * at Byte offset 000h.
13 enum intercept_words {
24 /* Byte offset 000h (word 0) */
25 INTERCEPT_CR0_READ = 0,
26 INTERCEPT_CR3_READ = 3,
27 INTERCEPT_CR4_READ = 4,
28 INTERCEPT_CR8_READ = 8,
29 INTERCEPT_CR0_WRITE = 16,
30 INTERCEPT_CR3_WRITE = 16 + 3,
31 INTERCEPT_CR4_WRITE = 16 + 4,
32 INTERCEPT_CR8_WRITE = 16 + 8,
33 /* Byte offset 004h (word 1) */
34 INTERCEPT_DR0_READ = 32,
42 INTERCEPT_DR0_WRITE = 48,
50 /* Byte offset 008h (word 2) */
51 INTERCEPT_EXCEPTION_OFFSET = 64,
52 /* Byte offset 00Ch (word 3) */
58 INTERCEPT_SELECTIVE_CR0,
82 INTERCEPT_TASK_SWITCH,
83 INTERCEPT_FERR_FREEZE,
85 /* Byte offset 010h (word 4) */
86 INTERCEPT_VMRUN = 128,
101 /* Byte offset 014h (word 5) */
102 INTERCEPT_INVLPGB = 160,
103 INTERCEPT_INVLPGB_ILLEGAL,
110 struct __attribute__ ((__packed__)) vmcb_control_area {
111 u32 intercepts[MAX_INTERCEPT];
112 u32 reserved_1[15 - MAX_INTERCEPT];
113 u16 pause_filter_thresh;
114 u16 pause_filter_count;
130 u32 exit_int_info_err;
143 u64 avic_backing_page; /* Offset 0xe0 */
144 u8 reserved_6[8]; /* Offset 0xe8 */
145 u64 avic_logical_id; /* Offset 0xf0 */
146 u64 avic_physical_id; /* Offset 0xf8 */
150 #define TLB_CONTROL_DO_NOTHING 0
151 #define TLB_CONTROL_FLUSH_ALL_ASID 1
152 #define TLB_CONTROL_FLUSH_ASID 3
153 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
155 #define V_TPR_MASK 0x0f
157 #define V_IRQ_SHIFT 8
158 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
160 #define V_GIF_SHIFT 9
161 #define V_GIF_MASK (1 << V_GIF_SHIFT)
163 #define V_INTR_PRIO_SHIFT 16
164 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
166 #define V_IGN_TPR_SHIFT 20
167 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
169 #define V_INTR_MASKING_SHIFT 24
170 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
172 #define V_GIF_ENABLE_SHIFT 25
173 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
175 #define AVIC_ENABLE_SHIFT 31
176 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
178 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
179 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
181 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
182 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
184 #define SVM_IOIO_STR_SHIFT 2
185 #define SVM_IOIO_REP_SHIFT 3
186 #define SVM_IOIO_SIZE_SHIFT 4
187 #define SVM_IOIO_ASIZE_SHIFT 7
189 #define SVM_IOIO_TYPE_MASK 1
190 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
191 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
192 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
193 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
195 #define SVM_VM_CR_VALID_MASK 0x001fULL
196 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
197 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
199 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
200 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
209 struct vmcb_save_area {
216 struct vmcb_seg gdtr;
217 struct vmcb_seg ldtr;
218 struct vmcb_seg idtr;
254 * The following part of the save area is valid only for
255 * SEV-ES guests when referenced through the GHCB.
258 u64 reserved_8; /* rax already available at 0x01f8 */
262 u64 reserved_9; /* rsp already available at 0x01d8 */
286 struct vmcb_save_area save;
287 u8 reserved_save[2048 - sizeof(struct vmcb_save_area)];
289 u8 shared_buffer[2032];
292 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
297 #define EXPECTED_VMCB_SAVE_AREA_SIZE 1032
298 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 256
299 #define EXPECTED_GHCB_SIZE PAGE_SIZE
301 static inline void __unused_size_checks(void)
303 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
304 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
305 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
309 struct vmcb_control_area control;
310 u8 reserved_control[1024 - sizeof(struct vmcb_control_area)];
311 struct vmcb_save_area save;
314 #define SVM_CPUID_FUNC 0x8000000a
316 #define SVM_VM_CR_SVM_DISABLE 4
318 #define SVM_SELECTOR_S_SHIFT 4
319 #define SVM_SELECTOR_DPL_SHIFT 5
320 #define SVM_SELECTOR_P_SHIFT 7
321 #define SVM_SELECTOR_AVL_SHIFT 8
322 #define SVM_SELECTOR_L_SHIFT 9
323 #define SVM_SELECTOR_DB_SHIFT 10
324 #define SVM_SELECTOR_G_SHIFT 11
326 #define SVM_SELECTOR_TYPE_MASK (0xf)
327 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
328 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
329 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
330 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
331 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
332 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
333 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
335 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
336 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
337 #define SVM_SELECTOR_CODE_MASK (1 << 3)
339 #define SVM_EVTINJ_VEC_MASK 0xff
341 #define SVM_EVTINJ_TYPE_SHIFT 8
342 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
344 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
345 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
346 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
347 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
349 #define SVM_EVTINJ_VALID (1 << 31)
350 #define SVM_EVTINJ_VALID_ERR (1 << 11)
352 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
353 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
355 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
356 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
357 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
358 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
360 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
361 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
363 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
364 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
365 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
367 #define SVM_EXITINFO_REG_MASK 0x0F
369 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
371 /* GHCB Accessor functions */
373 #define GHCB_BITMAP_IDX(field) \
374 (offsetof(struct vmcb_save_area, field) / sizeof(u64))
376 #define DEFINE_GHCB_ACCESSORS(field) \
377 static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
379 return test_bit(GHCB_BITMAP_IDX(field), \
380 (unsigned long *)&ghcb->save.valid_bitmap); \
383 static inline u64 ghcb_get_##field(struct ghcb *ghcb) \
385 return ghcb->save.field; \
388 static inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
390 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
393 static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
395 __set_bit(GHCB_BITMAP_IDX(field), \
396 (unsigned long *)&ghcb->save.valid_bitmap); \
397 ghcb->save.field = value; \
400 DEFINE_GHCB_ACCESSORS(cpl)
401 DEFINE_GHCB_ACCESSORS(rip)
402 DEFINE_GHCB_ACCESSORS(rsp)
403 DEFINE_GHCB_ACCESSORS(rax)
404 DEFINE_GHCB_ACCESSORS(rcx)
405 DEFINE_GHCB_ACCESSORS(rdx)
406 DEFINE_GHCB_ACCESSORS(rbx)
407 DEFINE_GHCB_ACCESSORS(rbp)
408 DEFINE_GHCB_ACCESSORS(rsi)
409 DEFINE_GHCB_ACCESSORS(rdi)
410 DEFINE_GHCB_ACCESSORS(r8)
411 DEFINE_GHCB_ACCESSORS(r9)
412 DEFINE_GHCB_ACCESSORS(r10)
413 DEFINE_GHCB_ACCESSORS(r11)
414 DEFINE_GHCB_ACCESSORS(r12)
415 DEFINE_GHCB_ACCESSORS(r13)
416 DEFINE_GHCB_ACCESSORS(r14)
417 DEFINE_GHCB_ACCESSORS(r15)
418 DEFINE_GHCB_ACCESSORS(sw_exit_code)
419 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
420 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
421 DEFINE_GHCB_ACCESSORS(sw_scratch)
422 DEFINE_GHCB_ACCESSORS(xcr0)