arch/x86/include/asm/intel-family.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_INTEL_FAMILY_H
   3 #define _ASM_X86_INTEL_FAMILY_H
   4
   5 /*
   6  * "Big Core" Processors (Branded as Core, Xeon, etc...)
   7  *
   8  * While adding a new CPUID for a new microarchitecture, add a new
   9  * group to keep logically sorted out in chronological order. Within
  10  * that group keep the CPUID for the variants sorted by model number.
  11  *
  12  * The defined symbol names have the following form:
  13  *      INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
  14  * where:
  15  * OPTFAMILY    Describes the family of CPUs that this belongs to. Default
  16  *              is assumed to be "_CORE" (and should be omitted). Other values
  17  *              currently in use are _ATOM and _XEON_PHI
  18  * MICROARCH    Is the code name for the micro-architecture for this core.
  19  *              N.B. Not the platform name.
  20  * OPTDIFF      If needed, a short string to differentiate by market segment.
  21  *
  22  *              Common OPTDIFFs:
  23  *
  24  *                      - regular client parts
  25  *              _L      - regular mobile parts
  26  *              _G      - parts with extra graphics on
  27  *              _X      - regular server parts
  28  *              _D      - micro server parts
  29  *
  30  *              Historical OPTDIFFs:
  31  *
  32  *              _EP     - 2 socket server parts
  33  *              _EX     - 4+ socket server parts
  34  *
  35  * The #define line may optionally include a comment including platform names.
  36  */
  37
  38 /* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
  39 #define INTEL_FAM6_ANY                  X86_MODEL_ANY
  40
  41 #define INTEL_FAM6_CORE_YONAH           0x0E
  42
  43 #define INTEL_FAM6_CORE2_MEROM          0x0F
  44 #define INTEL_FAM6_CORE2_MEROM_L        0x16
  45 #define INTEL_FAM6_CORE2_PENRYN         0x17
  46 #define INTEL_FAM6_CORE2_DUNNINGTON     0x1D
  47
  48 #define INTEL_FAM6_NEHALEM              0x1E
  49 #define INTEL_FAM6_NEHALEM_G            0x1F /* Auburndale / Havendale */
  50 #define INTEL_FAM6_NEHALEM_EP           0x1A
  51 #define INTEL_FAM6_NEHALEM_EX           0x2E
  52
  53 #define INTEL_FAM6_WESTMERE             0x25
  54 #define INTEL_FAM6_WESTMERE_EP          0x2C
  55 #define INTEL_FAM6_WESTMERE_EX          0x2F
  56
  57 #define INTEL_FAM6_SANDYBRIDGE          0x2A
  58 #define INTEL_FAM6_SANDYBRIDGE_X        0x2D
  59 #define INTEL_FAM6_IVYBRIDGE            0x3A
  60 #define INTEL_FAM6_IVYBRIDGE_X          0x3E
  61
  62 #define INTEL_FAM6_HASWELL              0x3C
  63 #define INTEL_FAM6_HASWELL_X            0x3F
  64 #define INTEL_FAM6_HASWELL_L            0x45
  65 #define INTEL_FAM6_HASWELL_G            0x46
  66
  67 #define INTEL_FAM6_BROADWELL            0x3D
  68 #define INTEL_FAM6_BROADWELL_G          0x47
  69 #define INTEL_FAM6_BROADWELL_X          0x4F
  70 #define INTEL_FAM6_BROADWELL_D          0x56
  71
  72 #define INTEL_FAM6_SKYLAKE_L            0x4E
  73 #define INTEL_FAM6_SKYLAKE              0x5E
  74 #define INTEL_FAM6_SKYLAKE_X            0x55
  75 #define INTEL_FAM6_KABYLAKE_L           0x8E
  76 #define INTEL_FAM6_KABYLAKE             0x9E
  77
  78 #define INTEL_FAM6_CANNONLAKE_L         0x66
  79
  80 #define INTEL_FAM6_ICELAKE_X            0x6A
  81 #define INTEL_FAM6_ICELAKE_D            0x6C
  82 #define INTEL_FAM6_ICELAKE              0x7D
  83 #define INTEL_FAM6_ICELAKE_L            0x7E
  84 #define INTEL_FAM6_ICELAKE_NNPI         0x9D
  85
  86 #define INTEL_FAM6_TIGERLAKE_L          0x8C
  87 #define INTEL_FAM6_TIGERLAKE            0x8D
  88
  89 #define INTEL_FAM6_COMETLAKE            0xA5
  90 #define INTEL_FAM6_COMETLAKE_L          0xA6
  91
  92 #define INTEL_FAM6_ROCKETLAKE           0xA7
  93
  94 #define INTEL_FAM6_SAPPHIRERAPIDS_X     0x8F
  95
  96 /* Hybrid Core/Atom Processors */
  97
  98 #define INTEL_FAM6_LAKEFIELD            0x8A
  99 #define INTEL_FAM6_ALDERLAKE            0x97
 100
 101 /* "Small Core" Processors (Atom) */
 102
 103 #define INTEL_FAM6_ATOM_BONNELL         0x1C /* Diamondville, Pineview */
 104 #define INTEL_FAM6_ATOM_BONNELL_MID     0x26 /* Silverthorne, Lincroft */
 105
 106 #define INTEL_FAM6_ATOM_SALTWELL        0x36 /* Cedarview */
 107 #define INTEL_FAM6_ATOM_SALTWELL_MID    0x27 /* Penwell */
 108 #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
 109
 110 #define INTEL_FAM6_ATOM_SILVERMONT      0x37 /* Bay Trail, Valleyview */
 111 #define INTEL_FAM6_ATOM_SILVERMONT_D    0x4D /* Avaton, Rangely */
 112 #define INTEL_FAM6_ATOM_SILVERMONT_MID  0x4A /* Merriefield */
 113
 114 #define INTEL_FAM6_ATOM_AIRMONT         0x4C /* Cherry Trail, Braswell */
 115 #define INTEL_FAM6_ATOM_AIRMONT_MID     0x5A /* Moorefield */
 116 #define INTEL_FAM6_ATOM_AIRMONT_NP      0x75 /* Lightning Mountain */
 117
 118 #define INTEL_FAM6_ATOM_GOLDMONT        0x5C /* Apollo Lake */
 119 #define INTEL_FAM6_ATOM_GOLDMONT_D      0x5F /* Denverton */
 120
 121 /* Note: the micro-architecture is "Goldmont Plus" */
 122 #define INTEL_FAM6_ATOM_GOLDMONT_PLUS   0x7A /* Gemini Lake */
 123
 124 #define INTEL_FAM6_ATOM_TREMONT_D       0x86 /* Jacobsville */
 125 #define INTEL_FAM6_ATOM_TREMONT         0x96 /* Elkhart Lake */
 126 #define INTEL_FAM6_ATOM_TREMONT_L       0x9C /* Jasper Lake */
 127
 128 /* Xeon Phi */
 129
 130 #define INTEL_FAM6_XEON_PHI_KNL         0x57 /* Knights Landing */
 131 #define INTEL_FAM6_XEON_PHI_KNM         0x85 /* Knights Mill */
 132
 133 /* Family 5 */
 134 #define INTEL_FAM5_QUARK_X1000          0x09 /* Quark X1000 SoC */
 135
 136 #endif /* _ASM_X86_INTEL_FAMILY_H */