2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
60 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61 * from just a typename, as opposed to an actual function.
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
70 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
74 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
75 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
77 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
78 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
79 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
82 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
85 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
88 * This one is magic, it will get called even when PMU init fails (because
89 * there is no PMU), in which case it should simply return NULL.
91 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
93 u64 __read_mostly hw_cache_event_ids
94 [PERF_COUNT_HW_CACHE_MAX]
95 [PERF_COUNT_HW_CACHE_OP_MAX]
96 [PERF_COUNT_HW_CACHE_RESULT_MAX];
97 u64 __read_mostly hw_cache_extra_regs
98 [PERF_COUNT_HW_CACHE_MAX]
99 [PERF_COUNT_HW_CACHE_OP_MAX]
100 [PERF_COUNT_HW_CACHE_RESULT_MAX];
103 * Propagate event elapsed time into the generic event.
104 * Can only be executed on the CPU where the event is active.
105 * Returns the delta events processed.
107 u64 x86_perf_event_update(struct perf_event *event)
109 struct hw_perf_event *hwc = &event->hw;
110 int shift = 64 - x86_pmu.cntval_bits;
111 u64 prev_raw_count, new_raw_count;
114 if (unlikely(!hwc->event_base))
117 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
118 return x86_pmu.update_topdown_event(event);
121 * Careful: an NMI might modify the previous event value.
123 * Our tactic to handle this is to first atomically read and
124 * exchange a new raw count - then add that new-prev delta
125 * count to the generic event atomically:
128 prev_raw_count = local64_read(&hwc->prev_count);
129 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
131 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
132 new_raw_count) != prev_raw_count)
136 * Now we have the new raw value and have updated the prev
137 * timestamp already. We can now calculate the elapsed delta
138 * (event-)time and add that to the generic event.
140 * Careful, not all hw sign-extends above the physical width
143 delta = (new_raw_count << shift) - (prev_raw_count << shift);
146 local64_add(delta, &event->count);
147 local64_sub(delta, &hwc->period_left);
149 return new_raw_count;
153 * Find and validate any extra registers to set up.
155 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
157 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
158 struct hw_perf_event_extra *reg;
159 struct extra_reg *er;
161 reg = &event->hw.extra_reg;
166 for (er = extra_regs; er->msr; er++) {
167 if (er->event != (config & er->config_mask))
169 if (event->attr.config1 & ~er->valid_mask)
171 /* Check if the extra msrs can be safely accessed*/
172 if (!er->extra_msr_access)
176 reg->config = event->attr.config1;
183 static atomic_t active_events;
184 static atomic_t pmc_refcount;
185 static DEFINE_MUTEX(pmc_reserve_mutex);
187 #ifdef CONFIG_X86_LOCAL_APIC
189 static inline int get_possible_num_counters(void)
191 int i, num_counters = x86_pmu.num_counters;
196 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
197 num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
202 static bool reserve_pmc_hardware(void)
204 int i, num_counters = get_possible_num_counters();
206 for (i = 0; i < num_counters; i++) {
207 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
211 for (i = 0; i < num_counters; i++) {
212 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
219 for (i--; i >= 0; i--)
220 release_evntsel_nmi(x86_pmu_config_addr(i));
225 for (i--; i >= 0; i--)
226 release_perfctr_nmi(x86_pmu_event_addr(i));
231 static void release_pmc_hardware(void)
233 int i, num_counters = get_possible_num_counters();
235 for (i = 0; i < num_counters; i++) {
236 release_perfctr_nmi(x86_pmu_event_addr(i));
237 release_evntsel_nmi(x86_pmu_config_addr(i));
243 static bool reserve_pmc_hardware(void) { return true; }
244 static void release_pmc_hardware(void) {}
248 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
250 u64 val, val_fail = -1, val_new= ~0;
251 int i, reg, reg_fail = -1, ret = 0;
256 * Check to see if the BIOS enabled any of the counters, if so
259 for (i = 0; i < num_counters; i++) {
260 reg = x86_pmu_config_addr(i);
261 ret = rdmsrl_safe(reg, &val);
264 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
273 if (num_counters_fixed) {
274 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
275 ret = rdmsrl_safe(reg, &val);
278 for (i = 0; i < num_counters_fixed; i++) {
279 if (fixed_counter_disabled(i, pmu))
281 if (val & (0x03ULL << i*4)) {
290 * If all the counters are enabled, the below test will always
291 * fail. The tools will also become useless in this scenario.
292 * Just fail and disable the hardware counters.
295 if (reg_safe == -1) {
301 * Read the current value, change it and read it back to see if it
302 * matches, this is needed to detect certain hardware emulators
303 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
305 reg = x86_pmu_event_addr(reg_safe);
306 if (rdmsrl_safe(reg, &val))
309 ret = wrmsrl_safe(reg, val);
310 ret |= rdmsrl_safe(reg, &val_new);
311 if (ret || val != val_new)
315 * We still allow the PMU driver to operate:
318 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
319 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
326 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
327 pr_cont("PMU not available due to virtualization, using software events only.\n");
329 pr_cont("Broken PMU hardware detected, using software events only.\n");
330 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
337 static void hw_perf_event_destroy(struct perf_event *event)
339 x86_release_hardware();
340 atomic_dec(&active_events);
343 void hw_perf_lbr_event_destroy(struct perf_event *event)
345 hw_perf_event_destroy(event);
347 /* undo the lbr/bts event accounting */
348 x86_del_exclusive(x86_lbr_exclusive_lbr);
351 static inline int x86_pmu_initialized(void)
353 return x86_pmu.handle_irq != NULL;
357 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
359 struct perf_event_attr *attr = &event->attr;
360 unsigned int cache_type, cache_op, cache_result;
363 config = attr->config;
365 cache_type = (config >> 0) & 0xff;
366 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
368 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
370 cache_op = (config >> 8) & 0xff;
371 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
373 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
375 cache_result = (config >> 16) & 0xff;
376 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
378 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
380 val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
388 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
389 return x86_pmu_extra_regs(val, event);
392 int x86_reserve_hardware(void)
396 if (!atomic_inc_not_zero(&pmc_refcount)) {
397 mutex_lock(&pmc_reserve_mutex);
398 if (atomic_read(&pmc_refcount) == 0) {
399 if (!reserve_pmc_hardware()) {
402 reserve_ds_buffers();
403 reserve_lbr_buffers();
407 atomic_inc(&pmc_refcount);
408 mutex_unlock(&pmc_reserve_mutex);
414 void x86_release_hardware(void)
416 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
417 release_pmc_hardware();
418 release_ds_buffers();
419 release_lbr_buffers();
420 mutex_unlock(&pmc_reserve_mutex);
425 * Check if we can create event of a certain type (that no conflicting events
428 int x86_add_exclusive(unsigned int what)
433 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
434 * LBR and BTS are still mutually exclusive.
436 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
439 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
440 mutex_lock(&pmc_reserve_mutex);
441 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
442 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
445 atomic_inc(&x86_pmu.lbr_exclusive[what]);
446 mutex_unlock(&pmc_reserve_mutex);
450 atomic_inc(&active_events);
454 mutex_unlock(&pmc_reserve_mutex);
458 void x86_del_exclusive(unsigned int what)
460 atomic_dec(&active_events);
463 * See the comment in x86_add_exclusive().
465 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
468 atomic_dec(&x86_pmu.lbr_exclusive[what]);
471 int x86_setup_perfctr(struct perf_event *event)
473 struct perf_event_attr *attr = &event->attr;
474 struct hw_perf_event *hwc = &event->hw;
477 if (!is_sampling_event(event)) {
478 hwc->sample_period = x86_pmu.max_period;
479 hwc->last_period = hwc->sample_period;
480 local64_set(&hwc->period_left, hwc->sample_period);
483 if (attr->type == event->pmu->type)
484 return x86_pmu_extra_regs(event->attr.config, event);
486 if (attr->type == PERF_TYPE_HW_CACHE)
487 return set_ext_hw_attr(hwc, event);
489 if (attr->config >= x86_pmu.max_events)
492 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
497 config = x86_pmu.event_map(attr->config);
505 hwc->config |= config;
511 * check that branch_sample_type is compatible with
512 * settings needed for precise_ip > 1 which implies
513 * using the LBR to capture ALL taken branches at the
514 * priv levels of the measurement
516 static inline int precise_br_compat(struct perf_event *event)
518 u64 m = event->attr.branch_sample_type;
521 /* must capture all branches */
522 if (!(m & PERF_SAMPLE_BRANCH_ANY))
525 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
527 if (!event->attr.exclude_user)
528 b |= PERF_SAMPLE_BRANCH_USER;
530 if (!event->attr.exclude_kernel)
531 b |= PERF_SAMPLE_BRANCH_KERNEL;
534 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
540 int x86_pmu_max_precise(void)
544 /* Support for constant skid */
545 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
548 /* Support for IP fixup */
549 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
552 if (x86_pmu.pebs_prec_dist)
558 int x86_pmu_hw_config(struct perf_event *event)
560 if (event->attr.precise_ip) {
561 int precise = x86_pmu_max_precise();
563 if (event->attr.precise_ip > precise)
566 /* There's no sense in having PEBS for non sampling events: */
567 if (!is_sampling_event(event))
571 * check that PEBS LBR correction does not conflict with
572 * whatever the user is asking with attr->branch_sample_type
574 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
575 u64 *br_type = &event->attr.branch_sample_type;
577 if (has_branch_stack(event)) {
578 if (!precise_br_compat(event))
581 /* branch_sample_type is compatible */
585 * user did not specify branch_sample_type
587 * For PEBS fixups, we capture all
588 * the branches at the priv level of the
591 *br_type = PERF_SAMPLE_BRANCH_ANY;
593 if (!event->attr.exclude_user)
594 *br_type |= PERF_SAMPLE_BRANCH_USER;
596 if (!event->attr.exclude_kernel)
597 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
601 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
602 event->attach_state |= PERF_ATTACH_TASK_DATA;
606 * (keep 'enabled' bit clear for now)
608 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
611 * Count user and OS events unless requested not to
613 if (!event->attr.exclude_user)
614 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
615 if (!event->attr.exclude_kernel)
616 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
618 if (event->attr.type == event->pmu->type)
619 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
621 if (event->attr.sample_period && x86_pmu.limit_period) {
622 if (x86_pmu.limit_period(event, event->attr.sample_period) >
623 event->attr.sample_period)
627 /* sample_regs_user never support XMM registers */
628 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
631 * Besides the general purpose registers, XMM registers may
632 * be collected in PEBS on some platforms, e.g. Icelake
634 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
635 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
638 if (!event->attr.precise_ip)
642 return x86_setup_perfctr(event);
646 * Setup the hardware configuration for a given attr_type
648 static int __x86_pmu_event_init(struct perf_event *event)
652 if (!x86_pmu_initialized())
655 err = x86_reserve_hardware();
659 atomic_inc(&active_events);
660 event->destroy = hw_perf_event_destroy;
663 event->hw.last_cpu = -1;
664 event->hw.last_tag = ~0ULL;
667 event->hw.extra_reg.idx = EXTRA_REG_NONE;
668 event->hw.branch_reg.idx = EXTRA_REG_NONE;
670 return x86_pmu.hw_config(event);
673 void x86_pmu_disable_all(void)
675 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
678 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
679 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
682 if (!test_bit(idx, cpuc->active_mask))
684 rdmsrl(x86_pmu_config_addr(idx), val);
685 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
687 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
688 wrmsrl(x86_pmu_config_addr(idx), val);
689 if (is_counter_pair(hwc))
690 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
694 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
696 return static_call(x86_pmu_guest_get_msrs)(nr);
698 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
701 * There may be PMI landing after enabled=0. The PMI hitting could be before or
704 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
705 * It will not be re-enabled in the NMI handler again, because enabled=0. After
706 * handling the NMI, disable_all will be called, which will not change the
707 * state either. If PMI hits after disable_all, the PMU is already disabled
708 * before entering NMI handler. The NMI handler will not change the state
711 * So either situation is harmless.
713 static void x86_pmu_disable(struct pmu *pmu)
715 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
717 if (!x86_pmu_initialized())
727 static_call(x86_pmu_disable_all)();
730 void x86_pmu_enable_all(int added)
732 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
735 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
736 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
738 if (!test_bit(idx, cpuc->active_mask))
741 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
745 static inline int is_x86_event(struct perf_event *event)
750 return event->pmu == &pmu;
752 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
753 if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
760 struct pmu *x86_get_pmu(unsigned int cpu)
762 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
765 * All CPUs of the hybrid type have been offline.
766 * The x86_get_pmu() should not be invoked.
768 if (WARN_ON_ONCE(!cpuc->pmu))
774 * Event scheduler state:
776 * Assign events iterating over all events and counters, beginning
777 * with events with least weights first. Keep the current iterator
778 * state in struct sched_state.
782 int event; /* event index */
783 int counter; /* counter index */
784 int unassigned; /* number of events to be assigned left */
785 int nr_gp; /* number of GP counters used */
789 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
790 #define SCHED_STATES_MAX 2
797 struct event_constraint **constraints;
798 struct sched_state state;
799 struct sched_state saved[SCHED_STATES_MAX];
803 * Initialize iterator that runs through all events and counters.
805 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
806 int num, int wmin, int wmax, int gpmax)
810 memset(sched, 0, sizeof(*sched));
811 sched->max_events = num;
812 sched->max_weight = wmax;
813 sched->max_gp = gpmax;
814 sched->constraints = constraints;
816 for (idx = 0; idx < num; idx++) {
817 if (constraints[idx]->weight == wmin)
821 sched->state.event = idx; /* start with min weight */
822 sched->state.weight = wmin;
823 sched->state.unassigned = num;
826 static void perf_sched_save_state(struct perf_sched *sched)
828 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
831 sched->saved[sched->saved_states] = sched->state;
832 sched->saved_states++;
835 static bool perf_sched_restore_state(struct perf_sched *sched)
837 if (!sched->saved_states)
840 sched->saved_states--;
841 sched->state = sched->saved[sched->saved_states];
843 /* this assignment didn't work out */
844 /* XXX broken vs EVENT_PAIR */
845 sched->state.used &= ~BIT_ULL(sched->state.counter);
847 /* try the next one */
848 sched->state.counter++;
854 * Select a counter for the current event to schedule. Return true on
857 static bool __perf_sched_find_counter(struct perf_sched *sched)
859 struct event_constraint *c;
862 if (!sched->state.unassigned)
865 if (sched->state.event >= sched->max_events)
868 c = sched->constraints[sched->state.event];
869 /* Prefer fixed purpose counters */
870 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
871 idx = INTEL_PMC_IDX_FIXED;
872 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
873 u64 mask = BIT_ULL(idx);
875 if (sched->state.used & mask)
878 sched->state.used |= mask;
883 /* Grab the first unused counter starting with idx */
884 idx = sched->state.counter;
885 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
886 u64 mask = BIT_ULL(idx);
888 if (c->flags & PERF_X86_EVENT_PAIR)
891 if (sched->state.used & mask)
894 if (sched->state.nr_gp++ >= sched->max_gp)
897 sched->state.used |= mask;
904 sched->state.counter = idx;
907 perf_sched_save_state(sched);
912 static bool perf_sched_find_counter(struct perf_sched *sched)
914 while (!__perf_sched_find_counter(sched)) {
915 if (!perf_sched_restore_state(sched))
923 * Go through all unassigned events and find the next one to schedule.
924 * Take events with the least weight first. Return true on success.
926 static bool perf_sched_next_event(struct perf_sched *sched)
928 struct event_constraint *c;
930 if (!sched->state.unassigned || !--sched->state.unassigned)
935 sched->state.event++;
936 if (sched->state.event >= sched->max_events) {
938 sched->state.event = 0;
939 sched->state.weight++;
940 if (sched->state.weight > sched->max_weight)
943 c = sched->constraints[sched->state.event];
944 } while (c->weight != sched->state.weight);
946 sched->state.counter = 0; /* start with first counter */
952 * Assign a counter for each event.
954 int perf_assign_events(struct event_constraint **constraints, int n,
955 int wmin, int wmax, int gpmax, int *assign)
957 struct perf_sched sched;
959 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
962 if (!perf_sched_find_counter(&sched))
965 assign[sched.state.event] = sched.state.counter;
966 } while (perf_sched_next_event(&sched));
968 return sched.state.unassigned;
970 EXPORT_SYMBOL_GPL(perf_assign_events);
972 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
974 int num_counters = hybrid(cpuc->pmu, num_counters);
975 struct event_constraint *c;
976 struct perf_event *e;
977 int n0, i, wmin, wmax, unsched = 0;
978 struct hw_perf_event *hwc;
982 * Compute the number of events already present; see x86_pmu_add(),
983 * validate_group() and x86_pmu_commit_txn(). For the former two
984 * cpuc->n_events hasn't been updated yet, while for the latter
985 * cpuc->n_txn contains the number of events added in the current
989 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
992 static_call_cond(x86_pmu_start_scheduling)(cpuc);
994 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
995 c = cpuc->event_constraint[i];
998 * Previously scheduled events should have a cached constraint,
999 * while new events should not have one.
1001 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
1004 * Request constraints for new events; or for those events that
1005 * have a dynamic constraint -- for those the constraint can
1006 * change due to external factors (sibling state, allow_tfa).
1008 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
1009 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
1010 cpuc->event_constraint[i] = c;
1013 wmin = min(wmin, c->weight);
1014 wmax = max(wmax, c->weight);
1018 * fastpath, try to reuse previous register
1020 for (i = 0; i < n; i++) {
1023 hwc = &cpuc->event_list[i]->hw;
1024 c = cpuc->event_constraint[i];
1026 /* never assigned */
1030 /* constraint still honored */
1031 if (!test_bit(hwc->idx, c->idxmsk))
1034 mask = BIT_ULL(hwc->idx);
1035 if (is_counter_pair(hwc))
1038 /* not already used */
1039 if (used_mask & mask)
1045 assign[i] = hwc->idx;
1050 int gpmax = num_counters;
1053 * Do not allow scheduling of more than half the available
1056 * This helps avoid counter starvation of sibling thread by
1057 * ensuring at most half the counters cannot be in exclusive
1058 * mode. There is no designated counters for the limits. Any
1059 * N/2 counters can be used. This helps with events with
1060 * specific counter constraints.
1062 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1063 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1067 * Reduce the amount of available counters to allow fitting
1068 * the extra Merge events needed by large increment events.
1070 if (x86_pmu.flags & PMU_FL_PAIR) {
1071 gpmax = num_counters - cpuc->n_pair;
1072 WARN_ON(gpmax <= 0);
1075 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1076 wmax, gpmax, assign);
1080 * In case of success (unsched = 0), mark events as committed,
1081 * so we do not put_constraint() in case new events are added
1082 * and fail to be scheduled
1084 * We invoke the lower level commit callback to lock the resource
1086 * We do not need to do all of this in case we are called to
1087 * validate an event group (assign == NULL)
1089 if (!unsched && assign) {
1090 for (i = 0; i < n; i++) {
1091 e = cpuc->event_list[i];
1092 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1095 for (i = n0; i < n; i++) {
1096 e = cpuc->event_list[i];
1099 * release events that failed scheduling
1101 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1103 cpuc->event_constraint[i] = NULL;
1107 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1109 return unsched ? -EINVAL : 0;
1112 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1113 struct perf_event *event)
1115 if (is_metric_event(event)) {
1116 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1119 cpuc->n_txn_metric++;
1125 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1126 struct perf_event *event)
1128 if (is_metric_event(event))
1132 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1133 int max_count, int n)
1135 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1137 if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1140 if (n >= max_count + cpuc->n_metric)
1143 cpuc->event_list[n] = event;
1144 if (is_counter_pair(&event->hw)) {
1153 * dogrp: true if must collect siblings events (group)
1154 * returns total number of events and error code
1156 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1158 int num_counters = hybrid(cpuc->pmu, num_counters);
1159 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1160 struct perf_event *event;
1163 max_count = num_counters + num_counters_fixed;
1165 /* current number of events already accepted */
1167 if (!cpuc->n_events)
1168 cpuc->pebs_output = 0;
1170 if (!cpuc->is_fake && leader->attr.precise_ip) {
1172 * For PEBS->PT, if !aux_event, the group leader (PT) went
1173 * away, the group was broken down and this singleton event
1174 * can't schedule any more.
1176 if (is_pebs_pt(leader) && !leader->aux_event)
1180 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1182 if (cpuc->pebs_output &&
1183 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1186 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1189 if (is_x86_event(leader)) {
1190 if (collect_event(cpuc, leader, max_count, n))
1198 for_each_sibling_event(event, leader) {
1199 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1202 if (collect_event(cpuc, event, max_count, n))
1210 static inline void x86_assign_hw_event(struct perf_event *event,
1211 struct cpu_hw_events *cpuc, int i)
1213 struct hw_perf_event *hwc = &event->hw;
1216 idx = hwc->idx = cpuc->assign[i];
1217 hwc->last_cpu = smp_processor_id();
1218 hwc->last_tag = ++cpuc->tags[i];
1221 case INTEL_PMC_IDX_FIXED_BTS:
1222 case INTEL_PMC_IDX_FIXED_VLBR:
1223 hwc->config_base = 0;
1224 hwc->event_base = 0;
1227 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1228 /* All the metric events are mapped onto the fixed counter 3. */
1229 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1231 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1232 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1233 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1234 (idx - INTEL_PMC_IDX_FIXED);
1235 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1236 INTEL_PMC_FIXED_RDPMC_BASE;
1240 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1241 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1242 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1248 * x86_perf_rdpmc_index - Return PMC counter used for event
1249 * @event: the perf_event to which the PMC counter was assigned
1251 * The counter assigned to this performance event may change if interrupts
1252 * are enabled. This counter should thus never be used while interrupts are
1253 * enabled. Before this function is used to obtain the assigned counter the
1254 * event should be checked for validity using, for example,
1255 * perf_event_read_local(), within the same interrupt disabled section in
1256 * which this counter is planned to be used.
1258 * Return: The index of the performance monitoring counter assigned to
1261 int x86_perf_rdpmc_index(struct perf_event *event)
1263 lockdep_assert_irqs_disabled();
1265 return event->hw.event_base_rdpmc;
1268 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1269 struct cpu_hw_events *cpuc,
1272 return hwc->idx == cpuc->assign[i] &&
1273 hwc->last_cpu == smp_processor_id() &&
1274 hwc->last_tag == cpuc->tags[i];
1277 static void x86_pmu_start(struct perf_event *event, int flags);
1279 static void x86_pmu_enable(struct pmu *pmu)
1281 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1282 struct perf_event *event;
1283 struct hw_perf_event *hwc;
1284 int i, added = cpuc->n_added;
1286 if (!x86_pmu_initialized())
1292 if (cpuc->n_added) {
1293 int n_running = cpuc->n_events - cpuc->n_added;
1295 * apply assignment obtained either from
1296 * hw_perf_group_sched_in() or x86_pmu_enable()
1298 * step1: save events moving to new counters
1300 for (i = 0; i < n_running; i++) {
1301 event = cpuc->event_list[i];
1305 * we can avoid reprogramming counter if:
1306 * - assigned same counter as last time
1307 * - running on same CPU as last time
1308 * - no other event has used the counter since
1310 if (hwc->idx == -1 ||
1311 match_prev_assignment(hwc, cpuc, i))
1315 * Ensure we don't accidentally enable a stopped
1316 * counter simply because we rescheduled.
1318 if (hwc->state & PERF_HES_STOPPED)
1319 hwc->state |= PERF_HES_ARCH;
1321 x86_pmu_stop(event, PERF_EF_UPDATE);
1325 * step2: reprogram moved events into new counters
1327 for (i = 0; i < cpuc->n_events; i++) {
1328 event = cpuc->event_list[i];
1331 if (!match_prev_assignment(hwc, cpuc, i))
1332 x86_assign_hw_event(event, cpuc, i);
1333 else if (i < n_running)
1336 if (hwc->state & PERF_HES_ARCH)
1339 x86_pmu_start(event, PERF_EF_RELOAD);
1342 perf_events_lapic_init();
1348 static_call(x86_pmu_enable_all)(added);
1351 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1354 * Set the next IRQ period, based on the hwc->period_left value.
1355 * To be called with the event disabled in hw:
1357 int x86_perf_event_set_period(struct perf_event *event)
1359 struct hw_perf_event *hwc = &event->hw;
1360 s64 left = local64_read(&hwc->period_left);
1361 s64 period = hwc->sample_period;
1362 int ret = 0, idx = hwc->idx;
1364 if (unlikely(!hwc->event_base))
1367 if (unlikely(is_topdown_count(event)) &&
1368 x86_pmu.set_topdown_event_period)
1369 return x86_pmu.set_topdown_event_period(event);
1372 * If we are way outside a reasonable range then just skip forward:
1374 if (unlikely(left <= -period)) {
1376 local64_set(&hwc->period_left, left);
1377 hwc->last_period = period;
1381 if (unlikely(left <= 0)) {
1383 local64_set(&hwc->period_left, left);
1384 hwc->last_period = period;
1388 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1390 if (unlikely(left < 2))
1393 if (left > x86_pmu.max_period)
1394 left = x86_pmu.max_period;
1396 if (x86_pmu.limit_period)
1397 left = x86_pmu.limit_period(event, left);
1399 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1402 * The hw event starts counting from this event offset,
1403 * mark it to be able to extra future deltas:
1405 local64_set(&hwc->prev_count, (u64)-left);
1407 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1410 * Sign extend the Merge event counter's upper 16 bits since
1411 * we currently declare a 48-bit counter width
1413 if (is_counter_pair(hwc))
1414 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1417 * Due to erratum on certan cpu we need
1418 * a second write to be sure the register
1419 * is updated properly
1421 if (x86_pmu.perfctr_second_write) {
1422 wrmsrl(hwc->event_base,
1423 (u64)(-left) & x86_pmu.cntval_mask);
1426 perf_event_update_userpage(event);
1431 void x86_pmu_enable_event(struct perf_event *event)
1433 if (__this_cpu_read(cpu_hw_events.enabled))
1434 __x86_pmu_enable_event(&event->hw,
1435 ARCH_PERFMON_EVENTSEL_ENABLE);
1439 * Add a single event to the PMU.
1441 * The event is added to the group of enabled events
1442 * but only if it can be scheduled with existing events.
1444 static int x86_pmu_add(struct perf_event *event, int flags)
1446 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1447 struct hw_perf_event *hwc;
1448 int assign[X86_PMC_IDX_MAX];
1453 n0 = cpuc->n_events;
1454 ret = n = collect_events(cpuc, event, false);
1458 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1459 if (!(flags & PERF_EF_START))
1460 hwc->state |= PERF_HES_ARCH;
1463 * If group events scheduling transaction was started,
1464 * skip the schedulability test here, it will be performed
1465 * at commit time (->commit_txn) as a whole.
1467 * If commit fails, we'll call ->del() on all events
1468 * for which ->add() was called.
1470 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1473 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1477 * copy new assignment, now we know it is possible
1478 * will be used by hw_perf_enable()
1480 memcpy(cpuc->assign, assign, n*sizeof(int));
1484 * Commit the collect_events() state. See x86_pmu_del() and
1488 cpuc->n_added += n - n0;
1489 cpuc->n_txn += n - n0;
1492 * This is before x86_pmu_enable() will call x86_pmu_start(),
1493 * so we enable LBRs before an event needs them etc..
1495 static_call_cond(x86_pmu_add)(event);
1502 static void x86_pmu_start(struct perf_event *event, int flags)
1504 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1505 int idx = event->hw.idx;
1507 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1510 if (WARN_ON_ONCE(idx == -1))
1513 if (flags & PERF_EF_RELOAD) {
1514 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1515 x86_perf_event_set_period(event);
1518 event->hw.state = 0;
1520 cpuc->events[idx] = event;
1521 __set_bit(idx, cpuc->active_mask);
1522 static_call(x86_pmu_enable)(event);
1523 perf_event_update_userpage(event);
1526 void perf_event_print_debug(void)
1528 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1530 int cpu = smp_processor_id();
1531 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1532 int num_counters = hybrid(cpuc->pmu, num_counters);
1533 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1534 struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1535 unsigned long flags;
1541 local_irq_save(flags);
1543 if (x86_pmu.version >= 2) {
1544 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1545 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1546 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1547 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1550 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1551 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1552 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1553 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1554 if (pebs_constraints) {
1555 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1556 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1558 if (x86_pmu.lbr_nr) {
1559 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1560 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1563 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1565 for (idx = 0; idx < num_counters; idx++) {
1566 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1567 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1569 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1571 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1572 cpu, idx, pmc_ctrl);
1573 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1574 cpu, idx, pmc_count);
1575 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1576 cpu, idx, prev_left);
1578 for (idx = 0; idx < num_counters_fixed; idx++) {
1579 if (fixed_counter_disabled(idx, cpuc->pmu))
1581 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1583 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1584 cpu, idx, pmc_count);
1586 local_irq_restore(flags);
1589 void x86_pmu_stop(struct perf_event *event, int flags)
1591 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1592 struct hw_perf_event *hwc = &event->hw;
1594 if (test_bit(hwc->idx, cpuc->active_mask)) {
1595 static_call(x86_pmu_disable)(event);
1596 __clear_bit(hwc->idx, cpuc->active_mask);
1597 cpuc->events[hwc->idx] = NULL;
1598 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1599 hwc->state |= PERF_HES_STOPPED;
1602 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1604 * Drain the remaining delta count out of a event
1605 * that we are disabling:
1607 x86_perf_event_update(event);
1608 hwc->state |= PERF_HES_UPTODATE;
1612 static void x86_pmu_del(struct perf_event *event, int flags)
1614 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1615 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1619 * If we're called during a txn, we only need to undo x86_pmu.add.
1620 * The events never got scheduled and ->cancel_txn will truncate
1623 * XXX assumes any ->del() called during a TXN will only be on
1624 * an event added during that same TXN.
1626 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1629 __set_bit(event->hw.idx, cpuc->dirty);
1632 * Not a TXN, therefore cleanup properly.
1634 x86_pmu_stop(event, PERF_EF_UPDATE);
1636 for (i = 0; i < cpuc->n_events; i++) {
1637 if (event == cpuc->event_list[i])
1641 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1644 /* If we have a newly added event; make sure to decrease n_added. */
1645 if (i >= cpuc->n_events - cpuc->n_added)
1648 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1650 /* Delete the array entry. */
1651 while (++i < cpuc->n_events) {
1652 cpuc->event_list[i-1] = cpuc->event_list[i];
1653 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1655 cpuc->event_constraint[i-1] = NULL;
1657 if (intel_cap.perf_metrics)
1658 del_nr_metric_event(cpuc, event);
1660 perf_event_update_userpage(event);
1665 * This is after x86_pmu_stop(); so we disable LBRs after any
1666 * event can need them etc..
1668 static_call_cond(x86_pmu_del)(event);
1671 int x86_pmu_handle_irq(struct pt_regs *regs)
1673 struct perf_sample_data data;
1674 struct cpu_hw_events *cpuc;
1675 struct perf_event *event;
1676 int idx, handled = 0;
1679 cpuc = this_cpu_ptr(&cpu_hw_events);
1682 * Some chipsets need to unmask the LVTPC in a particular spot
1683 * inside the nmi handler. As a result, the unmasking was pushed
1684 * into all the nmi handlers.
1686 * This generic handler doesn't seem to have any issues where the
1687 * unmasking occurs so it was left at the top.
1689 apic_write(APIC_LVTPC, APIC_DM_NMI);
1691 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1692 if (!test_bit(idx, cpuc->active_mask))
1695 event = cpuc->events[idx];
1697 val = x86_perf_event_update(event);
1698 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1705 perf_sample_data_init(&data, 0, event->hw.last_period);
1707 if (!x86_perf_event_set_period(event))
1710 if (perf_event_overflow(event, &data, regs))
1711 x86_pmu_stop(event, 0);
1715 inc_irq_stat(apic_perf_irqs);
1720 void perf_events_lapic_init(void)
1722 if (!x86_pmu.apic || !x86_pmu_initialized())
1726 * Always use NMI for PMU
1728 apic_write(APIC_LVTPC, APIC_DM_NMI);
1732 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1739 * All PMUs/events that share this PMI handler should make sure to
1740 * increment active_events for their events.
1742 if (!atomic_read(&active_events))
1745 start_clock = sched_clock();
1746 ret = static_call(x86_pmu_handle_irq)(regs);
1747 finish_clock = sched_clock();
1749 perf_sample_event_took(finish_clock - start_clock);
1753 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1755 struct event_constraint emptyconstraint;
1756 struct event_constraint unconstrained;
1758 static int x86_pmu_prepare_cpu(unsigned int cpu)
1760 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1763 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1764 cpuc->kfree_on_online[i] = NULL;
1765 if (x86_pmu.cpu_prepare)
1766 return x86_pmu.cpu_prepare(cpu);
1770 static int x86_pmu_dead_cpu(unsigned int cpu)
1772 if (x86_pmu.cpu_dead)
1773 x86_pmu.cpu_dead(cpu);
1777 static int x86_pmu_online_cpu(unsigned int cpu)
1779 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1782 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1783 kfree(cpuc->kfree_on_online[i]);
1784 cpuc->kfree_on_online[i] = NULL;
1789 static int x86_pmu_starting_cpu(unsigned int cpu)
1791 if (x86_pmu.cpu_starting)
1792 x86_pmu.cpu_starting(cpu);
1796 static int x86_pmu_dying_cpu(unsigned int cpu)
1798 if (x86_pmu.cpu_dying)
1799 x86_pmu.cpu_dying(cpu);
1803 static void __init pmu_check_apic(void)
1805 if (boot_cpu_has(X86_FEATURE_APIC))
1809 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1810 pr_info("no hardware sampling interrupt available.\n");
1813 * If we have a PMU initialized but no APIC
1814 * interrupts, we cannot sample hardware
1815 * events (user-space has to fall back and
1816 * sample via a hrtimer based software event):
1818 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1822 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1827 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1829 struct perf_pmu_events_attr *pmu_attr =
1830 container_of(attr, struct perf_pmu_events_attr, attr);
1833 if (pmu_attr->id < x86_pmu.max_events)
1834 config = x86_pmu.event_map(pmu_attr->id);
1836 /* string trumps id */
1837 if (pmu_attr->event_str)
1838 return sprintf(page, "%s", pmu_attr->event_str);
1840 return x86_pmu.events_sysfs_show(page, config);
1842 EXPORT_SYMBOL_GPL(events_sysfs_show);
1844 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1847 struct perf_pmu_events_ht_attr *pmu_attr =
1848 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1851 * Report conditional events depending on Hyper-Threading.
1853 * This is overly conservative as usually the HT special
1854 * handling is not needed if the other CPU thread is idle.
1856 * Note this does not (and cannot) handle the case when thread
1857 * siblings are invisible, for example with virtualization
1858 * if they are owned by some other guest. The user tool
1859 * has to re-read when a thread sibling gets onlined later.
1861 return sprintf(page, "%s",
1862 topology_max_smt_threads() > 1 ?
1863 pmu_attr->event_str_ht :
1864 pmu_attr->event_str_noht);
1867 ssize_t events_hybrid_sysfs_show(struct device *dev,
1868 struct device_attribute *attr,
1871 struct perf_pmu_events_hybrid_attr *pmu_attr =
1872 container_of(attr, struct perf_pmu_events_hybrid_attr, attr);
1873 struct x86_hybrid_pmu *pmu;
1874 const char *str, *next_str;
1877 if (hweight64(pmu_attr->pmu_type) == 1)
1878 return sprintf(page, "%s", pmu_attr->event_str);
1881 * Hybrid PMUs may support the same event name, but with different
1882 * event encoding, e.g., the mem-loads event on an Atom PMU has
1883 * different event encoding from a Core PMU.
1885 * The event_str includes all event encodings. Each event encoding
1886 * is divided by ";". The order of the event encodings must follow
1887 * the order of the hybrid PMU index.
1889 pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
1891 str = pmu_attr->event_str;
1892 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
1893 if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type))
1895 if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) {
1896 next_str = strchr(str, ';');
1898 return snprintf(page, next_str - str + 1, "%s", str);
1900 return sprintf(page, "%s", str);
1902 str = strchr(str, ';');
1908 EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show);
1910 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1911 EVENT_ATTR(instructions, INSTRUCTIONS );
1912 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1913 EVENT_ATTR(cache-misses, CACHE_MISSES );
1914 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1915 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1916 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1917 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1918 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1919 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1921 static struct attribute *empty_attrs;
1923 static struct attribute *events_attr[] = {
1924 EVENT_PTR(CPU_CYCLES),
1925 EVENT_PTR(INSTRUCTIONS),
1926 EVENT_PTR(CACHE_REFERENCES),
1927 EVENT_PTR(CACHE_MISSES),
1928 EVENT_PTR(BRANCH_INSTRUCTIONS),
1929 EVENT_PTR(BRANCH_MISSES),
1930 EVENT_PTR(BUS_CYCLES),
1931 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1932 EVENT_PTR(STALLED_CYCLES_BACKEND),
1933 EVENT_PTR(REF_CPU_CYCLES),
1938 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1939 * out of events_attr attributes.
1942 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1944 struct perf_pmu_events_attr *pmu_attr;
1946 if (idx >= x86_pmu.max_events)
1949 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1951 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1954 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1956 .attrs = events_attr,
1957 .is_visible = is_visible,
1960 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1962 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1963 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1964 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1965 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1966 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1967 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1971 * We have whole page size to spend and just little data
1972 * to write, so we can safely use sprintf.
1974 ret = sprintf(page, "event=0x%02llx", event);
1977 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1980 ret += sprintf(page + ret, ",edge");
1983 ret += sprintf(page + ret, ",pc");
1986 ret += sprintf(page + ret, ",any");
1989 ret += sprintf(page + ret, ",inv");
1992 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1994 ret += sprintf(page + ret, "\n");
1999 static struct attribute_group x86_pmu_attr_group;
2000 static struct attribute_group x86_pmu_caps_group;
2002 static void x86_pmu_static_call_update(void)
2004 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
2005 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
2006 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
2007 static_call_update(x86_pmu_enable, x86_pmu.enable);
2008 static_call_update(x86_pmu_disable, x86_pmu.disable);
2010 static_call_update(x86_pmu_add, x86_pmu.add);
2011 static_call_update(x86_pmu_del, x86_pmu.del);
2012 static_call_update(x86_pmu_read, x86_pmu.read);
2014 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
2015 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
2016 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
2018 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
2019 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
2020 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
2022 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
2023 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
2025 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
2026 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
2028 static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
2031 static void _x86_pmu_read(struct perf_event *event)
2033 x86_perf_event_update(event);
2036 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2039 pr_info("... version: %d\n", x86_pmu.version);
2040 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2041 pr_info("... generic registers: %d\n", num_counters);
2042 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2043 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2044 pr_info("... fixed-purpose events: %lu\n",
2045 hweight64((((1ULL << num_counters_fixed) - 1)
2046 << INTEL_PMC_IDX_FIXED) & intel_ctrl));
2047 pr_info("... event mask: %016Lx\n", intel_ctrl);
2051 * The generic code is not hybrid friendly. The hybrid_pmu->pmu
2052 * of the first registered PMU is unconditionally assigned to
2053 * each possible cpuctx->ctx.pmu.
2054 * Update the correct hybrid PMU to the cpuctx->ctx.pmu.
2056 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu)
2058 struct perf_cpu_context *cpuctx;
2060 if (!pmu->pmu_cpu_context)
2063 cpuctx = per_cpu_ptr(pmu->pmu_cpu_context, cpu);
2064 cpuctx->ctx.pmu = pmu;
2067 static int __init init_hw_perf_events(void)
2069 struct x86_pmu_quirk *quirk;
2072 pr_info("Performance Events: ");
2074 switch (boot_cpu_data.x86_vendor) {
2075 case X86_VENDOR_INTEL:
2076 err = intel_pmu_init();
2078 case X86_VENDOR_AMD:
2079 err = amd_pmu_init();
2081 case X86_VENDOR_HYGON:
2082 err = amd_pmu_init();
2083 x86_pmu.name = "HYGON";
2085 case X86_VENDOR_ZHAOXIN:
2086 case X86_VENDOR_CENTAUR:
2087 err = zhaoxin_pmu_init();
2093 pr_cont("no PMU driver, software events only.\n");
2099 /* sanity check that the hardware exists or is emulated */
2100 if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2103 pr_cont("%s PMU driver.\n", x86_pmu.name);
2105 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2107 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2110 if (!x86_pmu.intel_ctrl)
2111 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2113 perf_events_lapic_init();
2114 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2116 unconstrained = (struct event_constraint)
2117 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2118 0, x86_pmu.num_counters, 0, 0);
2120 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2122 if (!x86_pmu.events_sysfs_show)
2123 x86_pmu_events_group.attrs = &empty_attrs;
2125 pmu.attr_update = x86_pmu.attr_update;
2128 x86_pmu_show_pmu_cap(x86_pmu.num_counters,
2129 x86_pmu.num_counters_fixed,
2130 x86_pmu.intel_ctrl);
2134 x86_pmu.read = _x86_pmu_read;
2136 if (!x86_pmu.guest_get_msrs)
2137 x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2139 x86_pmu_static_call_update();
2142 * Install callbacks. Core will call them for each online
2145 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2146 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2150 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2151 "perf/x86:starting", x86_pmu_starting_cpu,
2156 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2157 x86_pmu_online_cpu, NULL);
2162 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2166 u8 cpu_type = get_this_hybrid_cpu_type();
2167 struct x86_hybrid_pmu *hybrid_pmu;
2170 if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
2171 cpu_type = x86_pmu.get_hybrid_cpu_type();
2173 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
2174 hybrid_pmu = &x86_pmu.hybrid_pmu[i];
2176 hybrid_pmu->pmu = pmu;
2177 hybrid_pmu->pmu.type = -1;
2178 hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
2179 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
2180 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;
2182 err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,
2183 (hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
2187 if (cpu_type == hybrid_pmu->cpu_type)
2188 x86_pmu_update_cpu_context(&hybrid_pmu->pmu, raw_smp_processor_id());
2191 if (i < x86_pmu.num_hybrid_pmus) {
2192 for (j = 0; j < i; j++)
2193 perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu);
2194 pr_warn("Failed to register hybrid PMUs\n");
2195 kfree(x86_pmu.hybrid_pmu);
2196 x86_pmu.hybrid_pmu = NULL;
2197 x86_pmu.num_hybrid_pmus = 0;
2205 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2207 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2209 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2212 early_initcall(init_hw_perf_events);
2214 static void x86_pmu_read(struct perf_event *event)
2216 static_call(x86_pmu_read)(event);
2220 * Start group events scheduling transaction
2221 * Set the flag to make pmu::enable() not perform the
2222 * schedulability test, it will be performed at commit time
2224 * We only support PERF_PMU_TXN_ADD transactions. Save the
2225 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2228 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2230 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2232 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2234 cpuc->txn_flags = txn_flags;
2235 if (txn_flags & ~PERF_PMU_TXN_ADD)
2238 perf_pmu_disable(pmu);
2239 __this_cpu_write(cpu_hw_events.n_txn, 0);
2240 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2241 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2245 * Stop group events scheduling transaction
2246 * Clear the flag and pmu::enable() will perform the
2247 * schedulability test.
2249 static void x86_pmu_cancel_txn(struct pmu *pmu)
2251 unsigned int txn_flags;
2252 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2254 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2256 txn_flags = cpuc->txn_flags;
2257 cpuc->txn_flags = 0;
2258 if (txn_flags & ~PERF_PMU_TXN_ADD)
2262 * Truncate collected array by the number of events added in this
2263 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2265 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2266 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2267 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2268 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2269 perf_pmu_enable(pmu);
2273 * Commit group events scheduling transaction
2274 * Perform the group schedulability test as a whole
2275 * Return 0 if success
2277 * Does not cancel the transaction on failure; expects the caller to do this.
2279 static int x86_pmu_commit_txn(struct pmu *pmu)
2281 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2282 int assign[X86_PMC_IDX_MAX];
2285 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2287 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2288 cpuc->txn_flags = 0;
2294 if (!x86_pmu_initialized())
2297 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2302 * copy new assignment, now we know it is possible
2303 * will be used by hw_perf_enable()
2305 memcpy(cpuc->assign, assign, n*sizeof(int));
2307 cpuc->txn_flags = 0;
2308 perf_pmu_enable(pmu);
2312 * a fake_cpuc is used to validate event groups. Due to
2313 * the extra reg logic, we need to also allocate a fake
2314 * per_core and per_cpu structure. Otherwise, group events
2315 * using extra reg may conflict without the kernel being
2316 * able to catch this when the last event gets added to
2319 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2321 intel_cpuc_finish(cpuc);
2325 static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu)
2327 struct cpu_hw_events *cpuc;
2330 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2332 return ERR_PTR(-ENOMEM);
2336 struct x86_hybrid_pmu *h_pmu;
2338 h_pmu = hybrid_pmu(event_pmu);
2339 if (cpumask_empty(&h_pmu->supported_cpus))
2341 cpu = cpumask_first(&h_pmu->supported_cpus);
2343 cpu = raw_smp_processor_id();
2344 cpuc->pmu = event_pmu;
2346 if (intel_cpuc_prepare(cpuc, cpu))
2351 free_fake_cpuc(cpuc);
2352 return ERR_PTR(-ENOMEM);
2356 * validate that we can schedule this event
2358 static int validate_event(struct perf_event *event)
2360 struct cpu_hw_events *fake_cpuc;
2361 struct event_constraint *c;
2364 fake_cpuc = allocate_fake_cpuc(event->pmu);
2365 if (IS_ERR(fake_cpuc))
2366 return PTR_ERR(fake_cpuc);
2368 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2370 if (!c || !c->weight)
2373 if (x86_pmu.put_event_constraints)
2374 x86_pmu.put_event_constraints(fake_cpuc, event);
2376 free_fake_cpuc(fake_cpuc);
2382 * validate a single event group
2384 * validation include:
2385 * - check events are compatible which each other
2386 * - events do not compete for the same counter
2387 * - number of events <= number of counters
2389 * validation ensures the group can be loaded onto the
2390 * PMU if it was the only group available.
2392 static int validate_group(struct perf_event *event)
2394 struct perf_event *leader = event->group_leader;
2395 struct cpu_hw_events *fake_cpuc;
2396 int ret = -EINVAL, n;
2399 * Reject events from different hybrid PMUs.
2402 struct perf_event *sibling;
2403 struct pmu *pmu = NULL;
2405 if (is_x86_event(leader))
2408 for_each_sibling_event(sibling, leader) {
2409 if (!is_x86_event(sibling))
2413 else if (pmu != sibling->pmu)
2418 fake_cpuc = allocate_fake_cpuc(event->pmu);
2419 if (IS_ERR(fake_cpuc))
2420 return PTR_ERR(fake_cpuc);
2422 * the event is not yet connected with its
2423 * siblings therefore we must first collect
2424 * existing siblings, then add the new event
2425 * before we can simulate the scheduling
2427 n = collect_events(fake_cpuc, leader, true);
2431 fake_cpuc->n_events = n;
2432 n = collect_events(fake_cpuc, event, false);
2436 fake_cpuc->n_events = 0;
2437 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2440 free_fake_cpuc(fake_cpuc);
2444 static int x86_pmu_event_init(struct perf_event *event)
2446 struct x86_hybrid_pmu *pmu = NULL;
2449 if ((event->attr.type != event->pmu->type) &&
2450 (event->attr.type != PERF_TYPE_HARDWARE) &&
2451 (event->attr.type != PERF_TYPE_HW_CACHE))
2454 if (is_hybrid() && (event->cpu != -1)) {
2455 pmu = hybrid_pmu(event->pmu);
2456 if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus))
2460 err = __x86_pmu_event_init(event);
2462 if (event->group_leader != event)
2463 err = validate_group(event);
2465 err = validate_event(event);
2469 event->destroy(event);
2472 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2473 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2474 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2479 void perf_clear_dirty_counters(void)
2481 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2484 /* Don't need to clear the assigned counter. */
2485 for (i = 0; i < cpuc->n_events; i++)
2486 __clear_bit(cpuc->assign[i], cpuc->dirty);
2488 if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX))
2491 for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {
2492 if (i >= INTEL_PMC_IDX_FIXED) {
2493 /* Metrics and fake events don't have corresponding HW counters. */
2494 if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed))
2497 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0);
2499 wrmsrl(x86_pmu_event_addr(i), 0);
2503 bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX);
2506 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2508 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2512 * This function relies on not being called concurrently in two
2513 * tasks in the same mm. Otherwise one task could observe
2514 * perf_rdpmc_allowed > 1 and return all the way back to
2515 * userspace with CR4.PCE clear while another task is still
2516 * doing on_each_cpu_mask() to propagate CR4.PCE.
2518 * For now, this can't happen because all callers hold mmap_lock
2519 * for write. If this changes, we'll need a different solution.
2521 mmap_assert_write_locked(mm);
2523 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2524 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2527 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2529 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2532 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2533 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2536 static int x86_pmu_event_idx(struct perf_event *event)
2538 struct hw_perf_event *hwc = &event->hw;
2540 if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2543 if (is_metric_idx(hwc->idx))
2544 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2546 return hwc->event_base_rdpmc + 1;
2549 static ssize_t get_attr_rdpmc(struct device *cdev,
2550 struct device_attribute *attr,
2553 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2556 static ssize_t set_attr_rdpmc(struct device *cdev,
2557 struct device_attribute *attr,
2558 const char *buf, size_t count)
2563 ret = kstrtoul(buf, 0, &val);
2570 if (x86_pmu.attr_rdpmc_broken)
2573 if (val != x86_pmu.attr_rdpmc) {
2575 * Changing into or out of never available or always available,
2576 * aka perf-event-bypassing mode. This path is extremely slow,
2577 * but only root can trigger it, so it's okay.
2580 static_branch_inc(&rdpmc_never_available_key);
2581 else if (x86_pmu.attr_rdpmc == 0)
2582 static_branch_dec(&rdpmc_never_available_key);
2585 static_branch_inc(&rdpmc_always_available_key);
2586 else if (x86_pmu.attr_rdpmc == 2)
2587 static_branch_dec(&rdpmc_always_available_key);
2589 on_each_cpu(cr4_update_pce, NULL, 1);
2590 x86_pmu.attr_rdpmc = val;
2596 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2598 static struct attribute *x86_pmu_attrs[] = {
2599 &dev_attr_rdpmc.attr,
2603 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2604 .attrs = x86_pmu_attrs,
2607 static ssize_t max_precise_show(struct device *cdev,
2608 struct device_attribute *attr,
2611 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2614 static DEVICE_ATTR_RO(max_precise);
2616 static struct attribute *x86_pmu_caps_attrs[] = {
2617 &dev_attr_max_precise.attr,
2621 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2623 .attrs = x86_pmu_caps_attrs,
2626 static const struct attribute_group *x86_pmu_attr_groups[] = {
2627 &x86_pmu_attr_group,
2628 &x86_pmu_format_group,
2629 &x86_pmu_events_group,
2630 &x86_pmu_caps_group,
2634 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2636 static_call_cond(x86_pmu_sched_task)(ctx, sched_in);
2639 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2640 struct perf_event_context *next)
2642 static_call_cond(x86_pmu_swap_task_ctx)(prev, next);
2645 void perf_check_microcode(void)
2647 if (x86_pmu.check_microcode)
2648 x86_pmu.check_microcode();
2651 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2653 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2656 if (value && x86_pmu.limit_period) {
2657 if (x86_pmu.limit_period(event, value) > value)
2664 static int x86_pmu_aux_output_match(struct perf_event *event)
2666 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2669 if (x86_pmu.aux_output_match)
2670 return x86_pmu.aux_output_match(event);
2675 static int x86_pmu_filter_match(struct perf_event *event)
2677 if (x86_pmu.filter_match)
2678 return x86_pmu.filter_match(event);
2683 static struct pmu pmu = {
2684 .pmu_enable = x86_pmu_enable,
2685 .pmu_disable = x86_pmu_disable,
2687 .attr_groups = x86_pmu_attr_groups,
2689 .event_init = x86_pmu_event_init,
2691 .event_mapped = x86_pmu_event_mapped,
2692 .event_unmapped = x86_pmu_event_unmapped,
2696 .start = x86_pmu_start,
2697 .stop = x86_pmu_stop,
2698 .read = x86_pmu_read,
2700 .start_txn = x86_pmu_start_txn,
2701 .cancel_txn = x86_pmu_cancel_txn,
2702 .commit_txn = x86_pmu_commit_txn,
2704 .event_idx = x86_pmu_event_idx,
2705 .sched_task = x86_pmu_sched_task,
2706 .swap_task_ctx = x86_pmu_swap_task_ctx,
2707 .check_period = x86_pmu_check_period,
2709 .aux_output_match = x86_pmu_aux_output_match,
2711 .filter_match = x86_pmu_filter_match,
2714 void arch_perf_update_userpage(struct perf_event *event,
2715 struct perf_event_mmap_page *userpg, u64 now)
2717 struct cyc2ns_data data;
2720 userpg->cap_user_time = 0;
2721 userpg->cap_user_time_zero = 0;
2722 userpg->cap_user_rdpmc =
2723 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2724 userpg->pmc_width = x86_pmu.cntval_bits;
2726 if (!using_native_sched_clock() || !sched_clock_stable())
2729 cyc2ns_read_begin(&data);
2731 offset = data.cyc2ns_offset + __sched_clock_offset;
2734 * Internal timekeeping for enabled/running/stopped times
2735 * is always in the local_clock domain.
2737 userpg->cap_user_time = 1;
2738 userpg->time_mult = data.cyc2ns_mul;
2739 userpg->time_shift = data.cyc2ns_shift;
2740 userpg->time_offset = offset - now;
2743 * cap_user_time_zero doesn't make sense when we're using a different
2744 * time base for the records.
2746 if (!event->attr.use_clockid) {
2747 userpg->cap_user_time_zero = 1;
2748 userpg->time_zero = offset;
2755 * Determine whether the regs were taken from an irq/exception handler rather
2756 * than from perf_arch_fetch_caller_regs().
2758 static bool perf_hw_regs(struct pt_regs *regs)
2760 return regs->flags & X86_EFLAGS_FIXED;
2764 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2766 struct unwind_state state;
2769 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2770 /* TODO: We don't support guest os callchain now */
2774 if (perf_callchain_store(entry, regs->ip))
2777 if (perf_hw_regs(regs))
2778 unwind_start(&state, current, regs, NULL);
2780 unwind_start(&state, current, NULL, (void *)regs->sp);
2782 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2783 addr = unwind_get_return_address(&state);
2784 if (!addr || perf_callchain_store(entry, addr))
2790 valid_user_frame(const void __user *fp, unsigned long size)
2792 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2795 static unsigned long get_segment_base(unsigned int segment)
2797 struct desc_struct *desc;
2798 unsigned int idx = segment >> 3;
2800 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2801 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2802 struct ldt_struct *ldt;
2804 /* IRQs are off, so this synchronizes with smp_store_release */
2805 ldt = READ_ONCE(current->active_mm->context.ldt);
2806 if (!ldt || idx >= ldt->nr_entries)
2809 desc = &ldt->entries[idx];
2814 if (idx >= GDT_ENTRIES)
2817 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2820 return get_desc_base(desc);
2823 #ifdef CONFIG_IA32_EMULATION
2825 #include <linux/compat.h>
2828 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2830 /* 32-bit process in 64-bit kernel. */
2831 unsigned long ss_base, cs_base;
2832 struct stack_frame_ia32 frame;
2833 const struct stack_frame_ia32 __user *fp;
2835 if (user_64bit_mode(regs))
2838 cs_base = get_segment_base(regs->cs);
2839 ss_base = get_segment_base(regs->ss);
2841 fp = compat_ptr(ss_base + regs->bp);
2842 pagefault_disable();
2843 while (entry->nr < entry->max_stack) {
2844 if (!valid_user_frame(fp, sizeof(frame)))
2847 if (__get_user(frame.next_frame, &fp->next_frame))
2849 if (__get_user(frame.return_address, &fp->return_address))
2852 perf_callchain_store(entry, cs_base + frame.return_address);
2853 fp = compat_ptr(ss_base + frame.next_frame);
2860 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2867 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2869 struct stack_frame frame;
2870 const struct stack_frame __user *fp;
2872 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2873 /* TODO: We don't support guest os callchain now */
2878 * We don't know what to do with VM86 stacks.. ignore them for now.
2880 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2883 fp = (void __user *)regs->bp;
2885 perf_callchain_store(entry, regs->ip);
2887 if (!nmi_uaccess_okay())
2890 if (perf_callchain_user32(regs, entry))
2893 pagefault_disable();
2894 while (entry->nr < entry->max_stack) {
2895 if (!valid_user_frame(fp, sizeof(frame)))
2898 if (__get_user(frame.next_frame, &fp->next_frame))
2900 if (__get_user(frame.return_address, &fp->return_address))
2903 perf_callchain_store(entry, frame.return_address);
2904 fp = (void __user *)frame.next_frame;
2910 * Deal with code segment offsets for the various execution modes:
2912 * VM86 - the good olde 16 bit days, where the linear address is
2913 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2915 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2916 * to figure out what the 32bit base address is.
2918 * X32 - has TIF_X32 set, but is running in x86_64
2920 * X86_64 - CS,DS,SS,ES are all zero based.
2922 static unsigned long code_segment_base(struct pt_regs *regs)
2925 * For IA32 we look at the GDT/LDT segment base to convert the
2926 * effective IP to a linear address.
2929 #ifdef CONFIG_X86_32
2931 * If we are in VM86 mode, add the segment offset to convert to a
2934 if (regs->flags & X86_VM_MASK)
2935 return 0x10 * regs->cs;
2937 if (user_mode(regs) && regs->cs != __USER_CS)
2938 return get_segment_base(regs->cs);
2940 if (user_mode(regs) && !user_64bit_mode(regs) &&
2941 regs->cs != __USER32_CS)
2942 return get_segment_base(regs->cs);
2947 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2949 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2950 return perf_guest_cbs->get_guest_ip();
2952 return regs->ip + code_segment_base(regs);
2955 unsigned long perf_misc_flags(struct pt_regs *regs)
2959 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2960 if (perf_guest_cbs->is_user_mode())
2961 misc |= PERF_RECORD_MISC_GUEST_USER;
2963 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2965 if (user_mode(regs))
2966 misc |= PERF_RECORD_MISC_USER;
2968 misc |= PERF_RECORD_MISC_KERNEL;
2971 if (regs->flags & PERF_EFLAGS_EXACT)
2972 misc |= PERF_RECORD_MISC_EXACT_IP;
2977 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2979 cap->version = x86_pmu.version;
2981 * KVM doesn't support the hybrid PMU yet.
2982 * Return the common value in global x86_pmu,
2983 * which available for all cores.
2985 cap->num_counters_gp = x86_pmu.num_counters;
2986 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2987 cap->bit_width_gp = x86_pmu.cntval_bits;
2988 cap->bit_width_fixed = x86_pmu.cntval_bits;
2989 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2990 cap->events_mask_len = x86_pmu.events_mask_len;
2992 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);