1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Advanced Micro Devices, Inc.
5 * Author: Jacob Shin <jacob.shin@amd.com>
8 #include <linux/perf_event.h>
9 #include <linux/percpu.h>
10 #include <linux/types.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13 #include <linux/cpu.h>
14 #include <linux/cpumask.h>
16 #include <asm/cpufeature.h>
17 #include <asm/perf_event.h>
21 #define NUM_COUNTERS_NB 4
22 #define NUM_COUNTERS_L2 4
23 #define NUM_COUNTERS_L3 6
24 #define MAX_COUNTERS 6
26 #define RDPMC_BASE_NB 6
27 #define RDPMC_BASE_LLC 10
29 #define COUNTER_SHIFT 16
32 #define pr_fmt(fmt) "amd_uncore: " fmt
34 static int num_counters_llc;
35 static int num_counters_nb;
38 static HLIST_HEAD(uncore_unused_list);
47 cpumask_t *active_mask;
49 struct perf_event *events[MAX_COUNTERS];
50 struct hlist_node node;
53 static struct amd_uncore * __percpu *amd_uncore_nb;
54 static struct amd_uncore * __percpu *amd_uncore_llc;
56 static struct pmu amd_nb_pmu;
57 static struct pmu amd_llc_pmu;
59 static cpumask_t amd_nb_active_mask;
60 static cpumask_t amd_llc_active_mask;
62 static bool is_nb_event(struct perf_event *event)
64 return event->pmu->type == amd_nb_pmu.type;
67 static bool is_llc_event(struct perf_event *event)
69 return event->pmu->type == amd_llc_pmu.type;
72 static struct amd_uncore *event_to_amd_uncore(struct perf_event *event)
74 if (is_nb_event(event) && amd_uncore_nb)
75 return *per_cpu_ptr(amd_uncore_nb, event->cpu);
76 else if (is_llc_event(event) && amd_uncore_llc)
77 return *per_cpu_ptr(amd_uncore_llc, event->cpu);
82 static void amd_uncore_read(struct perf_event *event)
84 struct hw_perf_event *hwc = &event->hw;
89 * since we do not enable counter overflow interrupts,
90 * we do not have to worry about prev_count changing on us
93 prev = local64_read(&hwc->prev_count);
94 rdpmcl(hwc->event_base_rdpmc, new);
95 local64_set(&hwc->prev_count, new);
96 delta = (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
97 delta >>= COUNTER_SHIFT;
98 local64_add(delta, &event->count);
101 static void amd_uncore_start(struct perf_event *event, int flags)
103 struct hw_perf_event *hwc = &event->hw;
105 if (flags & PERF_EF_RELOAD)
106 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count));
109 wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE));
110 perf_event_update_userpage(event);
113 static void amd_uncore_stop(struct perf_event *event, int flags)
115 struct hw_perf_event *hwc = &event->hw;
117 wrmsrl(hwc->config_base, hwc->config);
118 hwc->state |= PERF_HES_STOPPED;
120 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
121 amd_uncore_read(event);
122 hwc->state |= PERF_HES_UPTODATE;
126 static int amd_uncore_add(struct perf_event *event, int flags)
129 struct amd_uncore *uncore = event_to_amd_uncore(event);
130 struct hw_perf_event *hwc = &event->hw;
132 /* are we already assigned? */
133 if (hwc->idx != -1 && uncore->events[hwc->idx] == event)
136 for (i = 0; i < uncore->num_counters; i++) {
137 if (uncore->events[i] == event) {
143 /* if not, take the first available counter */
145 for (i = 0; i < uncore->num_counters; i++) {
146 if (cmpxchg(&uncore->events[i], NULL, event) == NULL) {
156 hwc->config_base = uncore->msr_base + (2 * hwc->idx);
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx);
158 hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx;
159 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
161 if (flags & PERF_EF_START)
162 amd_uncore_start(event, PERF_EF_RELOAD);
167 static void amd_uncore_del(struct perf_event *event, int flags)
170 struct amd_uncore *uncore = event_to_amd_uncore(event);
171 struct hw_perf_event *hwc = &event->hw;
173 amd_uncore_stop(event, PERF_EF_UPDATE);
175 for (i = 0; i < uncore->num_counters; i++) {
176 if (cmpxchg(&uncore->events[i], event, NULL) == event)
184 * Return a full thread and slice mask until per-CPU is
185 * properly supported.
187 static u64 l3_thread_slice_mask(void)
189 if (boot_cpu_data.x86 <= 0x18)
190 return AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK;
192 return AMD64_L3_EN_ALL_SLICES | AMD64_L3_EN_ALL_CORES |
193 AMD64_L3_F19H_THREAD_MASK;
196 static int amd_uncore_event_init(struct perf_event *event)
198 struct amd_uncore *uncore;
199 struct hw_perf_event *hwc = &event->hw;
201 if (event->attr.type != event->pmu->type)
205 * NB and Last level cache counters (MSRs) are shared across all cores
206 * that share the same NB / Last level cache. On family 16h and below,
207 * Interrupts can be directed to a single target core, however, event
208 * counts generated by processes running on other cores cannot be masked
209 * out. So we do not support sampling and per-thread events via
210 * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
212 hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
219 * SliceMask and ThreadMask need to be set for certain L3 events.
220 * For other events, the two fields do not affect the count.
222 if (l3_mask && is_llc_event(event))
223 hwc->config |= l3_thread_slice_mask();
225 uncore = event_to_amd_uncore(event);
230 * since request can come in to any of the shared cores, we will remap
231 * to a single common cpu.
233 event->cpu = uncore->cpu;
238 static ssize_t amd_uncore_attr_show_cpumask(struct device *dev,
239 struct device_attribute *attr,
242 cpumask_t *active_mask;
243 struct pmu *pmu = dev_get_drvdata(dev);
245 if (pmu->type == amd_nb_pmu.type)
246 active_mask = &amd_nb_active_mask;
247 else if (pmu->type == amd_llc_pmu.type)
248 active_mask = &amd_llc_active_mask;
252 return cpumap_print_to_pagebuf(true, buf, active_mask);
254 static DEVICE_ATTR(cpumask, S_IRUGO, amd_uncore_attr_show_cpumask, NULL);
256 static struct attribute *amd_uncore_attrs[] = {
257 &dev_attr_cpumask.attr,
261 static struct attribute_group amd_uncore_attr_group = {
262 .attrs = amd_uncore_attrs,
265 #define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
266 static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
267 struct kobj_attribute *attr, \
270 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
271 return sprintf(page, _format "\n"); \
273 static struct kobj_attribute format_attr_##_var = \
274 __ATTR(_name, 0444, __uncore_##_var##_show, NULL)
276 DEFINE_UNCORE_FORMAT_ATTR(event12, event, "config:0-7,32-35");
277 DEFINE_UNCORE_FORMAT_ATTR(event14, event, "config:0-7,32-35,59-60"); /* F17h+ DF */
278 DEFINE_UNCORE_FORMAT_ATTR(event8, event, "config:0-7"); /* F17h+ L3 */
279 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
281 static struct attribute *amd_uncore_df_format_attr[] = {
282 &format_attr_event12.attr, /* event14 if F17h+ */
283 &format_attr_umask.attr,
287 static struct attribute *amd_uncore_l3_format_attr[] = {
288 &format_attr_event12.attr, /* event8 if F17h+ */
289 &format_attr_umask.attr,
293 static struct attribute_group amd_uncore_df_format_group = {
295 .attrs = amd_uncore_df_format_attr,
298 static struct attribute_group amd_uncore_l3_format_group = {
300 .attrs = amd_uncore_l3_format_attr,
303 static const struct attribute_group *amd_uncore_df_attr_groups[] = {
304 &amd_uncore_attr_group,
305 &amd_uncore_df_format_group,
309 static const struct attribute_group *amd_uncore_l3_attr_groups[] = {
310 &amd_uncore_attr_group,
311 &amd_uncore_l3_format_group,
315 static struct pmu amd_nb_pmu = {
316 .task_ctx_nr = perf_invalid_context,
317 .attr_groups = amd_uncore_df_attr_groups,
319 .event_init = amd_uncore_event_init,
320 .add = amd_uncore_add,
321 .del = amd_uncore_del,
322 .start = amd_uncore_start,
323 .stop = amd_uncore_stop,
324 .read = amd_uncore_read,
325 .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
328 static struct pmu amd_llc_pmu = {
329 .task_ctx_nr = perf_invalid_context,
330 .attr_groups = amd_uncore_l3_attr_groups,
332 .event_init = amd_uncore_event_init,
333 .add = amd_uncore_add,
334 .del = amd_uncore_del,
335 .start = amd_uncore_start,
336 .stop = amd_uncore_stop,
337 .read = amd_uncore_read,
338 .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
341 static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
343 return kzalloc_node(sizeof(struct amd_uncore), GFP_KERNEL,
347 static int amd_uncore_cpu_up_prepare(unsigned int cpu)
349 struct amd_uncore *uncore_nb = NULL, *uncore_llc;
352 uncore_nb = amd_uncore_alloc(cpu);
355 uncore_nb->cpu = cpu;
356 uncore_nb->num_counters = num_counters_nb;
357 uncore_nb->rdpmc_base = RDPMC_BASE_NB;
358 uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL;
359 uncore_nb->active_mask = &amd_nb_active_mask;
360 uncore_nb->pmu = &amd_nb_pmu;
362 *per_cpu_ptr(amd_uncore_nb, cpu) = uncore_nb;
365 if (amd_uncore_llc) {
366 uncore_llc = amd_uncore_alloc(cpu);
369 uncore_llc->cpu = cpu;
370 uncore_llc->num_counters = num_counters_llc;
371 uncore_llc->rdpmc_base = RDPMC_BASE_LLC;
372 uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL;
373 uncore_llc->active_mask = &amd_llc_active_mask;
374 uncore_llc->pmu = &amd_llc_pmu;
376 *per_cpu_ptr(amd_uncore_llc, cpu) = uncore_llc;
383 *per_cpu_ptr(amd_uncore_nb, cpu) = NULL;
388 static struct amd_uncore *
389 amd_uncore_find_online_sibling(struct amd_uncore *this,
390 struct amd_uncore * __percpu *uncores)
393 struct amd_uncore *that;
395 for_each_online_cpu(cpu) {
396 that = *per_cpu_ptr(uncores, cpu);
404 if (this->id == that->id) {
405 hlist_add_head(&this->node, &uncore_unused_list);
415 static int amd_uncore_cpu_starting(unsigned int cpu)
417 unsigned int eax, ebx, ecx, edx;
418 struct amd_uncore *uncore;
421 uncore = *per_cpu_ptr(amd_uncore_nb, cpu);
422 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
423 uncore->id = ecx & 0xff;
425 uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_nb);
426 *per_cpu_ptr(amd_uncore_nb, cpu) = uncore;
429 if (amd_uncore_llc) {
430 uncore = *per_cpu_ptr(amd_uncore_llc, cpu);
431 uncore->id = per_cpu(cpu_llc_id, cpu);
433 uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc);
434 *per_cpu_ptr(amd_uncore_llc, cpu) = uncore;
440 static void uncore_clean_online(void)
442 struct amd_uncore *uncore;
443 struct hlist_node *n;
445 hlist_for_each_entry_safe(uncore, n, &uncore_unused_list, node) {
446 hlist_del(&uncore->node);
451 static void uncore_online(unsigned int cpu,
452 struct amd_uncore * __percpu *uncores)
454 struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu);
456 uncore_clean_online();
458 if (cpu == uncore->cpu)
459 cpumask_set_cpu(cpu, uncore->active_mask);
462 static int amd_uncore_cpu_online(unsigned int cpu)
465 uncore_online(cpu, amd_uncore_nb);
468 uncore_online(cpu, amd_uncore_llc);
473 static void uncore_down_prepare(unsigned int cpu,
474 struct amd_uncore * __percpu *uncores)
477 struct amd_uncore *this = *per_cpu_ptr(uncores, cpu);
479 if (this->cpu != cpu)
482 /* this cpu is going down, migrate to a shared sibling if possible */
483 for_each_online_cpu(i) {
484 struct amd_uncore *that = *per_cpu_ptr(uncores, i);
490 perf_pmu_migrate_context(this->pmu, cpu, i);
491 cpumask_clear_cpu(cpu, that->active_mask);
492 cpumask_set_cpu(i, that->active_mask);
499 static int amd_uncore_cpu_down_prepare(unsigned int cpu)
502 uncore_down_prepare(cpu, amd_uncore_nb);
505 uncore_down_prepare(cpu, amd_uncore_llc);
510 static void uncore_dead(unsigned int cpu, struct amd_uncore * __percpu *uncores)
512 struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu);
514 if (cpu == uncore->cpu)
515 cpumask_clear_cpu(cpu, uncore->active_mask);
517 if (!--uncore->refcnt)
519 *per_cpu_ptr(uncores, cpu) = NULL;
522 static int amd_uncore_cpu_dead(unsigned int cpu)
525 uncore_dead(cpu, amd_uncore_nb);
528 uncore_dead(cpu, amd_uncore_llc);
533 static int __init amd_uncore_init(void)
535 struct attribute **df_attr = amd_uncore_df_format_attr;
536 struct attribute **l3_attr = amd_uncore_l3_format_attr;
539 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
540 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
543 if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
546 num_counters_nb = NUM_COUNTERS_NB;
547 num_counters_llc = NUM_COUNTERS_L2;
548 if (boot_cpu_data.x86 >= 0x17) {
550 * For F17h and above, the Northbridge counters are
551 * repurposed as Data Fabric counters. Also, L3
552 * counters are supported too. The PMUs are exported
553 * based on family as either L2 or L3 and NB or DF.
555 num_counters_llc = NUM_COUNTERS_L3;
556 amd_nb_pmu.name = "amd_df";
557 amd_llc_pmu.name = "amd_l3";
561 if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {
562 if (boot_cpu_data.x86 >= 0x17)
563 *df_attr = &format_attr_event14.attr;
565 amd_uncore_nb = alloc_percpu(struct amd_uncore *);
566 if (!amd_uncore_nb) {
570 ret = perf_pmu_register(&amd_nb_pmu, amd_nb_pmu.name, -1);
574 pr_info("%s NB counters detected\n",
575 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
580 if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) {
581 if (boot_cpu_data.x86 >= 0x17)
582 *l3_attr = &format_attr_event8.attr;
584 amd_uncore_llc = alloc_percpu(struct amd_uncore *);
585 if (!amd_uncore_llc) {
589 ret = perf_pmu_register(&amd_llc_pmu, amd_llc_pmu.name, -1);
593 pr_info("%s LLC counters detected\n",
594 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
600 * Install callbacks. Core will call them for each online cpu.
602 if (cpuhp_setup_state(CPUHP_PERF_X86_AMD_UNCORE_PREP,
603 "perf/x86/amd/uncore:prepare",
604 amd_uncore_cpu_up_prepare, amd_uncore_cpu_dead))
607 if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,
608 "perf/x86/amd/uncore:starting",
609 amd_uncore_cpu_starting, NULL))
611 if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE,
612 "perf/x86/amd/uncore:online",
613 amd_uncore_cpu_online,
614 amd_uncore_cpu_down_prepare))
619 cpuhp_remove_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING);
621 cpuhp_remove_state(CPUHP_PERF_X86_AMD_UNCORE_PREP);
623 if (boot_cpu_has(X86_FEATURE_PERFCTR_NB))
624 perf_pmu_unregister(&amd_nb_pmu);
626 free_percpu(amd_uncore_llc);
629 free_percpu(amd_uncore_nb);
633 device_initcall(amd_uncore_init);