arch/s390/kernel/irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *    Copyright IBM Corp. 2004, 2011
   4  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
   5  *               Holger Smolinski <Holger.Smolinski@de.ibm.com>,
   6  *               Thomas Spatzier <tspat@de.ibm.com>,
   7  *
   8  * This file contains interrupt related functions.
   9  */
  10
  11 #include <linux/kernel_stat.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/proc_fs.h>
  15 #include <linux/profile.h>
  16 #include <linux/export.h>
  17 #include <linux/kernel.h>
  18 #include <linux/ftrace.h>
  19 #include <linux/errno.h>
  20 #include <linux/slab.h>
  21 #include <linux/init.h>
  22 #include <linux/cpu.h>
  23 #include <linux/irq.h>
  24 #include <linux/entry-common.h>
  25 #include <asm/irq_regs.h>
  26 #include <asm/cputime.h>
  27 #include <asm/lowcore.h>
  28 #include <asm/irq.h>
  29 #include <asm/hw_irq.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/softirq_stack.h>
  32 #include "entry.h"
  33
  34 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
  35 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
  36
  37 struct irq_class {
  38         int irq;
  39         char *name;
  40         char *desc;
  41 };
  42
  43 /*
  44  * The list of "main" irq classes on s390. This is the list of interrupts
  45  * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
  46  * Historically only external and I/O interrupts have been part of /proc/stat.
  47  * We can't add the split external and I/O sub classes since the first field
  48  * in the "intr" line in /proc/stat is supposed to be the sum of all other
  49  * fields.
  50  * Since the external and I/O interrupt fields are already sums we would end
  51  * up with having a sum which accounts each interrupt twice.
  52  */
  53 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
  54         {.irq = EXT_INTERRUPT,  .name = "EXT"},
  55         {.irq = IO_INTERRUPT,   .name = "I/O"},
  56         {.irq = THIN_INTERRUPT, .name = "AIO"},
  57 };
  58
  59 /*
  60  * The list of split external and I/O interrupts that appear only in
  61  * /proc/interrupts.
  62  * In addition this list contains non external / I/O events like NMIs.
  63  */
  64 static const struct irq_class irqclass_sub_desc[] = {
  65         {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
  66         {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
  67         {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
  68         {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
  69         {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
  70         {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
  71         {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
  72         {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
  73         {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
  74         {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
  75         {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
  76         {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
  77         {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
  78         {.irq = IRQIO_CIO,  .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
  79         {.irq = IRQIO_DAS,  .name = "DAS", .desc = "[I/O] DASD"},
  80         {.irq = IRQIO_C15,  .name = "C15", .desc = "[I/O] 3215"},
  81         {.irq = IRQIO_C70,  .name = "C70", .desc = "[I/O] 3270"},
  82         {.irq = IRQIO_TAP,  .name = "TAP", .desc = "[I/O] Tape"},
  83         {.irq = IRQIO_VMR,  .name = "VMR", .desc = "[I/O] Unit Record Devices"},
  84         {.irq = IRQIO_LCS,  .name = "LCS", .desc = "[I/O] LCS"},
  85         {.irq = IRQIO_CTC,  .name = "CTC", .desc = "[I/O] CTC"},
  86         {.irq = IRQIO_ADM,  .name = "ADM", .desc = "[I/O] EADM Subchannel"},
  87         {.irq = IRQIO_CSC,  .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
  88         {.irq = IRQIO_VIR,  .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
  89         {.irq = IRQIO_QAI,  .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
  90         {.irq = IRQIO_APB,  .name = "APB", .desc = "[AIO] AP Bus"},
  91         {.irq = IRQIO_PCF,  .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
  92         {.irq = IRQIO_PCD,  .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
  93         {.irq = IRQIO_MSI,  .name = "MSI", .desc = "[AIO] MSI Interrupt"},
  94         {.irq = IRQIO_VAI,  .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
  95         {.irq = IRQIO_GAL,  .name = "GAL", .desc = "[AIO] GIB Alert"},
  96         {.irq = NMI_NMI,    .name = "NMI", .desc = "[NMI] Machine Check"},
  97         {.irq = CPU_RST,    .name = "RST", .desc = "[CPU] CPU Restart"},
  98 };
  99
 100 static void do_IRQ(struct pt_regs *regs, int irq)
 101 {
 102         if (tod_after_eq(S390_lowcore.int_clock,
 103                          S390_lowcore.clock_comparator))
 104                 /* Serve timer interrupts first. */
 105                 clock_comparator_work();
 106         generic_handle_irq(irq);
 107 }
 108
 109 static int on_async_stack(void)
 110 {
 111         unsigned long frame = current_frame_address();
 112
 113         return !!!((S390_lowcore.async_stack - frame) >> (PAGE_SHIFT + THREAD_SIZE_ORDER));
 114 }
 115
 116 static void do_irq_async(struct pt_regs *regs, int irq)
 117 {
 118         if (on_async_stack())
 119                 do_IRQ(regs, irq);
 120         else
 121                 CALL_ON_STACK(do_IRQ, S390_lowcore.async_stack, 2, regs, irq);
 122 }
 123
 124 static int irq_pending(struct pt_regs *regs)
 125 {
 126         int cc;
 127
 128         asm volatile("tpi 0\n"
 129                      "ipm %0" : "=d" (cc) : : "cc");
 130         return cc >> 28;
 131 }
 132
 133 void noinstr do_io_irq(struct pt_regs *regs)
 134 {
 135         irqentry_state_t state = irqentry_enter(regs);
 136         struct pt_regs *old_regs = set_irq_regs(regs);
 137         int from_idle;
 138
 139         irq_enter();
 140
 141         if (user_mode(regs))
 142                 update_timer_sys();
 143
 144         from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit;
 145         if (from_idle)
 146                 account_idle_time_irq();
 147
 148         do {
 149                 regs->tpi_info = S390_lowcore.tpi_info;
 150                 if (S390_lowcore.tpi_info.adapter_IO)
 151                         do_irq_async(regs, THIN_INTERRUPT);
 152                 else
 153                         do_irq_async(regs, IO_INTERRUPT);
 154         } while (MACHINE_IS_LPAR && irq_pending(regs));
 155
 156         irq_exit();
 157         set_irq_regs(old_regs);
 158         irqentry_exit(regs, state);
 159
 160         if (from_idle)
 161                 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
 162 }
 163
 164 void noinstr do_ext_irq(struct pt_regs *regs)
 165 {
 166         irqentry_state_t state = irqentry_enter(regs);
 167         struct pt_regs *old_regs = set_irq_regs(regs);
 168         int from_idle;
 169
 170         irq_enter();
 171
 172         if (user_mode(regs))
 173                 update_timer_sys();
 174
 175         regs->int_code = S390_lowcore.ext_int_code_addr;
 176         regs->int_parm = S390_lowcore.ext_params;
 177         regs->int_parm_long = S390_lowcore.ext_params2;
 178
 179         from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit;
 180         if (from_idle)
 181                 account_idle_time_irq();
 182
 183         do_irq_async(regs, EXT_INTERRUPT);
 184
 185         irq_exit();
 186         set_irq_regs(old_regs);
 187         irqentry_exit(regs, state);
 188
 189         if (from_idle)
 190                 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
 191 }
 192
 193 static void show_msi_interrupt(struct seq_file *p, int irq)
 194 {
 195         struct irq_desc *desc;
 196         unsigned long flags;
 197         int cpu;
 198
 199         irq_lock_sparse();
 200         desc = irq_to_desc(irq);
 201         if (!desc)
 202                 goto out;
 203
 204         raw_spin_lock_irqsave(&desc->lock, flags);
 205         seq_printf(p, "%3d: ", irq);
 206         for_each_online_cpu(cpu)
 207                 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu));
 208
 209         if (desc->irq_data.chip)
 210                 seq_printf(p, " %8s", desc->irq_data.chip->name);
 211
 212         if (desc->action)
 213                 seq_printf(p, "  %s", desc->action->name);
 214
 215         seq_putc(p, '\n');
 216         raw_spin_unlock_irqrestore(&desc->lock, flags);
 217 out:
 218         irq_unlock_sparse();
 219 }
 220
 221 /*
 222  * show_interrupts is needed by /proc/interrupts.
 223  */
 224 int show_interrupts(struct seq_file *p, void *v)
 225 {
 226         int index = *(loff_t *) v;
 227         int cpu, irq;
 228
 229         get_online_cpus();
 230         if (index == 0) {
 231                 seq_puts(p, "           ");
 232                 for_each_online_cpu(cpu)
 233                         seq_printf(p, "CPU%-8d", cpu);
 234                 seq_putc(p, '\n');
 235         }
 236         if (index < NR_IRQS_BASE) {
 237                 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
 238                 irq = irqclass_main_desc[index].irq;
 239                 for_each_online_cpu(cpu)
 240                         seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
 241                 seq_putc(p, '\n');
 242                 goto out;
 243         }
 244         if (index < nr_irqs) {
 245                 show_msi_interrupt(p, index);
 246                 goto out;
 247         }
 248         for (index = 0; index < NR_ARCH_IRQS; index++) {
 249                 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
 250                 irq = irqclass_sub_desc[index].irq;
 251                 for_each_online_cpu(cpu)
 252                         seq_printf(p, "%10u ",
 253                                    per_cpu(irq_stat, cpu).irqs[irq]);
 254                 if (irqclass_sub_desc[index].desc)
 255                         seq_printf(p, "  %s", irqclass_sub_desc[index].desc);
 256                 seq_putc(p, '\n');
 257         }
 258 out:
 259         put_online_cpus();
 260         return 0;
 261 }
 262
 263 unsigned int arch_dynirq_lower_bound(unsigned int from)
 264 {
 265         return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
 266 }
 267
 268 /*
 269  * Switch to the asynchronous interrupt stack for softirq execution.
 270  */
 271 void do_softirq_own_stack(void)
 272 {
 273         unsigned long old, new;
 274
 275         old = current_stack_pointer();
 276         /* Check against async. stack address range. */
 277         new = S390_lowcore.async_stack;
 278         if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) {
 279                 CALL_ON_STACK(__do_softirq, new, 0);
 280         } else {
 281                 /* We are already on the async stack. */
 282                 __do_softirq();
 283         }
 284 }
 285
 286 /*
 287  * ext_int_hash[index] is the list head for all external interrupts that hash
 288  * to this index.
 289  */
 290 static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
 291
 292 struct ext_int_info {
 293         ext_int_handler_t handler;
 294         struct hlist_node entry;
 295         struct rcu_head rcu;
 296         u16 code;
 297 };
 298
 299 /* ext_int_hash_lock protects the handler lists for external interrupts */
 300 static DEFINE_SPINLOCK(ext_int_hash_lock);
 301
 302 static inline int ext_hash(u16 code)
 303 {
 304         BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
 305
 306         return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
 307 }
 308
 309 int register_external_irq(u16 code, ext_int_handler_t handler)
 310 {
 311         struct ext_int_info *p;
 312         unsigned long flags;
 313         int index;
 314
 315         p = kmalloc(sizeof(*p), GFP_ATOMIC);
 316         if (!p)
 317                 return -ENOMEM;
 318         p->code = code;
 319         p->handler = handler;
 320         index = ext_hash(code);
 321
 322         spin_lock_irqsave(&ext_int_hash_lock, flags);
 323         hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
 324         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
 325         return 0;
 326 }
 327 EXPORT_SYMBOL(register_external_irq);
 328
 329 int unregister_external_irq(u16 code, ext_int_handler_t handler)
 330 {
 331         struct ext_int_info *p;
 332         unsigned long flags;
 333         int index = ext_hash(code);
 334
 335         spin_lock_irqsave(&ext_int_hash_lock, flags);
 336         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
 337                 if (p->code == code && p->handler == handler) {
 338                         hlist_del_rcu(&p->entry);
 339                         kfree_rcu(p, rcu);
 340                 }
 341         }
 342         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
 343         return 0;
 344 }
 345 EXPORT_SYMBOL(unregister_external_irq);
 346
 347 static irqreturn_t do_ext_interrupt(int irq, void *dummy)
 348 {
 349         struct pt_regs *regs = get_irq_regs();
 350         struct ext_code ext_code;
 351         struct ext_int_info *p;
 352         int index;
 353
 354         ext_code = *(struct ext_code *) &regs->int_code;
 355         if (ext_code.code != EXT_IRQ_CLK_COMP)
 356                 set_cpu_flag(CIF_NOHZ_DELAY);
 357
 358         index = ext_hash(ext_code.code);
 359         rcu_read_lock();
 360         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
 361                 if (unlikely(p->code != ext_code.code))
 362                         continue;
 363                 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
 364         }
 365         rcu_read_unlock();
 366         return IRQ_HANDLED;
 367 }
 368
 369 static void __init init_ext_interrupts(void)
 370 {
 371         int idx;
 372
 373         for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
 374                 INIT_HLIST_HEAD(&ext_int_hash[idx]);
 375
 376         irq_set_chip_and_handler(EXT_INTERRUPT,
 377                                  &dummy_irq_chip, handle_percpu_irq);
 378         if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL))
 379                 panic("Failed to register EXT interrupt\n");
 380 }
 381
 382 void __init init_IRQ(void)
 383 {
 384         BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
 385         init_cio_interrupts();
 386         init_airq_interrupts();
 387         init_ext_interrupts();
 388 }
 389
 390 static DEFINE_SPINLOCK(irq_subclass_lock);
 391 static unsigned char irq_subclass_refcount[64];
 392
 393 void irq_subclass_register(enum irq_subclass subclass)
 394 {
 395         spin_lock(&irq_subclass_lock);
 396         if (!irq_subclass_refcount[subclass])
 397                 ctl_set_bit(0, subclass);
 398         irq_subclass_refcount[subclass]++;
 399         spin_unlock(&irq_subclass_lock);
 400 }
 401 EXPORT_SYMBOL(irq_subclass_register);
 402
 403 void irq_subclass_unregister(enum irq_subclass subclass)
 404 {
 405         spin_lock(&irq_subclass_lock);
 406         irq_subclass_refcount[subclass]--;
 407         if (!irq_subclass_refcount[subclass])
 408                 ctl_clear_bit(0, subclass);
 409         spin_unlock(&irq_subclass_lock);
 410 }
 411 EXPORT_SYMBOL(irq_subclass_unregister);