RISC-V: fixups to work with crash tool
[linux-2.6-microblaze.git] / arch / riscv / mm / dma-noncoherent.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * RISC-V specific functions to support DMA for non-coherent devices
4  *
5  * Copyright (c) 2021 Western Digital Corporation or its affiliates.
6  */
7
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
10 #include <linux/mm.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <asm/cacheflush.h>
14
15 static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
16 static bool noncoherent_supported;
17
18 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
19                               enum dma_data_direction dir)
20 {
21         void *vaddr = phys_to_virt(paddr);
22
23         switch (dir) {
24         case DMA_TO_DEVICE:
25                 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
26                 break;
27         case DMA_FROM_DEVICE:
28                 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
29                 break;
30         case DMA_BIDIRECTIONAL:
31                 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
32                 break;
33         default:
34                 break;
35         }
36 }
37
38 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
39                            enum dma_data_direction dir)
40 {
41         void *vaddr = phys_to_virt(paddr);
42
43         switch (dir) {
44         case DMA_TO_DEVICE:
45                 break;
46         case DMA_FROM_DEVICE:
47         case DMA_BIDIRECTIONAL:
48                 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
49                 break;
50         default:
51                 break;
52         }
53 }
54
55 void arch_dma_prep_coherent(struct page *page, size_t size)
56 {
57         void *flush_addr = page_address(page);
58
59         ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
60 }
61
62 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
63                 const struct iommu_ops *iommu, bool coherent)
64 {
65         WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN,
66                    TAINT_CPU_OUT_OF_SPEC,
67                    "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)",
68                    dev_driver_string(dev), dev_name(dev),
69                    ARCH_DMA_MINALIGN, riscv_cbom_block_size);
70
71         WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC,
72                    "%s %s: device non-coherent but no non-coherent operations supported",
73                    dev_driver_string(dev), dev_name(dev));
74
75         dev->dma_coherent = coherent;
76 }
77
78 #ifdef CONFIG_RISCV_ISA_ZICBOM
79 void riscv_init_cbom_blocksize(void)
80 {
81         struct device_node *node;
82         int ret;
83         u32 val;
84
85         for_each_of_cpu_node(node) {
86                 unsigned long hartid;
87                 int cbom_hartid;
88
89                 ret = riscv_of_processor_hartid(node, &hartid);
90                 if (ret)
91                         continue;
92
93                 if (hartid < 0)
94                         continue;
95
96                 /* set block-size for cbom extension if available */
97                 ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
98                 if (ret)
99                         continue;
100
101                 if (!riscv_cbom_block_size) {
102                         riscv_cbom_block_size = val;
103                         cbom_hartid = hartid;
104                 } else {
105                         if (riscv_cbom_block_size != val)
106                                 pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
107                                         cbom_hartid, hartid);
108                 }
109         }
110 }
111 #endif
112
113 void riscv_noncoherent_supported(void)
114 {
115         noncoherent_supported = true;
116 }