arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5
   6 #include "microchip-mpfs.dtsi"
   7
   8 /* Clock frequency (in Hz) of the rtcclk */
   9 #define RTCCLK_FREQ             1000000
  10
  11 / {
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14         model = "Microchip PolarFire-SoC Icicle Kit";
  15         compatible = "microchip,mpfs-icicle-kit";
  16
  17         chosen {
  18                 stdout-path = &serial0;
  19         };
  20
  21         cpus {
  22                 timebase-frequency = <RTCCLK_FREQ>;
  23         };
  24
  25         memory@80000000 {
  26                 device_type = "memory";
  27                 reg = <0x0 0x80000000 0x0 0x40000000>;
  28                 clocks = <&clkcfg 26>;
  29         };
  30
  31         soc {
  32         };
  33 };
  34
  35 &serial0 {
  36         status = "okay";
  37 };
  38
  39 &serial1 {
  40         status = "okay";
  41 };
  42
  43 &serial2 {
  44         status = "okay";
  45 };
  46
  47 &serial3 {
  48         status = "okay";
  49 };
  50
  51 &sdcard {
  52         status = "okay";
  53 };
  54
  55 &emac0 {
  56         phy-mode = "sgmii";
  57         phy-handle = <&phy0>;
  58         phy0: ethernet-phy@8 {
  59                 reg = <8>;
  60                 ti,fifo-depth = <0x01>;
  61         };
  62 };
  63
  64 &emac1 {
  65         status = "okay";
  66         phy-mode = "sgmii";
  67         phy-handle = <&phy1>;
  68         phy1: ethernet-phy@9 {
  69                 reg = <9>;
  70                 ti,fifo-depth = <0x01>;
  71         };
  72 };