arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/memblock.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/string.h>
  34 #include <linux/pci.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/crash_dump.h>
  37 #include <linux/memory.h>
  38 #include <linux/of.h>
  39 #include <linux/iommu.h>
  40 #include <linux/rculist.h>
  41 #include <asm/io.h>
  42 #include <asm/prom.h>
  43 #include <asm/rtas.h>
  44 #include <asm/iommu.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/machdep.h>
  47 #include <asm/firmware.h>
  48 #include <asm/tce.h>
  49 #include <asm/ppc-pci.h>
  50 #include <asm/udbg.h>
  51 #include <asm/mmzone.h>
  52 #include <asm/plpar_wrappers.h>
  53
  54 #include "pseries.h"
  55
  56 static struct iommu_table_group *iommu_pseries_alloc_group(int node)
  57 {
  58         struct iommu_table_group *table_group;
  59         struct iommu_table *tbl;
  60         struct iommu_table_group_link *tgl;
  61
  62         table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
  63                            node);
  64         if (!table_group)
  65                 return NULL;
  66
  67         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
  68         if (!tbl)
  69                 goto free_group;
  70
  71         tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
  72                         node);
  73         if (!tgl)
  74                 goto free_table;
  75
  76         INIT_LIST_HEAD_RCU(&tbl->it_group_list);
  77         kref_init(&tbl->it_kref);
  78         tgl->table_group = table_group;
  79         list_add_rcu(&tgl->next, &tbl->it_group_list);
  80
  81         table_group->tables[0] = tbl;
  82
  83         return table_group;
  84
  85 free_table:
  86         kfree(tbl);
  87 free_group:
  88         kfree(table_group);
  89         return NULL;
  90 }
  91
  92 static void iommu_pseries_free_group(struct iommu_table_group *table_group,
  93                 const char *node_name)
  94 {
  95         struct iommu_table *tbl;
  96 #ifdef CONFIG_IOMMU_API
  97         struct iommu_table_group_link *tgl;
  98 #endif
  99
 100         if (!table_group)
 101                 return;
 102
 103         tbl = table_group->tables[0];
 104 #ifdef CONFIG_IOMMU_API
 105         tgl = list_first_entry_or_null(&tbl->it_group_list,
 106                         struct iommu_table_group_link, next);
 107
 108         WARN_ON_ONCE(!tgl);
 109         if (tgl) {
 110                 list_del_rcu(&tgl->next);
 111                 kfree(tgl);
 112         }
 113         if (table_group->group) {
 114                 iommu_group_put(table_group->group);
 115                 BUG_ON(table_group->group);
 116         }
 117 #endif
 118         iommu_tce_table_put(tbl);
 119
 120         kfree(table_group);
 121 }
 122
 123 static int tce_build_pSeries(struct iommu_table *tbl, long index,
 124                               long npages, unsigned long uaddr,
 125                               enum dma_data_direction direction,
 126                               unsigned long attrs)
 127 {
 128         u64 proto_tce;
 129         __be64 *tcep, *tces;
 130         u64 rpn;
 131
 132         proto_tce = TCE_PCI_READ; // Read allowed
 133
 134         if (direction != DMA_TO_DEVICE)
 135                 proto_tce |= TCE_PCI_WRITE;
 136
 137         tces = tcep = ((__be64 *)tbl->it_base) + index;
 138
 139         while (npages--) {
 140                 /* can't move this out since we might cross MEMBLOCK boundary */
 141                 rpn = __pa(uaddr) >> TCE_SHIFT;
 142                 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 143
 144                 uaddr += TCE_PAGE_SIZE;
 145                 tcep++;
 146         }
 147         return 0;
 148 }
 149
 150
 151 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 152 {
 153         __be64 *tcep, *tces;
 154
 155         tces = tcep = ((__be64 *)tbl->it_base) + index;
 156
 157         while (npages--)
 158                 *(tcep++) = 0;
 159 }
 160
 161 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
 162 {
 163         __be64 *tcep;
 164
 165         tcep = ((__be64 *)tbl->it_base) + index;
 166
 167         return be64_to_cpu(*tcep);
 168 }
 169
 170 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
 171 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 172
 173 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
 174                                 long npages, unsigned long uaddr,
 175                                 enum dma_data_direction direction,
 176                                 unsigned long attrs)
 177 {
 178         u64 rc = 0;
 179         u64 proto_tce, tce;
 180         u64 rpn;
 181         int ret = 0;
 182         long tcenum_start = tcenum, npages_start = npages;
 183
 184         rpn = __pa(uaddr) >> TCE_SHIFT;
 185         proto_tce = TCE_PCI_READ;
 186         if (direction != DMA_TO_DEVICE)
 187                 proto_tce |= TCE_PCI_WRITE;
 188
 189         while (npages--) {
 190                 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 191                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
 192
 193                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 194                         ret = (int)rc;
 195                         tce_free_pSeriesLP(tbl, tcenum_start,
 196                                            (npages_start - (npages + 1)));
 197                         break;
 198                 }
 199
 200                 if (rc && printk_ratelimit()) {
 201                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 202                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 203                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 204                         printk("\ttce val = 0x%llx\n", tce );
 205                         dump_stack();
 206                 }
 207
 208                 tcenum++;
 209                 rpn++;
 210         }
 211         return ret;
 212 }
 213
 214 static DEFINE_PER_CPU(__be64 *, tce_page);
 215
 216 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 217                                      long npages, unsigned long uaddr,
 218                                      enum dma_data_direction direction,
 219                                      unsigned long attrs)
 220 {
 221         u64 rc = 0;
 222         u64 proto_tce;
 223         __be64 *tcep;
 224         u64 rpn;
 225         long l, limit;
 226         long tcenum_start = tcenum, npages_start = npages;
 227         int ret = 0;
 228         unsigned long flags;
 229
 230         if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) {
 231                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 232                                            direction, attrs);
 233         }
 234
 235         local_irq_save(flags);  /* to protect tcep and the page behind it */
 236
 237         tcep = __this_cpu_read(tce_page);
 238
 239         /* This is safe to do since interrupts are off when we're called
 240          * from iommu_alloc{,_sg}()
 241          */
 242         if (!tcep) {
 243                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 244                 /* If allocation fails, fall back to the loop implementation */
 245                 if (!tcep) {
 246                         local_irq_restore(flags);
 247                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 248                                             direction, attrs);
 249                 }
 250                 __this_cpu_write(tce_page, tcep);
 251         }
 252
 253         rpn = __pa(uaddr) >> TCE_SHIFT;
 254         proto_tce = TCE_PCI_READ;
 255         if (direction != DMA_TO_DEVICE)
 256                 proto_tce |= TCE_PCI_WRITE;
 257
 258         /* We can map max one pageful of TCEs at a time */
 259         do {
 260                 /*
 261                  * Set up the page with TCE data, looping through and setting
 262                  * the values.
 263                  */
 264                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 265
 266                 for (l = 0; l < limit; l++) {
 267                         tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 268                         rpn++;
 269                 }
 270
 271                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 272                                             (u64)tcenum << 12,
 273                                             (u64)__pa(tcep),
 274                                             limit);
 275
 276                 npages -= limit;
 277                 tcenum += limit;
 278         } while (npages > 0 && !rc);
 279
 280         local_irq_restore(flags);
 281
 282         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 283                 ret = (int)rc;
 284                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 285                                         (npages_start - (npages + limit)));
 286                 return ret;
 287         }
 288
 289         if (rc && printk_ratelimit()) {
 290                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 291                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 292                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 293                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 294                 dump_stack();
 295         }
 296         return ret;
 297 }
 298
 299 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 300 {
 301         u64 rc;
 302
 303         while (npages--) {
 304                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
 305
 306                 if (rc && printk_ratelimit()) {
 307                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 308                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 309                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 310                         dump_stack();
 311                 }
 312
 313                 tcenum++;
 314         }
 315 }
 316
 317
 318 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 319 {
 320         u64 rc;
 321
 322         if (!firmware_has_feature(FW_FEATURE_MULTITCE))
 323                 return tce_free_pSeriesLP(tbl, tcenum, npages);
 324
 325         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 326
 327         if (rc && printk_ratelimit()) {
 328                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 329                 printk("\trc      = %lld\n", rc);
 330                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 331                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 332                 dump_stack();
 333         }
 334 }
 335
 336 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 337 {
 338         u64 rc;
 339         unsigned long tce_ret;
 340
 341         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 342
 343         if (rc && printk_ratelimit()) {
 344                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 345                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 346                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 347                 dump_stack();
 348         }
 349
 350         return tce_ret;
 351 }
 352
 353 /* this is compatible with cells for the device tree property */
 354 struct dynamic_dma_window_prop {
 355         __be32  liobn;          /* tce table number */
 356         __be64  dma_base;       /* address hi,lo */
 357         __be32  tce_shift;      /* ilog2(tce_page_size) */
 358         __be32  window_shift;   /* ilog2(tce_window_size) */
 359 };
 360
 361 struct direct_window {
 362         struct device_node *device;
 363         const struct dynamic_dma_window_prop *prop;
 364         struct list_head list;
 365 };
 366
 367 /* Dynamic DMA Window support */
 368 struct ddw_query_response {
 369         u32 windows_available;
 370         u32 largest_available_block;
 371         u32 page_size;
 372         u32 migration_capable;
 373 };
 374
 375 struct ddw_create_response {
 376         u32 liobn;
 377         u32 addr_hi;
 378         u32 addr_lo;
 379 };
 380
 381 static LIST_HEAD(direct_window_list);
 382 /* prevents races between memory on/offline and window creation */
 383 static DEFINE_SPINLOCK(direct_window_list_lock);
 384 /* protects initializing window twice for same device */
 385 static DEFINE_MUTEX(direct_window_init_mutex);
 386 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 387
 388 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 389                                         unsigned long num_pfn, const void *arg)
 390 {
 391         const struct dynamic_dma_window_prop *maprange = arg;
 392         int rc;
 393         u64 tce_size, num_tce, dma_offset, next;
 394         u32 tce_shift;
 395         long limit;
 396
 397         tce_shift = be32_to_cpu(maprange->tce_shift);
 398         tce_size = 1ULL << tce_shift;
 399         next = start_pfn << PAGE_SHIFT;
 400         num_tce = num_pfn << PAGE_SHIFT;
 401
 402         /* round back to the beginning of the tce page size */
 403         num_tce += next & (tce_size - 1);
 404         next &= ~(tce_size - 1);
 405
 406         /* covert to number of tces */
 407         num_tce |= tce_size - 1;
 408         num_tce >>= tce_shift;
 409
 410         do {
 411                 /*
 412                  * Set up the page with TCE data, looping through and setting
 413                  * the values.
 414                  */
 415                 limit = min_t(long, num_tce, 512);
 416                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 417
 418                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 419                                              dma_offset,
 420                                              0, limit);
 421                 next += limit * tce_size;
 422                 num_tce -= limit;
 423         } while (num_tce > 0 && !rc);
 424
 425         return rc;
 426 }
 427
 428 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 429                                         unsigned long num_pfn, const void *arg)
 430 {
 431         const struct dynamic_dma_window_prop *maprange = arg;
 432         u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 433         __be64 *tcep;
 434         u32 tce_shift;
 435         u64 rc = 0;
 436         long l, limit;
 437
 438         local_irq_disable();    /* to protect tcep and the page behind it */
 439         tcep = __this_cpu_read(tce_page);
 440
 441         if (!tcep) {
 442                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 443                 if (!tcep) {
 444                         local_irq_enable();
 445                         return -ENOMEM;
 446                 }
 447                 __this_cpu_write(tce_page, tcep);
 448         }
 449
 450         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 451
 452         liobn = (u64)be32_to_cpu(maprange->liobn);
 453         tce_shift = be32_to_cpu(maprange->tce_shift);
 454         tce_size = 1ULL << tce_shift;
 455         next = start_pfn << PAGE_SHIFT;
 456         num_tce = num_pfn << PAGE_SHIFT;
 457
 458         /* round back to the beginning of the tce page size */
 459         num_tce += next & (tce_size - 1);
 460         next &= ~(tce_size - 1);
 461
 462         /* covert to number of tces */
 463         num_tce |= tce_size - 1;
 464         num_tce >>= tce_shift;
 465
 466         /* We can map max one pageful of TCEs at a time */
 467         do {
 468                 /*
 469                  * Set up the page with TCE data, looping through and setting
 470                  * the values.
 471                  */
 472                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 473                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 474
 475                 for (l = 0; l < limit; l++) {
 476                         tcep[l] = cpu_to_be64(proto_tce | next);
 477                         next += tce_size;
 478                 }
 479
 480                 rc = plpar_tce_put_indirect(liobn,
 481                                             dma_offset,
 482                                             (u64)__pa(tcep),
 483                                             limit);
 484
 485                 num_tce -= limit;
 486         } while (num_tce > 0 && !rc);
 487
 488         /* error cleanup: caller will clear whole range */
 489
 490         local_irq_enable();
 491         return rc;
 492 }
 493
 494 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 495                 unsigned long num_pfn, void *arg)
 496 {
 497         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 498 }
 499
 500 static void iommu_table_setparms(struct pci_controller *phb,
 501                                  struct device_node *dn,
 502                                  struct iommu_table *tbl)
 503 {
 504         struct device_node *node;
 505         const unsigned long *basep;
 506         const u32 *sizep;
 507
 508         node = phb->dn;
 509
 510         basep = of_get_property(node, "linux,tce-base", NULL);
 511         sizep = of_get_property(node, "linux,tce-size", NULL);
 512         if (basep == NULL || sizep == NULL) {
 513                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %pOF has "
 514                                 "missing tce entries !\n", dn);
 515                 return;
 516         }
 517
 518         tbl->it_base = (unsigned long)__va(*basep);
 519
 520         if (!is_kdump_kernel())
 521                 memset((void *)tbl->it_base, 0, *sizep);
 522
 523         tbl->it_busno = phb->bus->number;
 524         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 525
 526         /* Units of tce entries */
 527         tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 528
 529         /* Test if we are going over 2GB of DMA space */
 530         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 531                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 532                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 533         }
 534
 535         phb->dma_window_base_cur += phb->dma_window_size;
 536
 537         /* Set the tce table size - measured in entries */
 538         tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 539
 540         tbl->it_index = 0;
 541         tbl->it_blocksize = 16;
 542         tbl->it_type = TCE_PCI;
 543 }
 544
 545 /*
 546  * iommu_table_setparms_lpar
 547  *
 548  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 549  */
 550 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 551                                       struct device_node *dn,
 552                                       struct iommu_table *tbl,
 553                                       struct iommu_table_group *table_group,
 554                                       const __be32 *dma_window)
 555 {
 556         unsigned long offset, size;
 557
 558         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 559
 560         tbl->it_busno = phb->bus->number;
 561         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 562         tbl->it_base   = 0;
 563         tbl->it_blocksize  = 16;
 564         tbl->it_type = TCE_PCI;
 565         tbl->it_offset = offset >> tbl->it_page_shift;
 566         tbl->it_size = size >> tbl->it_page_shift;
 567
 568         table_group->tce32_start = offset;
 569         table_group->tce32_size = size;
 570 }
 571
 572 struct iommu_table_ops iommu_table_pseries_ops = {
 573         .set = tce_build_pSeries,
 574         .clear = tce_free_pSeries,
 575         .get = tce_get_pseries
 576 };
 577
 578 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 579 {
 580         struct device_node *dn;
 581         struct iommu_table *tbl;
 582         struct device_node *isa_dn, *isa_dn_orig;
 583         struct device_node *tmp;
 584         struct pci_dn *pci;
 585         int children;
 586
 587         dn = pci_bus_to_OF_node(bus);
 588
 589         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %pOF\n", dn);
 590
 591         if (bus->self) {
 592                 /* This is not a root bus, any setup will be done for the
 593                  * device-side of the bridge in iommu_dev_setup_pSeries().
 594                  */
 595                 return;
 596         }
 597         pci = PCI_DN(dn);
 598
 599         /* Check if the ISA bus on the system is under
 600          * this PHB.
 601          */
 602         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 603
 604         while (isa_dn && isa_dn != dn)
 605                 isa_dn = isa_dn->parent;
 606
 607         of_node_put(isa_dn_orig);
 608
 609         /* Count number of direct PCI children of the PHB. */
 610         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 611                 children++;
 612
 613         pr_debug("Children: %d\n", children);
 614
 615         /* Calculate amount of DMA window per slot. Each window must be
 616          * a power of two (due to pci_alloc_consistent requirements).
 617          *
 618          * Keep 256MB aside for PHBs with ISA.
 619          */
 620
 621         if (!isa_dn) {
 622                 /* No ISA/IDE - just set window size and return */
 623                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 624
 625                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 626                         pci->phb->dma_window_size >>= 1;
 627                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 628                          pci->phb->dma_window_size);
 629                 pci->phb->dma_window_base_cur = 0;
 630
 631                 return;
 632         }
 633
 634         /* If we have ISA, then we probably have an IDE
 635          * controller too. Allocate a 128MB table but
 636          * skip the first 128MB to avoid stepping on ISA
 637          * space.
 638          */
 639         pci->phb->dma_window_size = 0x8000000ul;
 640         pci->phb->dma_window_base_cur = 0x8000000ul;
 641
 642         pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
 643         tbl = pci->table_group->tables[0];
 644
 645         iommu_table_setparms(pci->phb, dn, tbl);
 646         tbl->it_ops = &iommu_table_pseries_ops;
 647         iommu_init_table(tbl, pci->phb->node);
 648         iommu_register_group(pci->table_group, pci_domain_nr(bus), 0);
 649
 650         /* Divide the rest (1.75GB) among the children */
 651         pci->phb->dma_window_size = 0x80000000ul;
 652         while (pci->phb->dma_window_size * children > 0x70000000ul)
 653                 pci->phb->dma_window_size >>= 1;
 654
 655         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 656 }
 657
 658 #ifdef CONFIG_IOMMU_API
 659 static int tce_exchange_pseries(struct iommu_table *tbl, long index, unsigned
 660                                 long *tce, enum dma_data_direction *direction)
 661 {
 662         long rc;
 663         unsigned long ioba = (unsigned long) index << tbl->it_page_shift;
 664         unsigned long flags, oldtce = 0;
 665         u64 proto_tce = iommu_direction_to_tce_perm(*direction);
 666         unsigned long newtce = *tce | proto_tce;
 667
 668         spin_lock_irqsave(&tbl->large_pool.lock, flags);
 669
 670         rc = plpar_tce_get((u64)tbl->it_index, ioba, &oldtce);
 671         if (!rc)
 672                 rc = plpar_tce_put((u64)tbl->it_index, ioba, newtce);
 673
 674         if (!rc) {
 675                 *direction = iommu_tce_direction(oldtce);
 676                 *tce = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE);
 677         }
 678
 679         spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
 680
 681         return rc;
 682 }
 683 #endif
 684
 685 struct iommu_table_ops iommu_table_lpar_multi_ops = {
 686         .set = tce_buildmulti_pSeriesLP,
 687 #ifdef CONFIG_IOMMU_API
 688         .exchange = tce_exchange_pseries,
 689 #endif
 690         .clear = tce_freemulti_pSeriesLP,
 691         .get = tce_get_pSeriesLP
 692 };
 693
 694 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 695 {
 696         struct iommu_table *tbl;
 697         struct device_node *dn, *pdn;
 698         struct pci_dn *ppci;
 699         const __be32 *dma_window = NULL;
 700
 701         dn = pci_bus_to_OF_node(bus);
 702
 703         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %pOF\n",
 704                  dn);
 705
 706         /* Find nearest ibm,dma-window, walking up the device tree */
 707         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 708                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 709                 if (dma_window != NULL)
 710                         break;
 711         }
 712
 713         if (dma_window == NULL) {
 714                 pr_debug("  no ibm,dma-window property !\n");
 715                 return;
 716         }
 717
 718         ppci = PCI_DN(pdn);
 719
 720         pr_debug("  parent is %pOF, iommu_table: 0x%p\n",
 721                  pdn, ppci->table_group);
 722
 723         if (!ppci->table_group) {
 724                 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node);
 725                 tbl = ppci->table_group->tables[0];
 726                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl,
 727                                 ppci->table_group, dma_window);
 728                 tbl->it_ops = &iommu_table_lpar_multi_ops;
 729                 iommu_init_table(tbl, ppci->phb->node);
 730                 iommu_register_group(ppci->table_group,
 731                                 pci_domain_nr(bus), 0);
 732                 pr_debug("  created table: %p\n", ppci->table_group);
 733         }
 734 }
 735
 736
 737 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 738 {
 739         struct device_node *dn;
 740         struct iommu_table *tbl;
 741
 742         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 743
 744         dn = dev->dev.of_node;
 745
 746         /* If we're the direct child of a root bus, then we need to allocate
 747          * an iommu table ourselves. The bus setup code should have setup
 748          * the window sizes already.
 749          */
 750         if (!dev->bus->self) {
 751                 struct pci_controller *phb = PCI_DN(dn)->phb;
 752
 753                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 754                 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node);
 755                 tbl = PCI_DN(dn)->table_group->tables[0];
 756                 iommu_table_setparms(phb, dn, tbl);
 757                 tbl->it_ops = &iommu_table_pseries_ops;
 758                 iommu_init_table(tbl, phb->node);
 759                 iommu_register_group(PCI_DN(dn)->table_group,
 760                                 pci_domain_nr(phb->bus), 0);
 761                 set_iommu_table_base(&dev->dev, tbl);
 762                 iommu_add_device(&dev->dev);
 763                 return;
 764         }
 765
 766         /* If this device is further down the bus tree, search upwards until
 767          * an already allocated iommu table is found and use that.
 768          */
 769
 770         while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL)
 771                 dn = dn->parent;
 772
 773         if (dn && PCI_DN(dn)) {
 774                 set_iommu_table_base(&dev->dev,
 775                                 PCI_DN(dn)->table_group->tables[0]);
 776                 iommu_add_device(&dev->dev);
 777         } else
 778                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 779                        pci_name(dev));
 780 }
 781
 782 static int __read_mostly disable_ddw;
 783
 784 static int __init disable_ddw_setup(char *str)
 785 {
 786         disable_ddw = 1;
 787         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 788
 789         return 0;
 790 }
 791
 792 early_param("disable_ddw", disable_ddw_setup);
 793
 794 static void remove_ddw(struct device_node *np, bool remove_prop)
 795 {
 796         struct dynamic_dma_window_prop *dwp;
 797         struct property *win64;
 798         u32 ddw_avail[3];
 799         u64 liobn;
 800         int ret = 0;
 801
 802         ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
 803                                          &ddw_avail[0], 3);
 804
 805         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 806         if (!win64)
 807                 return;
 808
 809         if (ret || win64->length < sizeof(*dwp))
 810                 goto delprop;
 811
 812         dwp = win64->value;
 813         liobn = (u64)be32_to_cpu(dwp->liobn);
 814
 815         /* clear the whole window, note the arg is in kernel pages */
 816         ret = tce_clearrange_multi_pSeriesLP(0,
 817                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 818         if (ret)
 819                 pr_warn("%pOF failed to clear tces in window.\n",
 820                         np);
 821         else
 822                 pr_debug("%pOF successfully cleared tces in window.\n",
 823                          np);
 824
 825         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 826         if (ret)
 827                 pr_warn("%pOF: failed to remove direct window: rtas returned "
 828                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 829                         np, ret, ddw_avail[2], liobn);
 830         else
 831                 pr_debug("%pOF: successfully removed direct window: rtas returned "
 832                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 833                         np, ret, ddw_avail[2], liobn);
 834
 835 delprop:
 836         if (remove_prop)
 837                 ret = of_remove_property(np, win64);
 838         if (ret)
 839                 pr_warn("%pOF: failed to remove direct window property: %d\n",
 840                         np, ret);
 841 }
 842
 843 static u64 find_existing_ddw(struct device_node *pdn)
 844 {
 845         struct direct_window *window;
 846         const struct dynamic_dma_window_prop *direct64;
 847         u64 dma_addr = 0;
 848
 849         spin_lock(&direct_window_list_lock);
 850         /* check if we already created a window and dupe that config if so */
 851         list_for_each_entry(window, &direct_window_list, list) {
 852                 if (window->device == pdn) {
 853                         direct64 = window->prop;
 854                         dma_addr = be64_to_cpu(direct64->dma_base);
 855                         break;
 856                 }
 857         }
 858         spin_unlock(&direct_window_list_lock);
 859
 860         return dma_addr;
 861 }
 862
 863 static int find_existing_ddw_windows(void)
 864 {
 865         int len;
 866         struct device_node *pdn;
 867         struct direct_window *window;
 868         const struct dynamic_dma_window_prop *direct64;
 869
 870         if (!firmware_has_feature(FW_FEATURE_LPAR))
 871                 return 0;
 872
 873         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 874                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 875                 if (!direct64)
 876                         continue;
 877
 878                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 879                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 880                         kfree(window);
 881                         remove_ddw(pdn, true);
 882                         continue;
 883                 }
 884
 885                 window->device = pdn;
 886                 window->prop = direct64;
 887                 spin_lock(&direct_window_list_lock);
 888                 list_add(&window->list, &direct_window_list);
 889                 spin_unlock(&direct_window_list_lock);
 890         }
 891
 892         return 0;
 893 }
 894 machine_arch_initcall(pseries, find_existing_ddw_windows);
 895
 896 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 897                         struct ddw_query_response *query)
 898 {
 899         struct device_node *dn;
 900         struct pci_dn *pdn;
 901         u32 cfg_addr;
 902         u64 buid;
 903         int ret;
 904
 905         /*
 906          * Get the config address and phb buid of the PE window.
 907          * Rely on eeh to retrieve this for us.
 908          * Retrieve them from the pci device, not the node with the
 909          * dma-window property
 910          */
 911         dn = pci_device_to_OF_node(dev);
 912         pdn = PCI_DN(dn);
 913         buid = pdn->phb->buid;
 914         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 915
 916         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 917                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 918         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 919                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 920                 BUID_LO(buid), ret);
 921         return ret;
 922 }
 923
 924 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 925                         struct ddw_create_response *create, int page_shift,
 926                         int window_shift)
 927 {
 928         struct device_node *dn;
 929         struct pci_dn *pdn;
 930         u32 cfg_addr;
 931         u64 buid;
 932         int ret;
 933
 934         /*
 935          * Get the config address and phb buid of the PE window.
 936          * Rely on eeh to retrieve this for us.
 937          * Retrieve them from the pci device, not the node with the
 938          * dma-window property
 939          */
 940         dn = pci_device_to_OF_node(dev);
 941         pdn = PCI_DN(dn);
 942         buid = pdn->phb->buid;
 943         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 944
 945         do {
 946                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 947                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
 948                                 cfg_addr, BUID_HI(buid), BUID_LO(buid),
 949                                 page_shift, window_shift);
 950         } while (rtas_busy_delay(ret));
 951         dev_info(&dev->dev,
 952                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 953                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 954                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 955                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 956
 957         return ret;
 958 }
 959
 960 struct failed_ddw_pdn {
 961         struct device_node *pdn;
 962         struct list_head list;
 963 };
 964
 965 static LIST_HEAD(failed_ddw_pdn_list);
 966
 967 /*
 968  * If the PE supports dynamic dma windows, and there is space for a table
 969  * that can map all pages in a linear offset, then setup such a table,
 970  * and record the dma-offset in the struct device.
 971  *
 972  * dev: the pci device we are checking
 973  * pdn: the parent pe node with the ibm,dma_window property
 974  * Future: also check if we can remap the base window for our base page size
 975  *
 976  * returns the dma offset for use by dma_set_mask
 977  */
 978 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
 979 {
 980         int len, ret;
 981         struct ddw_query_response query;
 982         struct ddw_create_response create;
 983         int page_shift;
 984         u64 dma_addr, max_addr;
 985         struct device_node *dn;
 986         u32 ddw_avail[3];
 987         struct direct_window *window;
 988         struct property *win64;
 989         struct dynamic_dma_window_prop *ddwprop;
 990         struct failed_ddw_pdn *fpdn;
 991
 992         mutex_lock(&direct_window_init_mutex);
 993
 994         dma_addr = find_existing_ddw(pdn);
 995         if (dma_addr != 0)
 996                 goto out_unlock;
 997
 998         /*
 999          * If we already went through this for a previous function of
1000          * the same device and failed, we don't want to muck with the
1001          * DMA window again, as it will race with in-flight operations
1002          * and can lead to EEHs. The above mutex protects access to the
1003          * list.
1004          */
1005         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
1006                 if (fpdn->pdn == pdn)
1007                         goto out_unlock;
1008         }
1009
1010         /*
1011          * the ibm,ddw-applicable property holds the tokens for:
1012          * ibm,query-pe-dma-window
1013          * ibm,create-pe-dma-window
1014          * ibm,remove-pe-dma-window
1015          * for the given node in that order.
1016          * the property is actually in the parent, not the PE
1017          */
1018         ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
1019                                          &ddw_avail[0], 3);
1020         if (ret)
1021                 goto out_failed;
1022
1023        /*
1024          * Query if there is a second window of size to map the
1025          * whole partition.  Query returns number of windows, largest
1026          * block assigned to PE (partition endpoint), and two bitmasks
1027          * of page sizes: supported and supported for migrate-dma.
1028          */
1029         dn = pci_device_to_OF_node(dev);
1030         ret = query_ddw(dev, ddw_avail, &query);
1031         if (ret != 0)
1032                 goto out_failed;
1033
1034         if (query.windows_available == 0) {
1035                 /*
1036                  * no additional windows are available for this device.
1037                  * We might be able to reallocate the existing window,
1038                  * trading in for a larger page size.
1039                  */
1040                 dev_dbg(&dev->dev, "no free dynamic windows");
1041                 goto out_failed;
1042         }
1043         if (query.page_size & 4) {
1044                 page_shift = 24; /* 16MB */
1045         } else if (query.page_size & 2) {
1046                 page_shift = 16; /* 64kB */
1047         } else if (query.page_size & 1) {
1048                 page_shift = 12; /* 4kB */
1049         } else {
1050                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1051                           query.page_size);
1052                 goto out_failed;
1053         }
1054         /* verify the window * number of ptes will map the partition */
1055         /* check largest block * page size > max memory hotplug addr */
1056         max_addr = memory_hotplug_max();
1057         if (query.largest_available_block < (max_addr >> page_shift)) {
1058                 dev_dbg(&dev->dev, "can't map partition max 0x%llx with %u "
1059                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
1060                           1ULL << page_shift);
1061                 goto out_failed;
1062         }
1063         len = order_base_2(max_addr);
1064         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1065         if (!win64) {
1066                 dev_info(&dev->dev,
1067                         "couldn't allocate property for 64bit dma window\n");
1068                 goto out_failed;
1069         }
1070         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1071         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1072         win64->length = sizeof(*ddwprop);
1073         if (!win64->name || !win64->value) {
1074                 dev_info(&dev->dev,
1075                         "couldn't allocate property name and value\n");
1076                 goto out_free_prop;
1077         }
1078
1079         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1080         if (ret != 0)
1081                 goto out_free_prop;
1082
1083         ddwprop->liobn = cpu_to_be32(create.liobn);
1084         ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1085                         create.addr_lo);
1086         ddwprop->tce_shift = cpu_to_be32(page_shift);
1087         ddwprop->window_shift = cpu_to_be32(len);
1088
1089         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %pOF\n",
1090                   create.liobn, dn);
1091
1092         window = kzalloc(sizeof(*window), GFP_KERNEL);
1093         if (!window)
1094                 goto out_clear_window;
1095
1096         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1097                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1098         if (ret) {
1099                 dev_info(&dev->dev, "failed to map direct window for %pOF: %d\n",
1100                          dn, ret);
1101                 goto out_free_window;
1102         }
1103
1104         ret = of_add_property(pdn, win64);
1105         if (ret) {
1106                 dev_err(&dev->dev, "unable to add dma window property for %pOF: %d",
1107                          pdn, ret);
1108                 goto out_free_window;
1109         }
1110
1111         window->device = pdn;
1112         window->prop = ddwprop;
1113         spin_lock(&direct_window_list_lock);
1114         list_add(&window->list, &direct_window_list);
1115         spin_unlock(&direct_window_list_lock);
1116
1117         dma_addr = be64_to_cpu(ddwprop->dma_base);
1118         goto out_unlock;
1119
1120 out_free_window:
1121         kfree(window);
1122
1123 out_clear_window:
1124         remove_ddw(pdn, true);
1125
1126 out_free_prop:
1127         kfree(win64->name);
1128         kfree(win64->value);
1129         kfree(win64);
1130
1131 out_failed:
1132
1133         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1134         if (!fpdn)
1135                 goto out_unlock;
1136         fpdn->pdn = pdn;
1137         list_add(&fpdn->list, &failed_ddw_pdn_list);
1138
1139 out_unlock:
1140         mutex_unlock(&direct_window_init_mutex);
1141         return dma_addr;
1142 }
1143
1144 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1145 {
1146         struct device_node *pdn, *dn;
1147         struct iommu_table *tbl;
1148         const __be32 *dma_window = NULL;
1149         struct pci_dn *pci;
1150
1151         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1152
1153         /* dev setup for LPAR is a little tricky, since the device tree might
1154          * contain the dma-window properties per-device and not necessarily
1155          * for the bus. So we need to search upwards in the tree until we
1156          * either hit a dma-window property, OR find a parent with a table
1157          * already allocated.
1158          */
1159         dn = pci_device_to_OF_node(dev);
1160         pr_debug("  node is %pOF\n", dn);
1161
1162         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1163              pdn = pdn->parent) {
1164                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1165                 if (dma_window)
1166                         break;
1167         }
1168
1169         if (!pdn || !PCI_DN(pdn)) {
1170                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1171                        "no DMA window found for pci dev=%s dn=%pOF\n",
1172                                  pci_name(dev), dn);
1173                 return;
1174         }
1175         pr_debug("  parent is %pOF\n", pdn);
1176
1177         pci = PCI_DN(pdn);
1178         if (!pci->table_group) {
1179                 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
1180                 tbl = pci->table_group->tables[0];
1181                 iommu_table_setparms_lpar(pci->phb, pdn, tbl,
1182                                 pci->table_group, dma_window);
1183                 tbl->it_ops = &iommu_table_lpar_multi_ops;
1184                 iommu_init_table(tbl, pci->phb->node);
1185                 iommu_register_group(pci->table_group,
1186                                 pci_domain_nr(pci->phb->bus), 0);
1187                 pr_debug("  created table: %p\n", pci->table_group);
1188         } else {
1189                 pr_debug("  found DMA window, table: %p\n", pci->table_group);
1190         }
1191
1192         set_iommu_table_base(&dev->dev, pci->table_group->tables[0]);
1193         iommu_add_device(&dev->dev);
1194 }
1195
1196 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1197 {
1198         bool ddw_enabled = false;
1199         struct device_node *pdn, *dn;
1200         struct pci_dev *pdev;
1201         const __be32 *dma_window = NULL;
1202         u64 dma_offset;
1203
1204         if (!dev->dma_mask)
1205                 return -EIO;
1206
1207         if (!dev_is_pci(dev))
1208                 goto check_mask;
1209
1210         pdev = to_pci_dev(dev);
1211
1212         /* only attempt to use a new window if 64-bit DMA is requested */
1213         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1214                 dn = pci_device_to_OF_node(pdev);
1215                 dev_dbg(dev, "node is %pOF\n", dn);
1216
1217                 /*
1218                  * the device tree might contain the dma-window properties
1219                  * per-device and not necessarily for the bus. So we need to
1220                  * search upwards in the tree until we either hit a dma-window
1221                  * property, OR find a parent with a table already allocated.
1222                  */
1223                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1224                                 pdn = pdn->parent) {
1225                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1226                         if (dma_window)
1227                                 break;
1228                 }
1229                 if (pdn && PCI_DN(pdn)) {
1230                         dma_offset = enable_ddw(pdev, pdn);
1231                         if (dma_offset != 0) {
1232                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1233                                 set_dma_offset(dev, dma_offset);
1234                                 set_dma_ops(dev, &dma_nommu_ops);
1235                                 ddw_enabled = true;
1236                         }
1237                 }
1238         }
1239
1240         /* fall back on iommu ops */
1241         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1242                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1243                 set_dma_ops(dev, &dma_iommu_ops);
1244         }
1245
1246 check_mask:
1247         if (!dma_supported(dev, dma_mask))
1248                 return -EIO;
1249
1250         *dev->dma_mask = dma_mask;
1251         return 0;
1252 }
1253
1254 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1255 {
1256         if (!dev->dma_mask)
1257                 return 0;
1258
1259         if (!disable_ddw && dev_is_pci(dev)) {
1260                 struct pci_dev *pdev = to_pci_dev(dev);
1261                 struct device_node *dn;
1262
1263                 dn = pci_device_to_OF_node(pdev);
1264
1265                 /* search upwards for ibm,dma-window */
1266                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->table_group;
1267                                 dn = dn->parent)
1268                         if (of_get_property(dn, "ibm,dma-window", NULL))
1269                                 break;
1270                 /* if there is a ibm,ddw-applicable property require 64 bits */
1271                 if (dn && PCI_DN(dn) &&
1272                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1273                         return DMA_BIT_MASK(64);
1274         }
1275
1276         return dma_iommu_ops.get_required_mask(dev);
1277 }
1278
1279 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1280                 void *data)
1281 {
1282         struct direct_window *window;
1283         struct memory_notify *arg = data;
1284         int ret = 0;
1285
1286         switch (action) {
1287         case MEM_GOING_ONLINE:
1288                 spin_lock(&direct_window_list_lock);
1289                 list_for_each_entry(window, &direct_window_list, list) {
1290                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1291                                         arg->nr_pages, window->prop);
1292                         /* XXX log error */
1293                 }
1294                 spin_unlock(&direct_window_list_lock);
1295                 break;
1296         case MEM_CANCEL_ONLINE:
1297         case MEM_OFFLINE:
1298                 spin_lock(&direct_window_list_lock);
1299                 list_for_each_entry(window, &direct_window_list, list) {
1300                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1301                                         arg->nr_pages, window->prop);
1302                         /* XXX log error */
1303                 }
1304                 spin_unlock(&direct_window_list_lock);
1305                 break;
1306         default:
1307                 break;
1308         }
1309         if (ret && action != MEM_CANCEL_ONLINE)
1310                 return NOTIFY_BAD;
1311
1312         return NOTIFY_OK;
1313 }
1314
1315 static struct notifier_block iommu_mem_nb = {
1316         .notifier_call = iommu_mem_notifier,
1317 };
1318
1319 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
1320 {
1321         int err = NOTIFY_OK;
1322         struct of_reconfig_data *rd = data;
1323         struct device_node *np = rd->dn;
1324         struct pci_dn *pci = PCI_DN(np);
1325         struct direct_window *window;
1326
1327         switch (action) {
1328         case OF_RECONFIG_DETACH_NODE:
1329                 /*
1330                  * Removing the property will invoke the reconfig
1331                  * notifier again, which causes dead-lock on the
1332                  * read-write semaphore of the notifier chain. So
1333                  * we have to remove the property when releasing
1334                  * the device node.
1335                  */
1336                 remove_ddw(np, false);
1337                 if (pci && pci->table_group)
1338                         iommu_pseries_free_group(pci->table_group,
1339                                         np->full_name);
1340
1341                 spin_lock(&direct_window_list_lock);
1342                 list_for_each_entry(window, &direct_window_list, list) {
1343                         if (window->device == np) {
1344                                 list_del(&window->list);
1345                                 kfree(window);
1346                                 break;
1347                         }
1348                 }
1349                 spin_unlock(&direct_window_list_lock);
1350                 break;
1351         default:
1352                 err = NOTIFY_DONE;
1353                 break;
1354         }
1355         return err;
1356 }
1357
1358 static struct notifier_block iommu_reconfig_nb = {
1359         .notifier_call = iommu_reconfig_notifier,
1360 };
1361
1362 /* These are called very early. */
1363 void iommu_init_early_pSeries(void)
1364 {
1365         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1366                 return;
1367
1368         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1369                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1370                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1371                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1372                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1373         } else {
1374                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1375                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1376         }
1377
1378
1379         of_reconfig_notifier_register(&iommu_reconfig_nb);
1380         register_memory_notifier(&iommu_mem_nb);
1381
1382         set_pci_dma_ops(&dma_iommu_ops);
1383 }
1384
1385 static int __init disable_multitce(char *str)
1386 {
1387         if (strcmp(str, "off") == 0 &&
1388             firmware_has_feature(FW_FEATURE_LPAR) &&
1389             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1390                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1391                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1392         }
1393         return 1;
1394 }
1395
1396 __setup("multitce=", disable_multitce);
1397
1398 machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);