arch/powerpc/platforms/powernv/opal-imc.c

   1 /*
   2  * OPAL IMC interface detection driver
   3  * Supported on POWERNV platform
   4  *
   5  * Copyright    (C) 2017 Madhavan Srinivasan, IBM Corporation.
   6  *              (C) 2017 Anju T Sudhakar, IBM Corporation.
   7  *              (C) 2017 Hemant K Shaw, IBM Corporation.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or later version.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/crash_dump.h>
  20 #include <asm/opal.h>
  21 #include <asm/io.h>
  22 #include <asm/imc-pmu.h>
  23 #include <asm/cputhreads.h>
  24
  25 /*
  26  * imc_get_mem_addr_nest: Function to get nest counter memory region
  27  * for each chip
  28  */
  29 static int imc_get_mem_addr_nest(struct device_node *node,
  30                                  struct imc_pmu *pmu_ptr,
  31                                  u32 offset)
  32 {
  33         int nr_chips = 0, i;
  34         u64 *base_addr_arr, baddr;
  35         u32 *chipid_arr;
  36
  37         nr_chips = of_property_count_u32_elems(node, "chip-id");
  38         if (nr_chips <= 0)
  39                 return -ENODEV;
  40
  41         base_addr_arr = kcalloc(nr_chips, sizeof(u64), GFP_KERNEL);
  42         if (!base_addr_arr)
  43                 return -ENOMEM;
  44
  45         chipid_arr = kcalloc(nr_chips, sizeof(u32), GFP_KERNEL);
  46         if (!chipid_arr)
  47                 return -ENOMEM;
  48
  49         if (of_property_read_u32_array(node, "chip-id", chipid_arr, nr_chips))
  50                 goto error;
  51
  52         if (of_property_read_u64_array(node, "base-addr", base_addr_arr,
  53                                                                 nr_chips))
  54                 goto error;
  55
  56         pmu_ptr->mem_info = kcalloc(nr_chips, sizeof(struct imc_mem_info),
  57                                                                 GFP_KERNEL);
  58         if (!pmu_ptr->mem_info)
  59                 goto error;
  60
  61         for (i = 0; i < nr_chips; i++) {
  62                 pmu_ptr->mem_info[i].id = chipid_arr[i];
  63                 baddr = base_addr_arr[i] + offset;
  64                 pmu_ptr->mem_info[i].vbase = phys_to_virt(baddr);
  65         }
  66
  67         pmu_ptr->imc_counter_mmaped = true;
  68         kfree(base_addr_arr);
  69         kfree(chipid_arr);
  70         return 0;
  71
  72 error:
  73         kfree(pmu_ptr->mem_info);
  74         kfree(base_addr_arr);
  75         kfree(chipid_arr);
  76         return -1;
  77 }
  78
  79 /*
  80  * imc_pmu_create : Takes the parent device which is the pmu unit, pmu_index
  81  *                  and domain as the inputs.
  82  * Allocates memory for the struct imc_pmu, sets up its domain, size and offsets
  83  */
  84 static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain)
  85 {
  86         int ret = 0;
  87         struct imc_pmu *pmu_ptr;
  88         u32 offset;
  89
  90         /* memory for pmu */
  91         pmu_ptr = kzalloc(sizeof(struct imc_pmu), GFP_KERNEL);
  92         if (!pmu_ptr)
  93                 return -ENOMEM;
  94
  95         /* Set the domain */
  96         pmu_ptr->domain = domain;
  97
  98         ret = of_property_read_u32(parent, "size", &pmu_ptr->counter_mem_size);
  99         if (ret) {
 100                 ret = -EINVAL;
 101                 goto free_pmu;
 102         }
 103
 104         if (!of_property_read_u32(parent, "offset", &offset)) {
 105                 if (imc_get_mem_addr_nest(parent, pmu_ptr, offset)) {
 106                         ret = -EINVAL;
 107                         goto free_pmu;
 108                 }
 109         }
 110
 111         /* Function to register IMC pmu */
 112         ret = init_imc_pmu(parent, pmu_ptr, pmu_index);
 113         if (ret)
 114                 pr_err("IMC PMU %s Register failed\n", pmu_ptr->pmu.name);
 115
 116         return 0;
 117
 118 free_pmu:
 119         kfree(pmu_ptr);
 120         return ret;
 121 }
 122
 123 static void disable_nest_pmu_counters(void)
 124 {
 125         int nid, cpu;
 126         const struct cpumask *l_cpumask;
 127
 128         get_online_cpus();
 129         for_each_online_node(nid) {
 130                 l_cpumask = cpumask_of_node(nid);
 131                 cpu = cpumask_first(l_cpumask);
 132                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
 133                                        get_hard_smp_processor_id(cpu));
 134         }
 135         put_online_cpus();
 136 }
 137
 138 static void disable_core_pmu_counters(void)
 139 {
 140         cpumask_t cores_map;
 141         int cpu, rc;
 142
 143         get_online_cpus();
 144         /* Disable the IMC Core functions */
 145         cores_map = cpu_online_cores_map();
 146         for_each_cpu(cpu, &cores_map) {
 147                 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
 148                                             get_hard_smp_processor_id(cpu));
 149                 if (rc)
 150                         pr_err("%s: Failed to stop Core (cpu = %d)\n",
 151                                 __FUNCTION__, cpu);
 152         }
 153         put_online_cpus();
 154 }
 155
 156 int get_max_nest_dev(void)
 157 {
 158         struct device_node *node;
 159         u32 pmu_units = 0, type;
 160
 161         for_each_compatible_node(node, NULL, IMC_DTB_UNIT_COMPAT) {
 162                 if (of_property_read_u32(node, "type", &type))
 163                         continue;
 164
 165                 if (type == IMC_TYPE_CHIP)
 166                         pmu_units++;
 167         }
 168
 169         return pmu_units;
 170 }
 171
 172 static int opal_imc_counters_probe(struct platform_device *pdev)
 173 {
 174         struct device_node *imc_dev = pdev->dev.of_node;
 175         int pmu_count = 0, domain;
 176         u32 type;
 177
 178         /*
 179          * Check whether this is kdump kernel. If yes, force the engines to
 180          * stop and return.
 181          */
 182         if (is_kdump_kernel()) {
 183                 disable_nest_pmu_counters();
 184                 disable_core_pmu_counters();
 185                 return -ENODEV;
 186         }
 187
 188         for_each_compatible_node(imc_dev, NULL, IMC_DTB_UNIT_COMPAT) {
 189                 if (of_property_read_u32(imc_dev, "type", &type)) {
 190                         pr_warn("IMC Device without type property\n");
 191                         continue;
 192                 }
 193
 194                 switch (type) {
 195                 case IMC_TYPE_CHIP:
 196                         domain = IMC_DOMAIN_NEST;
 197                         break;
 198                 case IMC_TYPE_CORE:
 199                         domain =IMC_DOMAIN_CORE;
 200                         break;
 201                 case IMC_TYPE_THREAD:
 202                         domain = IMC_DOMAIN_THREAD;
 203                         break;
 204                 default:
 205                         pr_warn("IMC Unknown Device type \n");
 206                         domain = -1;
 207                         break;
 208                 }
 209
 210                 if (!imc_pmu_create(imc_dev, pmu_count, domain)) {
 211                         if (domain == IMC_DOMAIN_NEST)
 212                                 pmu_count++;
 213                 }
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void opal_imc_counters_shutdown(struct platform_device *pdev)
 220 {
 221         /*
 222          * Function only stops the engines which is bare minimum.
 223          * TODO: Need to handle proper memory cleanup and pmu
 224          * unregister.
 225          */
 226         disable_nest_pmu_counters();
 227         disable_core_pmu_counters();
 228 }
 229
 230 static const struct of_device_id opal_imc_match[] = {
 231         { .compatible = IMC_DTB_COMPAT },
 232         {},
 233 };
 234
 235 static struct platform_driver opal_imc_driver = {
 236         .driver = {
 237                 .name = "opal-imc-counters",
 238                 .of_match_table = opal_imc_match,
 239         },
 240         .probe = opal_imc_counters_probe,
 241         .shutdown = opal_imc_counters_shutdown,
 242 };
 243
 244 builtin_platform_driver(opal_imc_driver);