arch/powerpc/platforms/powermac/smp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * SMP support for power macintosh.
   4  *
   5  * We support both the old "powersurge" SMP architecture
   6  * and the current Core99 (G4 PowerMac) machines.
   7  *
   8  * Note that we don't support the very first rev. of
   9  * Apple/DayStar 2 CPUs board, the one with the funky
  10  * watchdog. Hopefully, none of these should be there except
  11  * maybe internally to Apple. I should probably still add some
  12  * code to detect this card though and disable SMP. --BenH.
  13  *
  14  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  15  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  16  *
  17  * Support for DayStar quad CPU cards
  18  * Copyright (C) XLR8, Inc. 1994-2000
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/sched/hotplug.h>
  23 #include <linux/smp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel_stat.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/errno.h>
  30 #include <linux/hardirq.h>
  31 #include <linux/cpu.h>
  32 #include <linux/compiler.h>
  33 #include <linux/pgtable.h>
  34
  35 #include <asm/ptrace.h>
  36 #include <linux/atomic.h>
  37 #include <asm/code-patching.h>
  38 #include <asm/irq.h>
  39 #include <asm/page.h>
  40 #include <asm/sections.h>
  41 #include <asm/io.h>
  42 #include <asm/prom.h>
  43 #include <asm/smp.h>
  44 #include <asm/machdep.h>
  45 #include <asm/pmac_feature.h>
  46 #include <asm/time.h>
  47 #include <asm/mpic.h>
  48 #include <asm/cacheflush.h>
  49 #include <asm/keylargo.h>
  50 #include <asm/pmac_low_i2c.h>
  51 #include <asm/pmac_pfunc.h>
  52 #include <asm/inst.h>
  53
  54 #include "pmac.h"
  55
  56 #undef DEBUG
  57
  58 #ifdef DEBUG
  59 #define DBG(fmt...) udbg_printf(fmt)
  60 #else
  61 #define DBG(fmt...)
  62 #endif
  63
  64 extern void __secondary_start_pmac_0(void);
  65
  66 static void (*pmac_tb_freeze)(int freeze);
  67 static u64 timebase;
  68 static int tb_req;
  69
  70 #ifdef CONFIG_PPC_PMAC32_PSURGE
  71
  72 /*
  73  * Powersurge (old powermac SMP) support.
  74  */
  75
  76 /* Addresses for powersurge registers */
  77 #define HAMMERHEAD_BASE         0xf8000000
  78 #define HHEAD_CONFIG            0x90
  79 #define HHEAD_SEC_INTR          0xc0
  80
  81 /* register for interrupting the primary processor on the powersurge */
  82 /* N.B. this is actually the ethernet ROM! */
  83 #define PSURGE_PRI_INTR         0xf3019000
  84
  85 /* register for storing the start address for the secondary processor */
  86 /* N.B. this is the PCI config space address register for the 1st bridge */
  87 #define PSURGE_START            0xf2800000
  88
  89 /* Daystar/XLR8 4-CPU card */
  90 #define PSURGE_QUAD_REG_ADDR    0xf8800000
  91
  92 #define PSURGE_QUAD_IRQ_SET     0
  93 #define PSURGE_QUAD_IRQ_CLR     1
  94 #define PSURGE_QUAD_IRQ_PRIMARY 2
  95 #define PSURGE_QUAD_CKSTOP_CTL  3
  96 #define PSURGE_QUAD_PRIMARY_ARB 4
  97 #define PSURGE_QUAD_BOARD_ID    6
  98 #define PSURGE_QUAD_WHICH_CPU   7
  99 #define PSURGE_QUAD_CKSTOP_RDBK 8
 100 #define PSURGE_QUAD_RESET_CTL   11
 101
 102 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
 103 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
 104 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
 105 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
 106
 107 /* virtual addresses for the above */
 108 static volatile u8 __iomem *hhead_base;
 109 static volatile u8 __iomem *quad_base;
 110 static volatile u32 __iomem *psurge_pri_intr;
 111 static volatile u8 __iomem *psurge_sec_intr;
 112 static volatile u32 __iomem *psurge_start;
 113
 114 /* values for psurge_type */
 115 #define PSURGE_NONE             -1
 116 #define PSURGE_DUAL             0
 117 #define PSURGE_QUAD_OKEE        1
 118 #define PSURGE_QUAD_COTTON      2
 119 #define PSURGE_QUAD_ICEGRASS    3
 120
 121 /* what sort of powersurge board we have */
 122 static int psurge_type = PSURGE_NONE;
 123
 124 /* irq for secondary cpus to report */
 125 static struct irq_domain *psurge_host;
 126 int psurge_secondary_virq;
 127
 128 /*
 129  * Set and clear IPIs for powersurge.
 130  */
 131 static inline void psurge_set_ipi(int cpu)
 132 {
 133         if (psurge_type == PSURGE_NONE)
 134                 return;
 135         if (cpu == 0)
 136                 in_be32(psurge_pri_intr);
 137         else if (psurge_type == PSURGE_DUAL)
 138                 out_8(psurge_sec_intr, 0);
 139         else
 140                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
 141 }
 142
 143 static inline void psurge_clr_ipi(int cpu)
 144 {
 145         if (cpu > 0) {
 146                 switch(psurge_type) {
 147                 case PSURGE_DUAL:
 148                         out_8(psurge_sec_intr, ~0);
 149                         break;
 150                 case PSURGE_NONE:
 151                         break;
 152                 default:
 153                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
 154                 }
 155         }
 156 }
 157
 158 /*
 159  * On powersurge (old SMP powermac architecture) we don't have
 160  * separate IPIs for separate messages like openpic does.  Instead
 161  * use the generic demux helpers
 162  *  -- paulus.
 163  */
 164 static irqreturn_t psurge_ipi_intr(int irq, void *d)
 165 {
 166         psurge_clr_ipi(smp_processor_id());
 167         smp_ipi_demux();
 168
 169         return IRQ_HANDLED;
 170 }
 171
 172 static void smp_psurge_cause_ipi(int cpu)
 173 {
 174         psurge_set_ipi(cpu);
 175 }
 176
 177 static int psurge_host_map(struct irq_domain *h, unsigned int virq,
 178                          irq_hw_number_t hw)
 179 {
 180         irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq);
 181
 182         return 0;
 183 }
 184
 185 static const struct irq_domain_ops psurge_host_ops = {
 186         .map    = psurge_host_map,
 187 };
 188
 189 static int psurge_secondary_ipi_init(void)
 190 {
 191         int rc = -ENOMEM;
 192
 193         psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL);
 194
 195         if (psurge_host)
 196                 psurge_secondary_virq = irq_create_direct_mapping(psurge_host);
 197
 198         if (psurge_secondary_virq)
 199                 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr,
 200                         IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL);
 201
 202         if (rc)
 203                 pr_err("Failed to setup secondary cpu IPI\n");
 204
 205         return rc;
 206 }
 207
 208 /*
 209  * Determine a quad card presence. We read the board ID register, we
 210  * force the data bus to change to something else, and we read it again.
 211  * It it's stable, then the register probably exist (ugh !)
 212  */
 213 static int __init psurge_quad_probe(void)
 214 {
 215         int type;
 216         unsigned int i;
 217
 218         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
 219         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
 220             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 221                 return PSURGE_DUAL;
 222
 223         /* looks OK, try a slightly more rigorous test */
 224         /* bogus is not necessarily cacheline-aligned,
 225            though I don't suppose that really matters.  -- paulus */
 226         for (i = 0; i < 100; i++) {
 227                 volatile u32 bogus[8];
 228                 bogus[(0+i)%8] = 0x00000000;
 229                 bogus[(1+i)%8] = 0x55555555;
 230                 bogus[(2+i)%8] = 0xFFFFFFFF;
 231                 bogus[(3+i)%8] = 0xAAAAAAAA;
 232                 bogus[(4+i)%8] = 0x33333333;
 233                 bogus[(5+i)%8] = 0xCCCCCCCC;
 234                 bogus[(6+i)%8] = 0xCCCCCCCC;
 235                 bogus[(7+i)%8] = 0x33333333;
 236                 wmb();
 237                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
 238                 mb();
 239                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 240                         return PSURGE_DUAL;
 241         }
 242         return type;
 243 }
 244
 245 static void __init psurge_quad_init(void)
 246 {
 247         int procbits;
 248
 249         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
 250         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
 251         if (psurge_type == PSURGE_QUAD_ICEGRASS)
 252                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 253         else
 254                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
 255         mdelay(33);
 256         out_8(psurge_sec_intr, ~0);
 257         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
 258         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 259         if (psurge_type != PSURGE_QUAD_ICEGRASS)
 260                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
 261         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
 262         mdelay(33);
 263         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
 264         mdelay(33);
 265         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
 266         mdelay(33);
 267 }
 268
 269 static void __init smp_psurge_probe(void)
 270 {
 271         int i, ncpus;
 272         struct device_node *dn;
 273
 274         /*
 275          * The powersurge cpu board can be used in the generation
 276          * of powermacs that have a socket for an upgradeable cpu card,
 277          * including the 7500, 8500, 9500, 9600.
 278          * The device tree doesn't tell you if you have 2 cpus because
 279          * OF doesn't know anything about the 2nd processor.
 280          * Instead we look for magic bits in magic registers,
 281          * in the hammerhead memory controller in the case of the
 282          * dual-cpu powersurge board.  -- paulus.
 283          */
 284         dn = of_find_node_by_name(NULL, "hammerhead");
 285         if (dn == NULL)
 286                 return;
 287         of_node_put(dn);
 288
 289         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
 290         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
 291         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
 292
 293         psurge_type = psurge_quad_probe();
 294         if (psurge_type != PSURGE_DUAL) {
 295                 psurge_quad_init();
 296                 /* All released cards using this HW design have 4 CPUs */
 297                 ncpus = 4;
 298                 /* No sure how timebase sync works on those, let's use SW */
 299                 smp_ops->give_timebase = smp_generic_give_timebase;
 300                 smp_ops->take_timebase = smp_generic_take_timebase;
 301         } else {
 302                 iounmap(quad_base);
 303                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
 304                         /* not a dual-cpu card */
 305                         iounmap(hhead_base);
 306                         psurge_type = PSURGE_NONE;
 307                         return;
 308                 }
 309                 ncpus = 2;
 310         }
 311
 312         if (psurge_secondary_ipi_init())
 313                 return;
 314
 315         psurge_start = ioremap(PSURGE_START, 4);
 316         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
 317
 318         /* This is necessary because OF doesn't know about the
 319          * secondary cpu(s), and thus there aren't nodes in the
 320          * device tree for them, and smp_setup_cpu_maps hasn't
 321          * set their bits in cpu_present_mask.
 322          */
 323         if (ncpus > NR_CPUS)
 324                 ncpus = NR_CPUS;
 325         for (i = 1; i < ncpus ; ++i)
 326                 set_cpu_present(i, true);
 327
 328         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
 329 }
 330
 331 static int __init smp_psurge_kick_cpu(int nr)
 332 {
 333         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
 334         unsigned long a, flags;
 335         int i, j;
 336
 337         /* Defining this here is evil ... but I prefer hiding that
 338          * crap to avoid giving people ideas that they can do the
 339          * same.
 340          */
 341         extern volatile unsigned int cpu_callin_map[NR_CPUS];
 342
 343         /* may need to flush here if secondary bats aren't setup */
 344         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
 345                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
 346         asm volatile("sync");
 347
 348         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
 349
 350         /* This is going to freeze the timeebase, we disable interrupts */
 351         local_irq_save(flags);
 352
 353         out_be32(psurge_start, start);
 354         mb();
 355
 356         psurge_set_ipi(nr);
 357
 358         /*
 359          * We can't use udelay here because the timebase is now frozen.
 360          */
 361         for (i = 0; i < 2000; ++i)
 362                 asm volatile("nop" : : : "memory");
 363         psurge_clr_ipi(nr);
 364
 365         /*
 366          * Also, because the timebase is frozen, we must not return to the
 367          * caller which will try to do udelay's etc... Instead, we wait -here-
 368          * for the CPU to callin.
 369          */
 370         for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
 371                 for (j = 1; j < 10000; j++)
 372                         asm volatile("nop" : : : "memory");
 373                 asm volatile("sync" : : : "memory");
 374         }
 375         if (!cpu_callin_map[nr])
 376                 goto stuck;
 377
 378         /* And we do the TB sync here too for standard dual CPU cards */
 379         if (psurge_type == PSURGE_DUAL) {
 380                 while(!tb_req)
 381                         barrier();
 382                 tb_req = 0;
 383                 mb();
 384                 timebase = get_tb();
 385                 mb();
 386                 while (timebase)
 387                         barrier();
 388                 mb();
 389         }
 390  stuck:
 391         /* now interrupt the secondary, restarting both TBs */
 392         if (psurge_type == PSURGE_DUAL)
 393                 psurge_set_ipi(1);
 394
 395         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
 396
 397         return 0;
 398 }
 399
 400 static void __init smp_psurge_setup_cpu(int cpu_nr)
 401 {
 402         unsigned long flags = IRQF_PERCPU | IRQF_NO_THREAD;
 403         int irq;
 404
 405         if (cpu_nr != 0 || !psurge_start)
 406                 return;
 407
 408         /* reset the entry point so if we get another intr we won't
 409          * try to startup again */
 410         out_be32(psurge_start, 0x100);
 411         irq = irq_create_mapping(NULL, 30);
 412         if (request_irq(irq, psurge_ipi_intr, flags, "primary IPI", NULL))
 413                 printk(KERN_ERR "Couldn't get primary IPI interrupt");
 414 }
 415
 416 void __init smp_psurge_take_timebase(void)
 417 {
 418         if (psurge_type != PSURGE_DUAL)
 419                 return;
 420
 421         tb_req = 1;
 422         mb();
 423         while (!timebase)
 424                 barrier();
 425         mb();
 426         set_tb(timebase >> 32, timebase & 0xffffffff);
 427         timebase = 0;
 428         mb();
 429         set_dec(tb_ticks_per_jiffy/2);
 430 }
 431
 432 void __init smp_psurge_give_timebase(void)
 433 {
 434         /* Nothing to do here */
 435 }
 436
 437 /* PowerSurge-style Macs */
 438 struct smp_ops_t psurge_smp_ops = {
 439         .message_pass   = NULL, /* Use smp_muxed_ipi_message_pass */
 440         .cause_ipi      = smp_psurge_cause_ipi,
 441         .cause_nmi_ipi  = NULL,
 442         .probe          = smp_psurge_probe,
 443         .kick_cpu       = smp_psurge_kick_cpu,
 444         .setup_cpu      = smp_psurge_setup_cpu,
 445         .give_timebase  = smp_psurge_give_timebase,
 446         .take_timebase  = smp_psurge_take_timebase,
 447 };
 448 #endif /* CONFIG_PPC_PMAC32_PSURGE */
 449
 450 /*
 451  * Core 99 and later support
 452  */
 453
 454
 455 static void smp_core99_give_timebase(void)
 456 {
 457         unsigned long flags;
 458
 459         local_irq_save(flags);
 460
 461         while(!tb_req)
 462                 barrier();
 463         tb_req = 0;
 464         (*pmac_tb_freeze)(1);
 465         mb();
 466         timebase = get_tb();
 467         mb();
 468         while (timebase)
 469                 barrier();
 470         mb();
 471         (*pmac_tb_freeze)(0);
 472         mb();
 473
 474         local_irq_restore(flags);
 475 }
 476
 477
 478 static void smp_core99_take_timebase(void)
 479 {
 480         unsigned long flags;
 481
 482         local_irq_save(flags);
 483
 484         tb_req = 1;
 485         mb();
 486         while (!timebase)
 487                 barrier();
 488         mb();
 489         set_tb(timebase >> 32, timebase & 0xffffffff);
 490         timebase = 0;
 491         mb();
 492
 493         local_irq_restore(flags);
 494 }
 495
 496 #ifdef CONFIG_PPC64
 497 /*
 498  * G5s enable/disable the timebase via an i2c-connected clock chip.
 499  */
 500 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
 501 static u8 pmac_tb_pulsar_addr;
 502
 503 static void smp_core99_cypress_tb_freeze(int freeze)
 504 {
 505         u8 data;
 506         int rc;
 507
 508         /* Strangely, the device-tree says address is 0xd2, but darwin
 509          * accesses 0xd0 ...
 510          */
 511         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 512                          pmac_i2c_mode_combined);
 513         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 514                            0xd0 | pmac_i2c_read,
 515                            1, 0x81, &data, 1);
 516         if (rc != 0)
 517                 goto bail;
 518
 519         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
 520
 521         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 522         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 523                            0xd0 | pmac_i2c_write,
 524                            1, 0x81, &data, 1);
 525
 526  bail:
 527         if (rc != 0) {
 528                 printk("Cypress Timebase %s rc: %d\n",
 529                        freeze ? "freeze" : "unfreeze", rc);
 530                 panic("Timebase freeze failed !\n");
 531         }
 532 }
 533
 534
 535 static void smp_core99_pulsar_tb_freeze(int freeze)
 536 {
 537         u8 data;
 538         int rc;
 539
 540         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 541                          pmac_i2c_mode_combined);
 542         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 543                            pmac_tb_pulsar_addr | pmac_i2c_read,
 544                            1, 0x2e, &data, 1);
 545         if (rc != 0)
 546                 goto bail;
 547
 548         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
 549
 550         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 551         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 552                            pmac_tb_pulsar_addr | pmac_i2c_write,
 553                            1, 0x2e, &data, 1);
 554  bail:
 555         if (rc != 0) {
 556                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
 557                        freeze ? "freeze" : "unfreeze", rc);
 558                 panic("Timebase freeze failed !\n");
 559         }
 560 }
 561
 562 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
 563 {
 564         struct device_node *cc = NULL;
 565         struct device_node *p;
 566         const char *name = NULL;
 567         const u32 *reg;
 568         int ok;
 569
 570         /* Look for the clock chip */
 571         for_each_node_by_name(cc, "i2c-hwclock") {
 572                 p = of_get_parent(cc);
 573                 ok = p && of_device_is_compatible(p, "uni-n-i2c");
 574                 of_node_put(p);
 575                 if (!ok)
 576                         continue;
 577
 578                 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
 579                 if (pmac_tb_clock_chip_host == NULL)
 580                         continue;
 581                 reg = of_get_property(cc, "reg", NULL);
 582                 if (reg == NULL)
 583                         continue;
 584                 switch (*reg) {
 585                 case 0xd2:
 586                         if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
 587                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 588                                 pmac_tb_pulsar_addr = 0xd2;
 589                                 name = "Pulsar";
 590                         } else if (of_device_is_compatible(cc, "cy28508")) {
 591                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
 592                                 name = "Cypress";
 593                         }
 594                         break;
 595                 case 0xd4:
 596                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 597                         pmac_tb_pulsar_addr = 0xd4;
 598                         name = "Pulsar";
 599                         break;
 600                 }
 601                 if (pmac_tb_freeze != NULL)
 602                         break;
 603         }
 604         if (pmac_tb_freeze != NULL) {
 605                 /* Open i2c bus for synchronous access */
 606                 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
 607                         printk(KERN_ERR "Failed top open i2c bus for clock"
 608                                " sync, fallback to software sync !\n");
 609                         goto no_i2c_sync;
 610                 }
 611                 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
 612                        name);
 613                 return;
 614         }
 615  no_i2c_sync:
 616         pmac_tb_freeze = NULL;
 617         pmac_tb_clock_chip_host = NULL;
 618 }
 619
 620
 621
 622 /*
 623  * Newer G5s uses a platform function
 624  */
 625
 626 static void smp_core99_pfunc_tb_freeze(int freeze)
 627 {
 628         struct device_node *cpus;
 629         struct pmf_args args;
 630
 631         cpus = of_find_node_by_path("/cpus");
 632         BUG_ON(cpus == NULL);
 633         args.count = 1;
 634         args.u[0].v = !freeze;
 635         pmf_call_function(cpus, "cpu-timebase", &args);
 636         of_node_put(cpus);
 637 }
 638
 639 #else /* CONFIG_PPC64 */
 640
 641 /*
 642  * SMP G4 use a GPIO to enable/disable the timebase.
 643  */
 644
 645 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
 646
 647 static void smp_core99_gpio_tb_freeze(int freeze)
 648 {
 649         if (freeze)
 650                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
 651         else
 652                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
 653         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 654 }
 655
 656
 657 #endif /* !CONFIG_PPC64 */
 658
 659 static void core99_init_caches(int cpu)
 660 {
 661 #ifndef CONFIG_PPC64
 662         /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
 663         static long int core99_l2_cache;
 664         static long int core99_l3_cache;
 665
 666         if (!cpu_has_feature(CPU_FTR_L2CR))
 667                 return;
 668
 669         if (cpu == 0) {
 670                 core99_l2_cache = _get_L2CR();
 671                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
 672         } else {
 673                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
 674                 _set_L2CR(0);
 675                 _set_L2CR(core99_l2_cache);
 676                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
 677         }
 678
 679         if (!cpu_has_feature(CPU_FTR_L3CR))
 680                 return;
 681
 682         if (cpu == 0){
 683                 core99_l3_cache = _get_L3CR();
 684                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
 685         } else {
 686                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
 687                 _set_L3CR(0);
 688                 _set_L3CR(core99_l3_cache);
 689                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
 690         }
 691 #endif /* !CONFIG_PPC64 */
 692 }
 693
 694 static void __init smp_core99_setup(int ncpus)
 695 {
 696 #ifdef CONFIG_PPC64
 697
 698         /* i2c based HW sync on some G5s */
 699         if (of_machine_is_compatible("PowerMac7,2") ||
 700             of_machine_is_compatible("PowerMac7,3") ||
 701             of_machine_is_compatible("RackMac3,1"))
 702                 smp_core99_setup_i2c_hwsync(ncpus);
 703
 704         /* pfunc based HW sync on recent G5s */
 705         if (pmac_tb_freeze == NULL) {
 706                 struct device_node *cpus =
 707                         of_find_node_by_path("/cpus");
 708                 if (cpus &&
 709                     of_get_property(cpus, "platform-cpu-timebase", NULL)) {
 710                         pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
 711                         printk(KERN_INFO "Processor timebase sync using"
 712                                " platform function\n");
 713                 }
 714         }
 715
 716 #else /* CONFIG_PPC64 */
 717
 718         /* GPIO based HW sync on ppc32 Core99 */
 719         if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
 720                 struct device_node *cpu;
 721                 const u32 *tbprop = NULL;
 722
 723                 core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
 724                 cpu = of_find_node_by_type(NULL, "cpu");
 725                 if (cpu != NULL) {
 726                         tbprop = of_get_property(cpu, "timebase-enable", NULL);
 727                         if (tbprop)
 728                                 core99_tb_gpio = *tbprop;
 729                         of_node_put(cpu);
 730                 }
 731                 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
 732                 printk(KERN_INFO "Processor timebase sync using"
 733                        " GPIO 0x%02x\n", core99_tb_gpio);
 734         }
 735
 736 #endif /* CONFIG_PPC64 */
 737
 738         /* No timebase sync, fallback to software */
 739         if (pmac_tb_freeze == NULL) {
 740                 smp_ops->give_timebase = smp_generic_give_timebase;
 741                 smp_ops->take_timebase = smp_generic_take_timebase;
 742                 printk(KERN_INFO "Processor timebase sync using software\n");
 743         }
 744
 745 #ifndef CONFIG_PPC64
 746         {
 747                 int i;
 748
 749                 /* XXX should get this from reg properties */
 750                 for (i = 1; i < ncpus; ++i)
 751                         set_hard_smp_processor_id(i, i);
 752         }
 753 #endif
 754
 755         /* 32 bits SMP can't NAP */
 756         if (!of_machine_is_compatible("MacRISC4"))
 757                 powersave_nap = 0;
 758 }
 759
 760 static void __init smp_core99_probe(void)
 761 {
 762         struct device_node *cpus;
 763         int ncpus = 0;
 764
 765         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 766
 767         /* Count CPUs in the device-tree */
 768         for_each_node_by_type(cpus, "cpu")
 769                 ++ncpus;
 770
 771         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
 772
 773         /* Nothing more to do if less than 2 of them */
 774         if (ncpus <= 1)
 775                 return;
 776
 777         /* We need to perform some early initialisations before we can start
 778          * setting up SMP as we are running before initcalls
 779          */
 780         pmac_pfunc_base_install();
 781         pmac_i2c_init();
 782
 783         /* Setup various bits like timebase sync method, ability to nap, ... */
 784         smp_core99_setup(ncpus);
 785
 786         /* Install IPIs */
 787         mpic_request_ipis();
 788
 789         /* Collect l2cr and l3cr values from CPU 0 */
 790         core99_init_caches(0);
 791 }
 792
 793 static int smp_core99_kick_cpu(int nr)
 794 {
 795         unsigned int save_vector;
 796         unsigned long target, flags;
 797         unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
 798
 799         if (nr < 0 || nr > 3)
 800                 return -ENOENT;
 801
 802         if (ppc_md.progress)
 803                 ppc_md.progress("smp_core99_kick_cpu", 0x346);
 804
 805         local_irq_save(flags);
 806
 807         /* Save reset vector */
 808         save_vector = *vector;
 809
 810         /* Setup fake reset vector that does
 811          *   b __secondary_start_pmac_0 + nr*8
 812          */
 813         target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
 814         patch_branch(vector, target, BRANCH_SET_LINK);
 815
 816         /* Put some life in our friend */
 817         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 818
 819         /* FIXME: We wait a bit for the CPU to take the exception, I should
 820          * instead wait for the entry code to set something for me. Well,
 821          * ideally, all that crap will be done in prom.c and the CPU left
 822          * in a RAM-based wait loop like CHRP.
 823          */
 824         mdelay(1);
 825
 826         /* Restore our exception vector */
 827         patch_instruction(vector, ppc_inst(save_vector));
 828
 829         local_irq_restore(flags);
 830         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 831
 832         return 0;
 833 }
 834
 835 static void smp_core99_setup_cpu(int cpu_nr)
 836 {
 837         /* Setup L2/L3 */
 838         if (cpu_nr != 0)
 839                 core99_init_caches(cpu_nr);
 840
 841         /* Setup openpic */
 842         mpic_setup_this_cpu();
 843 }
 844
 845 #ifdef CONFIG_PPC64
 846 #ifdef CONFIG_HOTPLUG_CPU
 847 static unsigned int smp_core99_host_open;
 848
 849 static int smp_core99_cpu_prepare(unsigned int cpu)
 850 {
 851         int rc;
 852
 853         /* Open i2c bus if it was used for tb sync */
 854         if (pmac_tb_clock_chip_host && !smp_core99_host_open) {
 855                 rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1);
 856                 if (rc) {
 857                         pr_err("Failed to open i2c bus for time sync\n");
 858                         return notifier_from_errno(rc);
 859                 }
 860                 smp_core99_host_open = 1;
 861         }
 862         return 0;
 863 }
 864
 865 static int smp_core99_cpu_online(unsigned int cpu)
 866 {
 867         /* Close i2c bus if it was used for tb sync */
 868         if (pmac_tb_clock_chip_host && smp_core99_host_open) {
 869                 pmac_i2c_close(pmac_tb_clock_chip_host);
 870                 smp_core99_host_open = 0;
 871         }
 872         return 0;
 873 }
 874 #endif /* CONFIG_HOTPLUG_CPU */
 875
 876 static void __init smp_core99_bringup_done(void)
 877 {
 878         extern void g5_phy_disable_cpu1(void);
 879
 880         /* Close i2c bus if it was used for tb sync */
 881         if (pmac_tb_clock_chip_host)
 882                 pmac_i2c_close(pmac_tb_clock_chip_host);
 883
 884         /* If we didn't start the second CPU, we must take
 885          * it off the bus.
 886          */
 887         if (of_machine_is_compatible("MacRISC4") &&
 888             num_online_cpus() < 2) {
 889                 set_cpu_present(1, false);
 890                 g5_phy_disable_cpu1();
 891         }
 892 #ifdef CONFIG_HOTPLUG_CPU
 893         cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE,
 894                                   "powerpc/pmac:prepare", smp_core99_cpu_prepare,
 895                                   NULL);
 896         cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online",
 897                                   smp_core99_cpu_online, NULL);
 898 #endif
 899
 900         if (ppc_md.progress)
 901                 ppc_md.progress("smp_core99_bringup_done", 0x349);
 902 }
 903 #endif /* CONFIG_PPC64 */
 904
 905 #ifdef CONFIG_HOTPLUG_CPU
 906
 907 static int smp_core99_cpu_disable(void)
 908 {
 909         int rc = generic_cpu_disable();
 910         if (rc)
 911                 return rc;
 912
 913         mpic_cpu_set_priority(0xf);
 914
 915         cleanup_cpu_mmu_context();
 916
 917         return 0;
 918 }
 919
 920 #ifdef CONFIG_PPC32
 921
 922 static void pmac_cpu_offline_self(void)
 923 {
 924         int cpu = smp_processor_id();
 925
 926         local_irq_disable();
 927         idle_task_exit();
 928         pr_debug("CPU%d offline\n", cpu);
 929         generic_set_cpu_dead(cpu);
 930         smp_wmb();
 931         mb();
 932         low_cpu_offline_self();
 933 }
 934
 935 #else /* CONFIG_PPC32 */
 936
 937 static void pmac_cpu_offline_self(void)
 938 {
 939         int cpu = smp_processor_id();
 940
 941         local_irq_disable();
 942         idle_task_exit();
 943
 944         /*
 945          * turn off as much as possible, we'll be
 946          * kicked out as this will only be invoked
 947          * on core99 platforms for now ...
 948          */
 949
 950         printk(KERN_INFO "CPU#%d offline\n", cpu);
 951         generic_set_cpu_dead(cpu);
 952         smp_wmb();
 953
 954         /*
 955          * Re-enable interrupts. The NAP code needs to enable them
 956          * anyways, do it now so we deal with the case where one already
 957          * happened while soft-disabled.
 958          * We shouldn't get any external interrupts, only decrementer, and the
 959          * decrementer handler is safe for use on offline CPUs
 960          */
 961         local_irq_enable();
 962
 963         while (1) {
 964                 /* let's not take timer interrupts too often ... */
 965                 set_dec(0x7fffffff);
 966
 967                 /* Enter NAP mode */
 968                 power4_idle();
 969         }
 970 }
 971
 972 #endif /* else CONFIG_PPC32 */
 973 #endif /* CONFIG_HOTPLUG_CPU */
 974
 975 /* Core99 Macs (dual G4s and G5s) */
 976 static struct smp_ops_t core99_smp_ops = {
 977         .message_pass   = smp_mpic_message_pass,
 978         .probe          = smp_core99_probe,
 979 #ifdef CONFIG_PPC64
 980         .bringup_done   = smp_core99_bringup_done,
 981 #endif
 982         .kick_cpu       = smp_core99_kick_cpu,
 983         .setup_cpu      = smp_core99_setup_cpu,
 984         .give_timebase  = smp_core99_give_timebase,
 985         .take_timebase  = smp_core99_take_timebase,
 986 #if defined(CONFIG_HOTPLUG_CPU)
 987         .cpu_disable    = smp_core99_cpu_disable,
 988         .cpu_die        = generic_cpu_die,
 989 #endif
 990 };
 991
 992 void __init pmac_setup_smp(void)
 993 {
 994         struct device_node *np;
 995
 996         /* Check for Core99 */
 997         np = of_find_node_by_name(NULL, "uni-n");
 998         if (!np)
 999                 np = of_find_node_by_name(NULL, "u3");
1000         if (!np)
1001                 np = of_find_node_by_name(NULL, "u4");
1002         if (np) {
1003                 of_node_put(np);
1004                 smp_ops = &core99_smp_ops;
1005         }
1006 #ifdef CONFIG_PPC_PMAC32_PSURGE
1007         else {
1008                 /* We have to set bits in cpu_possible_mask here since the
1009                  * secondary CPU(s) aren't in the device tree. Various
1010                  * things won't be initialized for CPUs not in the possible
1011                  * map, so we really need to fix it up here.
1012                  */
1013                 int cpu;
1014
1015                 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
1016                         set_cpu_possible(cpu, true);
1017                 smp_ops = &psurge_smp_ops;
1018         }
1019 #endif /* CONFIG_PPC_PMAC32_PSURGE */
1020
1021 #ifdef CONFIG_HOTPLUG_CPU
1022         smp_ops->cpu_offline_self = pmac_cpu_offline_self;
1023 #endif
1024 }
1025
1026