1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains common routines for dealing with free of page tables
4 * Along with common page table handling code
6 * Derived from arch/powerpc/mm/tlb_64.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 * Dave Engebretsen <engebret@us.ibm.com>
17 * Rework for PPC64 port.
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
23 #include <linux/percpu.h>
24 #include <linux/hardirq.h>
25 #include <linux/hugetlb.h>
26 #include <asm/tlbflush.h>
28 #include <asm/hugetlb.h>
29 #include <asm/pte-walk.h>
32 #define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD)
34 #define PGD_ALIGN PAGE_SIZE
37 pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN);
39 static inline int is_exec_fault(void)
41 return current->thread.regs && TRAP(current->thread.regs) == 0x400;
44 /* We only try to do i/d cache coherency on stuff that looks like
45 * reasonably "normal" PTEs. We currently require a PTE to be present
46 * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
49 static inline int pte_looks_normal(pte_t pte)
52 if (pte_present(pte) && !pte_special(pte)) {
61 static struct page *maybe_pte_to_page(pte_t pte)
63 unsigned long pfn = pte_pfn(pte);
66 if (unlikely(!pfn_valid(pfn)))
68 page = pfn_to_page(pfn);
69 if (PageReserved(page))
74 #ifdef CONFIG_PPC_BOOK3S
76 /* Server-style MMU handles coherency when hashing if HW exec permission
77 * is supposed per page (currently 64-bit only). If not, then, we always
78 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
79 * support falls into the same category.
82 static pte_t set_pte_filter_hash(pte_t pte)
84 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
85 if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
86 cpu_has_feature(CPU_FTR_NOEXECUTE))) {
87 struct page *pg = maybe_pte_to_page(pte);
90 if (!test_bit(PG_dcache_clean, &pg->flags)) {
91 flush_dcache_icache_page(pg);
92 set_bit(PG_dcache_clean, &pg->flags);
98 #else /* CONFIG_PPC_BOOK3S */
100 static pte_t set_pte_filter_hash(pte_t pte) { return pte; }
102 #endif /* CONFIG_PPC_BOOK3S */
104 /* Embedded type MMU with HW exec support. This is a bit more complicated
105 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
106 * instead we "filter out" the exec permission for non clean pages.
108 static inline pte_t set_pte_filter(pte_t pte)
115 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
116 return set_pte_filter_hash(pte);
118 /* No exec permission in the first place, move on */
119 if (!pte_exec(pte) || !pte_looks_normal(pte))
122 /* If you set _PAGE_EXEC on weird pages you're on your own */
123 pg = maybe_pte_to_page(pte);
127 /* If the page clean, we move on */
128 if (test_bit(PG_dcache_clean, &pg->flags))
131 /* If it's an exec fault, we flush the cache and make it clean */
132 if (is_exec_fault()) {
133 flush_dcache_icache_page(pg);
134 set_bit(PG_dcache_clean, &pg->flags);
138 /* Else, we filter out _PAGE_EXEC */
139 return pte_exprotect(pte);
142 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
147 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
150 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
153 /* So here, we only care about exec faults, as we use them
154 * to recover lost _PAGE_EXEC and perform I$/D$ coherency
155 * if necessary. Also if _PAGE_EXEC is already set, same deal,
158 if (dirty || pte_exec(pte) || !is_exec_fault())
161 #ifdef CONFIG_DEBUG_VM
162 /* So this is an exec fault, _PAGE_EXEC is not set. If it was
163 * an error we would have bailed out earlier in do_page_fault()
164 * but let's make sure of it
166 if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
168 #endif /* CONFIG_DEBUG_VM */
170 /* If you set _PAGE_EXEC on weird pages you're on your own */
171 pg = maybe_pte_to_page(pte);
175 /* If the page is already clean, we move on */
176 if (test_bit(PG_dcache_clean, &pg->flags))
179 /* Clean the page and set PG_dcache_clean */
180 flush_dcache_icache_page(pg);
181 set_bit(PG_dcache_clean, &pg->flags);
184 return pte_mkexec(pte);
188 * set_pte stores a linux PTE into the linux page table.
190 void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
194 * Make sure hardware valid bit is not set. We don't do
195 * tlb flush for this update.
197 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
199 /* Note: mm->context.id might not yet have been assigned as
200 * this context might not have been activated yet when this
203 pte = set_pte_filter(pte);
205 /* Perform the setting of the PTE */
206 __set_pte_at(mm, addr, ptep, pte, 0);
210 * This is called when relaxing access to a PTE. It's also called in the page
211 * fault path when we don't hit any of the major fault cases, ie, a minor
212 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
213 * handled those two for us, we additionally deal with missing execute
214 * permission here on some processors
216 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
217 pte_t *ptep, pte_t entry, int dirty)
220 entry = set_access_flags_filter(entry, vma, dirty);
221 changed = !pte_same(*(ptep), entry);
223 assert_pte_locked(vma->vm_mm, address);
224 __ptep_set_access_flags(vma, ptep, entry,
225 address, mmu_virtual_psize);
230 #ifdef CONFIG_HUGETLB_PAGE
231 int huge_ptep_set_access_flags(struct vm_area_struct *vma,
232 unsigned long addr, pte_t *ptep,
233 pte_t pte, int dirty)
235 #ifdef HUGETLB_NEED_PRELOAD
237 * The "return 1" forces a call of update_mmu_cache, which will write a
238 * TLB entry. Without this, platforms that don't do a write of the TLB
239 * entry in the TLB miss handler asm will fault ad infinitum.
241 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
246 pte = set_access_flags_filter(pte, vma, dirty);
247 changed = !pte_same(*(ptep), pte);
250 #ifdef CONFIG_PPC_BOOK3S_64
251 struct hstate *h = hstate_vma(vma);
253 psize = hstate_get_psize(h);
254 #ifdef CONFIG_DEBUG_VM
255 assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
260 * Not used on non book3s64 platforms.
261 * 8xx compares it with mmu_virtual_psize to
262 * know if it is a huge page or not.
264 psize = MMU_PAGE_COUNT;
266 __ptep_set_access_flags(vma, ptep, pte, addr, psize);
272 #if defined(CONFIG_PPC_8xx)
273 void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
275 pmd_t *pmd = pmd_off(mm, addr);
277 pte_basic_t *entry = (pte_basic_t *)ptep;
281 * Make sure hardware valid bit is not set. We don't do
282 * tlb flush for this update.
284 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
286 pte = set_pte_filter(pte);
290 num = number_of_cells_per_pte(pmd, val, 1);
292 for (i = 0; i < num; i++, entry++, val += SZ_4K)
296 #endif /* CONFIG_HUGETLB_PAGE */
298 #ifdef CONFIG_DEBUG_VM
299 void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
308 pgd = mm->pgd + pgd_index(addr);
309 BUG_ON(pgd_none(*pgd));
310 p4d = p4d_offset(pgd, addr);
311 BUG_ON(p4d_none(*p4d));
312 pud = pud_offset(p4d, addr);
313 BUG_ON(pud_none(*pud));
314 pmd = pmd_offset(pud, addr);
316 * khugepaged to collapse normal pages to hugepage, first set
317 * pmd to none to force page fault/gup to take mmap_lock. After
318 * pmd is set to none, we do a pte_clear which does this assertion
319 * so if we find pmd none, return.
323 BUG_ON(!pmd_present(*pmd));
324 assert_spin_locked(pte_lockptr(mm, pmd));
326 #endif /* CONFIG_DEBUG_VM */
328 unsigned long vmalloc_to_phys(void *va)
330 unsigned long pfn = vmalloc_to_pfn(va);
333 return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
335 EXPORT_SYMBOL_GPL(vmalloc_to_phys);
338 * We have 4 cases for pgds and pmds:
339 * (1) invalid (all zeroes)
340 * (2) pointer to next table, as normal; bottom 6 bits == 0
341 * (3) leaf pte for huge page _PAGE_PTE set
342 * (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table
344 * So long as we atomically load page table pointers we are safe against teardown,
345 * we can follow the address down to the the page and take a ref on it.
346 * This function need to be called with interrupts disabled. We use this variant
347 * when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED
349 pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea,
350 bool *is_thp, unsigned *hpage_shift)
357 hugepd_t *hpdp = NULL;
367 * Always operate on the local stack value. This make sure the
368 * value don't get updated by a parallel THP split/collapse,
369 * page fault or a page unmap. The return pte_t * is still not
370 * stable. So should be checked there for above conditions.
371 * Top level is an exception because it is folded into p4d.
373 pgdp = pgdir + pgd_index(ea);
374 p4dp = p4d_offset(pgdp, ea);
375 p4d = READ_ONCE(*p4dp);
381 if (p4d_is_leaf(p4d)) {
382 ret_pte = (pte_t *)p4dp;
386 if (is_hugepd(__hugepd(p4d_val(p4d)))) {
387 hpdp = (hugepd_t *)&p4d;
392 * Even if we end up with an unmap, the pgtable will not
393 * be freed, because we do an rcu free and here we are
397 pudp = pud_offset(&p4d, ea);
398 pud = READ_ONCE(*pudp);
403 if (pud_is_leaf(pud)) {
404 ret_pte = (pte_t *)pudp;
408 if (is_hugepd(__hugepd(pud_val(pud)))) {
409 hpdp = (hugepd_t *)&pud;
414 pmdp = pmd_offset(&pud, ea);
415 pmd = READ_ONCE(*pmdp);
418 * A hugepage collapse is captured by this condition, see
419 * pmdp_collapse_flush.
424 #ifdef CONFIG_PPC_BOOK3S_64
426 * A hugepage split is captured by this condition, see
429 * Huge page modification can be caught here too.
431 if (pmd_is_serializing(pmd))
435 if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) {
438 ret_pte = (pte_t *)pmdp;
442 if (pmd_is_leaf(pmd)) {
443 ret_pte = (pte_t *)pmdp;
447 if (is_hugepd(__hugepd(pmd_val(pmd)))) {
448 hpdp = (hugepd_t *)&pmd;
452 return pte_offset_kernel(&pmd, ea);
458 ret_pte = hugepte_offset(*hpdp, ea, pdshift);
459 pdshift = hugepd_shift(*hpdp);
462 *hpage_shift = pdshift;
465 EXPORT_SYMBOL_GPL(__find_linux_pte);