2 * native hashtable management.
4 * SMP scalability work:
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <linux/processor.h>
19 #include <linux/threads.h>
20 #include <linux/smp.h>
22 #include <asm/machdep.h>
24 #include <asm/mmu_context.h>
25 #include <asm/pgtable.h>
26 #include <asm/tlbflush.h>
27 #include <asm/trace.h>
29 #include <asm/cputable.h>
31 #include <asm/kexec.h>
32 #include <asm/ppc-opcode.h>
34 #include <misc/cxl-base.h>
37 #define DBG_LOW(fmt...) udbg_printf(fmt)
39 #define DBG_LOW(fmt...)
43 #define HPTE_LOCK_BIT 3
45 #define HPTE_LOCK_BIT (56+3)
48 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
50 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
57 * We need 14 to 65 bits of va for a tlibe of 4K page
58 * With vpn we ignore the lower VPN_SHIFT bits already.
59 * And top two bits are already ignored because we can
60 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
63 va = vpn << VPN_SHIFT;
65 * clear top 16 bits of 64bit va, non SLS segment
66 * Older versions of the architecture (2.02 and earler) require the
67 * masking of the top 16 bits.
69 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
70 va &= ~(0xffffULL << 48);
74 /* clear out bits after (52) [0....52.....63] */
75 va &= ~((1ul << (64 - 52)) - 1);
77 sllp = get_sllp_encoding(apsize);
79 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
80 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
84 /* We need 14 to 14 + i bits of va */
85 penc = mmu_psize_defs[psize].penc[apsize];
86 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
91 * We don't need all the bits, but rest of the bits
92 * must be ignored by the processor.
93 * vpn cover upto 65 bits of va. (0...65) and we need
96 va |= (vpn & 0xfe); /* AVAL */
98 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
99 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
103 trace_tlbie(0, 0, va, 0, 0, 0, 0);
106 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
112 /* VPN_SHIFT can be atmost 12 */
113 va = vpn << VPN_SHIFT;
115 * clear top 16 bits of 64 bit va, non SLS segment
116 * Older versions of the architecture (2.02 and earler) require the
117 * masking of the top 16 bits.
119 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
120 va &= ~(0xffffULL << 48);
124 /* clear out bits after(52) [0....52.....63] */
125 va &= ~((1ul << (64 - 52)) - 1);
127 sllp = get_sllp_encoding(apsize);
129 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,0", %1)
130 : : "r" (va), "i" (CPU_FTR_ARCH_206)
134 /* We need 14 to 14 + i bits of va */
135 penc = mmu_psize_defs[psize].penc[apsize];
136 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
141 * We don't need all the bits, but rest of the bits
142 * must be ignored by the processor.
143 * vpn cover upto 65 bits of va. (0...65) and we need
148 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,1", %1)
149 : : "r" (va), "i" (CPU_FTR_ARCH_206)
153 trace_tlbie(0, 1, va, 0, 0, 0, 0);
157 static inline void tlbie(unsigned long vpn, int psize, int apsize,
158 int ssize, int local)
160 unsigned int use_local;
161 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
163 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
166 use_local = mmu_psize_defs[psize].tlbiel;
167 if (lock_tlbie && !use_local)
168 raw_spin_lock(&native_tlbie_lock);
169 asm volatile("ptesync": : :"memory");
171 __tlbiel(vpn, psize, apsize, ssize);
172 asm volatile("ptesync": : :"memory");
174 __tlbie(vpn, psize, apsize, ssize);
175 asm volatile("eieio; tlbsync; ptesync": : :"memory");
177 if (lock_tlbie && !use_local)
178 raw_spin_unlock(&native_tlbie_lock);
181 static inline void native_lock_hpte(struct hash_pte *hptep)
183 unsigned long *word = (unsigned long *)&hptep->v;
186 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
189 while(test_bit(HPTE_LOCK_BIT, word))
195 static inline void native_unlock_hpte(struct hash_pte *hptep)
197 unsigned long *word = (unsigned long *)&hptep->v;
199 clear_bit_unlock(HPTE_LOCK_BIT, word);
202 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
203 unsigned long pa, unsigned long rflags,
204 unsigned long vflags, int psize, int apsize, int ssize)
206 struct hash_pte *hptep = htab_address + hpte_group;
207 unsigned long hpte_v, hpte_r;
210 if (!(vflags & HPTE_V_BOLTED)) {
211 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
212 " rflags=%lx, vflags=%lx, psize=%d)\n",
213 hpte_group, vpn, pa, rflags, vflags, psize);
216 for (i = 0; i < HPTES_PER_GROUP; i++) {
217 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
218 /* retry with lock held */
219 native_lock_hpte(hptep);
220 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
222 native_unlock_hpte(hptep);
228 if (i == HPTES_PER_GROUP)
231 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
232 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
234 if (!(vflags & HPTE_V_BOLTED)) {
235 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
239 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
240 hpte_r = hpte_old_to_new_r(hpte_v, hpte_r);
241 hpte_v = hpte_old_to_new_v(hpte_v);
244 hptep->r = cpu_to_be64(hpte_r);
245 /* Guarantee the second dword is visible before the valid bit */
248 * Now set the first dword including the valid bit
249 * NOTE: this also unlocks the hpte
251 hptep->v = cpu_to_be64(hpte_v);
253 __asm__ __volatile__ ("ptesync" : : : "memory");
255 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
258 static long native_hpte_remove(unsigned long hpte_group)
260 struct hash_pte *hptep;
263 unsigned long hpte_v;
265 DBG_LOW(" remove(group=%lx)\n", hpte_group);
267 /* pick a random entry to start at */
268 slot_offset = mftb() & 0x7;
270 for (i = 0; i < HPTES_PER_GROUP; i++) {
271 hptep = htab_address + hpte_group + slot_offset;
272 hpte_v = be64_to_cpu(hptep->v);
274 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
275 /* retry with lock held */
276 native_lock_hpte(hptep);
277 hpte_v = be64_to_cpu(hptep->v);
278 if ((hpte_v & HPTE_V_VALID)
279 && !(hpte_v & HPTE_V_BOLTED))
281 native_unlock_hpte(hptep);
288 if (i == HPTES_PER_GROUP)
291 /* Invalidate the hpte. NOTE: this also unlocks it */
297 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
298 unsigned long vpn, int bpsize,
299 int apsize, int ssize, unsigned long flags)
301 struct hash_pte *hptep = htab_address + slot;
302 unsigned long hpte_v, want_v;
303 int ret = 0, local = 0;
305 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
307 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
308 vpn, want_v & HPTE_V_AVPN, slot, newpp);
310 hpte_v = be64_to_cpu(hptep->v);
311 if (cpu_has_feature(CPU_FTR_ARCH_300))
312 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
314 * We need to invalidate the TLB always because hpte_remove doesn't do
315 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
316 * random entry from it. When we do that we don't invalidate the TLB
317 * (hpte_remove) because we assume the old translation is still
318 * technically "valid".
320 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
321 DBG_LOW(" -> miss\n");
324 native_lock_hpte(hptep);
325 /* recheck with locks held */
326 hpte_v = be64_to_cpu(hptep->v);
327 if (cpu_has_feature(CPU_FTR_ARCH_300))
328 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
329 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
330 !(hpte_v & HPTE_V_VALID))) {
333 DBG_LOW(" -> hit\n");
334 /* Update the HPTE */
335 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
336 ~(HPTE_R_PPP | HPTE_R_N)) |
337 (newpp & (HPTE_R_PPP | HPTE_R_N |
340 native_unlock_hpte(hptep);
343 if (flags & HPTE_LOCAL_UPDATE)
346 * Ensure it is out of the tlb too if it is not a nohpte fault
348 if (!(flags & HPTE_NOHPTE_UPDATE))
349 tlbie(vpn, bpsize, apsize, ssize, local);
354 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
356 struct hash_pte *hptep;
360 unsigned long want_v, hpte_v;
362 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
363 want_v = hpte_encode_avpn(vpn, psize, ssize);
365 /* Bolted mappings are only ever in the primary group */
366 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
367 for (i = 0; i < HPTES_PER_GROUP; i++) {
368 hptep = htab_address + slot;
369 hpte_v = be64_to_cpu(hptep->v);
370 if (cpu_has_feature(CPU_FTR_ARCH_300))
371 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
373 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
383 * Update the page protection bits. Intended to be used to create
384 * guard pages for kernel data structures on pages which are bolted
385 * in the HPT. Assumes pages being operated on will not be stolen.
387 * No need to lock here because we should be the only user.
389 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
390 int psize, int ssize)
395 struct hash_pte *hptep;
397 vsid = get_kernel_vsid(ea, ssize);
398 vpn = hpt_vpn(ea, vsid, ssize);
400 slot = native_hpte_find(vpn, psize, ssize);
402 panic("could not find page to bolt\n");
403 hptep = htab_address + slot;
405 /* Update the HPTE */
406 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
407 ~(HPTE_R_PPP | HPTE_R_N)) |
408 (newpp & (HPTE_R_PPP | HPTE_R_N)));
410 * Ensure it is out of the tlb too. Bolted entries base and
411 * actual page size will be same.
413 tlbie(vpn, psize, psize, ssize, 0);
417 * Remove a bolted kernel entry. Memory hotplug uses this.
419 * No need to lock here because we should be the only user.
421 static int native_hpte_removebolted(unsigned long ea, int psize, int ssize)
426 struct hash_pte *hptep;
428 vsid = get_kernel_vsid(ea, ssize);
429 vpn = hpt_vpn(ea, vsid, ssize);
431 slot = native_hpte_find(vpn, psize, ssize);
435 hptep = htab_address + slot;
437 VM_WARN_ON(!(be64_to_cpu(hptep->v) & HPTE_V_BOLTED));
439 /* Invalidate the hpte */
442 /* Invalidate the TLB */
443 tlbie(vpn, psize, psize, ssize, 0);
448 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
449 int bpsize, int apsize, int ssize, int local)
451 struct hash_pte *hptep = htab_address + slot;
452 unsigned long hpte_v;
453 unsigned long want_v;
456 local_irq_save(flags);
458 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
460 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
461 native_lock_hpte(hptep);
462 hpte_v = be64_to_cpu(hptep->v);
463 if (cpu_has_feature(CPU_FTR_ARCH_300))
464 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
467 * We need to invalidate the TLB always because hpte_remove doesn't do
468 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
469 * random entry from it. When we do that we don't invalidate the TLB
470 * (hpte_remove) because we assume the old translation is still
471 * technically "valid".
473 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
474 native_unlock_hpte(hptep);
476 /* Invalidate the hpte. NOTE: this also unlocks it */
479 /* Invalidate the TLB */
480 tlbie(vpn, bpsize, apsize, ssize, local);
482 local_irq_restore(flags);
485 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
486 static void native_hugepage_invalidate(unsigned long vsid,
488 unsigned char *hpte_slot_array,
489 int psize, int ssize, int local)
492 struct hash_pte *hptep;
493 int actual_psize = MMU_PAGE_16M;
494 unsigned int max_hpte_count, valid;
495 unsigned long flags, s_addr = addr;
496 unsigned long hpte_v, want_v, shift;
497 unsigned long hidx, vpn = 0, hash, slot;
499 shift = mmu_psize_defs[psize].shift;
500 max_hpte_count = 1U << (PMD_SHIFT - shift);
502 local_irq_save(flags);
503 for (i = 0; i < max_hpte_count; i++) {
504 valid = hpte_valid(hpte_slot_array, i);
507 hidx = hpte_hash_index(hpte_slot_array, i);
510 addr = s_addr + (i * (1ul << shift));
511 vpn = hpt_vpn(addr, vsid, ssize);
512 hash = hpt_hash(vpn, shift, ssize);
513 if (hidx & _PTEIDX_SECONDARY)
516 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
517 slot += hidx & _PTEIDX_GROUP_IX;
519 hptep = htab_address + slot;
520 want_v = hpte_encode_avpn(vpn, psize, ssize);
521 native_lock_hpte(hptep);
522 hpte_v = be64_to_cpu(hptep->v);
523 if (cpu_has_feature(CPU_FTR_ARCH_300))
524 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
526 /* Even if we miss, we need to invalidate the TLB */
527 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
528 native_unlock_hpte(hptep);
530 /* Invalidate the hpte. NOTE: this also unlocks it */
533 * We need to do tlb invalidate for all the address, tlbie
534 * instruction compares entry_VA in tlb with the VA specified
537 tlbie(vpn, psize, actual_psize, ssize, local);
539 local_irq_restore(flags);
542 static void native_hugepage_invalidate(unsigned long vsid,
544 unsigned char *hpte_slot_array,
545 int psize, int ssize, int local)
547 WARN(1, "%s called without THP support\n", __func__);
551 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
552 int *psize, int *apsize, int *ssize, unsigned long *vpn)
554 unsigned long avpn, pteg, vpi;
555 unsigned long hpte_v = be64_to_cpu(hpte->v);
556 unsigned long hpte_r = be64_to_cpu(hpte->r);
557 unsigned long vsid, seg_off;
558 int size, a_size, shift;
559 /* Look at the 8 bit LP value */
560 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
562 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
563 hpte_v = hpte_new_to_old_v(hpte_v, hpte_r);
564 hpte_r = hpte_new_to_old_r(hpte_r);
566 if (!(hpte_v & HPTE_V_LARGE)) {
568 a_size = MMU_PAGE_4K;
570 size = hpte_page_sizes[lp] & 0xf;
571 a_size = hpte_page_sizes[lp] >> 4;
573 /* This works for all page sizes, and for 256M and 1T segments */
574 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
575 shift = mmu_psize_defs[size].shift;
577 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
578 pteg = slot / HPTES_PER_GROUP;
579 if (hpte_v & HPTE_V_SECONDARY)
583 case MMU_SEGSIZE_256M:
584 /* We only have 28 - 23 bits of seg_off in avpn */
585 seg_off = (avpn & 0x1f) << 23;
587 /* We can find more bits from the pteg value */
589 vpi = (vsid ^ pteg) & htab_hash_mask;
590 seg_off |= vpi << shift;
592 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
595 /* We only have 40 - 23 bits of seg_off in avpn */
596 seg_off = (avpn & 0x1ffff) << 23;
599 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
600 seg_off |= vpi << shift;
602 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
612 * clear all mappings on kexec. All cpus are in real mode (or they will
613 * be when they isi), and we are the only one left. We rely on our kernel
614 * mapping being 0xC0's and the hardware ignoring those two real bits.
616 * This must be called with interrupts disabled.
618 * Taking the native_tlbie_lock is unsafe here due to the possibility of
619 * lockdep being on. On pre POWER5 hardware, not taking the lock could
620 * cause deadlock. POWER5 and newer not taking the lock is fine. This only
621 * gets called during boot before secondary CPUs have come up and during
622 * crashdump and all bets are off anyway.
624 * TODO: add batching support when enabled. remember, no dynamic memory here,
625 * although there is the control page available...
627 static void native_hpte_clear(void)
629 unsigned long vpn = 0;
630 unsigned long slot, slots;
631 struct hash_pte *hptep = htab_address;
632 unsigned long hpte_v;
633 unsigned long pteg_count;
634 int psize, apsize, ssize;
636 pteg_count = htab_hash_mask + 1;
638 slots = pteg_count * HPTES_PER_GROUP;
640 for (slot = 0; slot < slots; slot++, hptep++) {
642 * we could lock the pte here, but we are the only cpu
643 * running, right? and for crash dump, we probably
644 * don't want to wait for a maybe bad cpu.
646 hpte_v = be64_to_cpu(hptep->v);
649 * Call __tlbie() here rather than tlbie() since we can't take the
652 if (hpte_v & HPTE_V_VALID) {
653 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
655 __tlbie(vpn, psize, apsize, ssize);
659 asm volatile("eieio; tlbsync; ptesync":::"memory");
663 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
664 * the lock all the time
666 static void native_flush_hash_range(unsigned long number, int local)
669 unsigned long hash, index, hidx, shift, slot;
670 struct hash_pte *hptep;
671 unsigned long hpte_v;
672 unsigned long want_v;
675 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
676 unsigned long psize = batch->psize;
677 int ssize = batch->ssize;
679 unsigned int use_local;
681 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&
682 mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();
684 local_irq_save(flags);
686 for (i = 0; i < number; i++) {
690 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
691 hash = hpt_hash(vpn, shift, ssize);
692 hidx = __rpte_to_hidx(pte, index);
693 if (hidx & _PTEIDX_SECONDARY)
695 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
696 slot += hidx & _PTEIDX_GROUP_IX;
697 hptep = htab_address + slot;
698 want_v = hpte_encode_avpn(vpn, psize, ssize);
699 native_lock_hpte(hptep);
700 hpte_v = be64_to_cpu(hptep->v);
701 if (cpu_has_feature(CPU_FTR_ARCH_300))
702 hpte_v = hpte_new_to_old_v(hpte_v,
703 be64_to_cpu(hptep->r));
704 if (!HPTE_V_COMPARE(hpte_v, want_v) ||
705 !(hpte_v & HPTE_V_VALID))
706 native_unlock_hpte(hptep);
709 } pte_iterate_hashed_end();
713 asm volatile("ptesync":::"memory");
714 for (i = 0; i < number; i++) {
718 pte_iterate_hashed_subpages(pte, psize,
720 __tlbiel(vpn, psize, psize, ssize);
721 } pte_iterate_hashed_end();
723 asm volatile("ptesync":::"memory");
725 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
728 raw_spin_lock(&native_tlbie_lock);
730 asm volatile("ptesync":::"memory");
731 for (i = 0; i < number; i++) {
735 pte_iterate_hashed_subpages(pte, psize,
737 __tlbie(vpn, psize, psize, ssize);
738 } pte_iterate_hashed_end();
740 asm volatile("eieio; tlbsync; ptesync":::"memory");
743 raw_spin_unlock(&native_tlbie_lock);
746 local_irq_restore(flags);
749 static int native_register_proc_table(unsigned long base, unsigned long page_size,
750 unsigned long table_size)
752 unsigned long patb1 = base << 25; /* VSID */
754 patb1 |= (page_size << 5); /* sllp */
757 partition_tb->patb1 = cpu_to_be64(patb1);
761 void __init hpte_init_native(void)
763 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
764 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
765 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
766 mmu_hash_ops.hpte_removebolted = native_hpte_removebolted;
767 mmu_hash_ops.hpte_insert = native_hpte_insert;
768 mmu_hash_ops.hpte_remove = native_hpte_remove;
769 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
770 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
771 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;
773 if (cpu_has_feature(CPU_FTR_ARCH_300))
774 register_process_table = native_register_proc_table;