arch/powerpc/lib/sstep.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Single-step support.
   4  *
   5  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/kprobes.h>
   9 #include <linux/ptrace.h>
  10 #include <linux/prefetch.h>
  11 #include <asm/sstep.h>
  12 #include <asm/processor.h>
  13 #include <linux/uaccess.h>
  14 #include <asm/cpu_has_feature.h>
  15 #include <asm/cputable.h>
  16 #include <asm/disassemble.h>
  17
  18 extern char system_call_common[];
  19 extern char system_call_vectored_emulate[];
  20
  21 #ifdef CONFIG_PPC64
  22 /* Bits in SRR1 that are copied from MSR */
  23 #define MSR_MASK        0xffffffff87c0ffffUL
  24 #else
  25 #define MSR_MASK        0x87c0ffff
  26 #endif
  27
  28 /* Bits in XER */
  29 #define XER_SO          0x80000000U
  30 #define XER_OV          0x40000000U
  31 #define XER_CA          0x20000000U
  32 #define XER_OV32        0x00080000U
  33 #define XER_CA32        0x00040000U
  34
  35 #ifdef CONFIG_VSX
  36 #define VSX_REGISTER_XTP(rd)   ((((rd) & 1) << 5) | ((rd) & 0xfe))
  37 #endif
  38
  39 #ifdef CONFIG_PPC_FPU
  40 /*
  41  * Functions in ldstfp.S
  42  */
  43 extern void get_fpr(int rn, double *p);
  44 extern void put_fpr(int rn, const double *p);
  45 extern void get_vr(int rn, __vector128 *p);
  46 extern void put_vr(int rn, __vector128 *p);
  47 extern void load_vsrn(int vsr, const void *p);
  48 extern void store_vsrn(int vsr, void *p);
  49 extern void conv_sp_to_dp(const float *sp, double *dp);
  50 extern void conv_dp_to_sp(const double *dp, float *sp);
  51 #endif
  52
  53 #ifdef __powerpc64__
  54 /*
  55  * Functions in quad.S
  56  */
  57 extern int do_lq(unsigned long ea, unsigned long *regs);
  58 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  59 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  60 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  61                     unsigned int *crp);
  62 #endif
  63
  64 #ifdef __LITTLE_ENDIAN__
  65 #define IS_LE   1
  66 #define IS_BE   0
  67 #else
  68 #define IS_LE   0
  69 #define IS_BE   1
  70 #endif
  71
  72 /*
  73  * Emulate the truncation of 64 bit values in 32-bit mode.
  74  */
  75 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  76                                                         unsigned long val)
  77 {
  78 #ifdef __powerpc64__
  79         if ((msr & MSR_64BIT) == 0)
  80                 val &= 0xffffffffUL;
  81 #endif
  82         return val;
  83 }
  84
  85 /*
  86  * Determine whether a conditional branch instruction would branch.
  87  */
  88 static nokprobe_inline int branch_taken(unsigned int instr,
  89                                         const struct pt_regs *regs,
  90                                         struct instruction_op *op)
  91 {
  92         unsigned int bo = (instr >> 21) & 0x1f;
  93         unsigned int bi;
  94
  95         if ((bo & 4) == 0) {
  96                 /* decrement counter */
  97                 op->type |= DECCTR;
  98                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  99                         return 0;
 100         }
 101         if ((bo & 0x10) == 0) {
 102                 /* check bit from CR */
 103                 bi = (instr >> 16) & 0x1f;
 104                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 105                         return 0;
 106         }
 107         return 1;
 108 }
 109
 110 static nokprobe_inline long address_ok(struct pt_regs *regs,
 111                                        unsigned long ea, int nb)
 112 {
 113         if (!user_mode(regs))
 114                 return 1;
 115         if (__access_ok(ea, nb))
 116                 return 1;
 117         if (__access_ok(ea, 1))
 118                 /* Access overlaps the end of the user region */
 119                 regs->dar = TASK_SIZE_MAX - 1;
 120         else
 121                 regs->dar = ea;
 122         return 0;
 123 }
 124
 125 /*
 126  * Calculate effective address for a D-form instruction
 127  */
 128 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 129                                               const struct pt_regs *regs)
 130 {
 131         int ra;
 132         unsigned long ea;
 133
 134         ra = (instr >> 16) & 0x1f;
 135         ea = (signed short) instr;              /* sign-extend */
 136         if (ra)
 137                 ea += regs->gpr[ra];
 138
 139         return ea;
 140 }
 141
 142 #ifdef __powerpc64__
 143 /*
 144  * Calculate effective address for a DS-form instruction
 145  */
 146 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 147                                                const struct pt_regs *regs)
 148 {
 149         int ra;
 150         unsigned long ea;
 151
 152         ra = (instr >> 16) & 0x1f;
 153         ea = (signed short) (instr & ~3);       /* sign-extend */
 154         if (ra)
 155                 ea += regs->gpr[ra];
 156
 157         return ea;
 158 }
 159
 160 /*
 161  * Calculate effective address for a DQ-form instruction
 162  */
 163 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 164                                                const struct pt_regs *regs)
 165 {
 166         int ra;
 167         unsigned long ea;
 168
 169         ra = (instr >> 16) & 0x1f;
 170         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 171         if (ra)
 172                 ea += regs->gpr[ra];
 173
 174         return ea;
 175 }
 176 #endif /* __powerpc64 */
 177
 178 /*
 179  * Calculate effective address for an X-form instruction
 180  */
 181 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 182                                               const struct pt_regs *regs)
 183 {
 184         int ra, rb;
 185         unsigned long ea;
 186
 187         ra = (instr >> 16) & 0x1f;
 188         rb = (instr >> 11) & 0x1f;
 189         ea = regs->gpr[rb];
 190         if (ra)
 191                 ea += regs->gpr[ra];
 192
 193         return ea;
 194 }
 195
 196 /*
 197  * Calculate effective address for a MLS:D-form / 8LS:D-form
 198  * prefixed instruction
 199  */
 200 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
 201                                                   unsigned int suffix,
 202                                                   const struct pt_regs *regs)
 203 {
 204         int ra, prefix_r;
 205         unsigned int  dd;
 206         unsigned long ea, d0, d1, d;
 207
 208         prefix_r = GET_PREFIX_R(instr);
 209         ra = GET_PREFIX_RA(suffix);
 210
 211         d0 = instr & 0x3ffff;
 212         d1 = suffix & 0xffff;
 213         d = (d0 << 16) | d1;
 214
 215         /*
 216          * sign extend a 34 bit number
 217          */
 218         dd = (unsigned int)(d >> 2);
 219         ea = (signed int)dd;
 220         ea = (ea << 2) | (d & 0x3);
 221
 222         if (!prefix_r && ra)
 223                 ea += regs->gpr[ra];
 224         else if (!prefix_r && !ra)
 225                 ; /* Leave ea as is */
 226         else if (prefix_r)
 227                 ea += regs->nip;
 228
 229         /*
 230          * (prefix_r && ra) is an invalid form. Should already be
 231          * checked for by caller!
 232          */
 233
 234         return ea;
 235 }
 236
 237 /*
 238  * Return the largest power of 2, not greater than sizeof(unsigned long),
 239  * such that x is a multiple of it.
 240  */
 241 static nokprobe_inline unsigned long max_align(unsigned long x)
 242 {
 243         x |= sizeof(unsigned long);
 244         return x & -x;          /* isolates rightmost bit */
 245 }
 246
 247 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 248 {
 249         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 250 }
 251
 252 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 253 {
 254         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 255                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 256 }
 257
 258 #ifdef __powerpc64__
 259 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 260 {
 261         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 262 }
 263 #endif
 264
 265 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 266 {
 267         switch (nb) {
 268         case 2:
 269                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 270                 break;
 271         case 4:
 272                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 273                 break;
 274 #ifdef __powerpc64__
 275         case 8:
 276                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 277                 break;
 278         case 16: {
 279                 unsigned long *up = (unsigned long *)ptr;
 280                 unsigned long tmp;
 281                 tmp = byterev_8(up[0]);
 282                 up[0] = byterev_8(up[1]);
 283                 up[1] = tmp;
 284                 break;
 285         }
 286         case 32: {
 287                 unsigned long *up = (unsigned long *)ptr;
 288                 unsigned long tmp;
 289
 290                 tmp = byterev_8(up[0]);
 291                 up[0] = byterev_8(up[3]);
 292                 up[3] = tmp;
 293                 tmp = byterev_8(up[2]);
 294                 up[2] = byterev_8(up[1]);
 295                 up[1] = tmp;
 296                 break;
 297         }
 298
 299 #endif
 300         default:
 301                 WARN_ON_ONCE(1);
 302         }
 303 }
 304
 305 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 306                                             unsigned long ea, int nb,
 307                                             struct pt_regs *regs)
 308 {
 309         int err = 0;
 310         unsigned long x = 0;
 311
 312         switch (nb) {
 313         case 1:
 314                 err = __get_user(x, (unsigned char __user *) ea);
 315                 break;
 316         case 2:
 317                 err = __get_user(x, (unsigned short __user *) ea);
 318                 break;
 319         case 4:
 320                 err = __get_user(x, (unsigned int __user *) ea);
 321                 break;
 322 #ifdef __powerpc64__
 323         case 8:
 324                 err = __get_user(x, (unsigned long __user *) ea);
 325                 break;
 326 #endif
 327         }
 328         if (!err)
 329                 *dest = x;
 330         else
 331                 regs->dar = ea;
 332         return err;
 333 }
 334
 335 /*
 336  * Copy from userspace to a buffer, using the largest possible
 337  * aligned accesses, up to sizeof(long).
 338  */
 339 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
 340                                        struct pt_regs *regs)
 341 {
 342         int err = 0;
 343         int c;
 344
 345         for (; nb > 0; nb -= c) {
 346                 c = max_align(ea);
 347                 if (c > nb)
 348                         c = max_align(nb);
 349                 switch (c) {
 350                 case 1:
 351                         err = __get_user(*dest, (unsigned char __user *) ea);
 352                         break;
 353                 case 2:
 354                         err = __get_user(*(u16 *)dest,
 355                                          (unsigned short __user *) ea);
 356                         break;
 357                 case 4:
 358                         err = __get_user(*(u32 *)dest,
 359                                          (unsigned int __user *) ea);
 360                         break;
 361 #ifdef __powerpc64__
 362                 case 8:
 363                         err = __get_user(*(unsigned long *)dest,
 364                                          (unsigned long __user *) ea);
 365                         break;
 366 #endif
 367                 }
 368                 if (err) {
 369                         regs->dar = ea;
 370                         return err;
 371                 }
 372                 dest += c;
 373                 ea += c;
 374         }
 375         return 0;
 376 }
 377
 378 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 379                                               unsigned long ea, int nb,
 380                                               struct pt_regs *regs)
 381 {
 382         union {
 383                 unsigned long ul;
 384                 u8 b[sizeof(unsigned long)];
 385         } u;
 386         int i;
 387         int err;
 388
 389         u.ul = 0;
 390         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 391         err = copy_mem_in(&u.b[i], ea, nb, regs);
 392         if (!err)
 393                 *dest = u.ul;
 394         return err;
 395 }
 396
 397 /*
 398  * Read memory at address ea for nb bytes, return 0 for success
 399  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 400  * If nb < sizeof(long), the result is right-justified on BE systems.
 401  */
 402 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 403                               struct pt_regs *regs)
 404 {
 405         if (!address_ok(regs, ea, nb))
 406                 return -EFAULT;
 407         if ((ea & (nb - 1)) == 0)
 408                 return read_mem_aligned(dest, ea, nb, regs);
 409         return read_mem_unaligned(dest, ea, nb, regs);
 410 }
 411 NOKPROBE_SYMBOL(read_mem);
 412
 413 static nokprobe_inline int write_mem_aligned(unsigned long val,
 414                                              unsigned long ea, int nb,
 415                                              struct pt_regs *regs)
 416 {
 417         int err = 0;
 418
 419         switch (nb) {
 420         case 1:
 421                 err = __put_user(val, (unsigned char __user *) ea);
 422                 break;
 423         case 2:
 424                 err = __put_user(val, (unsigned short __user *) ea);
 425                 break;
 426         case 4:
 427                 err = __put_user(val, (unsigned int __user *) ea);
 428                 break;
 429 #ifdef __powerpc64__
 430         case 8:
 431                 err = __put_user(val, (unsigned long __user *) ea);
 432                 break;
 433 #endif
 434         }
 435         if (err)
 436                 regs->dar = ea;
 437         return err;
 438 }
 439
 440 /*
 441  * Copy from a buffer to userspace, using the largest possible
 442  * aligned accesses, up to sizeof(long).
 443  */
 444 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
 445                                         struct pt_regs *regs)
 446 {
 447         int err = 0;
 448         int c;
 449
 450         for (; nb > 0; nb -= c) {
 451                 c = max_align(ea);
 452                 if (c > nb)
 453                         c = max_align(nb);
 454                 switch (c) {
 455                 case 1:
 456                         err = __put_user(*dest, (unsigned char __user *) ea);
 457                         break;
 458                 case 2:
 459                         err = __put_user(*(u16 *)dest,
 460                                          (unsigned short __user *) ea);
 461                         break;
 462                 case 4:
 463                         err = __put_user(*(u32 *)dest,
 464                                          (unsigned int __user *) ea);
 465                         break;
 466 #ifdef __powerpc64__
 467                 case 8:
 468                         err = __put_user(*(unsigned long *)dest,
 469                                          (unsigned long __user *) ea);
 470                         break;
 471 #endif
 472                 }
 473                 if (err) {
 474                         regs->dar = ea;
 475                         return err;
 476                 }
 477                 dest += c;
 478                 ea += c;
 479         }
 480         return 0;
 481 }
 482
 483 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 484                                                unsigned long ea, int nb,
 485                                                struct pt_regs *regs)
 486 {
 487         union {
 488                 unsigned long ul;
 489                 u8 b[sizeof(unsigned long)];
 490         } u;
 491         int i;
 492
 493         u.ul = val;
 494         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 495         return copy_mem_out(&u.b[i], ea, nb, regs);
 496 }
 497
 498 /*
 499  * Write memory at address ea for nb bytes, return 0 for success
 500  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 501  */
 502 static int write_mem(unsigned long val, unsigned long ea, int nb,
 503                                struct pt_regs *regs)
 504 {
 505         if (!address_ok(regs, ea, nb))
 506                 return -EFAULT;
 507         if ((ea & (nb - 1)) == 0)
 508                 return write_mem_aligned(val, ea, nb, regs);
 509         return write_mem_unaligned(val, ea, nb, regs);
 510 }
 511 NOKPROBE_SYMBOL(write_mem);
 512
 513 #ifdef CONFIG_PPC_FPU
 514 /*
 515  * These access either the real FP register or the image in the
 516  * thread_struct, depending on regs->msr & MSR_FP.
 517  */
 518 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 519                       struct pt_regs *regs, bool cross_endian)
 520 {
 521         int err, rn, nb;
 522         union {
 523                 int i;
 524                 unsigned int u;
 525                 float f;
 526                 double d[2];
 527                 unsigned long l[2];
 528                 u8 b[2 * sizeof(double)];
 529         } u;
 530
 531         nb = GETSIZE(op->type);
 532         if (!address_ok(regs, ea, nb))
 533                 return -EFAULT;
 534         rn = op->reg;
 535         err = copy_mem_in(u.b, ea, nb, regs);
 536         if (err)
 537                 return err;
 538         if (unlikely(cross_endian)) {
 539                 do_byte_reverse(u.b, min(nb, 8));
 540                 if (nb == 16)
 541                         do_byte_reverse(&u.b[8], 8);
 542         }
 543         preempt_disable();
 544         if (nb == 4) {
 545                 if (op->type & FPCONV)
 546                         conv_sp_to_dp(&u.f, &u.d[0]);
 547                 else if (op->type & SIGNEXT)
 548                         u.l[0] = u.i;
 549                 else
 550                         u.l[0] = u.u;
 551         }
 552         if (regs->msr & MSR_FP)
 553                 put_fpr(rn, &u.d[0]);
 554         else
 555                 current->thread.TS_FPR(rn) = u.l[0];
 556         if (nb == 16) {
 557                 /* lfdp */
 558                 rn |= 1;
 559                 if (regs->msr & MSR_FP)
 560                         put_fpr(rn, &u.d[1]);
 561                 else
 562                         current->thread.TS_FPR(rn) = u.l[1];
 563         }
 564         preempt_enable();
 565         return 0;
 566 }
 567 NOKPROBE_SYMBOL(do_fp_load);
 568
 569 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 570                        struct pt_regs *regs, bool cross_endian)
 571 {
 572         int rn, nb;
 573         union {
 574                 unsigned int u;
 575                 float f;
 576                 double d[2];
 577                 unsigned long l[2];
 578                 u8 b[2 * sizeof(double)];
 579         } u;
 580
 581         nb = GETSIZE(op->type);
 582         if (!address_ok(regs, ea, nb))
 583                 return -EFAULT;
 584         rn = op->reg;
 585         preempt_disable();
 586         if (regs->msr & MSR_FP)
 587                 get_fpr(rn, &u.d[0]);
 588         else
 589                 u.l[0] = current->thread.TS_FPR(rn);
 590         if (nb == 4) {
 591                 if (op->type & FPCONV)
 592                         conv_dp_to_sp(&u.d[0], &u.f);
 593                 else
 594                         u.u = u.l[0];
 595         }
 596         if (nb == 16) {
 597                 rn |= 1;
 598                 if (regs->msr & MSR_FP)
 599                         get_fpr(rn, &u.d[1]);
 600                 else
 601                         u.l[1] = current->thread.TS_FPR(rn);
 602         }
 603         preempt_enable();
 604         if (unlikely(cross_endian)) {
 605                 do_byte_reverse(u.b, min(nb, 8));
 606                 if (nb == 16)
 607                         do_byte_reverse(&u.b[8], 8);
 608         }
 609         return copy_mem_out(u.b, ea, nb, regs);
 610 }
 611 NOKPROBE_SYMBOL(do_fp_store);
 612 #endif
 613
 614 #ifdef CONFIG_ALTIVEC
 615 /* For Altivec/VMX, no need to worry about alignment */
 616 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 617                                        int size, struct pt_regs *regs,
 618                                        bool cross_endian)
 619 {
 620         int err;
 621         union {
 622                 __vector128 v;
 623                 u8 b[sizeof(__vector128)];
 624         } u = {};
 625
 626         if (!address_ok(regs, ea & ~0xfUL, 16))
 627                 return -EFAULT;
 628         /* align to multiple of size */
 629         ea &= ~(size - 1);
 630         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 631         if (err)
 632                 return err;
 633         if (unlikely(cross_endian))
 634                 do_byte_reverse(&u.b[ea & 0xf], size);
 635         preempt_disable();
 636         if (regs->msr & MSR_VEC)
 637                 put_vr(rn, &u.v);
 638         else
 639                 current->thread.vr_state.vr[rn] = u.v;
 640         preempt_enable();
 641         return 0;
 642 }
 643
 644 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 645                                         int size, struct pt_regs *regs,
 646                                         bool cross_endian)
 647 {
 648         union {
 649                 __vector128 v;
 650                 u8 b[sizeof(__vector128)];
 651         } u;
 652
 653         if (!address_ok(regs, ea & ~0xfUL, 16))
 654                 return -EFAULT;
 655         /* align to multiple of size */
 656         ea &= ~(size - 1);
 657
 658         preempt_disable();
 659         if (regs->msr & MSR_VEC)
 660                 get_vr(rn, &u.v);
 661         else
 662                 u.v = current->thread.vr_state.vr[rn];
 663         preempt_enable();
 664         if (unlikely(cross_endian))
 665                 do_byte_reverse(&u.b[ea & 0xf], size);
 666         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 667 }
 668 #endif /* CONFIG_ALTIVEC */
 669
 670 #ifdef __powerpc64__
 671 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 672                                       int reg, bool cross_endian)
 673 {
 674         int err;
 675
 676         if (!address_ok(regs, ea, 16))
 677                 return -EFAULT;
 678         /* if aligned, should be atomic */
 679         if ((ea & 0xf) == 0) {
 680                 err = do_lq(ea, &regs->gpr[reg]);
 681         } else {
 682                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 683                 if (!err)
 684                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 685         }
 686         if (!err && unlikely(cross_endian))
 687                 do_byte_reverse(&regs->gpr[reg], 16);
 688         return err;
 689 }
 690
 691 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 692                                        int reg, bool cross_endian)
 693 {
 694         int err;
 695         unsigned long vals[2];
 696
 697         if (!address_ok(regs, ea, 16))
 698                 return -EFAULT;
 699         vals[0] = regs->gpr[reg];
 700         vals[1] = regs->gpr[reg + 1];
 701         if (unlikely(cross_endian))
 702                 do_byte_reverse(vals, 16);
 703
 704         /* if aligned, should be atomic */
 705         if ((ea & 0xf) == 0)
 706                 return do_stq(ea, vals[0], vals[1]);
 707
 708         err = write_mem(vals[IS_LE], ea, 8, regs);
 709         if (!err)
 710                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 711         return err;
 712 }
 713 #endif /* __powerpc64 */
 714
 715 #ifdef CONFIG_VSX
 716 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 717                       const void *mem, bool rev)
 718 {
 719         int size, read_size;
 720         int i, j;
 721         const unsigned int *wp;
 722         const unsigned short *hp;
 723         const unsigned char *bp;
 724
 725         size = GETSIZE(op->type);
 726         reg->d[0] = reg->d[1] = 0;
 727
 728         switch (op->element_size) {
 729         case 32:
 730                 /* [p]lxvp[x] */
 731         case 16:
 732                 /* whole vector; lxv[x] or lxvl[l] */
 733                 if (size == 0)
 734                         break;
 735                 memcpy(reg, mem, size);
 736                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 737                         rev = !rev;
 738                 if (rev)
 739                         do_byte_reverse(reg, size);
 740                 break;
 741         case 8:
 742                 /* scalar loads, lxvd2x, lxvdsx */
 743                 read_size = (size >= 8) ? 8 : size;
 744                 i = IS_LE ? 8 : 8 - read_size;
 745                 memcpy(&reg->b[i], mem, read_size);
 746                 if (rev)
 747                         do_byte_reverse(&reg->b[i], 8);
 748                 if (size < 8) {
 749                         if (op->type & SIGNEXT) {
 750                                 /* size == 4 is the only case here */
 751                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 752                         } else if (op->vsx_flags & VSX_FPCONV) {
 753                                 preempt_disable();
 754                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 755                                               &reg->dp[IS_LE]);
 756                                 preempt_enable();
 757                         }
 758                 } else {
 759                         if (size == 16) {
 760                                 unsigned long v = *(unsigned long *)(mem + 8);
 761                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 762                         } else if (op->vsx_flags & VSX_SPLAT)
 763                                 reg->d[IS_BE] = reg->d[IS_LE];
 764                 }
 765                 break;
 766         case 4:
 767                 /* lxvw4x, lxvwsx */
 768                 wp = mem;
 769                 for (j = 0; j < size / 4; ++j) {
 770                         i = IS_LE ? 3 - j : j;
 771                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 772                 }
 773                 if (op->vsx_flags & VSX_SPLAT) {
 774                         u32 val = reg->w[IS_LE ? 3 : 0];
 775                         for (; j < 4; ++j) {
 776                                 i = IS_LE ? 3 - j : j;
 777                                 reg->w[i] = val;
 778                         }
 779                 }
 780                 break;
 781         case 2:
 782                 /* lxvh8x */
 783                 hp = mem;
 784                 for (j = 0; j < size / 2; ++j) {
 785                         i = IS_LE ? 7 - j : j;
 786                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 787                 }
 788                 break;
 789         case 1:
 790                 /* lxvb16x */
 791                 bp = mem;
 792                 for (j = 0; j < size; ++j) {
 793                         i = IS_LE ? 15 - j : j;
 794                         reg->b[i] = *bp++;
 795                 }
 796                 break;
 797         }
 798 }
 799 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 800 NOKPROBE_SYMBOL(emulate_vsx_load);
 801
 802 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 803                        void *mem, bool rev)
 804 {
 805         int size, write_size;
 806         int i, j;
 807         union vsx_reg buf;
 808         unsigned int *wp;
 809         unsigned short *hp;
 810         unsigned char *bp;
 811
 812         size = GETSIZE(op->type);
 813
 814         switch (op->element_size) {
 815         case 32:
 816                 /* [p]stxvp[x] */
 817                 if (size == 0)
 818                         break;
 819                 if (rev) {
 820                         /* reverse 32 bytes */
 821                         union vsx_reg buf32[2];
 822                         buf32[0].d[0] = byterev_8(reg[1].d[1]);
 823                         buf32[0].d[1] = byterev_8(reg[1].d[0]);
 824                         buf32[1].d[0] = byterev_8(reg[0].d[1]);
 825                         buf32[1].d[1] = byterev_8(reg[0].d[0]);
 826                         memcpy(mem, buf32, size);
 827                 } else {
 828                         memcpy(mem, reg, size);
 829                 }
 830                 break;
 831         case 16:
 832                 /* stxv, stxvx, stxvl, stxvll */
 833                 if (size == 0)
 834                         break;
 835                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 836                         rev = !rev;
 837                 if (rev) {
 838                         /* reverse 16 bytes */
 839                         buf.d[0] = byterev_8(reg->d[1]);
 840                         buf.d[1] = byterev_8(reg->d[0]);
 841                         reg = &buf;
 842                 }
 843                 memcpy(mem, reg, size);
 844                 break;
 845         case 8:
 846                 /* scalar stores, stxvd2x */
 847                 write_size = (size >= 8) ? 8 : size;
 848                 i = IS_LE ? 8 : 8 - write_size;
 849                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 850                         buf.d[0] = buf.d[1] = 0;
 851                         preempt_disable();
 852                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 853                         preempt_enable();
 854                         reg = &buf;
 855                 }
 856                 memcpy(mem, &reg->b[i], write_size);
 857                 if (size == 16)
 858                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 859                 if (unlikely(rev)) {
 860                         do_byte_reverse(mem, write_size);
 861                         if (size == 16)
 862                                 do_byte_reverse(mem + 8, 8);
 863                 }
 864                 break;
 865         case 4:
 866                 /* stxvw4x */
 867                 wp = mem;
 868                 for (j = 0; j < size / 4; ++j) {
 869                         i = IS_LE ? 3 - j : j;
 870                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 871                 }
 872                 break;
 873         case 2:
 874                 /* stxvh8x */
 875                 hp = mem;
 876                 for (j = 0; j < size / 2; ++j) {
 877                         i = IS_LE ? 7 - j : j;
 878                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 879                 }
 880                 break;
 881         case 1:
 882                 /* stvxb16x */
 883                 bp = mem;
 884                 for (j = 0; j < size; ++j) {
 885                         i = IS_LE ? 15 - j : j;
 886                         *bp++ = reg->b[i];
 887                 }
 888                 break;
 889         }
 890 }
 891 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 892 NOKPROBE_SYMBOL(emulate_vsx_store);
 893
 894 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 895                                        unsigned long ea, struct pt_regs *regs,
 896                                        bool cross_endian)
 897 {
 898         int reg = op->reg;
 899         int i, j, nr_vsx_regs;
 900         u8 mem[32];
 901         union vsx_reg buf[2];
 902         int size = GETSIZE(op->type);
 903
 904         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 905                 return -EFAULT;
 906
 907         nr_vsx_regs = size / sizeof(__vector128);
 908         emulate_vsx_load(op, buf, mem, cross_endian);
 909         preempt_disable();
 910         if (reg < 32) {
 911                 /* FP regs + extensions */
 912                 if (regs->msr & MSR_FP) {
 913                         for (i = 0; i < nr_vsx_regs; i++) {
 914                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 915                                 load_vsrn(reg + i, &buf[j].v);
 916                         }
 917                 } else {
 918                         for (i = 0; i < nr_vsx_regs; i++) {
 919                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 920                                 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
 921                                 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
 922                         }
 923                 }
 924         } else {
 925                 if (regs->msr & MSR_VEC) {
 926                         for (i = 0; i < nr_vsx_regs; i++) {
 927                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 928                                 load_vsrn(reg + i, &buf[j].v);
 929                         }
 930                 } else {
 931                         for (i = 0; i < nr_vsx_regs; i++) {
 932                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 933                                 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
 934                         }
 935                 }
 936         }
 937         preempt_enable();
 938         return 0;
 939 }
 940
 941 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 942                                         unsigned long ea, struct pt_regs *regs,
 943                                         bool cross_endian)
 944 {
 945         int reg = op->reg;
 946         int i, j, nr_vsx_regs;
 947         u8 mem[32];
 948         union vsx_reg buf[2];
 949         int size = GETSIZE(op->type);
 950
 951         if (!address_ok(regs, ea, size))
 952                 return -EFAULT;
 953
 954         nr_vsx_regs = size / sizeof(__vector128);
 955         preempt_disable();
 956         if (reg < 32) {
 957                 /* FP regs + extensions */
 958                 if (regs->msr & MSR_FP) {
 959                         for (i = 0; i < nr_vsx_regs; i++) {
 960                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 961                                 store_vsrn(reg + i, &buf[j].v);
 962                         }
 963                 } else {
 964                         for (i = 0; i < nr_vsx_regs; i++) {
 965                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 966                                 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
 967                                 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
 968                         }
 969                 }
 970         } else {
 971                 if (regs->msr & MSR_VEC) {
 972                         for (i = 0; i < nr_vsx_regs; i++) {
 973                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 974                                 store_vsrn(reg + i, &buf[j].v);
 975                         }
 976                 } else {
 977                         for (i = 0; i < nr_vsx_regs; i++) {
 978                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 979                                 buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
 980                         }
 981                 }
 982         }
 983         preempt_enable();
 984         emulate_vsx_store(op, buf, mem, cross_endian);
 985         return  copy_mem_out(mem, ea, size, regs);
 986 }
 987 #endif /* CONFIG_VSX */
 988
 989 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 990 {
 991         int err;
 992         unsigned long i, size;
 993
 994 #ifdef __powerpc64__
 995         size = ppc64_caches.l1d.block_size;
 996         if (!(regs->msr & MSR_64BIT))
 997                 ea &= 0xffffffffUL;
 998 #else
 999         size = L1_CACHE_BYTES;
1000 #endif
1001         ea &= ~(size - 1);
1002         if (!address_ok(regs, ea, size))
1003                 return -EFAULT;
1004         for (i = 0; i < size; i += sizeof(long)) {
1005                 err = __put_user(0, (unsigned long __user *) (ea + i));
1006                 if (err) {
1007                         regs->dar = ea;
1008                         return err;
1009                 }
1010         }
1011         return 0;
1012 }
1013 NOKPROBE_SYMBOL(emulate_dcbz);
1014
1015 #define __put_user_asmx(x, addr, err, op, cr)           \
1016         __asm__ __volatile__(                           \
1017                 "1:     " op " %2,0,%3\n"               \
1018                 "       mfcr    %1\n"                   \
1019                 "2:\n"                                  \
1020                 ".section .fixup,\"ax\"\n"              \
1021                 "3:     li      %0,%4\n"                \
1022                 "       b       2b\n"                   \
1023                 ".previous\n"                           \
1024                 EX_TABLE(1b, 3b)                        \
1025                 : "=r" (err), "=r" (cr)                 \
1026                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1027
1028 #define __get_user_asmx(x, addr, err, op)               \
1029         __asm__ __volatile__(                           \
1030                 "1:     "op" %1,0,%2\n"                 \
1031                 "2:\n"                                  \
1032                 ".section .fixup,\"ax\"\n"              \
1033                 "3:     li      %0,%3\n"                \
1034                 "       b       2b\n"                   \
1035                 ".previous\n"                           \
1036                 EX_TABLE(1b, 3b)                        \
1037                 : "=r" (err), "=r" (x)                  \
1038                 : "r" (addr), "i" (-EFAULT), "0" (err))
1039
1040 #define __cacheop_user_asmx(addr, err, op)              \
1041         __asm__ __volatile__(                           \
1042                 "1:     "op" 0,%1\n"                    \
1043                 "2:\n"                                  \
1044                 ".section .fixup,\"ax\"\n"              \
1045                 "3:     li      %0,%3\n"                \
1046                 "       b       2b\n"                   \
1047                 ".previous\n"                           \
1048                 EX_TABLE(1b, 3b)                        \
1049                 : "=r" (err)                            \
1050                 : "r" (addr), "i" (-EFAULT), "0" (err))
1051
1052 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1053                                     struct instruction_op *op)
1054 {
1055         long val = op->val;
1056
1057         op->type |= SETCC;
1058         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1059 #ifdef __powerpc64__
1060         if (!(regs->msr & MSR_64BIT))
1061                 val = (int) val;
1062 #endif
1063         if (val < 0)
1064                 op->ccval |= 0x80000000;
1065         else if (val > 0)
1066                 op->ccval |= 0x40000000;
1067         else
1068                 op->ccval |= 0x20000000;
1069 }
1070
1071 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1072 {
1073         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1074                 if (val)
1075                         op->xerval |= XER_CA32;
1076                 else
1077                         op->xerval &= ~XER_CA32;
1078         }
1079 }
1080
1081 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1082                                      struct instruction_op *op, int rd,
1083                                      unsigned long val1, unsigned long val2,
1084                                      unsigned long carry_in)
1085 {
1086         unsigned long val = val1 + val2;
1087
1088         if (carry_in)
1089                 ++val;
1090         op->type = COMPUTE + SETREG + SETXER;
1091         op->reg = rd;
1092         op->val = val;
1093 #ifdef __powerpc64__
1094         if (!(regs->msr & MSR_64BIT)) {
1095                 val = (unsigned int) val;
1096                 val1 = (unsigned int) val1;
1097         }
1098 #endif
1099         op->xerval = regs->xer;
1100         if (val < val1 || (carry_in && val == val1))
1101                 op->xerval |= XER_CA;
1102         else
1103                 op->xerval &= ~XER_CA;
1104
1105         set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1106                         (carry_in && (unsigned int)val == (unsigned int)val1));
1107 }
1108
1109 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1110                                           struct instruction_op *op,
1111                                           long v1, long v2, int crfld)
1112 {
1113         unsigned int crval, shift;
1114
1115         op->type = COMPUTE + SETCC;
1116         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1117         if (v1 < v2)
1118                 crval |= 8;
1119         else if (v1 > v2)
1120                 crval |= 4;
1121         else
1122                 crval |= 2;
1123         shift = (7 - crfld) * 4;
1124         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1125 }
1126
1127 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1128                                             struct instruction_op *op,
1129                                             unsigned long v1,
1130                                             unsigned long v2, int crfld)
1131 {
1132         unsigned int crval, shift;
1133
1134         op->type = COMPUTE + SETCC;
1135         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1136         if (v1 < v2)
1137                 crval |= 8;
1138         else if (v1 > v2)
1139                 crval |= 4;
1140         else
1141                 crval |= 2;
1142         shift = (7 - crfld) * 4;
1143         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1144 }
1145
1146 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1147                                     struct instruction_op *op,
1148                                     unsigned long v1, unsigned long v2)
1149 {
1150         unsigned long long out_val, mask;
1151         int i;
1152
1153         out_val = 0;
1154         for (i = 0; i < 8; i++) {
1155                 mask = 0xffUL << (i * 8);
1156                 if ((v1 & mask) == (v2 & mask))
1157                         out_val |= mask;
1158         }
1159         op->val = out_val;
1160 }
1161
1162 /*
1163  * The size parameter is used to adjust the equivalent popcnt instruction.
1164  * popcntb = 8, popcntw = 32, popcntd = 64
1165  */
1166 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1167                                       struct instruction_op *op,
1168                                       unsigned long v1, int size)
1169 {
1170         unsigned long long out = v1;
1171
1172         out -= (out >> 1) & 0x5555555555555555ULL;
1173         out = (0x3333333333333333ULL & out) +
1174               (0x3333333333333333ULL & (out >> 2));
1175         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1176
1177         if (size == 8) {        /* popcntb */
1178                 op->val = out;
1179                 return;
1180         }
1181         out += out >> 8;
1182         out += out >> 16;
1183         if (size == 32) {       /* popcntw */
1184                 op->val = out & 0x0000003f0000003fULL;
1185                 return;
1186         }
1187
1188         out = (out + (out >> 32)) & 0x7f;
1189         op->val = out;  /* popcntd */
1190 }
1191
1192 #ifdef CONFIG_PPC64
1193 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1194                                       struct instruction_op *op,
1195                                       unsigned long v1, unsigned long v2)
1196 {
1197         unsigned char perm, idx;
1198         unsigned int i;
1199
1200         perm = 0;
1201         for (i = 0; i < 8; i++) {
1202                 idx = (v1 >> (i * 8)) & 0xff;
1203                 if (idx < 64)
1204                         if (v2 & PPC_BIT(idx))
1205                                 perm |= 1 << i;
1206         }
1207         op->val = perm;
1208 }
1209 #endif /* CONFIG_PPC64 */
1210 /*
1211  * The size parameter adjusts the equivalent prty instruction.
1212  * prtyw = 32, prtyd = 64
1213  */
1214 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1215                                     struct instruction_op *op,
1216                                     unsigned long v, int size)
1217 {
1218         unsigned long long res = v ^ (v >> 8);
1219
1220         res ^= res >> 16;
1221         if (size == 32) {               /* prtyw */
1222                 op->val = res & 0x0000000100000001ULL;
1223                 return;
1224         }
1225
1226         res ^= res >> 32;
1227         op->val = res & 1;      /*prtyd */
1228 }
1229
1230 static nokprobe_inline int trap_compare(long v1, long v2)
1231 {
1232         int ret = 0;
1233
1234         if (v1 < v2)
1235                 ret |= 0x10;
1236         else if (v1 > v2)
1237                 ret |= 0x08;
1238         else
1239                 ret |= 0x04;
1240         if ((unsigned long)v1 < (unsigned long)v2)
1241                 ret |= 0x02;
1242         else if ((unsigned long)v1 > (unsigned long)v2)
1243                 ret |= 0x01;
1244         return ret;
1245 }
1246
1247 /*
1248  * Elements of 32-bit rotate and mask instructions.
1249  */
1250 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1251                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1252 #ifdef __powerpc64__
1253 #define MASK64_L(mb)    (~0UL >> (mb))
1254 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1255 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1256 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1257 #else
1258 #define DATA32(x)       (x)
1259 #endif
1260 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1261
1262 /*
1263  * Decode an instruction, and return information about it in *op
1264  * without changing *regs.
1265  * Integer arithmetic and logical instructions, branches, and barrier
1266  * instructions can be emulated just using the information in *op.
1267  *
1268  * Return value is 1 if the instruction can be emulated just by
1269  * updating *regs with the information in *op, -1 if we need the
1270  * GPRs but *regs doesn't contain the full register set, or 0
1271  * otherwise.
1272  */
1273 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1274                   struct ppc_inst instr)
1275 {
1276 #ifdef CONFIG_PPC64
1277         unsigned int suffixopcode, prefixtype, prefix_r;
1278 #endif
1279         unsigned int opcode, ra, rb, rc, rd, spr, u;
1280         unsigned long int imm;
1281         unsigned long int val, val2;
1282         unsigned int mb, me, sh;
1283         unsigned int word, suffix;
1284         long ival;
1285
1286         word = ppc_inst_val(instr);
1287         suffix = ppc_inst_suffix(instr);
1288
1289         op->type = COMPUTE;
1290
1291         opcode = ppc_inst_primary_opcode(instr);
1292         switch (opcode) {
1293         case 16:        /* bc */
1294                 op->type = BRANCH;
1295                 imm = (signed short)(word & 0xfffc);
1296                 if ((word & 2) == 0)
1297                         imm += regs->nip;
1298                 op->val = truncate_if_32bit(regs->msr, imm);
1299                 if (word & 1)
1300                         op->type |= SETLK;
1301                 if (branch_taken(word, regs, op))
1302                         op->type |= BRTAKEN;
1303                 return 1;
1304 #ifdef CONFIG_PPC64
1305         case 17:        /* sc */
1306                 if ((word & 0xfe2) == 2)
1307                         op->type = SYSCALL;
1308                 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1309                                 (word & 0xfe3) == 1)
1310                         op->type = SYSCALL_VECTORED_0;
1311                 else
1312                         op->type = UNKNOWN;
1313                 return 0;
1314 #endif
1315         case 18:        /* b */
1316                 op->type = BRANCH | BRTAKEN;
1317                 imm = word & 0x03fffffc;
1318                 if (imm & 0x02000000)
1319                         imm -= 0x04000000;
1320                 if ((word & 2) == 0)
1321                         imm += regs->nip;
1322                 op->val = truncate_if_32bit(regs->msr, imm);
1323                 if (word & 1)
1324                         op->type |= SETLK;
1325                 return 1;
1326         case 19:
1327                 switch ((word >> 1) & 0x3ff) {
1328                 case 0:         /* mcrf */
1329                         op->type = COMPUTE + SETCC;
1330                         rd = 7 - ((word >> 23) & 0x7);
1331                         ra = 7 - ((word >> 18) & 0x7);
1332                         rd *= 4;
1333                         ra *= 4;
1334                         val = (regs->ccr >> ra) & 0xf;
1335                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1336                         return 1;
1337
1338                 case 16:        /* bclr */
1339                 case 528:       /* bcctr */
1340                         op->type = BRANCH;
1341                         imm = (word & 0x400)? regs->ctr: regs->link;
1342                         op->val = truncate_if_32bit(regs->msr, imm);
1343                         if (word & 1)
1344                                 op->type |= SETLK;
1345                         if (branch_taken(word, regs, op))
1346                                 op->type |= BRTAKEN;
1347                         return 1;
1348
1349                 case 18:        /* rfid, scary */
1350                         if (regs->msr & MSR_PR)
1351                                 goto priv;
1352                         op->type = RFI;
1353                         return 0;
1354
1355                 case 150:       /* isync */
1356                         op->type = BARRIER | BARRIER_ISYNC;
1357                         return 1;
1358
1359                 case 33:        /* crnor */
1360                 case 129:       /* crandc */
1361                 case 193:       /* crxor */
1362                 case 225:       /* crnand */
1363                 case 257:       /* crand */
1364                 case 289:       /* creqv */
1365                 case 417:       /* crorc */
1366                 case 449:       /* cror */
1367                         op->type = COMPUTE + SETCC;
1368                         ra = (word >> 16) & 0x1f;
1369                         rb = (word >> 11) & 0x1f;
1370                         rd = (word >> 21) & 0x1f;
1371                         ra = (regs->ccr >> (31 - ra)) & 1;
1372                         rb = (regs->ccr >> (31 - rb)) & 1;
1373                         val = (word >> (6 + ra * 2 + rb)) & 1;
1374                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1375                                 (val << (31 - rd));
1376                         return 1;
1377                 }
1378                 break;
1379         case 31:
1380                 switch ((word >> 1) & 0x3ff) {
1381                 case 598:       /* sync */
1382                         op->type = BARRIER + BARRIER_SYNC;
1383 #ifdef __powerpc64__
1384                         switch ((word >> 21) & 3) {
1385                         case 1:         /* lwsync */
1386                                 op->type = BARRIER + BARRIER_LWSYNC;
1387                                 break;
1388                         case 2:         /* ptesync */
1389                                 op->type = BARRIER + BARRIER_PTESYNC;
1390                                 break;
1391                         }
1392 #endif
1393                         return 1;
1394
1395                 case 854:       /* eieio */
1396                         op->type = BARRIER + BARRIER_EIEIO;
1397                         return 1;
1398                 }
1399                 break;
1400         }
1401
1402         /* Following cases refer to regs->gpr[], so we need all regs */
1403         if (!FULL_REGS(regs))
1404                 return -1;
1405
1406         rd = (word >> 21) & 0x1f;
1407         ra = (word >> 16) & 0x1f;
1408         rb = (word >> 11) & 0x1f;
1409         rc = (word >> 6) & 0x1f;
1410
1411         switch (opcode) {
1412 #ifdef __powerpc64__
1413         case 1:
1414                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1415                         return -1;
1416
1417                 prefix_r = GET_PREFIX_R(word);
1418                 ra = GET_PREFIX_RA(suffix);
1419                 rd = (suffix >> 21) & 0x1f;
1420                 op->reg = rd;
1421                 op->val = regs->gpr[rd];
1422                 suffixopcode = get_op(suffix);
1423                 prefixtype = (word >> 24) & 0x3;
1424                 switch (prefixtype) {
1425                 case 2:
1426                         if (prefix_r && ra)
1427                                 return 0;
1428                         switch (suffixopcode) {
1429                         case 14:        /* paddi */
1430                                 op->type = COMPUTE | PREFIXED;
1431                                 op->val = mlsd_8lsd_ea(word, suffix, regs);
1432                                 goto compute_done;
1433                         }
1434                 }
1435                 break;
1436         case 2:         /* tdi */
1437                 if (rd & trap_compare(regs->gpr[ra], (short) word))
1438                         goto trap;
1439                 return 1;
1440 #endif
1441         case 3:         /* twi */
1442                 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1443                         goto trap;
1444                 return 1;
1445
1446 #ifdef __powerpc64__
1447         case 4:
1448                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1449                         return -1;
1450
1451                 switch (word & 0x3f) {
1452                 case 48:        /* maddhd */
1453                         asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1454                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1455                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1456                         goto compute_done;
1457
1458                 case 49:        /* maddhdu */
1459                         asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1460                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1461                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1462                         goto compute_done;
1463
1464                 case 51:        /* maddld */
1465                         asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1466                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1467                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1468                         goto compute_done;
1469                 }
1470
1471                 /*
1472                  * There are other instructions from ISA 3.0 with the same
1473                  * primary opcode which do not have emulation support yet.
1474                  */
1475                 return -1;
1476 #endif
1477
1478         case 7:         /* mulli */
1479                 op->val = regs->gpr[ra] * (short) word;
1480                 goto compute_done;
1481
1482         case 8:         /* subfic */
1483                 imm = (short) word;
1484                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1485                 return 1;
1486
1487         case 10:        /* cmpli */
1488                 imm = (unsigned short) word;
1489                 val = regs->gpr[ra];
1490 #ifdef __powerpc64__
1491                 if ((rd & 1) == 0)
1492                         val = (unsigned int) val;
1493 #endif
1494                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1495                 return 1;
1496
1497         case 11:        /* cmpi */
1498                 imm = (short) word;
1499                 val = regs->gpr[ra];
1500 #ifdef __powerpc64__
1501                 if ((rd & 1) == 0)
1502                         val = (int) val;
1503 #endif
1504                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1505                 return 1;
1506
1507         case 12:        /* addic */
1508                 imm = (short) word;
1509                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1510                 return 1;
1511
1512         case 13:        /* addic. */
1513                 imm = (short) word;
1514                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1515                 set_cr0(regs, op);
1516                 return 1;
1517
1518         case 14:        /* addi */
1519                 imm = (short) word;
1520                 if (ra)
1521                         imm += regs->gpr[ra];
1522                 op->val = imm;
1523                 goto compute_done;
1524
1525         case 15:        /* addis */
1526                 imm = ((short) word) << 16;
1527                 if (ra)
1528                         imm += regs->gpr[ra];
1529                 op->val = imm;
1530                 goto compute_done;
1531
1532         case 19:
1533                 if (((word >> 1) & 0x1f) == 2) {
1534                         /* addpcis */
1535                         imm = (short) (word & 0xffc1);  /* d0 + d2 fields */
1536                         imm |= (word >> 15) & 0x3e;     /* d1 field */
1537                         op->val = regs->nip + (imm << 16) + 4;
1538                         goto compute_done;
1539                 }
1540                 op->type = UNKNOWN;
1541                 return 0;
1542
1543         case 20:        /* rlwimi */
1544                 mb = (word >> 6) & 0x1f;
1545                 me = (word >> 1) & 0x1f;
1546                 val = DATA32(regs->gpr[rd]);
1547                 imm = MASK32(mb, me);
1548                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1549                 goto logical_done;
1550
1551         case 21:        /* rlwinm */
1552                 mb = (word >> 6) & 0x1f;
1553                 me = (word >> 1) & 0x1f;
1554                 val = DATA32(regs->gpr[rd]);
1555                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1556                 goto logical_done;
1557
1558         case 23:        /* rlwnm */
1559                 mb = (word >> 6) & 0x1f;
1560                 me = (word >> 1) & 0x1f;
1561                 rb = regs->gpr[rb] & 0x1f;
1562                 val = DATA32(regs->gpr[rd]);
1563                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1564                 goto logical_done;
1565
1566         case 24:        /* ori */
1567                 op->val = regs->gpr[rd] | (unsigned short) word;
1568                 goto logical_done_nocc;
1569
1570         case 25:        /* oris */
1571                 imm = (unsigned short) word;
1572                 op->val = regs->gpr[rd] | (imm << 16);
1573                 goto logical_done_nocc;
1574
1575         case 26:        /* xori */
1576                 op->val = regs->gpr[rd] ^ (unsigned short) word;
1577                 goto logical_done_nocc;
1578
1579         case 27:        /* xoris */
1580                 imm = (unsigned short) word;
1581                 op->val = regs->gpr[rd] ^ (imm << 16);
1582                 goto logical_done_nocc;
1583
1584         case 28:        /* andi. */
1585                 op->val = regs->gpr[rd] & (unsigned short) word;
1586                 set_cr0(regs, op);
1587                 goto logical_done_nocc;
1588
1589         case 29:        /* andis. */
1590                 imm = (unsigned short) word;
1591                 op->val = regs->gpr[rd] & (imm << 16);
1592                 set_cr0(regs, op);
1593                 goto logical_done_nocc;
1594
1595 #ifdef __powerpc64__
1596         case 30:        /* rld* */
1597                 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1598                 val = regs->gpr[rd];
1599                 if ((word & 0x10) == 0) {
1600                         sh = rb | ((word & 2) << 4);
1601                         val = ROTATE(val, sh);
1602                         switch ((word >> 2) & 3) {
1603                         case 0:         /* rldicl */
1604                                 val &= MASK64_L(mb);
1605                                 break;
1606                         case 1:         /* rldicr */
1607                                 val &= MASK64_R(mb);
1608                                 break;
1609                         case 2:         /* rldic */
1610                                 val &= MASK64(mb, 63 - sh);
1611                                 break;
1612                         case 3:         /* rldimi */
1613                                 imm = MASK64(mb, 63 - sh);
1614                                 val = (regs->gpr[ra] & ~imm) |
1615                                         (val & imm);
1616                         }
1617                         op->val = val;
1618                         goto logical_done;
1619                 } else {
1620                         sh = regs->gpr[rb] & 0x3f;
1621                         val = ROTATE(val, sh);
1622                         switch ((word >> 1) & 7) {
1623                         case 0:         /* rldcl */
1624                                 op->val = val & MASK64_L(mb);
1625                                 goto logical_done;
1626                         case 1:         /* rldcr */
1627                                 op->val = val & MASK64_R(mb);
1628                                 goto logical_done;
1629                         }
1630                 }
1631 #endif
1632                 op->type = UNKNOWN;     /* illegal instruction */
1633                 return 0;
1634
1635         case 31:
1636                 /* isel occupies 32 minor opcodes */
1637                 if (((word >> 1) & 0x1f) == 15) {
1638                         mb = (word >> 6) & 0x1f; /* bc field */
1639                         val = (regs->ccr >> (31 - mb)) & 1;
1640                         val2 = (ra) ? regs->gpr[ra] : 0;
1641
1642                         op->val = (val) ? val2 : regs->gpr[rb];
1643                         goto compute_done;
1644                 }
1645
1646                 switch ((word >> 1) & 0x3ff) {
1647                 case 4:         /* tw */
1648                         if (rd == 0x1f ||
1649                             (rd & trap_compare((int)regs->gpr[ra],
1650                                                (int)regs->gpr[rb])))
1651                                 goto trap;
1652                         return 1;
1653 #ifdef __powerpc64__
1654                 case 68:        /* td */
1655                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1656                                 goto trap;
1657                         return 1;
1658 #endif
1659                 case 83:        /* mfmsr */
1660                         if (regs->msr & MSR_PR)
1661                                 goto priv;
1662                         op->type = MFMSR;
1663                         op->reg = rd;
1664                         return 0;
1665                 case 146:       /* mtmsr */
1666                         if (regs->msr & MSR_PR)
1667                                 goto priv;
1668                         op->type = MTMSR;
1669                         op->reg = rd;
1670                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1671                         return 0;
1672 #ifdef CONFIG_PPC64
1673                 case 178:       /* mtmsrd */
1674                         if (regs->msr & MSR_PR)
1675                                 goto priv;
1676                         op->type = MTMSR;
1677                         op->reg = rd;
1678                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1679                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1680                         imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1681                         op->val = imm;
1682                         return 0;
1683 #endif
1684
1685                 case 19:        /* mfcr */
1686                         imm = 0xffffffffUL;
1687                         if ((word >> 20) & 1) {
1688                                 imm = 0xf0000000UL;
1689                                 for (sh = 0; sh < 8; ++sh) {
1690                                         if (word & (0x80000 >> sh))
1691                                                 break;
1692                                         imm >>= 4;
1693                                 }
1694                         }
1695                         op->val = regs->ccr & imm;
1696                         goto compute_done;
1697
1698                 case 144:       /* mtcrf */
1699                         op->type = COMPUTE + SETCC;
1700                         imm = 0xf0000000UL;
1701                         val = regs->gpr[rd];
1702                         op->ccval = regs->ccr;
1703                         for (sh = 0; sh < 8; ++sh) {
1704                                 if (word & (0x80000 >> sh))
1705                                         op->ccval = (op->ccval & ~imm) |
1706                                                 (val & imm);
1707                                 imm >>= 4;
1708                         }
1709                         return 1;
1710
1711                 case 339:       /* mfspr */
1712                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1713                         op->type = MFSPR;
1714                         op->reg = rd;
1715                         op->spr = spr;
1716                         if (spr == SPRN_XER || spr == SPRN_LR ||
1717                             spr == SPRN_CTR)
1718                                 return 1;
1719                         return 0;
1720
1721                 case 467:       /* mtspr */
1722                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1723                         op->type = MTSPR;
1724                         op->val = regs->gpr[rd];
1725                         op->spr = spr;
1726                         if (spr == SPRN_XER || spr == SPRN_LR ||
1727                             spr == SPRN_CTR)
1728                                 return 1;
1729                         return 0;
1730
1731 /*
1732  * Compare instructions
1733  */
1734                 case 0: /* cmp */
1735                         val = regs->gpr[ra];
1736                         val2 = regs->gpr[rb];
1737 #ifdef __powerpc64__
1738                         if ((rd & 1) == 0) {
1739                                 /* word (32-bit) compare */
1740                                 val = (int) val;
1741                                 val2 = (int) val2;
1742                         }
1743 #endif
1744                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1745                         return 1;
1746
1747                 case 32:        /* cmpl */
1748                         val = regs->gpr[ra];
1749                         val2 = regs->gpr[rb];
1750 #ifdef __powerpc64__
1751                         if ((rd & 1) == 0) {
1752                                 /* word (32-bit) compare */
1753                                 val = (unsigned int) val;
1754                                 val2 = (unsigned int) val2;
1755                         }
1756 #endif
1757                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1758                         return 1;
1759
1760                 case 508: /* cmpb */
1761                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1762                         goto logical_done_nocc;
1763
1764 /*
1765  * Arithmetic instructions
1766  */
1767                 case 8: /* subfc */
1768                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1769                                        regs->gpr[rb], 1);
1770                         goto arith_done;
1771 #ifdef __powerpc64__
1772                 case 9: /* mulhdu */
1773                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1774                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1775                         goto arith_done;
1776 #endif
1777                 case 10:        /* addc */
1778                         add_with_carry(regs, op, rd, regs->gpr[ra],
1779                                        regs->gpr[rb], 0);
1780                         goto arith_done;
1781
1782                 case 11:        /* mulhwu */
1783                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1784                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1785                         goto arith_done;
1786
1787                 case 40:        /* subf */
1788                         op->val = regs->gpr[rb] - regs->gpr[ra];
1789                         goto arith_done;
1790 #ifdef __powerpc64__
1791                 case 73:        /* mulhd */
1792                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1793                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1794                         goto arith_done;
1795 #endif
1796                 case 75:        /* mulhw */
1797                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1798                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1799                         goto arith_done;
1800
1801                 case 104:       /* neg */
1802                         op->val = -regs->gpr[ra];
1803                         goto arith_done;
1804
1805                 case 136:       /* subfe */
1806                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1807                                        regs->gpr[rb], regs->xer & XER_CA);
1808                         goto arith_done;
1809
1810                 case 138:       /* adde */
1811                         add_with_carry(regs, op, rd, regs->gpr[ra],
1812                                        regs->gpr[rb], regs->xer & XER_CA);
1813                         goto arith_done;
1814
1815                 case 200:       /* subfze */
1816                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1817                                        regs->xer & XER_CA);
1818                         goto arith_done;
1819
1820                 case 202:       /* addze */
1821                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1822                                        regs->xer & XER_CA);
1823                         goto arith_done;
1824
1825                 case 232:       /* subfme */
1826                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1827                                        regs->xer & XER_CA);
1828                         goto arith_done;
1829 #ifdef __powerpc64__
1830                 case 233:       /* mulld */
1831                         op->val = regs->gpr[ra] * regs->gpr[rb];
1832                         goto arith_done;
1833 #endif
1834                 case 234:       /* addme */
1835                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1836                                        regs->xer & XER_CA);
1837                         goto arith_done;
1838
1839                 case 235:       /* mullw */
1840                         op->val = (long)(int) regs->gpr[ra] *
1841                                 (int) regs->gpr[rb];
1842
1843                         goto arith_done;
1844 #ifdef __powerpc64__
1845                 case 265:       /* modud */
1846                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1847                                 return -1;
1848                         op->val = regs->gpr[ra] % regs->gpr[rb];
1849                         goto compute_done;
1850 #endif
1851                 case 266:       /* add */
1852                         op->val = regs->gpr[ra] + regs->gpr[rb];
1853                         goto arith_done;
1854
1855                 case 267:       /* moduw */
1856                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1857                                 return -1;
1858                         op->val = (unsigned int) regs->gpr[ra] %
1859                                 (unsigned int) regs->gpr[rb];
1860                         goto compute_done;
1861 #ifdef __powerpc64__
1862                 case 457:       /* divdu */
1863                         op->val = regs->gpr[ra] / regs->gpr[rb];
1864                         goto arith_done;
1865 #endif
1866                 case 459:       /* divwu */
1867                         op->val = (unsigned int) regs->gpr[ra] /
1868                                 (unsigned int) regs->gpr[rb];
1869                         goto arith_done;
1870 #ifdef __powerpc64__
1871                 case 489:       /* divd */
1872                         op->val = (long int) regs->gpr[ra] /
1873                                 (long int) regs->gpr[rb];
1874                         goto arith_done;
1875 #endif
1876                 case 491:       /* divw */
1877                         op->val = (int) regs->gpr[ra] /
1878                                 (int) regs->gpr[rb];
1879                         goto arith_done;
1880 #ifdef __powerpc64__
1881                 case 425:       /* divde[.] */
1882                         asm volatile(PPC_DIVDE(%0, %1, %2) :
1883                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1884                                 "r" (regs->gpr[rb]));
1885                         goto arith_done;
1886                 case 393:       /* divdeu[.] */
1887                         asm volatile(PPC_DIVDEU(%0, %1, %2) :
1888                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1889                                 "r" (regs->gpr[rb]));
1890                         goto arith_done;
1891 #endif
1892                 case 755:       /* darn */
1893                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1894                                 return -1;
1895                         switch (ra & 0x3) {
1896                         case 0:
1897                                 /* 32-bit conditioned */
1898                                 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1899                                 goto compute_done;
1900
1901                         case 1:
1902                                 /* 64-bit conditioned */
1903                                 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1904                                 goto compute_done;
1905
1906                         case 2:
1907                                 /* 64-bit raw */
1908                                 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1909                                 goto compute_done;
1910                         }
1911
1912                         return -1;
1913 #ifdef __powerpc64__
1914                 case 777:       /* modsd */
1915                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1916                                 return -1;
1917                         op->val = (long int) regs->gpr[ra] %
1918                                 (long int) regs->gpr[rb];
1919                         goto compute_done;
1920 #endif
1921                 case 779:       /* modsw */
1922                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1923                                 return -1;
1924                         op->val = (int) regs->gpr[ra] %
1925                                 (int) regs->gpr[rb];
1926                         goto compute_done;
1927
1928
1929 /*
1930  * Logical instructions
1931  */
1932                 case 26:        /* cntlzw */
1933                         val = (unsigned int) regs->gpr[rd];
1934                         op->val = ( val ? __builtin_clz(val) : 32 );
1935                         goto logical_done;
1936 #ifdef __powerpc64__
1937                 case 58:        /* cntlzd */
1938                         val = regs->gpr[rd];
1939                         op->val = ( val ? __builtin_clzl(val) : 64 );
1940                         goto logical_done;
1941 #endif
1942                 case 28:        /* and */
1943                         op->val = regs->gpr[rd] & regs->gpr[rb];
1944                         goto logical_done;
1945
1946                 case 60:        /* andc */
1947                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1948                         goto logical_done;
1949
1950                 case 122:       /* popcntb */
1951                         do_popcnt(regs, op, regs->gpr[rd], 8);
1952                         goto logical_done_nocc;
1953
1954                 case 124:       /* nor */
1955                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1956                         goto logical_done;
1957
1958                 case 154:       /* prtyw */
1959                         do_prty(regs, op, regs->gpr[rd], 32);
1960                         goto logical_done_nocc;
1961
1962                 case 186:       /* prtyd */
1963                         do_prty(regs, op, regs->gpr[rd], 64);
1964                         goto logical_done_nocc;
1965 #ifdef CONFIG_PPC64
1966                 case 252:       /* bpermd */
1967                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1968                         goto logical_done_nocc;
1969 #endif
1970                 case 284:       /* xor */
1971                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1972                         goto logical_done;
1973
1974                 case 316:       /* xor */
1975                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1976                         goto logical_done;
1977
1978                 case 378:       /* popcntw */
1979                         do_popcnt(regs, op, regs->gpr[rd], 32);
1980                         goto logical_done_nocc;
1981
1982                 case 412:       /* orc */
1983                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1984                         goto logical_done;
1985
1986                 case 444:       /* or */
1987                         op->val = regs->gpr[rd] | regs->gpr[rb];
1988                         goto logical_done;
1989
1990                 case 476:       /* nand */
1991                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1992                         goto logical_done;
1993 #ifdef CONFIG_PPC64
1994                 case 506:       /* popcntd */
1995                         do_popcnt(regs, op, regs->gpr[rd], 64);
1996                         goto logical_done_nocc;
1997 #endif
1998                 case 538:       /* cnttzw */
1999                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2000                                 return -1;
2001                         val = (unsigned int) regs->gpr[rd];
2002                         op->val = (val ? __builtin_ctz(val) : 32);
2003                         goto logical_done;
2004 #ifdef __powerpc64__
2005                 case 570:       /* cnttzd */
2006                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2007                                 return -1;
2008                         val = regs->gpr[rd];
2009                         op->val = (val ? __builtin_ctzl(val) : 64);
2010                         goto logical_done;
2011 #endif
2012                 case 922:       /* extsh */
2013                         op->val = (signed short) regs->gpr[rd];
2014                         goto logical_done;
2015
2016                 case 954:       /* extsb */
2017                         op->val = (signed char) regs->gpr[rd];
2018                         goto logical_done;
2019 #ifdef __powerpc64__
2020                 case 986:       /* extsw */
2021                         op->val = (signed int) regs->gpr[rd];
2022                         goto logical_done;
2023 #endif
2024
2025 /*
2026  * Shift instructions
2027  */
2028                 case 24:        /* slw */
2029                         sh = regs->gpr[rb] & 0x3f;
2030                         if (sh < 32)
2031                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2032                         else
2033                                 op->val = 0;
2034                         goto logical_done;
2035
2036                 case 536:       /* srw */
2037                         sh = regs->gpr[rb] & 0x3f;
2038                         if (sh < 32)
2039                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2040                         else
2041                                 op->val = 0;
2042                         goto logical_done;
2043
2044                 case 792:       /* sraw */
2045                         op->type = COMPUTE + SETREG + SETXER;
2046                         sh = regs->gpr[rb] & 0x3f;
2047                         ival = (signed int) regs->gpr[rd];
2048                         op->val = ival >> (sh < 32 ? sh : 31);
2049                         op->xerval = regs->xer;
2050                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2051                                 op->xerval |= XER_CA;
2052                         else
2053                                 op->xerval &= ~XER_CA;
2054                         set_ca32(op, op->xerval & XER_CA);
2055                         goto logical_done;
2056
2057                 case 824:       /* srawi */
2058                         op->type = COMPUTE + SETREG + SETXER;
2059                         sh = rb;
2060                         ival = (signed int) regs->gpr[rd];
2061                         op->val = ival >> sh;
2062                         op->xerval = regs->xer;
2063                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2064                                 op->xerval |= XER_CA;
2065                         else
2066                                 op->xerval &= ~XER_CA;
2067                         set_ca32(op, op->xerval & XER_CA);
2068                         goto logical_done;
2069
2070 #ifdef __powerpc64__
2071                 case 27:        /* sld */
2072                         sh = regs->gpr[rb] & 0x7f;
2073                         if (sh < 64)
2074                                 op->val = regs->gpr[rd] << sh;
2075                         else
2076                                 op->val = 0;
2077                         goto logical_done;
2078
2079                 case 539:       /* srd */
2080                         sh = regs->gpr[rb] & 0x7f;
2081                         if (sh < 64)
2082                                 op->val = regs->gpr[rd] >> sh;
2083                         else
2084                                 op->val = 0;
2085                         goto logical_done;
2086
2087                 case 794:       /* srad */
2088                         op->type = COMPUTE + SETREG + SETXER;
2089                         sh = regs->gpr[rb] & 0x7f;
2090                         ival = (signed long int) regs->gpr[rd];
2091                         op->val = ival >> (sh < 64 ? sh : 63);
2092                         op->xerval = regs->xer;
2093                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2094                                 op->xerval |= XER_CA;
2095                         else
2096                                 op->xerval &= ~XER_CA;
2097                         set_ca32(op, op->xerval & XER_CA);
2098                         goto logical_done;
2099
2100                 case 826:       /* sradi with sh_5 = 0 */
2101                 case 827:       /* sradi with sh_5 = 1 */
2102                         op->type = COMPUTE + SETREG + SETXER;
2103                         sh = rb | ((word & 2) << 4);
2104                         ival = (signed long int) regs->gpr[rd];
2105                         op->val = ival >> sh;
2106                         op->xerval = regs->xer;
2107                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2108                                 op->xerval |= XER_CA;
2109                         else
2110                                 op->xerval &= ~XER_CA;
2111                         set_ca32(op, op->xerval & XER_CA);
2112                         goto logical_done;
2113
2114                 case 890:       /* extswsli with sh_5 = 0 */
2115                 case 891:       /* extswsli with sh_5 = 1 */
2116                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2117                                 return -1;
2118                         op->type = COMPUTE + SETREG;
2119                         sh = rb | ((word & 2) << 4);
2120                         val = (signed int) regs->gpr[rd];
2121                         if (sh)
2122                                 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2123                         else
2124                                 op->val = val;
2125                         goto logical_done;
2126
2127 #endif /* __powerpc64__ */
2128
2129 /*
2130  * Cache instructions
2131  */
2132                 case 54:        /* dcbst */
2133                         op->type = MKOP(CACHEOP, DCBST, 0);
2134                         op->ea = xform_ea(word, regs);
2135                         return 0;
2136
2137                 case 86:        /* dcbf */
2138                         op->type = MKOP(CACHEOP, DCBF, 0);
2139                         op->ea = xform_ea(word, regs);
2140                         return 0;
2141
2142                 case 246:       /* dcbtst */
2143                         op->type = MKOP(CACHEOP, DCBTST, 0);
2144                         op->ea = xform_ea(word, regs);
2145                         op->reg = rd;
2146                         return 0;
2147
2148                 case 278:       /* dcbt */
2149                         op->type = MKOP(CACHEOP, DCBTST, 0);
2150                         op->ea = xform_ea(word, regs);
2151                         op->reg = rd;
2152                         return 0;
2153
2154                 case 982:       /* icbi */
2155                         op->type = MKOP(CACHEOP, ICBI, 0);
2156                         op->ea = xform_ea(word, regs);
2157                         return 0;
2158
2159                 case 1014:      /* dcbz */
2160                         op->type = MKOP(CACHEOP, DCBZ, 0);
2161                         op->ea = xform_ea(word, regs);
2162                         return 0;
2163                 }
2164                 break;
2165         }
2166
2167 /*
2168  * Loads and stores.
2169  */
2170         op->type = UNKNOWN;
2171         op->update_reg = ra;
2172         op->reg = rd;
2173         op->val = regs->gpr[rd];
2174         u = (word >> 20) & UPDATE;
2175         op->vsx_flags = 0;
2176
2177         switch (opcode) {
2178         case 31:
2179                 u = word & UPDATE;
2180                 op->ea = xform_ea(word, regs);
2181                 switch ((word >> 1) & 0x3ff) {
2182                 case 20:        /* lwarx */
2183                         op->type = MKOP(LARX, 0, 4);
2184                         break;
2185
2186                 case 150:       /* stwcx. */
2187                         op->type = MKOP(STCX, 0, 4);
2188                         break;
2189
2190 #ifdef __powerpc64__
2191                 case 84:        /* ldarx */
2192                         op->type = MKOP(LARX, 0, 8);
2193                         break;
2194
2195                 case 214:       /* stdcx. */
2196                         op->type = MKOP(STCX, 0, 8);
2197                         break;
2198
2199                 case 52:        /* lbarx */
2200                         op->type = MKOP(LARX, 0, 1);
2201                         break;
2202
2203                 case 694:       /* stbcx. */
2204                         op->type = MKOP(STCX, 0, 1);
2205                         break;
2206
2207                 case 116:       /* lharx */
2208                         op->type = MKOP(LARX, 0, 2);
2209                         break;
2210
2211                 case 726:       /* sthcx. */
2212                         op->type = MKOP(STCX, 0, 2);
2213                         break;
2214
2215                 case 276:       /* lqarx */
2216                         if (!((rd & 1) || rd == ra || rd == rb))
2217                                 op->type = MKOP(LARX, 0, 16);
2218                         break;
2219
2220                 case 182:       /* stqcx. */
2221                         if (!(rd & 1))
2222                                 op->type = MKOP(STCX, 0, 16);
2223                         break;
2224 #endif
2225
2226                 case 23:        /* lwzx */
2227                 case 55:        /* lwzux */
2228                         op->type = MKOP(LOAD, u, 4);
2229                         break;
2230
2231                 case 87:        /* lbzx */
2232                 case 119:       /* lbzux */
2233                         op->type = MKOP(LOAD, u, 1);
2234                         break;
2235
2236 #ifdef CONFIG_ALTIVEC
2237                 /*
2238                  * Note: for the load/store vector element instructions,
2239                  * bits of the EA say which field of the VMX register to use.
2240                  */
2241                 case 7:         /* lvebx */
2242                         op->type = MKOP(LOAD_VMX, 0, 1);
2243                         op->element_size = 1;
2244                         break;
2245
2246                 case 39:        /* lvehx */
2247                         op->type = MKOP(LOAD_VMX, 0, 2);
2248                         op->element_size = 2;
2249                         break;
2250
2251                 case 71:        /* lvewx */
2252                         op->type = MKOP(LOAD_VMX, 0, 4);
2253                         op->element_size = 4;
2254                         break;
2255
2256                 case 103:       /* lvx */
2257                 case 359:       /* lvxl */
2258                         op->type = MKOP(LOAD_VMX, 0, 16);
2259                         op->element_size = 16;
2260                         break;
2261
2262                 case 135:       /* stvebx */
2263                         op->type = MKOP(STORE_VMX, 0, 1);
2264                         op->element_size = 1;
2265                         break;
2266
2267                 case 167:       /* stvehx */
2268                         op->type = MKOP(STORE_VMX, 0, 2);
2269                         op->element_size = 2;
2270                         break;
2271
2272                 case 199:       /* stvewx */
2273                         op->type = MKOP(STORE_VMX, 0, 4);
2274                         op->element_size = 4;
2275                         break;
2276
2277                 case 231:       /* stvx */
2278                 case 487:       /* stvxl */
2279                         op->type = MKOP(STORE_VMX, 0, 16);
2280                         break;
2281 #endif /* CONFIG_ALTIVEC */
2282
2283 #ifdef __powerpc64__
2284                 case 21:        /* ldx */
2285                 case 53:        /* ldux */
2286                         op->type = MKOP(LOAD, u, 8);
2287                         break;
2288
2289                 case 149:       /* stdx */
2290                 case 181:       /* stdux */
2291                         op->type = MKOP(STORE, u, 8);
2292                         break;
2293 #endif
2294
2295                 case 151:       /* stwx */
2296                 case 183:       /* stwux */
2297                         op->type = MKOP(STORE, u, 4);
2298                         break;
2299
2300                 case 215:       /* stbx */
2301                 case 247:       /* stbux */
2302                         op->type = MKOP(STORE, u, 1);
2303                         break;
2304
2305                 case 279:       /* lhzx */
2306                 case 311:       /* lhzux */
2307                         op->type = MKOP(LOAD, u, 2);
2308                         break;
2309
2310 #ifdef __powerpc64__
2311                 case 341:       /* lwax */
2312                 case 373:       /* lwaux */
2313                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2314                         break;
2315 #endif
2316
2317                 case 343:       /* lhax */
2318                 case 375:       /* lhaux */
2319                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2320                         break;
2321
2322                 case 407:       /* sthx */
2323                 case 439:       /* sthux */
2324                         op->type = MKOP(STORE, u, 2);
2325                         break;
2326
2327 #ifdef __powerpc64__
2328                 case 532:       /* ldbrx */
2329                         op->type = MKOP(LOAD, BYTEREV, 8);
2330                         break;
2331
2332 #endif
2333                 case 533:       /* lswx */
2334                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2335                         break;
2336
2337                 case 534:       /* lwbrx */
2338                         op->type = MKOP(LOAD, BYTEREV, 4);
2339                         break;
2340
2341                 case 597:       /* lswi */
2342                         if (rb == 0)
2343                                 rb = 32;        /* # bytes to load */
2344                         op->type = MKOP(LOAD_MULTI, 0, rb);
2345                         op->ea = ra ? regs->gpr[ra] : 0;
2346                         break;
2347
2348 #ifdef CONFIG_PPC_FPU
2349                 case 535:       /* lfsx */
2350                 case 567:       /* lfsux */
2351                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2352                         break;
2353
2354                 case 599:       /* lfdx */
2355                 case 631:       /* lfdux */
2356                         op->type = MKOP(LOAD_FP, u, 8);
2357                         break;
2358
2359                 case 663:       /* stfsx */
2360                 case 695:       /* stfsux */
2361                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2362                         break;
2363
2364                 case 727:       /* stfdx */
2365                 case 759:       /* stfdux */
2366                         op->type = MKOP(STORE_FP, u, 8);
2367                         break;
2368
2369 #ifdef __powerpc64__
2370                 case 791:       /* lfdpx */
2371                         op->type = MKOP(LOAD_FP, 0, 16);
2372                         break;
2373
2374                 case 855:       /* lfiwax */
2375                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2376                         break;
2377
2378                 case 887:       /* lfiwzx */
2379                         op->type = MKOP(LOAD_FP, 0, 4);
2380                         break;
2381
2382                 case 919:       /* stfdpx */
2383                         op->type = MKOP(STORE_FP, 0, 16);
2384                         break;
2385
2386                 case 983:       /* stfiwx */
2387                         op->type = MKOP(STORE_FP, 0, 4);
2388                         break;
2389 #endif /* __powerpc64 */
2390 #endif /* CONFIG_PPC_FPU */
2391
2392 #ifdef __powerpc64__
2393                 case 660:       /* stdbrx */
2394                         op->type = MKOP(STORE, BYTEREV, 8);
2395                         op->val = byterev_8(regs->gpr[rd]);
2396                         break;
2397
2398 #endif
2399                 case 661:       /* stswx */
2400                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2401                         break;
2402
2403                 case 662:       /* stwbrx */
2404                         op->type = MKOP(STORE, BYTEREV, 4);
2405                         op->val = byterev_4(regs->gpr[rd]);
2406                         break;
2407
2408                 case 725:       /* stswi */
2409                         if (rb == 0)
2410                                 rb = 32;        /* # bytes to store */
2411                         op->type = MKOP(STORE_MULTI, 0, rb);
2412                         op->ea = ra ? regs->gpr[ra] : 0;
2413                         break;
2414
2415                 case 790:       /* lhbrx */
2416                         op->type = MKOP(LOAD, BYTEREV, 2);
2417                         break;
2418
2419                 case 918:       /* sthbrx */
2420                         op->type = MKOP(STORE, BYTEREV, 2);
2421                         op->val = byterev_2(regs->gpr[rd]);
2422                         break;
2423
2424 #ifdef CONFIG_VSX
2425                 case 12:        /* lxsiwzx */
2426                         op->reg = rd | ((word & 1) << 5);
2427                         op->type = MKOP(LOAD_VSX, 0, 4);
2428                         op->element_size = 8;
2429                         break;
2430
2431                 case 76:        /* lxsiwax */
2432                         op->reg = rd | ((word & 1) << 5);
2433                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2434                         op->element_size = 8;
2435                         break;
2436
2437                 case 140:       /* stxsiwx */
2438                         op->reg = rd | ((word & 1) << 5);
2439                         op->type = MKOP(STORE_VSX, 0, 4);
2440                         op->element_size = 8;
2441                         break;
2442
2443                 case 268:       /* lxvx */
2444                         op->reg = rd | ((word & 1) << 5);
2445                         op->type = MKOP(LOAD_VSX, 0, 16);
2446                         op->element_size = 16;
2447                         op->vsx_flags = VSX_CHECK_VEC;
2448                         break;
2449
2450                 case 269:       /* lxvl */
2451                 case 301: {     /* lxvll */
2452                         int nb;
2453                         op->reg = rd | ((word & 1) << 5);
2454                         op->ea = ra ? regs->gpr[ra] : 0;
2455                         nb = regs->gpr[rb] & 0xff;
2456                         if (nb > 16)
2457                                 nb = 16;
2458                         op->type = MKOP(LOAD_VSX, 0, nb);
2459                         op->element_size = 16;
2460                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2461                                 VSX_CHECK_VEC;
2462                         break;
2463                 }
2464                 case 332:       /* lxvdsx */
2465                         op->reg = rd | ((word & 1) << 5);
2466                         op->type = MKOP(LOAD_VSX, 0, 8);
2467                         op->element_size = 8;
2468                         op->vsx_flags = VSX_SPLAT;
2469                         break;
2470
2471                 case 333:       /* lxvpx */
2472                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2473                                 return -1;
2474                         op->reg = VSX_REGISTER_XTP(rd);
2475                         op->type = MKOP(LOAD_VSX, 0, 32);
2476                         op->element_size = 32;
2477                         break;
2478
2479                 case 364:       /* lxvwsx */
2480                         op->reg = rd | ((word & 1) << 5);
2481                         op->type = MKOP(LOAD_VSX, 0, 4);
2482                         op->element_size = 4;
2483                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2484                         break;
2485
2486                 case 396:       /* stxvx */
2487                         op->reg = rd | ((word & 1) << 5);
2488                         op->type = MKOP(STORE_VSX, 0, 16);
2489                         op->element_size = 16;
2490                         op->vsx_flags = VSX_CHECK_VEC;
2491                         break;
2492
2493                 case 397:       /* stxvl */
2494                 case 429: {     /* stxvll */
2495                         int nb;
2496                         op->reg = rd | ((word & 1) << 5);
2497                         op->ea = ra ? regs->gpr[ra] : 0;
2498                         nb = regs->gpr[rb] & 0xff;
2499                         if (nb > 16)
2500                                 nb = 16;
2501                         op->type = MKOP(STORE_VSX, 0, nb);
2502                         op->element_size = 16;
2503                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2504                                 VSX_CHECK_VEC;
2505                         break;
2506                 }
2507                 case 461:       /* stxvpx */
2508                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2509                                 return -1;
2510                         op->reg = VSX_REGISTER_XTP(rd);
2511                         op->type = MKOP(STORE_VSX, 0, 32);
2512                         op->element_size = 32;
2513                         break;
2514                 case 524:       /* lxsspx */
2515                         op->reg = rd | ((word & 1) << 5);
2516                         op->type = MKOP(LOAD_VSX, 0, 4);
2517                         op->element_size = 8;
2518                         op->vsx_flags = VSX_FPCONV;
2519                         break;
2520
2521                 case 588:       /* lxsdx */
2522                         op->reg = rd | ((word & 1) << 5);
2523                         op->type = MKOP(LOAD_VSX, 0, 8);
2524                         op->element_size = 8;
2525                         break;
2526
2527                 case 652:       /* stxsspx */
2528                         op->reg = rd | ((word & 1) << 5);
2529                         op->type = MKOP(STORE_VSX, 0, 4);
2530                         op->element_size = 8;
2531                         op->vsx_flags = VSX_FPCONV;
2532                         break;
2533
2534                 case 716:       /* stxsdx */
2535                         op->reg = rd | ((word & 1) << 5);
2536                         op->type = MKOP(STORE_VSX, 0, 8);
2537                         op->element_size = 8;
2538                         break;
2539
2540                 case 780:       /* lxvw4x */
2541                         op->reg = rd | ((word & 1) << 5);
2542                         op->type = MKOP(LOAD_VSX, 0, 16);
2543                         op->element_size = 4;
2544                         break;
2545
2546                 case 781:       /* lxsibzx */
2547                         op->reg = rd | ((word & 1) << 5);
2548                         op->type = MKOP(LOAD_VSX, 0, 1);
2549                         op->element_size = 8;
2550                         op->vsx_flags = VSX_CHECK_VEC;
2551                         break;
2552
2553                 case 812:       /* lxvh8x */
2554                         op->reg = rd | ((word & 1) << 5);
2555                         op->type = MKOP(LOAD_VSX, 0, 16);
2556                         op->element_size = 2;
2557                         op->vsx_flags = VSX_CHECK_VEC;
2558                         break;
2559
2560                 case 813:       /* lxsihzx */
2561                         op->reg = rd | ((word & 1) << 5);
2562                         op->type = MKOP(LOAD_VSX, 0, 2);
2563                         op->element_size = 8;
2564                         op->vsx_flags = VSX_CHECK_VEC;
2565                         break;
2566
2567                 case 844:       /* lxvd2x */
2568                         op->reg = rd | ((word & 1) << 5);
2569                         op->type = MKOP(LOAD_VSX, 0, 16);
2570                         op->element_size = 8;
2571                         break;
2572
2573                 case 876:       /* lxvb16x */
2574                         op->reg = rd | ((word & 1) << 5);
2575                         op->type = MKOP(LOAD_VSX, 0, 16);
2576                         op->element_size = 1;
2577                         op->vsx_flags = VSX_CHECK_VEC;
2578                         break;
2579
2580                 case 908:       /* stxvw4x */
2581                         op->reg = rd | ((word & 1) << 5);
2582                         op->type = MKOP(STORE_VSX, 0, 16);
2583                         op->element_size = 4;
2584                         break;
2585
2586                 case 909:       /* stxsibx */
2587                         op->reg = rd | ((word & 1) << 5);
2588                         op->type = MKOP(STORE_VSX, 0, 1);
2589                         op->element_size = 8;
2590                         op->vsx_flags = VSX_CHECK_VEC;
2591                         break;
2592
2593                 case 940:       /* stxvh8x */
2594                         op->reg = rd | ((word & 1) << 5);
2595                         op->type = MKOP(STORE_VSX, 0, 16);
2596                         op->element_size = 2;
2597                         op->vsx_flags = VSX_CHECK_VEC;
2598                         break;
2599
2600                 case 941:       /* stxsihx */
2601                         op->reg = rd | ((word & 1) << 5);
2602                         op->type = MKOP(STORE_VSX, 0, 2);
2603                         op->element_size = 8;
2604                         op->vsx_flags = VSX_CHECK_VEC;
2605                         break;
2606
2607                 case 972:       /* stxvd2x */
2608                         op->reg = rd | ((word & 1) << 5);
2609                         op->type = MKOP(STORE_VSX, 0, 16);
2610                         op->element_size = 8;
2611                         break;
2612
2613                 case 1004:      /* stxvb16x */
2614                         op->reg = rd | ((word & 1) << 5);
2615                         op->type = MKOP(STORE_VSX, 0, 16);
2616                         op->element_size = 1;
2617                         op->vsx_flags = VSX_CHECK_VEC;
2618                         break;
2619
2620 #endif /* CONFIG_VSX */
2621                 }
2622                 break;
2623
2624         case 32:        /* lwz */
2625         case 33:        /* lwzu */
2626                 op->type = MKOP(LOAD, u, 4);
2627                 op->ea = dform_ea(word, regs);
2628                 break;
2629
2630         case 34:        /* lbz */
2631         case 35:        /* lbzu */
2632                 op->type = MKOP(LOAD, u, 1);
2633                 op->ea = dform_ea(word, regs);
2634                 break;
2635
2636         case 36:        /* stw */
2637         case 37:        /* stwu */
2638                 op->type = MKOP(STORE, u, 4);
2639                 op->ea = dform_ea(word, regs);
2640                 break;
2641
2642         case 38:        /* stb */
2643         case 39:        /* stbu */
2644                 op->type = MKOP(STORE, u, 1);
2645                 op->ea = dform_ea(word, regs);
2646                 break;
2647
2648         case 40:        /* lhz */
2649         case 41:        /* lhzu */
2650                 op->type = MKOP(LOAD, u, 2);
2651                 op->ea = dform_ea(word, regs);
2652                 break;
2653
2654         case 42:        /* lha */
2655         case 43:        /* lhau */
2656                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2657                 op->ea = dform_ea(word, regs);
2658                 break;
2659
2660         case 44:        /* sth */
2661         case 45:        /* sthu */
2662                 op->type = MKOP(STORE, u, 2);
2663                 op->ea = dform_ea(word, regs);
2664                 break;
2665
2666         case 46:        /* lmw */
2667                 if (ra >= rd)
2668                         break;          /* invalid form, ra in range to load */
2669                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2670                 op->ea = dform_ea(word, regs);
2671                 break;
2672
2673         case 47:        /* stmw */
2674                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2675                 op->ea = dform_ea(word, regs);
2676                 break;
2677
2678 #ifdef CONFIG_PPC_FPU
2679         case 48:        /* lfs */
2680         case 49:        /* lfsu */
2681                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2682                 op->ea = dform_ea(word, regs);
2683                 break;
2684
2685         case 50:        /* lfd */
2686         case 51:        /* lfdu */
2687                 op->type = MKOP(LOAD_FP, u, 8);
2688                 op->ea = dform_ea(word, regs);
2689                 break;
2690
2691         case 52:        /* stfs */
2692         case 53:        /* stfsu */
2693                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2694                 op->ea = dform_ea(word, regs);
2695                 break;
2696
2697         case 54:        /* stfd */
2698         case 55:        /* stfdu */
2699                 op->type = MKOP(STORE_FP, u, 8);
2700                 op->ea = dform_ea(word, regs);
2701                 break;
2702 #endif
2703
2704 #ifdef __powerpc64__
2705         case 56:        /* lq */
2706                 if (!((rd & 1) || (rd == ra)))
2707                         op->type = MKOP(LOAD, 0, 16);
2708                 op->ea = dqform_ea(word, regs);
2709                 break;
2710 #endif
2711
2712 #ifdef CONFIG_VSX
2713         case 57:        /* lfdp, lxsd, lxssp */
2714                 op->ea = dsform_ea(word, regs);
2715                 switch (word & 3) {
2716                 case 0:         /* lfdp */
2717                         if (rd & 1)
2718                                 break;          /* reg must be even */
2719                         op->type = MKOP(LOAD_FP, 0, 16);
2720                         break;
2721                 case 2:         /* lxsd */
2722                         op->reg = rd + 32;
2723                         op->type = MKOP(LOAD_VSX, 0, 8);
2724                         op->element_size = 8;
2725                         op->vsx_flags = VSX_CHECK_VEC;
2726                         break;
2727                 case 3:         /* lxssp */
2728                         op->reg = rd + 32;
2729                         op->type = MKOP(LOAD_VSX, 0, 4);
2730                         op->element_size = 8;
2731                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2732                         break;
2733                 }
2734                 break;
2735 #endif /* CONFIG_VSX */
2736
2737 #ifdef __powerpc64__
2738         case 58:        /* ld[u], lwa */
2739                 op->ea = dsform_ea(word, regs);
2740                 switch (word & 3) {
2741                 case 0:         /* ld */
2742                         op->type = MKOP(LOAD, 0, 8);
2743                         break;
2744                 case 1:         /* ldu */
2745                         op->type = MKOP(LOAD, UPDATE, 8);
2746                         break;
2747                 case 2:         /* lwa */
2748                         op->type = MKOP(LOAD, SIGNEXT, 4);
2749                         break;
2750                 }
2751                 break;
2752 #endif
2753
2754 #ifdef CONFIG_VSX
2755         case 6:
2756                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2757                         return -1;
2758                 op->ea = dqform_ea(word, regs);
2759                 op->reg = VSX_REGISTER_XTP(rd);
2760                 op->element_size = 32;
2761                 switch (word & 0xf) {
2762                 case 0:         /* lxvp */
2763                         op->type = MKOP(LOAD_VSX, 0, 32);
2764                         break;
2765                 case 1:         /* stxvp */
2766                         op->type = MKOP(STORE_VSX, 0, 32);
2767                         break;
2768                 }
2769                 break;
2770
2771         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2772                 switch (word & 7) {
2773                 case 0:         /* stfdp with LSB of DS field = 0 */
2774                 case 4:         /* stfdp with LSB of DS field = 1 */
2775                         op->ea = dsform_ea(word, regs);
2776                         op->type = MKOP(STORE_FP, 0, 16);
2777                         break;
2778
2779                 case 1:         /* lxv */
2780                         op->ea = dqform_ea(word, regs);
2781                         if (word & 8)
2782                                 op->reg = rd + 32;
2783                         op->type = MKOP(LOAD_VSX, 0, 16);
2784                         op->element_size = 16;
2785                         op->vsx_flags = VSX_CHECK_VEC;
2786                         break;
2787
2788                 case 2:         /* stxsd with LSB of DS field = 0 */
2789                 case 6:         /* stxsd with LSB of DS field = 1 */
2790                         op->ea = dsform_ea(word, regs);
2791                         op->reg = rd + 32;
2792                         op->type = MKOP(STORE_VSX, 0, 8);
2793                         op->element_size = 8;
2794                         op->vsx_flags = VSX_CHECK_VEC;
2795                         break;
2796
2797                 case 3:         /* stxssp with LSB of DS field = 0 */
2798                 case 7:         /* stxssp with LSB of DS field = 1 */
2799                         op->ea = dsform_ea(word, regs);
2800                         op->reg = rd + 32;
2801                         op->type = MKOP(STORE_VSX, 0, 4);
2802                         op->element_size = 8;
2803                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2804                         break;
2805
2806                 case 5:         /* stxv */
2807                         op->ea = dqform_ea(word, regs);
2808                         if (word & 8)
2809                                 op->reg = rd + 32;
2810                         op->type = MKOP(STORE_VSX, 0, 16);
2811                         op->element_size = 16;
2812                         op->vsx_flags = VSX_CHECK_VEC;
2813                         break;
2814                 }
2815                 break;
2816 #endif /* CONFIG_VSX */
2817
2818 #ifdef __powerpc64__
2819         case 62:        /* std[u] */
2820                 op->ea = dsform_ea(word, regs);
2821                 switch (word & 3) {
2822                 case 0:         /* std */
2823                         op->type = MKOP(STORE, 0, 8);
2824                         break;
2825                 case 1:         /* stdu */
2826                         op->type = MKOP(STORE, UPDATE, 8);
2827                         break;
2828                 case 2:         /* stq */
2829                         if (!(rd & 1))
2830                                 op->type = MKOP(STORE, 0, 16);
2831                         break;
2832                 }
2833                 break;
2834         case 1: /* Prefixed instructions */
2835                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2836                         return -1;
2837
2838                 prefix_r = GET_PREFIX_R(word);
2839                 ra = GET_PREFIX_RA(suffix);
2840                 op->update_reg = ra;
2841                 rd = (suffix >> 21) & 0x1f;
2842                 op->reg = rd;
2843                 op->val = regs->gpr[rd];
2844
2845                 suffixopcode = get_op(suffix);
2846                 prefixtype = (word >> 24) & 0x3;
2847                 switch (prefixtype) {
2848                 case 0: /* Type 00  Eight-Byte Load/Store */
2849                         if (prefix_r && ra)
2850                                 break;
2851                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2852                         switch (suffixopcode) {
2853                         case 41:        /* plwa */
2854                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2855                                 break;
2856 #ifdef CONFIG_VSX
2857                         case 42:        /* plxsd */
2858                                 op->reg = rd + 32;
2859                                 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2860                                 op->element_size = 8;
2861                                 op->vsx_flags = VSX_CHECK_VEC;
2862                                 break;
2863                         case 43:        /* plxssp */
2864                                 op->reg = rd + 32;
2865                                 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2866                                 op->element_size = 8;
2867                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2868                                 break;
2869                         case 46:        /* pstxsd */
2870                                 op->reg = rd + 32;
2871                                 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2872                                 op->element_size = 8;
2873                                 op->vsx_flags = VSX_CHECK_VEC;
2874                                 break;
2875                         case 47:        /* pstxssp */
2876                                 op->reg = rd + 32;
2877                                 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2878                                 op->element_size = 8;
2879                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2880                                 break;
2881                         case 51:        /* plxv1 */
2882                                 op->reg += 32;
2883                                 fallthrough;
2884                         case 50:        /* plxv0 */
2885                                 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2886                                 op->element_size = 16;
2887                                 op->vsx_flags = VSX_CHECK_VEC;
2888                                 break;
2889                         case 55:        /* pstxv1 */
2890                                 op->reg = rd + 32;
2891                                 fallthrough;
2892                         case 54:        /* pstxv0 */
2893                                 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2894                                 op->element_size = 16;
2895                                 op->vsx_flags = VSX_CHECK_VEC;
2896                                 break;
2897 #endif /* CONFIG_VSX */
2898                         case 56:        /* plq */
2899                                 op->type = MKOP(LOAD, PREFIXED, 16);
2900                                 break;
2901                         case 57:        /* pld */
2902                                 op->type = MKOP(LOAD, PREFIXED, 8);
2903                                 break;
2904 #ifdef CONFIG_VSX
2905                         case 58:        /* plxvp */
2906                                 op->reg = VSX_REGISTER_XTP(rd);
2907                                 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
2908                                 op->element_size = 32;
2909                                 break;
2910 #endif /* CONFIG_VSX */
2911                         case 60:        /* pstq */
2912                                 op->type = MKOP(STORE, PREFIXED, 16);
2913                                 break;
2914                         case 61:        /* pstd */
2915                                 op->type = MKOP(STORE, PREFIXED, 8);
2916                                 break;
2917 #ifdef CONFIG_VSX
2918                         case 62:        /* pstxvp */
2919                                 op->reg = VSX_REGISTER_XTP(rd);
2920                                 op->type = MKOP(STORE_VSX, PREFIXED, 32);
2921                                 op->element_size = 32;
2922                                 break;
2923 #endif /* CONFIG_VSX */
2924                         }
2925                         break;
2926                 case 1: /* Type 01 Eight-Byte Register-to-Register */
2927                         break;
2928                 case 2: /* Type 10 Modified Load/Store */
2929                         if (prefix_r && ra)
2930                                 break;
2931                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2932                         switch (suffixopcode) {
2933                         case 32:        /* plwz */
2934                                 op->type = MKOP(LOAD, PREFIXED, 4);
2935                                 break;
2936                         case 34:        /* plbz */
2937                                 op->type = MKOP(LOAD, PREFIXED, 1);
2938                                 break;
2939                         case 36:        /* pstw */
2940                                 op->type = MKOP(STORE, PREFIXED, 4);
2941                                 break;
2942                         case 38:        /* pstb */
2943                                 op->type = MKOP(STORE, PREFIXED, 1);
2944                                 break;
2945                         case 40:        /* plhz */
2946                                 op->type = MKOP(LOAD, PREFIXED, 2);
2947                                 break;
2948                         case 42:        /* plha */
2949                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2950                                 break;
2951                         case 44:        /* psth */
2952                                 op->type = MKOP(STORE, PREFIXED, 2);
2953                                 break;
2954                         case 48:        /* plfs */
2955                                 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2956                                 break;
2957                         case 50:        /* plfd */
2958                                 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2959                                 break;
2960                         case 52:        /* pstfs */
2961                                 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2962                                 break;
2963                         case 54:        /* pstfd */
2964                                 op->type = MKOP(STORE_FP, PREFIXED, 8);
2965                                 break;
2966                         }
2967                         break;
2968                 case 3: /* Type 11 Modified Register-to-Register */
2969                         break;
2970                 }
2971 #endif /* __powerpc64__ */
2972
2973         }
2974
2975 #ifdef CONFIG_VSX
2976         if ((GETTYPE(op->type) == LOAD_VSX ||
2977              GETTYPE(op->type) == STORE_VSX) &&
2978             !cpu_has_feature(CPU_FTR_VSX)) {
2979                 return -1;
2980         }
2981 #endif /* CONFIG_VSX */
2982
2983         return 0;
2984
2985  logical_done:
2986         if (word & 1)
2987                 set_cr0(regs, op);
2988  logical_done_nocc:
2989         op->reg = ra;
2990         op->type |= SETREG;
2991         return 1;
2992
2993  arith_done:
2994         if (word & 1)
2995                 set_cr0(regs, op);
2996  compute_done:
2997         op->reg = rd;
2998         op->type |= SETREG;
2999         return 1;
3000
3001  priv:
3002         op->type = INTERRUPT | 0x700;
3003         op->val = SRR1_PROGPRIV;
3004         return 0;
3005
3006  trap:
3007         op->type = INTERRUPT | 0x700;
3008         op->val = SRR1_PROGTRAP;
3009         return 0;
3010 }
3011 EXPORT_SYMBOL_GPL(analyse_instr);
3012 NOKPROBE_SYMBOL(analyse_instr);
3013
3014 /*
3015  * For PPC32 we always use stwu with r1 to change the stack pointer.
3016  * So this emulated store may corrupt the exception frame, now we
3017  * have to provide the exception frame trampoline, which is pushed
3018  * below the kprobed function stack. So we only update gpr[1] but
3019  * don't emulate the real store operation. We will do real store
3020  * operation safely in exception return code by checking this flag.
3021  */
3022 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
3023 {
3024 #ifdef CONFIG_PPC32
3025         /*
3026          * Check if we will touch kernel stack overflow
3027          */
3028         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
3029                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
3030                 return -EINVAL;
3031         }
3032 #endif /* CONFIG_PPC32 */
3033         /*
3034          * Check if we already set since that means we'll
3035          * lose the previous value.
3036          */
3037         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3038         set_thread_flag(TIF_EMULATE_STACK_STORE);
3039         return 0;
3040 }
3041
3042 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3043 {
3044         switch (size) {
3045         case 2:
3046                 *valp = (signed short) *valp;
3047                 break;
3048         case 4:
3049                 *valp = (signed int) *valp;
3050                 break;
3051         }
3052 }
3053
3054 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3055 {
3056         switch (size) {
3057         case 2:
3058                 *valp = byterev_2(*valp);
3059                 break;
3060         case 4:
3061                 *valp = byterev_4(*valp);
3062                 break;
3063 #ifdef __powerpc64__
3064         case 8:
3065                 *valp = byterev_8(*valp);
3066                 break;
3067 #endif
3068         }
3069 }
3070
3071 /*
3072  * Emulate an instruction that can be executed just by updating
3073  * fields in *regs.
3074  */
3075 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3076 {
3077         unsigned long next_pc;
3078
3079         next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3080         switch (GETTYPE(op->type)) {
3081         case COMPUTE:
3082                 if (op->type & SETREG)
3083                         regs->gpr[op->reg] = op->val;
3084                 if (op->type & SETCC)
3085                         regs->ccr = op->ccval;
3086                 if (op->type & SETXER)
3087                         regs->xer = op->xerval;
3088                 break;
3089
3090         case BRANCH:
3091                 if (op->type & SETLK)
3092                         regs->link = next_pc;
3093                 if (op->type & BRTAKEN)
3094                         next_pc = op->val;
3095                 if (op->type & DECCTR)
3096                         --regs->ctr;
3097                 break;
3098
3099         case BARRIER:
3100                 switch (op->type & BARRIER_MASK) {
3101                 case BARRIER_SYNC:
3102                         mb();
3103                         break;
3104                 case BARRIER_ISYNC:
3105                         isync();
3106                         break;
3107                 case BARRIER_EIEIO:
3108                         eieio();
3109                         break;
3110                 case BARRIER_LWSYNC:
3111                         asm volatile("lwsync" : : : "memory");
3112                         break;
3113                 case BARRIER_PTESYNC:
3114                         asm volatile("ptesync" : : : "memory");
3115                         break;
3116                 }
3117                 break;
3118
3119         case MFSPR:
3120                 switch (op->spr) {
3121                 case SPRN_XER:
3122                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3123                         break;
3124                 case SPRN_LR:
3125                         regs->gpr[op->reg] = regs->link;
3126                         break;
3127                 case SPRN_CTR:
3128                         regs->gpr[op->reg] = regs->ctr;
3129                         break;
3130                 default:
3131                         WARN_ON_ONCE(1);
3132                 }
3133                 break;
3134
3135         case MTSPR:
3136                 switch (op->spr) {
3137                 case SPRN_XER:
3138                         regs->xer = op->val & 0xffffffffUL;
3139                         break;
3140                 case SPRN_LR:
3141                         regs->link = op->val;
3142                         break;
3143                 case SPRN_CTR:
3144                         regs->ctr = op->val;
3145                         break;
3146                 default:
3147                         WARN_ON_ONCE(1);
3148                 }
3149                 break;
3150
3151         default:
3152                 WARN_ON_ONCE(1);
3153         }
3154         regs->nip = next_pc;
3155 }
3156 NOKPROBE_SYMBOL(emulate_update_regs);
3157
3158 /*
3159  * Emulate a previously-analysed load or store instruction.
3160  * Return values are:
3161  * 0 = instruction emulated successfully
3162  * -EFAULT = address out of range or access faulted (regs->dar
3163  *           contains the faulting address)
3164  * -EACCES = misaligned access, instruction requires alignment
3165  * -EINVAL = unknown operation in *op
3166  */
3167 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3168 {
3169         int err, size, type;
3170         int i, rd, nb;
3171         unsigned int cr;
3172         unsigned long val;
3173         unsigned long ea;
3174         bool cross_endian;
3175
3176         err = 0;
3177         size = GETSIZE(op->type);
3178         type = GETTYPE(op->type);
3179         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3180         ea = truncate_if_32bit(regs->msr, op->ea);
3181
3182         switch (type) {
3183         case LARX:
3184                 if (ea & (size - 1))
3185                         return -EACCES;         /* can't handle misaligned */
3186                 if (!address_ok(regs, ea, size))
3187                         return -EFAULT;
3188                 err = 0;
3189                 val = 0;
3190                 switch (size) {
3191 #ifdef __powerpc64__
3192                 case 1:
3193                         __get_user_asmx(val, ea, err, "lbarx");
3194                         break;
3195                 case 2:
3196                         __get_user_asmx(val, ea, err, "lharx");
3197                         break;
3198 #endif
3199                 case 4:
3200                         __get_user_asmx(val, ea, err, "lwarx");
3201                         break;
3202 #ifdef __powerpc64__
3203                 case 8:
3204                         __get_user_asmx(val, ea, err, "ldarx");
3205                         break;
3206                 case 16:
3207                         err = do_lqarx(ea, &regs->gpr[op->reg]);
3208                         break;
3209 #endif
3210                 default:
3211                         return -EINVAL;
3212                 }
3213                 if (err) {
3214                         regs->dar = ea;
3215                         break;
3216                 }
3217                 if (size < 16)
3218                         regs->gpr[op->reg] = val;
3219                 break;
3220
3221         case STCX:
3222                 if (ea & (size - 1))
3223                         return -EACCES;         /* can't handle misaligned */
3224                 if (!address_ok(regs, ea, size))
3225                         return -EFAULT;
3226                 err = 0;
3227                 switch (size) {
3228 #ifdef __powerpc64__
3229                 case 1:
3230                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3231                         break;
3232                 case 2:
3233                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3234                         break;
3235 #endif
3236                 case 4:
3237                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3238                         break;
3239 #ifdef __powerpc64__
3240                 case 8:
3241                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3242                         break;
3243                 case 16:
3244                         err = do_stqcx(ea, regs->gpr[op->reg],
3245                                        regs->gpr[op->reg + 1], &cr);
3246                         break;
3247 #endif
3248                 default:
3249                         return -EINVAL;
3250                 }
3251                 if (!err)
3252                         regs->ccr = (regs->ccr & 0x0fffffff) |
3253                                 (cr & 0xe0000000) |
3254                                 ((regs->xer >> 3) & 0x10000000);
3255                 else
3256                         regs->dar = ea;
3257                 break;
3258
3259         case LOAD:
3260 #ifdef __powerpc64__
3261                 if (size == 16) {
3262                         err = emulate_lq(regs, ea, op->reg, cross_endian);
3263                         break;
3264                 }
3265 #endif
3266                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
3267                 if (!err) {
3268                         if (op->type & SIGNEXT)
3269                                 do_signext(&regs->gpr[op->reg], size);
3270                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3271                                 do_byterev(&regs->gpr[op->reg], size);
3272                 }
3273                 break;
3274
3275 #ifdef CONFIG_PPC_FPU
3276         case LOAD_FP:
3277                 /*
3278                  * If the instruction is in userspace, we can emulate it even
3279                  * if the VMX state is not live, because we have the state
3280                  * stored in the thread_struct.  If the instruction is in
3281                  * the kernel, we must not touch the state in the thread_struct.
3282                  */
3283                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3284                         return 0;
3285                 err = do_fp_load(op, ea, regs, cross_endian);
3286                 break;
3287 #endif
3288 #ifdef CONFIG_ALTIVEC
3289         case LOAD_VMX:
3290                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3291                         return 0;
3292                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3293                 break;
3294 #endif
3295 #ifdef CONFIG_VSX
3296         case LOAD_VSX: {
3297                 unsigned long msrbit = MSR_VSX;
3298
3299                 /*
3300                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3301                  * when the target of the instruction is a vector register.
3302                  */
3303                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3304                         msrbit = MSR_VEC;
3305                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3306                         return 0;
3307                 err = do_vsx_load(op, ea, regs, cross_endian);
3308                 break;
3309         }
3310 #endif
3311         case LOAD_MULTI:
3312                 if (!address_ok(regs, ea, size))
3313                         return -EFAULT;
3314                 rd = op->reg;
3315                 for (i = 0; i < size; i += 4) {
3316                         unsigned int v32 = 0;
3317
3318                         nb = size - i;
3319                         if (nb > 4)
3320                                 nb = 4;
3321                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3322                         if (err)
3323                                 break;
3324                         if (unlikely(cross_endian))
3325                                 v32 = byterev_4(v32);
3326                         regs->gpr[rd] = v32;
3327                         ea += 4;
3328                         /* reg number wraps from 31 to 0 for lsw[ix] */
3329                         rd = (rd + 1) & 0x1f;
3330                 }
3331                 break;
3332
3333         case STORE:
3334 #ifdef __powerpc64__
3335                 if (size == 16) {
3336                         err = emulate_stq(regs, ea, op->reg, cross_endian);
3337                         break;
3338                 }
3339 #endif
3340                 if ((op->type & UPDATE) && size == sizeof(long) &&
3341                     op->reg == 1 && op->update_reg == 1 &&
3342                     !(regs->msr & MSR_PR) &&
3343                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3344                         err = handle_stack_update(ea, regs);
3345                         break;
3346                 }
3347                 if (unlikely(cross_endian))
3348                         do_byterev(&op->val, size);
3349                 err = write_mem(op->val, ea, size, regs);
3350                 break;
3351
3352 #ifdef CONFIG_PPC_FPU
3353         case STORE_FP:
3354                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3355                         return 0;
3356                 err = do_fp_store(op, ea, regs, cross_endian);
3357                 break;
3358 #endif
3359 #ifdef CONFIG_ALTIVEC
3360         case STORE_VMX:
3361                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3362                         return 0;
3363                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3364                 break;
3365 #endif
3366 #ifdef CONFIG_VSX
3367         case STORE_VSX: {
3368                 unsigned long msrbit = MSR_VSX;
3369
3370                 /*
3371                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3372                  * when the target of the instruction is a vector register.
3373                  */
3374                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3375                         msrbit = MSR_VEC;
3376                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3377                         return 0;
3378                 err = do_vsx_store(op, ea, regs, cross_endian);
3379                 break;
3380         }
3381 #endif
3382         case STORE_MULTI:
3383                 if (!address_ok(regs, ea, size))
3384                         return -EFAULT;
3385                 rd = op->reg;
3386                 for (i = 0; i < size; i += 4) {
3387                         unsigned int v32 = regs->gpr[rd];
3388
3389                         nb = size - i;
3390                         if (nb > 4)
3391                                 nb = 4;
3392                         if (unlikely(cross_endian))
3393                                 v32 = byterev_4(v32);
3394                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3395                         if (err)
3396                                 break;
3397                         ea += 4;
3398                         /* reg number wraps from 31 to 0 for stsw[ix] */
3399                         rd = (rd + 1) & 0x1f;
3400                 }
3401                 break;
3402
3403         default:
3404                 return -EINVAL;
3405         }
3406
3407         if (err)
3408                 return err;
3409
3410         if (op->type & UPDATE)
3411                 regs->gpr[op->update_reg] = op->ea;
3412
3413         return 0;
3414 }
3415 NOKPROBE_SYMBOL(emulate_loadstore);
3416
3417 /*
3418  * Emulate instructions that cause a transfer of control,
3419  * loads and stores, and a few other instructions.
3420  * Returns 1 if the step was emulated, 0 if not,
3421  * or -1 if the instruction is one that should not be stepped,
3422  * such as an rfid, or a mtmsrd that would clear MSR_RI.
3423  */
3424 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3425 {
3426         struct instruction_op op;
3427         int r, err, type;
3428         unsigned long val;
3429         unsigned long ea;
3430
3431         r = analyse_instr(&op, regs, instr);
3432         if (r < 0)
3433                 return r;
3434         if (r > 0) {
3435                 emulate_update_regs(regs, &op);
3436                 return 1;
3437         }
3438
3439         err = 0;
3440         type = GETTYPE(op.type);
3441
3442         if (OP_IS_LOAD_STORE(type)) {
3443                 err = emulate_loadstore(regs, &op);
3444                 if (err)
3445                         return 0;
3446                 goto instr_done;
3447         }
3448
3449         switch (type) {
3450         case CACHEOP:
3451                 ea = truncate_if_32bit(regs->msr, op.ea);
3452                 if (!address_ok(regs, ea, 8))
3453                         return 0;
3454                 switch (op.type & CACHEOP_MASK) {
3455                 case DCBST:
3456                         __cacheop_user_asmx(ea, err, "dcbst");
3457                         break;
3458                 case DCBF:
3459                         __cacheop_user_asmx(ea, err, "dcbf");
3460                         break;
3461                 case DCBTST:
3462                         if (op.reg == 0)
3463                                 prefetchw((void *) ea);
3464                         break;
3465                 case DCBT:
3466                         if (op.reg == 0)
3467                                 prefetch((void *) ea);
3468                         break;
3469                 case ICBI:
3470                         __cacheop_user_asmx(ea, err, "icbi");
3471                         break;
3472                 case DCBZ:
3473                         err = emulate_dcbz(ea, regs);
3474                         break;
3475                 }
3476                 if (err) {
3477                         regs->dar = ea;
3478                         return 0;
3479                 }
3480                 goto instr_done;
3481
3482         case MFMSR:
3483                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3484                 goto instr_done;
3485
3486         case MTMSR:
3487                 val = regs->gpr[op.reg];
3488                 if ((val & MSR_RI) == 0)
3489                         /* can't step mtmsr[d] that would clear MSR_RI */
3490                         return -1;
3491                 /* here op.val is the mask of bits to change */
3492                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3493                 goto instr_done;
3494
3495 #ifdef CONFIG_PPC64
3496         case SYSCALL:   /* sc */
3497                 /*
3498                  * N.B. this uses knowledge about how the syscall
3499                  * entry code works.  If that is changed, this will
3500                  * need to be changed also.
3501                  */
3502                 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3503                                 cpu_has_feature(CPU_FTR_REAL_LE) &&
3504                                 regs->gpr[0] == 0x1ebe) {
3505                         regs->msr ^= MSR_LE;
3506                         goto instr_done;
3507                 }
3508                 regs->gpr[9] = regs->gpr[13];
3509                 regs->gpr[10] = MSR_KERNEL;
3510                 regs->gpr[11] = regs->nip + 4;
3511                 regs->gpr[12] = regs->msr & MSR_MASK;
3512                 regs->gpr[13] = (unsigned long) get_paca();
3513                 regs->nip = (unsigned long) &system_call_common;
3514                 regs->msr = MSR_KERNEL;
3515                 return 1;
3516
3517 #ifdef CONFIG_PPC_BOOK3S_64
3518         case SYSCALL_VECTORED_0:        /* scv 0 */
3519                 regs->gpr[9] = regs->gpr[13];
3520                 regs->gpr[10] = MSR_KERNEL;
3521                 regs->gpr[11] = regs->nip + 4;
3522                 regs->gpr[12] = regs->msr & MSR_MASK;
3523                 regs->gpr[13] = (unsigned long) get_paca();
3524                 regs->nip = (unsigned long) &system_call_vectored_emulate;
3525                 regs->msr = MSR_KERNEL;
3526                 return 1;
3527 #endif
3528
3529         case RFI:
3530                 return -1;
3531 #endif
3532         }
3533         return 0;
3534
3535  instr_done:
3536         regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3537         return 1;
3538 }
3539 NOKPROBE_SYMBOL(emulate_step);