2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/pkeys.h>
24 #include <linux/stddef.h>
25 #include <linux/unistd.h>
26 #include <linux/ptrace.h>
27 #include <linux/user.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/extable.h>
31 #include <linux/module.h> /* print_modules */
32 #include <linux/prctl.h>
33 #include <linux/delay.h>
34 #include <linux/kprobes.h>
35 #include <linux/kexec.h>
36 #include <linux/backlight.h>
37 #include <linux/bug.h>
38 #include <linux/kdebug.h>
39 #include <linux/ratelimit.h>
40 #include <linux/context_tracking.h>
41 #include <linux/smp.h>
43 #include <asm/emulated_ops.h>
44 #include <asm/pgtable.h>
45 #include <linux/uaccess.h>
46 #include <asm/debugfs.h>
48 #include <asm/machdep.h>
52 #ifdef CONFIG_PMAC_BACKLIGHT
53 #include <asm/backlight.h>
56 #include <asm/firmware.h>
57 #include <asm/processor.h>
60 #include <asm/kexec.h>
61 #include <asm/ppc-opcode.h>
63 #include <asm/fadump.h>
64 #include <asm/switch_to.h>
66 #include <asm/debug.h>
67 #include <asm/asm-prototypes.h>
69 #include <sysdev/fsl_pci.h>
70 #include <asm/kprobes.h>
72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
73 int (*__debugger)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
81 EXPORT_SYMBOL(__debugger);
82 EXPORT_SYMBOL(__debugger_ipi);
83 EXPORT_SYMBOL(__debugger_bpt);
84 EXPORT_SYMBOL(__debugger_sstep);
85 EXPORT_SYMBOL(__debugger_iabr_match);
86 EXPORT_SYMBOL(__debugger_break_match);
87 EXPORT_SYMBOL(__debugger_fault_handler);
90 /* Transactional Memory trap debug */
92 #define TM_DEBUG(x...) printk(KERN_INFO x)
94 #define TM_DEBUG(x...) do { } while(0)
98 * Trap & Exception support
101 #ifdef CONFIG_PMAC_BACKLIGHT
102 static void pmac_backlight_unblank(void)
104 mutex_lock(&pmac_backlight_mutex);
105 if (pmac_backlight) {
106 struct backlight_properties *props;
108 props = &pmac_backlight->props;
109 props->brightness = props->max_brightness;
110 props->power = FB_BLANK_UNBLANK;
111 backlight_update_status(pmac_backlight);
113 mutex_unlock(&pmac_backlight_mutex);
116 static inline void pmac_backlight_unblank(void) { }
120 * If oops/die is expected to crash the machine, return true here.
122 * This should not be expected to be 100% accurate, there may be
123 * notifiers registered or other unexpected conditions that may bring
124 * down the kernel. Or if the current process in the kernel is holding
125 * locks or has other critical state, the kernel may become effectively
128 bool die_will_crash(void)
130 if (should_fadump_crash())
132 if (kexec_should_crash(current))
134 if (in_interrupt() || panic_on_oops ||
135 !current->pid || is_global_init(current))
141 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
142 static int die_owner = -1;
143 static unsigned int die_nest_count;
144 static int die_counter;
146 static unsigned long oops_begin(struct pt_regs *regs)
153 /* racy, but better than risking deadlock. */
154 raw_local_irq_save(flags);
155 cpu = smp_processor_id();
156 if (!arch_spin_trylock(&die_lock)) {
157 if (cpu == die_owner)
158 /* nested oops. should stop eventually */;
160 arch_spin_lock(&die_lock);
166 if (machine_is(powermac))
167 pmac_backlight_unblank();
170 NOKPROBE_SYMBOL(oops_begin);
172 static void oops_end(unsigned long flags, struct pt_regs *regs,
176 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
180 if (!die_nest_count) {
181 /* Nest count reaches zero, release the lock. */
183 arch_spin_unlock(&die_lock);
185 raw_local_irq_restore(flags);
187 crash_fadump(regs, "die oops");
189 if (kexec_should_crash(current))
196 * While our oops output is serialised by a spinlock, output
197 * from panic() called below can race and corrupt it. If we
198 * know we are going to panic, delay for 1 second so we have a
199 * chance to get clean backtraces from all CPUs that are oopsing.
201 if (in_interrupt() || panic_on_oops || !current->pid ||
202 is_global_init(current)) {
203 mdelay(MSEC_PER_SEC);
207 panic("Fatal exception in interrupt");
209 panic("Fatal exception");
212 NOKPROBE_SYMBOL(oops_end);
214 static int __die(const char *str, struct pt_regs *regs, long err)
216 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
218 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
223 if (IS_ENABLED(CONFIG_PREEMPT))
226 if (IS_ENABLED(CONFIG_SMP))
227 pr_cont("SMP NR_CPUS=%d ", NR_CPUS);
229 if (debug_pagealloc_enabled())
230 pr_cont("DEBUG_PAGEALLOC ");
232 if (IS_ENABLED(CONFIG_NUMA))
235 pr_cont("%s\n", ppc_md.name ? ppc_md.name : "");
237 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
245 NOKPROBE_SYMBOL(__die);
247 void die(const char *str, struct pt_regs *regs, long err)
254 flags = oops_begin(regs);
255 if (__die(str, regs, err))
257 oops_end(flags, regs, err);
259 NOKPROBE_SYMBOL(die);
261 void user_single_step_siginfo(struct task_struct *tsk,
262 struct pt_regs *regs, siginfo_t *info)
264 memset(info, 0, sizeof(*info));
265 info->si_signo = SIGTRAP;
266 info->si_code = TRAP_TRACE;
267 info->si_addr = (void __user *)regs->nip;
271 void _exception_pkey(int signr, struct pt_regs *regs, int code,
272 unsigned long addr, int key)
275 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
276 "at %08lx nip %08lx lr %08lx code %x\n";
277 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
278 "at %016lx nip %016lx lr %016lx code %x\n";
280 if (!user_mode(regs)) {
281 die("Exception in kernel mode", regs, signr);
285 if (show_unhandled_signals && unhandled_signal(current, signr)) {
286 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
287 current->comm, current->pid, signr,
288 addr, regs->nip, regs->link, code);
291 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
294 current->thread.trap_nr = code;
295 memset(&info, 0, sizeof(info));
296 info.si_signo = signr;
298 info.si_addr = (void __user *) addr;
301 force_sig_info(signr, &info, current);
304 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
306 _exception_pkey(signr, regs, code, addr, 0);
309 void system_reset_exception(struct pt_regs *regs)
312 * Avoid crashes in case of nested NMI exceptions. Recoverability
313 * is determined by RI and in_nmi
315 bool nested = in_nmi();
319 __this_cpu_inc(irq_stat.sreset_irqs);
321 /* See if any machine dependent calls */
322 if (ppc_md.system_reset_exception) {
323 if (ppc_md.system_reset_exception(regs))
331 * A system reset is a request to dump, so we always send
332 * it through the crashdump code (if fadump or kdump are
335 crash_fadump(regs, "System Reset");
340 * We aren't the primary crash CPU. We need to send it
341 * to a holding pattern to avoid it ending up in the panic
344 crash_kexec_secondary(regs);
347 * No debugger or crash dump registered, print logs then
350 die("System Reset", regs, SIGABRT);
352 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
353 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
354 nmi_panic(regs, "System Reset");
357 #ifdef CONFIG_PPC_BOOK3S_64
358 BUG_ON(get_paca()->in_nmi == 0);
359 if (get_paca()->in_nmi > 1)
360 nmi_panic(regs, "Unrecoverable nested System Reset");
362 /* Must die if the interrupt is not recoverable */
363 if (!(regs->msr & MSR_RI))
364 nmi_panic(regs, "Unrecoverable System Reset");
369 /* What should we do here? We could issue a shutdown or hard reset. */
373 * I/O accesses can cause machine checks on powermacs.
374 * Check if the NIP corresponds to the address of a sync
375 * instruction for which there is an entry in the exception
377 * Note that the 601 only takes a machine check on TEA
378 * (transfer error ack) signal assertion, and does not
379 * set any of the top 16 bits of SRR1.
382 static inline int check_io_access(struct pt_regs *regs)
385 unsigned long msr = regs->msr;
386 const struct exception_table_entry *entry;
387 unsigned int *nip = (unsigned int *)regs->nip;
389 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
390 && (entry = search_exception_tables(regs->nip)) != NULL) {
392 * Check that it's a sync instruction, or somewhere
393 * in the twi; isync; nop sequence that inb/inw/inl uses.
394 * As the address is in the exception table
395 * we should be able to read the instr there.
396 * For the debug message, we look at the preceding
399 if (*nip == PPC_INST_NOP)
401 else if (*nip == PPC_INST_ISYNC)
403 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
407 rb = (*nip >> 11) & 0x1f;
408 printk(KERN_DEBUG "%s bad port %lx at %p\n",
409 (*nip & 0x100)? "OUT to": "IN from",
410 regs->gpr[rb] - _IO_BASE, nip);
412 regs->nip = extable_fixup(entry);
416 #endif /* CONFIG_PPC32 */
420 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
421 /* On 4xx, the reason for the machine check or program exception
423 #define get_reason(regs) ((regs)->dsisr)
424 #define REASON_FP ESR_FP
425 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
426 #define REASON_PRIVILEGED ESR_PPR
427 #define REASON_TRAP ESR_PTR
429 /* single-step stuff */
430 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
431 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
434 /* On non-4xx, the reason for the machine check or program
435 exception is in the MSR. */
436 #define get_reason(regs) ((regs)->msr)
437 #define REASON_TM SRR1_PROGTM
438 #define REASON_FP SRR1_PROGFPE
439 #define REASON_ILLEGAL SRR1_PROGILL
440 #define REASON_PRIVILEGED SRR1_PROGPRIV
441 #define REASON_TRAP SRR1_PROGTRAP
443 #define single_stepping(regs) ((regs)->msr & MSR_SE)
444 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
447 #if defined(CONFIG_E500)
448 int machine_check_e500mc(struct pt_regs *regs)
450 unsigned long mcsr = mfspr(SPRN_MCSR);
451 unsigned long pvr = mfspr(SPRN_PVR);
452 unsigned long reason = mcsr;
455 if (reason & MCSR_LD) {
456 recoverable = fsl_rio_mcheck_exception(regs);
457 if (recoverable == 1)
461 printk("Machine check in kernel mode.\n");
462 printk("Caused by (from MCSR=%lx): ", reason);
464 if (reason & MCSR_MCP)
465 printk("Machine Check Signal\n");
467 if (reason & MCSR_ICPERR) {
468 printk("Instruction Cache Parity Error\n");
471 * This is recoverable by invalidating the i-cache.
473 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
474 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
478 * This will generally be accompanied by an instruction
479 * fetch error report -- only treat MCSR_IF as fatal
480 * if it wasn't due to an L1 parity error.
485 if (reason & MCSR_DCPERR_MC) {
486 printk("Data Cache Parity Error\n");
489 * In write shadow mode we auto-recover from the error, but it
490 * may still get logged and cause a machine check. We should
491 * only treat the non-write shadow case as non-recoverable.
493 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
494 * is not implemented but L1 data cache always runs in write
495 * shadow mode. Hence on data cache parity errors HW will
496 * automatically invalidate the L1 Data Cache.
498 if (PVR_VER(pvr) != PVR_VER_E6500) {
499 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
504 if (reason & MCSR_L2MMU_MHIT) {
505 printk("Hit on multiple TLB entries\n");
509 if (reason & MCSR_NMI)
510 printk("Non-maskable interrupt\n");
512 if (reason & MCSR_IF) {
513 printk("Instruction Fetch Error Report\n");
517 if (reason & MCSR_LD) {
518 printk("Load Error Report\n");
522 if (reason & MCSR_ST) {
523 printk("Store Error Report\n");
527 if (reason & MCSR_LDG) {
528 printk("Guarded Load Error Report\n");
532 if (reason & MCSR_TLBSYNC)
533 printk("Simultaneous tlbsync operations\n");
535 if (reason & MCSR_BSL2_ERR) {
536 printk("Level 2 Cache Error\n");
540 if (reason & MCSR_MAV) {
543 addr = mfspr(SPRN_MCAR);
544 addr |= (u64)mfspr(SPRN_MCARU) << 32;
546 printk("Machine Check %s Address: %#llx\n",
547 reason & MCSR_MEA ? "Effective" : "Physical", addr);
551 mtspr(SPRN_MCSR, mcsr);
552 return mfspr(SPRN_MCSR) == 0 && recoverable;
555 int machine_check_e500(struct pt_regs *regs)
557 unsigned long reason = mfspr(SPRN_MCSR);
559 if (reason & MCSR_BUS_RBERR) {
560 if (fsl_rio_mcheck_exception(regs))
562 if (fsl_pci_mcheck_exception(regs))
566 printk("Machine check in kernel mode.\n");
567 printk("Caused by (from MCSR=%lx): ", reason);
569 if (reason & MCSR_MCP)
570 printk("Machine Check Signal\n");
571 if (reason & MCSR_ICPERR)
572 printk("Instruction Cache Parity Error\n");
573 if (reason & MCSR_DCP_PERR)
574 printk("Data Cache Push Parity Error\n");
575 if (reason & MCSR_DCPERR)
576 printk("Data Cache Parity Error\n");
577 if (reason & MCSR_BUS_IAERR)
578 printk("Bus - Instruction Address Error\n");
579 if (reason & MCSR_BUS_RAERR)
580 printk("Bus - Read Address Error\n");
581 if (reason & MCSR_BUS_WAERR)
582 printk("Bus - Write Address Error\n");
583 if (reason & MCSR_BUS_IBERR)
584 printk("Bus - Instruction Data Error\n");
585 if (reason & MCSR_BUS_RBERR)
586 printk("Bus - Read Data Bus Error\n");
587 if (reason & MCSR_BUS_WBERR)
588 printk("Bus - Write Data Bus Error\n");
589 if (reason & MCSR_BUS_IPERR)
590 printk("Bus - Instruction Parity Error\n");
591 if (reason & MCSR_BUS_RPERR)
592 printk("Bus - Read Parity Error\n");
597 int machine_check_generic(struct pt_regs *regs)
601 #elif defined(CONFIG_E200)
602 int machine_check_e200(struct pt_regs *regs)
604 unsigned long reason = mfspr(SPRN_MCSR);
606 printk("Machine check in kernel mode.\n");
607 printk("Caused by (from MCSR=%lx): ", reason);
609 if (reason & MCSR_MCP)
610 printk("Machine Check Signal\n");
611 if (reason & MCSR_CP_PERR)
612 printk("Cache Push Parity Error\n");
613 if (reason & MCSR_CPERR)
614 printk("Cache Parity Error\n");
615 if (reason & MCSR_EXCP_ERR)
616 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
617 if (reason & MCSR_BUS_IRERR)
618 printk("Bus - Read Bus Error on instruction fetch\n");
619 if (reason & MCSR_BUS_DRERR)
620 printk("Bus - Read Bus Error on data load\n");
621 if (reason & MCSR_BUS_WRERR)
622 printk("Bus - Write Bus Error on buffered store or cache line push\n");
626 #elif defined(CONFIG_PPC32)
627 int machine_check_generic(struct pt_regs *regs)
629 unsigned long reason = regs->msr;
631 printk("Machine check in kernel mode.\n");
632 printk("Caused by (from SRR1=%lx): ", reason);
633 switch (reason & 0x601F0000) {
635 printk("Machine check signal\n");
637 case 0: /* for 601 */
639 case 0x140000: /* 7450 MSS error and TEA */
640 printk("Transfer error ack signal\n");
643 printk("Data parity error signal\n");
646 printk("Address parity error signal\n");
649 printk("L1 Data Cache error\n");
652 printk("L1 Instruction Cache error\n");
655 printk("L2 data cache parity error\n");
658 printk("Unknown values in msr\n");
662 #endif /* everything else */
664 void machine_check_exception(struct pt_regs *regs)
667 bool nested = in_nmi();
671 /* 64s accounts the mce in machine_check_early when in HVMODE */
672 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE))
673 __this_cpu_inc(irq_stat.mce_exceptions);
675 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
677 /* See if any machine dependent calls. In theory, we would want
678 * to call the CPU first, and call the ppc_md. one if the CPU
679 * one returns a positive number. However there is existing code
680 * that assumes the board gets a first chance, so let's keep it
681 * that way for now and fix things later. --BenH.
683 if (ppc_md.machine_check_exception)
684 recover = ppc_md.machine_check_exception(regs);
685 else if (cur_cpu_spec->machine_check)
686 recover = cur_cpu_spec->machine_check(regs);
691 if (debugger_fault_handler(regs))
694 if (check_io_access(regs))
697 die("Machine check", regs, SIGBUS);
699 /* Must die if the interrupt is not recoverable */
700 if (!(regs->msr & MSR_RI))
701 nmi_panic(regs, "Unrecoverable Machine check");
708 void SMIException(struct pt_regs *regs)
710 die("System Management Interrupt", regs, SIGABRT);
714 static void p9_hmi_special_emu(struct pt_regs *regs)
716 unsigned int ra, rb, t, i, sel, instr, rc;
717 const void __user *addr;
719 unsigned long ea, msr, msr_mask;
722 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
726 * lxvb16x opcode: 0x7c0006d8
727 * lxvd2x opcode: 0x7c000698
728 * lxvh8x opcode: 0x7c000658
729 * lxvw4x opcode: 0x7c000618
731 if ((instr & 0xfc00073e) != 0x7c000618) {
732 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
734 smp_processor_id(), current->comm, current->pid,
739 /* Grab vector registers into the task struct */
740 msr = regs->msr; /* Grab msr before we flush the bits */
741 flush_vsx_to_thread(current);
742 enable_kernel_altivec();
745 * Is userspace running with a different endian (this is rare but
748 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
750 /* Decode the instruction */
751 ra = (instr >> 16) & 0x1f;
752 rb = (instr >> 11) & 0x1f;
753 t = (instr >> 21) & 0x1f;
755 vdst = (u8 *)¤t->thread.vr_state.vr[t];
757 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0];
759 /* Grab the vector address */
760 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
763 addr = (__force const void __user *)ea;
766 if (!access_ok(VERIFY_READ, addr, 16)) {
767 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
768 " instr=%08x addr=%016lx\n",
769 smp_processor_id(), current->comm, current->pid,
770 regs->nip, instr, (unsigned long)addr);
774 /* Read the vector */
776 if ((unsigned long)addr & 0xfUL)
778 rc = __copy_from_user_inatomic(vbuf, addr, 16);
780 __get_user_atomic_128_aligned(vbuf, addr, rc);
782 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
783 " instr=%08x addr=%016lx\n",
784 smp_processor_id(), current->comm, current->pid,
785 regs->nip, instr, (unsigned long)addr);
789 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
790 " instr=%08x addr=%016lx\n",
791 smp_processor_id(), current->comm, current->pid, regs->nip,
792 instr, (unsigned long) addr);
794 /* Grab instruction "selector" */
795 sel = (instr >> 6) & 3;
798 * Check to make sure the facility is actually enabled. This
799 * could happen if we get a false positive hit.
801 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
802 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
805 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
807 if (!(msr & msr_mask)) {
808 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
809 " instr=%08x msr:%016lx\n",
810 smp_processor_id(), current->comm, current->pid,
811 regs->nip, instr, msr);
815 /* Do logging here before we modify sel based on endian */
818 PPC_WARN_EMULATED(lxvw4x, regs);
821 PPC_WARN_EMULATED(lxvh8x, regs);
824 PPC_WARN_EMULATED(lxvd2x, regs);
826 case 3: /* lxvb16x */
827 PPC_WARN_EMULATED(lxvb16x, regs);
831 #ifdef __LITTLE_ENDIAN__
833 * An LE kernel stores the vector in the task struct as an LE
834 * byte array (effectively swapping both the components and
835 * the content of the components). Those instructions expect
836 * the components to remain in ascending address order, so we
839 * If we are running a BE user space, the expectation is that
840 * of a simple memcpy, so forcing the emulation to look like
841 * a lxvb16x should do the trick.
848 for (i = 0; i < 4; i++)
849 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
852 for (i = 0; i < 8; i++)
853 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
856 for (i = 0; i < 2; i++)
857 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
859 case 3: /* lxvb16x */
860 for (i = 0; i < 16; i++)
861 vdst[i] = vbuf[15-i];
864 #else /* __LITTLE_ENDIAN__ */
865 /* On a big endian kernel, a BE userspace only needs a memcpy */
869 /* Otherwise, we need to swap the content of the components */
872 for (i = 0; i < 4; i++)
873 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
876 for (i = 0; i < 8; i++)
877 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
880 for (i = 0; i < 2; i++)
881 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
883 case 3: /* lxvb16x */
884 memcpy(vdst, vbuf, 16);
887 #endif /* !__LITTLE_ENDIAN__ */
889 /* Go to next instruction */
892 #endif /* CONFIG_VSX */
894 void handle_hmi_exception(struct pt_regs *regs)
896 struct pt_regs *old_regs;
898 old_regs = set_irq_regs(regs);
902 /* Real mode flagged P9 special emu is needed */
903 if (local_paca->hmi_p9_special_emu) {
904 local_paca->hmi_p9_special_emu = 0;
907 * We don't want to take page faults while doing the
908 * emulation, we just replay the instruction if necessary.
911 p9_hmi_special_emu(regs);
914 #endif /* CONFIG_VSX */
916 if (ppc_md.handle_hmi_exception)
917 ppc_md.handle_hmi_exception(regs);
920 set_irq_regs(old_regs);
923 void unknown_exception(struct pt_regs *regs)
925 enum ctx_state prev_state = exception_enter();
927 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
928 regs->nip, regs->msr, regs->trap);
930 _exception(SIGTRAP, regs, 0, 0);
932 exception_exit(prev_state);
935 void instruction_breakpoint_exception(struct pt_regs *regs)
937 enum ctx_state prev_state = exception_enter();
939 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
940 5, SIGTRAP) == NOTIFY_STOP)
942 if (debugger_iabr_match(regs))
944 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
947 exception_exit(prev_state);
950 void RunModeException(struct pt_regs *regs)
952 _exception(SIGTRAP, regs, 0, 0);
955 void single_step_exception(struct pt_regs *regs)
957 enum ctx_state prev_state = exception_enter();
959 clear_single_step(regs);
961 if (kprobe_post_handler(regs))
964 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
965 5, SIGTRAP) == NOTIFY_STOP)
967 if (debugger_sstep(regs))
970 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
973 exception_exit(prev_state);
975 NOKPROBE_SYMBOL(single_step_exception);
978 * After we have successfully emulated an instruction, we have to
979 * check if the instruction was being single-stepped, and if so,
980 * pretend we got a single-step exception. This was pointed out
981 * by Kumar Gala. -- paulus
983 static void emulate_single_step(struct pt_regs *regs)
985 if (single_stepping(regs))
986 single_step_exception(regs);
989 static inline int __parse_fpscr(unsigned long fpscr)
993 /* Invalid operation */
994 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
998 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1002 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1005 /* Divide by zero */
1006 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1009 /* Inexact result */
1010 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1016 static void parse_fpe(struct pt_regs *regs)
1020 flush_fp_to_thread(current);
1022 code = __parse_fpscr(current->thread.fp_state.fpscr);
1024 _exception(SIGFPE, regs, code, regs->nip);
1028 * Illegal instruction emulation support. Originally written to
1029 * provide the PVR to user applications using the mfspr rd, PVR.
1030 * Return non-zero if we can't emulate, or -EFAULT if the associated
1031 * memory access caused an access fault. Return zero on success.
1033 * There are a couple of ways to do this, either "decode" the instruction
1034 * or directly match lots of bits. In this case, matching lots of
1035 * bits is faster and easier.
1038 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1040 u8 rT = (instword >> 21) & 0x1f;
1041 u8 rA = (instword >> 16) & 0x1f;
1042 u8 NB_RB = (instword >> 11) & 0x1f;
1047 /* Early out if we are an invalid form of lswx */
1048 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1049 if ((rT == rA) || (rT == NB_RB))
1052 EA = (rA == 0) ? 0 : regs->gpr[rA];
1054 switch (instword & PPC_INST_STRING_MASK) {
1056 case PPC_INST_STSWX:
1058 num_bytes = regs->xer & 0x7f;
1061 case PPC_INST_STSWI:
1062 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1068 while (num_bytes != 0)
1071 u32 shift = 8 * (3 - (pos & 0x3));
1073 /* if process is 32-bit, clear upper 32 bits of EA */
1074 if ((regs->msr & MSR_64BIT) == 0)
1077 switch ((instword & PPC_INST_STRING_MASK)) {
1080 if (get_user(val, (u8 __user *)EA))
1082 /* first time updating this reg,
1086 regs->gpr[rT] |= val << shift;
1088 case PPC_INST_STSWI:
1089 case PPC_INST_STSWX:
1090 val = regs->gpr[rT] >> shift;
1091 if (put_user(val, (u8 __user *)EA))
1095 /* move EA to next address */
1099 /* manage our position within the register */
1110 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1115 ra = (instword >> 16) & 0x1f;
1116 rs = (instword >> 21) & 0x1f;
1118 tmp = regs->gpr[rs];
1119 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1120 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1121 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1122 regs->gpr[ra] = tmp;
1127 static int emulate_isel(struct pt_regs *regs, u32 instword)
1129 u8 rT = (instword >> 21) & 0x1f;
1130 u8 rA = (instword >> 16) & 0x1f;
1131 u8 rB = (instword >> 11) & 0x1f;
1132 u8 BC = (instword >> 6) & 0x1f;
1136 tmp = (rA == 0) ? 0 : regs->gpr[rA];
1137 bit = (regs->ccr >> (31 - BC)) & 0x1;
1139 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1144 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1145 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1147 /* If we're emulating a load/store in an active transaction, we cannot
1148 * emulate it as the kernel operates in transaction suspended context.
1149 * We need to abort the transaction. This creates a persistent TM
1150 * abort so tell the user what caused it with a new code.
1152 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1160 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1166 static int emulate_instruction(struct pt_regs *regs)
1171 if (!user_mode(regs))
1173 CHECK_FULL_REGS(regs);
1175 if (get_user(instword, (u32 __user *)(regs->nip)))
1178 /* Emulate the mfspr rD, PVR. */
1179 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1180 PPC_WARN_EMULATED(mfpvr, regs);
1181 rd = (instword >> 21) & 0x1f;
1182 regs->gpr[rd] = mfspr(SPRN_PVR);
1186 /* Emulating the dcba insn is just a no-op. */
1187 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1188 PPC_WARN_EMULATED(dcba, regs);
1192 /* Emulate the mcrxr insn. */
1193 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1194 int shift = (instword >> 21) & 0x1c;
1195 unsigned long msk = 0xf0000000UL >> shift;
1197 PPC_WARN_EMULATED(mcrxr, regs);
1198 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1199 regs->xer &= ~0xf0000000UL;
1203 /* Emulate load/store string insn. */
1204 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1205 if (tm_abort_check(regs,
1206 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1208 PPC_WARN_EMULATED(string, regs);
1209 return emulate_string_inst(regs, instword);
1212 /* Emulate the popcntb (Population Count Bytes) instruction. */
1213 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1214 PPC_WARN_EMULATED(popcntb, regs);
1215 return emulate_popcntb_inst(regs, instword);
1218 /* Emulate isel (Integer Select) instruction */
1219 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1220 PPC_WARN_EMULATED(isel, regs);
1221 return emulate_isel(regs, instword);
1224 /* Emulate sync instruction variants */
1225 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1226 PPC_WARN_EMULATED(sync, regs);
1227 asm volatile("sync");
1232 /* Emulate the mfspr rD, DSCR. */
1233 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1234 PPC_INST_MFSPR_DSCR_USER) ||
1235 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1236 PPC_INST_MFSPR_DSCR)) &&
1237 cpu_has_feature(CPU_FTR_DSCR)) {
1238 PPC_WARN_EMULATED(mfdscr, regs);
1239 rd = (instword >> 21) & 0x1f;
1240 regs->gpr[rd] = mfspr(SPRN_DSCR);
1243 /* Emulate the mtspr DSCR, rD. */
1244 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1245 PPC_INST_MTSPR_DSCR_USER) ||
1246 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1247 PPC_INST_MTSPR_DSCR)) &&
1248 cpu_has_feature(CPU_FTR_DSCR)) {
1249 PPC_WARN_EMULATED(mtdscr, regs);
1250 rd = (instword >> 21) & 0x1f;
1251 current->thread.dscr = regs->gpr[rd];
1252 current->thread.dscr_inherit = 1;
1253 mtspr(SPRN_DSCR, current->thread.dscr);
1261 int is_valid_bugaddr(unsigned long addr)
1263 return is_kernel_addr(addr);
1266 #ifdef CONFIG_MATH_EMULATION
1267 static int emulate_math(struct pt_regs *regs)
1270 extern int do_mathemu(struct pt_regs *regs);
1272 ret = do_mathemu(regs);
1274 PPC_WARN_EMULATED(math, regs);
1278 emulate_single_step(regs);
1282 code = __parse_fpscr(current->thread.fp_state.fpscr);
1283 _exception(SIGFPE, regs, code, regs->nip);
1287 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1294 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1297 void program_check_exception(struct pt_regs *regs)
1299 enum ctx_state prev_state = exception_enter();
1300 unsigned int reason = get_reason(regs);
1302 /* We can now get here via a FP Unavailable exception if the core
1303 * has no FPU, in that case the reason flags will be 0 */
1305 if (reason & REASON_FP) {
1306 /* IEEE FP exception */
1310 if (reason & REASON_TRAP) {
1311 unsigned long bugaddr;
1312 /* Debugger is first in line to stop recursive faults in
1313 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1314 if (debugger_bpt(regs))
1317 if (kprobe_handler(regs))
1320 /* trap exception */
1321 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1325 bugaddr = regs->nip;
1327 * Fixup bugaddr for BUG_ON() in real mode
1329 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1330 bugaddr += PAGE_OFFSET;
1332 if (!(regs->msr & MSR_PR) && /* not user-mode */
1333 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1337 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1340 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1341 if (reason & REASON_TM) {
1342 /* This is a TM "Bad Thing Exception" program check.
1344 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1345 * transition in TM states.
1346 * - A trechkpt is attempted when transactional.
1347 * - A treclaim is attempted when non transactional.
1348 * - A tend is illegally attempted.
1349 * - writing a TM SPR when transactional.
1351 * If usermode caused this, it's done something illegal and
1352 * gets a SIGILL slap on the wrist. We call it an illegal
1353 * operand to distinguish from the instruction just being bad
1354 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1355 * illegal /placement/ of a valid instruction.
1357 if (user_mode(regs)) {
1358 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1361 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1362 "at %lx (msr 0x%x)\n", regs->nip, reason);
1363 die("Unrecoverable exception", regs, SIGABRT);
1369 * If we took the program check in the kernel skip down to sending a
1370 * SIGILL. The subsequent cases all relate to emulating instructions
1371 * which we should only do for userspace. We also do not want to enable
1372 * interrupts for kernel faults because that might lead to further
1373 * faults, and loose the context of the original exception.
1375 if (!user_mode(regs))
1378 /* We restore the interrupt state now */
1379 if (!arch_irq_disabled_regs(regs))
1382 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1383 * but there seems to be a hardware bug on the 405GP (RevD)
1384 * that means ESR is sometimes set incorrectly - either to
1385 * ESR_DST (!?) or 0. In the process of chasing this with the
1386 * hardware people - not sure if it can happen on any illegal
1387 * instruction or only on FP instructions, whether there is a
1388 * pattern to occurrences etc. -dgibson 31/Mar/2003
1390 if (!emulate_math(regs))
1393 /* Try to emulate it if we should. */
1394 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1395 switch (emulate_instruction(regs)) {
1398 emulate_single_step(regs);
1401 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1407 if (reason & REASON_PRIVILEGED)
1408 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1410 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1413 exception_exit(prev_state);
1415 NOKPROBE_SYMBOL(program_check_exception);
1418 * This occurs when running in hypervisor mode on POWER6 or later
1419 * and an illegal instruction is encountered.
1421 void emulation_assist_interrupt(struct pt_regs *regs)
1423 regs->msr |= REASON_ILLEGAL;
1424 program_check_exception(regs);
1426 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1428 void alignment_exception(struct pt_regs *regs)
1430 enum ctx_state prev_state = exception_enter();
1431 int sig, code, fixed = 0;
1433 /* We restore the interrupt state now */
1434 if (!arch_irq_disabled_regs(regs))
1437 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1440 /* we don't implement logging of alignment exceptions */
1441 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1442 fixed = fix_alignment(regs);
1445 regs->nip += 4; /* skip over emulated instruction */
1446 emulate_single_step(regs);
1450 /* Operand address was bad */
1451 if (fixed == -EFAULT) {
1458 if (user_mode(regs))
1459 _exception(sig, regs, code, regs->dar);
1461 bad_page_fault(regs, regs->dar, sig);
1464 exception_exit(prev_state);
1467 void slb_miss_bad_addr(struct pt_regs *regs)
1469 enum ctx_state prev_state = exception_enter();
1471 if (user_mode(regs))
1472 _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar);
1474 bad_page_fault(regs, regs->dar, SIGSEGV);
1476 exception_exit(prev_state);
1479 void StackOverflow(struct pt_regs *regs)
1481 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1482 current, regs->gpr[1]);
1485 panic("kernel stack overflow");
1488 void nonrecoverable_exception(struct pt_regs *regs)
1490 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1491 regs->nip, regs->msr);
1493 die("nonrecoverable exception", regs, SIGKILL);
1496 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1498 enum ctx_state prev_state = exception_enter();
1500 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1501 "%lx at %lx\n", regs->trap, regs->nip);
1502 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1504 exception_exit(prev_state);
1507 void altivec_unavailable_exception(struct pt_regs *regs)
1509 enum ctx_state prev_state = exception_enter();
1511 if (user_mode(regs)) {
1512 /* A user program has executed an altivec instruction,
1513 but this kernel doesn't support altivec. */
1514 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1518 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1519 "%lx at %lx\n", regs->trap, regs->nip);
1520 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1523 exception_exit(prev_state);
1526 void vsx_unavailable_exception(struct pt_regs *regs)
1528 if (user_mode(regs)) {
1529 /* A user program has executed an vsx instruction,
1530 but this kernel doesn't support vsx. */
1531 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1535 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1536 "%lx at %lx\n", regs->trap, regs->nip);
1537 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1541 static void tm_unavailable(struct pt_regs *regs)
1543 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1544 if (user_mode(regs)) {
1545 current->thread.load_tm++;
1546 regs->msr |= MSR_TM;
1548 tm_restore_sprs(¤t->thread);
1552 pr_emerg("Unrecoverable TM Unavailable Exception "
1553 "%lx at %lx\n", regs->trap, regs->nip);
1554 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1557 void facility_unavailable_exception(struct pt_regs *regs)
1559 static char *facility_strings[] = {
1560 [FSCR_FP_LG] = "FPU",
1561 [FSCR_VECVSX_LG] = "VMX/VSX",
1562 [FSCR_DSCR_LG] = "DSCR",
1563 [FSCR_PM_LG] = "PMU SPRs",
1564 [FSCR_BHRB_LG] = "BHRB",
1565 [FSCR_TM_LG] = "TM",
1566 [FSCR_EBB_LG] = "EBB",
1567 [FSCR_TAR_LG] = "TAR",
1568 [FSCR_MSGP_LG] = "MSGP",
1569 [FSCR_SCV_LG] = "SCV",
1571 char *facility = "unknown";
1577 hv = (TRAP(regs) == 0xf80);
1579 value = mfspr(SPRN_HFSCR);
1581 value = mfspr(SPRN_FSCR);
1583 status = value >> 56;
1584 if (status == FSCR_DSCR_LG) {
1586 * User is accessing the DSCR register using the problem
1587 * state only SPR number (0x03) either through a mfspr or
1588 * a mtspr instruction. If it is a write attempt through
1589 * a mtspr, then we set the inherit bit. This also allows
1590 * the user to write or read the register directly in the
1591 * future by setting via the FSCR DSCR bit. But in case it
1592 * is a read DSCR attempt through a mfspr instruction, we
1593 * just emulate the instruction instead. This code path will
1594 * always emulate all the mfspr instructions till the user
1595 * has attempted at least one mtspr instruction. This way it
1596 * preserves the same behaviour when the user is accessing
1597 * the DSCR through privilege level only SPR number (0x11)
1598 * which is emulated through illegal instruction exception.
1599 * We always leave HFSCR DSCR set.
1601 if (get_user(instword, (u32 __user *)(regs->nip))) {
1602 pr_err("Failed to fetch the user instruction\n");
1606 /* Write into DSCR (mtspr 0x03, RS) */
1607 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1608 == PPC_INST_MTSPR_DSCR_USER) {
1609 rd = (instword >> 21) & 0x1f;
1610 current->thread.dscr = regs->gpr[rd];
1611 current->thread.dscr_inherit = 1;
1612 current->thread.fscr |= FSCR_DSCR;
1613 mtspr(SPRN_FSCR, current->thread.fscr);
1616 /* Read from DSCR (mfspr RT, 0x03) */
1617 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1618 == PPC_INST_MFSPR_DSCR_USER) {
1619 if (emulate_instruction(regs)) {
1620 pr_err("DSCR based mfspr emulation failed\n");
1624 emulate_single_step(regs);
1629 if (status == FSCR_TM_LG) {
1631 * If we're here then the hardware is TM aware because it
1632 * generated an exception with FSRM_TM set.
1634 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1635 * told us not to do TM, or the kernel is not built with TM
1638 * If both of those things are true, then userspace can spam the
1639 * console by triggering the printk() below just by continually
1640 * doing tbegin (or any TM instruction). So in that case just
1641 * send the process a SIGILL immediately.
1643 if (!cpu_has_feature(CPU_FTR_TM))
1646 tm_unavailable(regs);
1650 if ((hv || status >= 2) &&
1651 (status < ARRAY_SIZE(facility_strings)) &&
1652 facility_strings[status])
1653 facility = facility_strings[status];
1655 /* We restore the interrupt state now */
1656 if (!arch_irq_disabled_regs(regs))
1659 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1660 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1663 if (user_mode(regs)) {
1664 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1668 die("Unexpected facility unavailable exception", regs, SIGABRT);
1672 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1674 void fp_unavailable_tm(struct pt_regs *regs)
1676 /* Note: This does not handle any kind of FP laziness. */
1678 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1679 regs->nip, regs->msr);
1681 /* We can only have got here if the task started using FP after
1682 * beginning the transaction. So, the transactional regs are just a
1683 * copy of the checkpointed ones. But, we still need to recheckpoint
1684 * as we're enabling FP for the process; it will return, abort the
1685 * transaction, and probably retry but now with FP enabled. So the
1686 * checkpointed FP registers need to be loaded.
1688 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1689 /* Reclaim didn't save out any FPRs to transact_fprs. */
1691 /* Enable FP for the task: */
1692 current->thread.load_fp = 1;
1694 /* This loads and recheckpoints the FP registers from
1695 * thread.fpr[]. They will remain in registers after the
1696 * checkpoint so we don't need to reload them after.
1697 * If VMX is in use, the VRs now hold checkpointed values,
1698 * so we don't want to load the VRs from the thread_struct.
1700 tm_recheckpoint(¤t->thread);
1703 void altivec_unavailable_tm(struct pt_regs *regs)
1705 /* See the comments in fp_unavailable_tm(). This function operates
1709 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1711 regs->nip, regs->msr);
1712 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1713 current->thread.load_vec = 1;
1714 tm_recheckpoint(¤t->thread);
1715 current->thread.used_vr = 1;
1718 void vsx_unavailable_tm(struct pt_regs *regs)
1720 /* See the comments in fp_unavailable_tm(). This works similarly,
1721 * though we're loading both FP and VEC registers in here.
1723 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1724 * regs. Either way, set MSR_VSX.
1727 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1729 regs->nip, regs->msr);
1731 current->thread.used_vsr = 1;
1733 /* This reclaims FP and/or VR regs if they're already enabled */
1734 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1736 current->thread.load_vec = 1;
1737 current->thread.load_fp = 1;
1739 tm_recheckpoint(¤t->thread);
1741 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1743 void performance_monitor_exception(struct pt_regs *regs)
1745 __this_cpu_inc(irq_stat.pmu_irqs);
1750 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1751 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1755 * Determine the cause of the debug event, clear the
1756 * event flags and send a trap to the handler. Torez
1758 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1759 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1760 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1761 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1763 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1766 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1767 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1768 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1771 } else if (debug_status & DBSR_IAC1) {
1772 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1773 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1774 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1777 } else if (debug_status & DBSR_IAC2) {
1778 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1779 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1782 } else if (debug_status & DBSR_IAC3) {
1783 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1784 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1785 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1788 } else if (debug_status & DBSR_IAC4) {
1789 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1790 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1795 * At the point this routine was called, the MSR(DE) was turned off.
1796 * Check all other debug flags and see if that bit needs to be turned
1799 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1800 current->thread.debug.dbcr1))
1801 regs->msr |= MSR_DE;
1803 /* Make sure the IDM flag is off */
1804 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1807 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1810 void DebugException(struct pt_regs *regs, unsigned long debug_status)
1812 current->thread.debug.dbsr = debug_status;
1814 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1815 * on server, it stops on the target of the branch. In order to simulate
1816 * the server behaviour, we thus restart right away with a single step
1817 * instead of stopping here when hitting a BT
1819 if (debug_status & DBSR_BT) {
1820 regs->msr &= ~MSR_DE;
1823 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1824 /* Clear the BT event */
1825 mtspr(SPRN_DBSR, DBSR_BT);
1827 /* Do the single step trick only when coming from userspace */
1828 if (user_mode(regs)) {
1829 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1830 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1831 regs->msr |= MSR_DE;
1835 if (kprobe_post_handler(regs))
1838 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1839 5, SIGTRAP) == NOTIFY_STOP) {
1842 if (debugger_sstep(regs))
1844 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1845 regs->msr &= ~MSR_DE;
1847 /* Disable instruction completion */
1848 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1849 /* Clear the instruction completion event */
1850 mtspr(SPRN_DBSR, DBSR_IC);
1852 if (kprobe_post_handler(regs))
1855 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1856 5, SIGTRAP) == NOTIFY_STOP) {
1860 if (debugger_sstep(regs))
1863 if (user_mode(regs)) {
1864 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1865 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1866 current->thread.debug.dbcr1))
1867 regs->msr |= MSR_DE;
1869 /* Make sure the IDM bit is off */
1870 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1873 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1875 handle_debug(regs, debug_status);
1877 NOKPROBE_SYMBOL(DebugException);
1878 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1880 #if !defined(CONFIG_TAU_INT)
1881 void TAUException(struct pt_regs *regs)
1883 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1884 regs->nip, regs->msr, regs->trap, print_tainted());
1886 #endif /* CONFIG_INT_TAU */
1888 #ifdef CONFIG_ALTIVEC
1889 void altivec_assist_exception(struct pt_regs *regs)
1893 if (!user_mode(regs)) {
1894 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1895 " at %lx\n", regs->nip);
1896 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1899 flush_altivec_to_thread(current);
1901 PPC_WARN_EMULATED(altivec, regs);
1902 err = emulate_altivec(regs);
1904 regs->nip += 4; /* skip emulated instruction */
1905 emulate_single_step(regs);
1909 if (err == -EFAULT) {
1910 /* got an error reading the instruction */
1911 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1913 /* didn't recognize the instruction */
1914 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1915 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1916 "in %s at %lx\n", current->comm, regs->nip);
1917 current->thread.vr_state.vscr.u[3] |= 0x10000;
1920 #endif /* CONFIG_ALTIVEC */
1922 #ifdef CONFIG_FSL_BOOKE
1923 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1924 unsigned long error_code)
1926 /* We treat cache locking instructions from the user
1927 * as priv ops, in the future we could try to do
1930 if (error_code & (ESR_DLK|ESR_ILK))
1931 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1934 #endif /* CONFIG_FSL_BOOKE */
1937 void SPEFloatingPointException(struct pt_regs *regs)
1939 extern int do_spe_mathemu(struct pt_regs *regs);
1940 unsigned long spefscr;
1945 flush_spe_to_thread(current);
1947 spefscr = current->thread.spefscr;
1948 fpexc_mode = current->thread.fpexc_mode;
1950 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1953 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1956 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1958 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1961 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1964 err = do_spe_mathemu(regs);
1966 regs->nip += 4; /* skip emulated instruction */
1967 emulate_single_step(regs);
1971 if (err == -EFAULT) {
1972 /* got an error reading the instruction */
1973 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1974 } else if (err == -EINVAL) {
1975 /* didn't recognize the instruction */
1976 printk(KERN_ERR "unrecognized spe instruction "
1977 "in %s at %lx\n", current->comm, regs->nip);
1979 _exception(SIGFPE, regs, code, regs->nip);
1985 void SPEFloatingPointRoundException(struct pt_regs *regs)
1987 extern int speround_handler(struct pt_regs *regs);
1991 if (regs->msr & MSR_SPE)
1992 giveup_spe(current);
1996 err = speround_handler(regs);
1998 regs->nip += 4; /* skip emulated instruction */
1999 emulate_single_step(regs);
2003 if (err == -EFAULT) {
2004 /* got an error reading the instruction */
2005 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2006 } else if (err == -EINVAL) {
2007 /* didn't recognize the instruction */
2008 printk(KERN_ERR "unrecognized spe instruction "
2009 "in %s at %lx\n", current->comm, regs->nip);
2011 _exception(SIGFPE, regs, 0, regs->nip);
2018 * We enter here if we get an unrecoverable exception, that is, one
2019 * that happened at a point where the RI (recoverable interrupt) bit
2020 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2021 * we therefore lost state by taking this exception.
2023 void unrecoverable_exception(struct pt_regs *regs)
2025 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
2026 regs->trap, regs->nip);
2027 die("Unrecoverable exception", regs, SIGABRT);
2029 NOKPROBE_SYMBOL(unrecoverable_exception);
2031 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2033 * Default handler for a Watchdog exception,
2034 * spins until a reboot occurs
2036 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2038 /* Generic WatchdogHandler, implement your own */
2039 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2043 void WatchdogException(struct pt_regs *regs)
2045 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2046 WatchdogHandler(regs);
2051 * We enter here if we discover during exception entry that we are
2052 * running in supervisor mode with a userspace value in the stack pointer.
2054 void kernel_bad_stack(struct pt_regs *regs)
2056 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2057 regs->gpr[1], regs->nip);
2058 die("Bad kernel stack pointer", regs, SIGABRT);
2060 NOKPROBE_SYMBOL(kernel_bad_stack);
2062 void __init trap_init(void)
2067 #ifdef CONFIG_PPC_EMULATED_STATS
2069 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2071 struct ppc_emulated ppc_emulated = {
2072 #ifdef CONFIG_ALTIVEC
2073 WARN_EMULATED_SETUP(altivec),
2075 WARN_EMULATED_SETUP(dcba),
2076 WARN_EMULATED_SETUP(dcbz),
2077 WARN_EMULATED_SETUP(fp_pair),
2078 WARN_EMULATED_SETUP(isel),
2079 WARN_EMULATED_SETUP(mcrxr),
2080 WARN_EMULATED_SETUP(mfpvr),
2081 WARN_EMULATED_SETUP(multiple),
2082 WARN_EMULATED_SETUP(popcntb),
2083 WARN_EMULATED_SETUP(spe),
2084 WARN_EMULATED_SETUP(string),
2085 WARN_EMULATED_SETUP(sync),
2086 WARN_EMULATED_SETUP(unaligned),
2087 #ifdef CONFIG_MATH_EMULATION
2088 WARN_EMULATED_SETUP(math),
2091 WARN_EMULATED_SETUP(vsx),
2094 WARN_EMULATED_SETUP(mfdscr),
2095 WARN_EMULATED_SETUP(mtdscr),
2096 WARN_EMULATED_SETUP(lq_stq),
2097 WARN_EMULATED_SETUP(lxvw4x),
2098 WARN_EMULATED_SETUP(lxvh8x),
2099 WARN_EMULATED_SETUP(lxvd2x),
2100 WARN_EMULATED_SETUP(lxvb16x),
2104 u32 ppc_warn_emulated;
2106 void ppc_warn_emulated_print(const char *type)
2108 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2112 static int __init ppc_warn_emulated_init(void)
2114 struct dentry *dir, *d;
2116 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2118 if (!powerpc_debugfs_root)
2121 dir = debugfs_create_dir("emulated_instructions",
2122 powerpc_debugfs_root);
2126 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
2127 &ppc_warn_emulated);
2131 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
2132 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
2133 (u32 *)&entries[i].val.counter);
2141 debugfs_remove_recursive(dir);
2145 device_initcall(ppc_warn_emulated_init);
2147 #endif /* CONFIG_PPC_EMULATED_STATS */