1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/random.h>
38 #include <linux/hw_breakpoint.h>
39 #include <linux/uaccess.h>
40 #include <linux/elf-randomize.h>
41 #include <linux/pkeys.h>
42 #include <linux/seq_buf.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
57 #include <asm/hw_irq.h>
59 #include <asm/code-patching.h>
61 #include <asm/livepatch.h>
62 #include <asm/cpu_has_feature.h>
63 #include <asm/asm-prototypes.h>
64 #include <asm/stacktrace.h>
65 #include <asm/hw_breakpoint.h>
67 #include <linux/kprobes.h>
68 #include <linux/kdebug.h>
70 /* Transactional Memory debug */
72 #define TM_DEBUG(x...) printk(KERN_INFO x)
74 #define TM_DEBUG(x...) do { } while(0)
77 extern unsigned long _get_SP(void);
79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
81 * Are we running in "Suspend disabled" mode? If so we have to block any
82 * sigreturn that would get us into suspended state, and we also warn in some
83 * other paths that we should never reach with suspend disabled.
85 bool tm_suspend_disabled __ro_after_init = false;
87 static void check_if_tm_restore_required(struct task_struct *tsk)
90 * If we are saving the current thread's registers, and the
91 * thread is in a transactional state, set the TIF_RESTORE_TM
92 * bit so that we know to restore the registers before
93 * returning to userspace.
95 if (tsk == current && tsk->thread.regs &&
96 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
97 !test_thread_flag(TIF_RESTORE_TM)) {
98 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
99 set_thread_flag(TIF_RESTORE_TM);
104 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
105 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
107 bool strict_msr_control;
108 EXPORT_SYMBOL(strict_msr_control);
110 static int __init enable_strict_msr_control(char *str)
112 strict_msr_control = true;
113 pr_info("Enabling strict facility control\n");
117 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
119 /* notrace because it's called by restore_math */
120 unsigned long notrace msr_check_and_set(unsigned long bits)
122 unsigned long oldmsr = mfmsr();
123 unsigned long newmsr;
125 newmsr = oldmsr | bits;
128 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
132 if (oldmsr != newmsr)
137 EXPORT_SYMBOL_GPL(msr_check_and_set);
139 /* notrace because it's called by restore_math */
140 void notrace __msr_check_and_clear(unsigned long bits)
142 unsigned long oldmsr = mfmsr();
143 unsigned long newmsr;
145 newmsr = oldmsr & ~bits;
148 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
152 if (oldmsr != newmsr)
155 EXPORT_SYMBOL(__msr_check_and_clear);
157 #ifdef CONFIG_PPC_FPU
158 static void __giveup_fpu(struct task_struct *tsk)
163 msr = tsk->thread.regs->msr;
164 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
166 if (cpu_has_feature(CPU_FTR_VSX))
169 tsk->thread.regs->msr = msr;
172 void giveup_fpu(struct task_struct *tsk)
174 check_if_tm_restore_required(tsk);
176 msr_check_and_set(MSR_FP);
178 msr_check_and_clear(MSR_FP);
180 EXPORT_SYMBOL(giveup_fpu);
183 * Make sure the floating-point register state in the
184 * the thread_struct is up to date for task tsk.
186 void flush_fp_to_thread(struct task_struct *tsk)
188 if (tsk->thread.regs) {
190 * We need to disable preemption here because if we didn't,
191 * another process could get scheduled after the regs->msr
192 * test but before we have finished saving the FP registers
193 * to the thread_struct. That process could take over the
194 * FPU, and then when we get scheduled again we would store
195 * bogus values for the remaining FP registers.
198 if (tsk->thread.regs->msr & MSR_FP) {
200 * This should only ever be called for current or
201 * for a stopped child process. Since we save away
202 * the FP register state on context switch,
203 * there is something wrong if a stopped child appears
204 * to still have its FP state in the CPU registers.
206 BUG_ON(tsk != current);
212 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
214 void enable_kernel_fp(void)
216 unsigned long cpumsr;
218 WARN_ON(preemptible());
220 cpumsr = msr_check_and_set(MSR_FP);
222 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
223 check_if_tm_restore_required(current);
225 * If a thread has already been reclaimed then the
226 * checkpointed registers are on the CPU but have definitely
227 * been saved by the reclaim code. Don't need to and *cannot*
228 * giveup as this would save to the 'live' structure not the
229 * checkpointed structure.
231 if (!MSR_TM_ACTIVE(cpumsr) &&
232 MSR_TM_ACTIVE(current->thread.regs->msr))
234 __giveup_fpu(current);
237 EXPORT_SYMBOL(enable_kernel_fp);
238 #endif /* CONFIG_PPC_FPU */
240 #ifdef CONFIG_ALTIVEC
241 static void __giveup_altivec(struct task_struct *tsk)
246 msr = tsk->thread.regs->msr;
249 if (cpu_has_feature(CPU_FTR_VSX))
252 tsk->thread.regs->msr = msr;
255 void giveup_altivec(struct task_struct *tsk)
257 check_if_tm_restore_required(tsk);
259 msr_check_and_set(MSR_VEC);
260 __giveup_altivec(tsk);
261 msr_check_and_clear(MSR_VEC);
263 EXPORT_SYMBOL(giveup_altivec);
265 void enable_kernel_altivec(void)
267 unsigned long cpumsr;
269 WARN_ON(preemptible());
271 cpumsr = msr_check_and_set(MSR_VEC);
273 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
274 check_if_tm_restore_required(current);
276 * If a thread has already been reclaimed then the
277 * checkpointed registers are on the CPU but have definitely
278 * been saved by the reclaim code. Don't need to and *cannot*
279 * giveup as this would save to the 'live' structure not the
280 * checkpointed structure.
282 if (!MSR_TM_ACTIVE(cpumsr) &&
283 MSR_TM_ACTIVE(current->thread.regs->msr))
285 __giveup_altivec(current);
288 EXPORT_SYMBOL(enable_kernel_altivec);
291 * Make sure the VMX/Altivec register state in the
292 * the thread_struct is up to date for task tsk.
294 void flush_altivec_to_thread(struct task_struct *tsk)
296 if (tsk->thread.regs) {
298 if (tsk->thread.regs->msr & MSR_VEC) {
299 BUG_ON(tsk != current);
305 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
306 #endif /* CONFIG_ALTIVEC */
309 static void __giveup_vsx(struct task_struct *tsk)
311 unsigned long msr = tsk->thread.regs->msr;
314 * We should never be ssetting MSR_VSX without also setting
317 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
319 /* __giveup_fpu will clear MSR_VSX */
323 __giveup_altivec(tsk);
326 static void giveup_vsx(struct task_struct *tsk)
328 check_if_tm_restore_required(tsk);
330 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
332 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
335 void enable_kernel_vsx(void)
337 unsigned long cpumsr;
339 WARN_ON(preemptible());
341 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
343 if (current->thread.regs &&
344 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
345 check_if_tm_restore_required(current);
347 * If a thread has already been reclaimed then the
348 * checkpointed registers are on the CPU but have definitely
349 * been saved by the reclaim code. Don't need to and *cannot*
350 * giveup as this would save to the 'live' structure not the
351 * checkpointed structure.
353 if (!MSR_TM_ACTIVE(cpumsr) &&
354 MSR_TM_ACTIVE(current->thread.regs->msr))
356 __giveup_vsx(current);
359 EXPORT_SYMBOL(enable_kernel_vsx);
361 void flush_vsx_to_thread(struct task_struct *tsk)
363 if (tsk->thread.regs) {
365 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
366 BUG_ON(tsk != current);
372 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
373 #endif /* CONFIG_VSX */
376 void giveup_spe(struct task_struct *tsk)
378 check_if_tm_restore_required(tsk);
380 msr_check_and_set(MSR_SPE);
382 msr_check_and_clear(MSR_SPE);
384 EXPORT_SYMBOL(giveup_spe);
386 void enable_kernel_spe(void)
388 WARN_ON(preemptible());
390 msr_check_and_set(MSR_SPE);
392 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
393 check_if_tm_restore_required(current);
394 __giveup_spe(current);
397 EXPORT_SYMBOL(enable_kernel_spe);
399 void flush_spe_to_thread(struct task_struct *tsk)
401 if (tsk->thread.regs) {
403 if (tsk->thread.regs->msr & MSR_SPE) {
404 BUG_ON(tsk != current);
405 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
411 #endif /* CONFIG_SPE */
413 static unsigned long msr_all_available;
415 static int __init init_msr_all_available(void)
417 #ifdef CONFIG_PPC_FPU
418 msr_all_available |= MSR_FP;
420 #ifdef CONFIG_ALTIVEC
421 if (cpu_has_feature(CPU_FTR_ALTIVEC))
422 msr_all_available |= MSR_VEC;
425 if (cpu_has_feature(CPU_FTR_VSX))
426 msr_all_available |= MSR_VSX;
429 if (cpu_has_feature(CPU_FTR_SPE))
430 msr_all_available |= MSR_SPE;
435 early_initcall(init_msr_all_available);
437 void giveup_all(struct task_struct *tsk)
439 unsigned long usermsr;
441 if (!tsk->thread.regs)
444 check_if_tm_restore_required(tsk);
446 usermsr = tsk->thread.regs->msr;
448 if ((usermsr & msr_all_available) == 0)
451 msr_check_and_set(msr_all_available);
453 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
455 #ifdef CONFIG_PPC_FPU
456 if (usermsr & MSR_FP)
459 #ifdef CONFIG_ALTIVEC
460 if (usermsr & MSR_VEC)
461 __giveup_altivec(tsk);
464 if (usermsr & MSR_SPE)
468 msr_check_and_clear(msr_all_available);
470 EXPORT_SYMBOL(giveup_all);
472 #ifdef CONFIG_PPC_BOOK3S_64
473 #ifdef CONFIG_PPC_FPU
474 static int restore_fp(struct task_struct *tsk)
476 if (tsk->thread.load_fp) {
477 load_fp_state(¤t->thread.fp_state);
478 current->thread.load_fp++;
484 static int restore_fp(struct task_struct *tsk) { return 0; }
485 #endif /* CONFIG_PPC_FPU */
487 #ifdef CONFIG_ALTIVEC
488 #define loadvec(thr) ((thr).load_vec)
489 static int restore_altivec(struct task_struct *tsk)
491 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) {
492 load_vr_state(&tsk->thread.vr_state);
493 tsk->thread.used_vr = 1;
494 tsk->thread.load_vec++;
501 #define loadvec(thr) 0
502 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
503 #endif /* CONFIG_ALTIVEC */
506 static int restore_vsx(struct task_struct *tsk)
508 if (cpu_has_feature(CPU_FTR_VSX)) {
509 tsk->thread.used_vsr = 1;
516 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
517 #endif /* CONFIG_VSX */
520 * The exception exit path calls restore_math() with interrupts hard disabled
521 * but the soft irq state not "reconciled". ftrace code that calls
522 * local_irq_save/restore causes warnings.
524 * Rather than complicate the exit path, just don't trace restore_math. This
525 * could be done by having ftrace entry code check for this un-reconciled
526 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
527 * temporarily fix it up for the duration of the ftrace call.
529 void notrace restore_math(struct pt_regs *regs)
533 if (!MSR_TM_ACTIVE(regs->msr) &&
534 !current->thread.load_fp && !loadvec(current->thread))
538 msr_check_and_set(msr_all_available);
541 * Only reload if the bit is not set in the user MSR, the bit BEING set
542 * indicates that the registers are hot
544 if ((!(msr & MSR_FP)) && restore_fp(current))
545 msr |= MSR_FP | current->thread.fpexc_mode;
547 if ((!(msr & MSR_VEC)) && restore_altivec(current))
550 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
551 restore_vsx(current)) {
555 msr_check_and_clear(msr_all_available);
561 static void save_all(struct task_struct *tsk)
563 unsigned long usermsr;
565 if (!tsk->thread.regs)
568 usermsr = tsk->thread.regs->msr;
570 if ((usermsr & msr_all_available) == 0)
573 msr_check_and_set(msr_all_available);
575 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
577 if (usermsr & MSR_FP)
580 if (usermsr & MSR_VEC)
583 if (usermsr & MSR_SPE)
586 msr_check_and_clear(msr_all_available);
587 thread_pkey_regs_save(&tsk->thread);
590 void flush_all_to_thread(struct task_struct *tsk)
592 if (tsk->thread.regs) {
594 BUG_ON(tsk != current);
596 if (tsk->thread.regs->msr & MSR_SPE)
597 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
604 EXPORT_SYMBOL(flush_all_to_thread);
606 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
607 void do_send_trap(struct pt_regs *regs, unsigned long address,
608 unsigned long error_code, int breakpt)
610 current->thread.trap_nr = TRAP_HWBKPT;
611 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
612 11, SIGSEGV) == NOTIFY_STOP)
615 /* Deliver the signal to userspace */
616 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
617 (void __user *)address);
619 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
620 void do_break (struct pt_regs *regs, unsigned long address,
621 unsigned long error_code)
623 current->thread.trap_nr = TRAP_HWBKPT;
624 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
625 11, SIGSEGV) == NOTIFY_STOP)
628 if (debugger_break_match(regs))
631 /* Deliver the signal to userspace */
632 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address);
634 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
636 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]);
638 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
640 * Set the debug registers back to their default "safe" values.
642 static void set_debug_reg_defaults(struct thread_struct *thread)
644 thread->debug.iac1 = thread->debug.iac2 = 0;
645 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
646 thread->debug.iac3 = thread->debug.iac4 = 0;
648 thread->debug.dac1 = thread->debug.dac2 = 0;
649 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
650 thread->debug.dvc1 = thread->debug.dvc2 = 0;
652 thread->debug.dbcr0 = 0;
655 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
657 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
658 DBCR1_IAC3US | DBCR1_IAC4US;
660 * Force Data Address Compare User/Supervisor bits to be User-only
661 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
663 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
665 thread->debug.dbcr1 = 0;
669 static void prime_debug_regs(struct debug_reg *debug)
672 * We could have inherited MSR_DE from userspace, since
673 * it doesn't get cleared on exception entry. Make sure
674 * MSR_DE is clear before we enable any debug events.
676 mtmsr(mfmsr() & ~MSR_DE);
678 mtspr(SPRN_IAC1, debug->iac1);
679 mtspr(SPRN_IAC2, debug->iac2);
680 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
681 mtspr(SPRN_IAC3, debug->iac3);
682 mtspr(SPRN_IAC4, debug->iac4);
684 mtspr(SPRN_DAC1, debug->dac1);
685 mtspr(SPRN_DAC2, debug->dac2);
686 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
687 mtspr(SPRN_DVC1, debug->dvc1);
688 mtspr(SPRN_DVC2, debug->dvc2);
690 mtspr(SPRN_DBCR0, debug->dbcr0);
691 mtspr(SPRN_DBCR1, debug->dbcr1);
693 mtspr(SPRN_DBCR2, debug->dbcr2);
697 * Unless neither the old or new thread are making use of the
698 * debug registers, set the debug registers from the values
699 * stored in the new thread.
701 void switch_booke_debug_regs(struct debug_reg *new_debug)
703 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
704 || (new_debug->dbcr0 & DBCR0_IDM))
705 prime_debug_regs(new_debug);
707 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
708 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
709 #ifndef CONFIG_HAVE_HW_BREAKPOINT
710 static void set_breakpoint(int i, struct arch_hw_breakpoint *brk)
713 __set_breakpoint(i, brk);
717 static void set_debug_reg_defaults(struct thread_struct *thread)
720 struct arch_hw_breakpoint null_brk = {0};
722 for (i = 0; i < nr_wp_slots(); i++) {
723 thread->hw_brk[i] = null_brk;
724 if (ppc_breakpoint_available())
725 set_breakpoint(i, &thread->hw_brk[i]);
729 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
730 struct arch_hw_breakpoint *b)
732 if (a->address != b->address)
734 if (a->type != b->type)
736 if (a->len != b->len)
738 /* no need to check hw_len. it's calculated from address and len */
742 static void switch_hw_breakpoint(struct task_struct *new)
746 for (i = 0; i < nr_wp_slots(); i++) {
747 if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]),
748 &new->thread.hw_brk[i])))
751 __set_breakpoint(i, &new->thread.hw_brk[i]);
754 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
755 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
757 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
758 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
760 mtspr(SPRN_DAC1, dabr);
761 #ifdef CONFIG_PPC_47x
766 #elif defined(CONFIG_PPC_BOOK3S)
767 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
769 mtspr(SPRN_DABR, dabr);
770 if (cpu_has_feature(CPU_FTR_DABRX))
771 mtspr(SPRN_DABRX, dabrx);
775 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
781 static inline int set_dabr(struct arch_hw_breakpoint *brk)
783 unsigned long dabr, dabrx;
785 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
786 dabrx = ((brk->type >> 3) & 0x7);
789 return ppc_md.set_dabr(dabr, dabrx);
791 return __set_dabr(dabr, dabrx);
794 static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk)
796 unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW |
798 unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN;
799 unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE);
800 unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE);
803 lctrl2 |= LCTRL2_LW0LA_F;
804 else if (end_addr == 0)
805 lctrl2 |= LCTRL2_LW0LA_E;
807 lctrl2 |= LCTRL2_LW0LA_EandF;
809 mtspr(SPRN_LCTRL2, 0);
811 if ((brk->type & HW_BRK_TYPE_RDWR) == 0)
814 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
815 lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO;
816 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
817 lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO;
819 mtspr(SPRN_CMPE, start_addr - 1);
820 mtspr(SPRN_CMPF, end_addr);
821 mtspr(SPRN_LCTRL1, lctrl1);
822 mtspr(SPRN_LCTRL2, lctrl2);
827 void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk)
829 memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk));
834 else if (IS_ENABLED(CONFIG_PPC_8xx))
835 set_breakpoint_8xx(brk);
836 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
840 // Shouldn't happen due to higher level checks
844 /* Check if we have DAWR or DABR hardware */
845 bool ppc_breakpoint_available(void)
848 return true; /* POWER8 DAWR or POWER9 forced DAWR */
849 if (cpu_has_feature(CPU_FTR_ARCH_207S))
850 return false; /* POWER9 with DAWR disabled */
851 /* DABR: Everything but POWER8 and POWER9 */
854 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
856 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
858 static inline bool tm_enabled(struct task_struct *tsk)
860 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
863 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
866 * Use the current MSR TM suspended bit to track if we have
867 * checkpointed state outstanding.
868 * On signal delivery, we'd normally reclaim the checkpointed
869 * state to obtain stack pointer (see:get_tm_stackpointer()).
870 * This will then directly return to userspace without going
871 * through __switch_to(). However, if the stack frame is bad,
872 * we need to exit this thread which calls __switch_to() which
873 * will again attempt to reclaim the already saved tm state.
874 * Hence we need to check that we've not already reclaimed
876 * We do this using the current MSR, rather tracking it in
877 * some specific thread_struct bit, as it has the additional
878 * benefit of checking for a potential TM bad thing exception.
880 if (!MSR_TM_SUSPENDED(mfmsr()))
883 giveup_all(container_of(thr, struct task_struct, thread));
885 tm_reclaim(thr, cause);
888 * If we are in a transaction and FP is off then we can't have
889 * used FP inside that transaction. Hence the checkpointed
890 * state is the same as the live state. We need to copy the
891 * live state to the checkpointed state so that when the
892 * transaction is restored, the checkpointed state is correct
893 * and the aborted transaction sees the correct state. We use
894 * ckpt_regs.msr here as that's what tm_reclaim will use to
895 * determine if it's going to write the checkpointed state or
896 * not. So either this will write the checkpointed registers,
897 * or reclaim will. Similarly for VMX.
899 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
900 memcpy(&thr->ckfp_state, &thr->fp_state,
901 sizeof(struct thread_fp_state));
902 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
903 memcpy(&thr->ckvr_state, &thr->vr_state,
904 sizeof(struct thread_vr_state));
907 void tm_reclaim_current(uint8_t cause)
910 tm_reclaim_thread(¤t->thread, cause);
913 static inline void tm_reclaim_task(struct task_struct *tsk)
915 /* We have to work out if we're switching from/to a task that's in the
916 * middle of a transaction.
918 * In switching we need to maintain a 2nd register state as
919 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
920 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
923 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
925 struct thread_struct *thr = &tsk->thread;
930 if (!MSR_TM_ACTIVE(thr->regs->msr))
931 goto out_and_saveregs;
933 WARN_ON(tm_suspend_disabled);
935 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
936 "ccr=%lx, msr=%lx, trap=%lx)\n",
937 tsk->pid, thr->regs->nip,
938 thr->regs->ccr, thr->regs->msr,
941 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
943 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
947 /* Always save the regs here, even if a transaction's not active.
948 * This context-switches a thread's TM info SPRs. We do it here to
949 * be consistent with the restore path (in recheckpoint) which
950 * cannot happen later in _switch().
955 extern void __tm_recheckpoint(struct thread_struct *thread);
957 void tm_recheckpoint(struct thread_struct *thread)
961 if (!(thread->regs->msr & MSR_TM))
964 /* We really can't be interrupted here as the TEXASR registers can't
965 * change and later in the trecheckpoint code, we have a userspace R1.
966 * So let's hard disable over this region.
968 local_irq_save(flags);
971 /* The TM SPRs are restored here, so that TEXASR.FS can be set
972 * before the trecheckpoint and no explosion occurs.
974 tm_restore_sprs(thread);
976 __tm_recheckpoint(thread);
978 local_irq_restore(flags);
981 static inline void tm_recheckpoint_new_task(struct task_struct *new)
983 if (!cpu_has_feature(CPU_FTR_TM))
986 /* Recheckpoint the registers of the thread we're about to switch to.
988 * If the task was using FP, we non-lazily reload both the original and
989 * the speculative FP register states. This is because the kernel
990 * doesn't see if/when a TM rollback occurs, so if we take an FP
991 * unavailable later, we are unable to determine which set of FP regs
992 * need to be restored.
994 if (!tm_enabled(new))
997 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
998 tm_restore_sprs(&new->thread);
1001 /* Recheckpoint to restore original checkpointed register state. */
1002 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1003 new->pid, new->thread.regs->msr);
1005 tm_recheckpoint(&new->thread);
1008 * The checkpointed state has been restored but the live state has
1009 * not, ensure all the math functionality is turned off to trigger
1010 * restore_math() to reload.
1012 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1014 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1015 "(kernel msr 0x%lx)\n",
1019 static inline void __switch_to_tm(struct task_struct *prev,
1020 struct task_struct *new)
1022 if (cpu_has_feature(CPU_FTR_TM)) {
1023 if (tm_enabled(prev) || tm_enabled(new))
1026 if (tm_enabled(prev)) {
1027 prev->thread.load_tm++;
1028 tm_reclaim_task(prev);
1029 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1030 prev->thread.regs->msr &= ~MSR_TM;
1033 tm_recheckpoint_new_task(new);
1038 * This is called if we are on the way out to userspace and the
1039 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1040 * FP and/or vector state and does so if necessary.
1041 * If userspace is inside a transaction (whether active or
1042 * suspended) and FP/VMX/VSX instructions have ever been enabled
1043 * inside that transaction, then we have to keep them enabled
1044 * and keep the FP/VMX/VSX state loaded while ever the transaction
1045 * continues. The reason is that if we didn't, and subsequently
1046 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1047 * we don't know whether it's the same transaction, and thus we
1048 * don't know which of the checkpointed state and the transactional
1051 void restore_tm_state(struct pt_regs *regs)
1053 unsigned long msr_diff;
1056 * This is the only moment we should clear TIF_RESTORE_TM as
1057 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1058 * again, anything else could lead to an incorrect ckpt_msr being
1059 * saved and therefore incorrect signal contexts.
1061 clear_thread_flag(TIF_RESTORE_TM);
1062 if (!MSR_TM_ACTIVE(regs->msr))
1065 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1066 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1068 /* Ensure that restore_math() will restore */
1069 if (msr_diff & MSR_FP)
1070 current->thread.load_fp = 1;
1071 #ifdef CONFIG_ALTIVEC
1072 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1073 current->thread.load_vec = 1;
1077 regs->msr |= msr_diff;
1081 #define tm_recheckpoint_new_task(new)
1082 #define __switch_to_tm(prev, new)
1083 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1085 static inline void save_sprs(struct thread_struct *t)
1087 #ifdef CONFIG_ALTIVEC
1088 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1089 t->vrsave = mfspr(SPRN_VRSAVE);
1091 #ifdef CONFIG_PPC_BOOK3S_64
1092 if (cpu_has_feature(CPU_FTR_DSCR))
1093 t->dscr = mfspr(SPRN_DSCR);
1095 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1096 t->bescr = mfspr(SPRN_BESCR);
1097 t->ebbhr = mfspr(SPRN_EBBHR);
1098 t->ebbrr = mfspr(SPRN_EBBRR);
1100 t->fscr = mfspr(SPRN_FSCR);
1103 * Note that the TAR is not available for use in the kernel.
1104 * (To provide this, the TAR should be backed up/restored on
1105 * exception entry/exit instead, and be in pt_regs. FIXME,
1106 * this should be in pt_regs anyway (for debug).)
1108 t->tar = mfspr(SPRN_TAR);
1112 thread_pkey_regs_save(t);
1115 static inline void restore_sprs(struct thread_struct *old_thread,
1116 struct thread_struct *new_thread)
1118 #ifdef CONFIG_ALTIVEC
1119 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1120 old_thread->vrsave != new_thread->vrsave)
1121 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1123 #ifdef CONFIG_PPC_BOOK3S_64
1124 if (cpu_has_feature(CPU_FTR_DSCR)) {
1125 u64 dscr = get_paca()->dscr_default;
1126 if (new_thread->dscr_inherit)
1127 dscr = new_thread->dscr;
1129 if (old_thread->dscr != dscr)
1130 mtspr(SPRN_DSCR, dscr);
1133 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1134 if (old_thread->bescr != new_thread->bescr)
1135 mtspr(SPRN_BESCR, new_thread->bescr);
1136 if (old_thread->ebbhr != new_thread->ebbhr)
1137 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1138 if (old_thread->ebbrr != new_thread->ebbrr)
1139 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1141 if (old_thread->fscr != new_thread->fscr)
1142 mtspr(SPRN_FSCR, new_thread->fscr);
1144 if (old_thread->tar != new_thread->tar)
1145 mtspr(SPRN_TAR, new_thread->tar);
1148 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1149 old_thread->tidr != new_thread->tidr)
1150 mtspr(SPRN_TIDR, new_thread->tidr);
1153 thread_pkey_regs_restore(new_thread, old_thread);
1156 struct task_struct *__switch_to(struct task_struct *prev,
1157 struct task_struct *new)
1159 struct thread_struct *new_thread, *old_thread;
1160 struct task_struct *last;
1161 #ifdef CONFIG_PPC_BOOK3S_64
1162 struct ppc64_tlb_batch *batch;
1165 new_thread = &new->thread;
1166 old_thread = ¤t->thread;
1168 WARN_ON(!irqs_disabled());
1170 #ifdef CONFIG_PPC_BOOK3S_64
1171 batch = this_cpu_ptr(&ppc64_tlb_batch);
1172 if (batch->active) {
1173 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1175 __flush_tlb_pending(batch);
1178 #endif /* CONFIG_PPC_BOOK3S_64 */
1180 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1181 switch_booke_debug_regs(&new->thread.debug);
1184 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1187 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1188 switch_hw_breakpoint(new);
1189 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1193 * We need to save SPRs before treclaim/trecheckpoint as these will
1194 * change a number of them.
1196 save_sprs(&prev->thread);
1198 /* Save FPU, Altivec, VSX and SPE state */
1201 __switch_to_tm(prev, new);
1203 if (!radix_enabled()) {
1205 * We can't take a PMU exception inside _switch() since there
1206 * is a window where the kernel stack SLB and the kernel stack
1207 * are out of sync. Hard disable here.
1213 * Call restore_sprs() before calling _switch(). If we move it after
1214 * _switch() then we miss out on calling it for new tasks. The reason
1215 * for this is we manually create a stack frame for new tasks that
1216 * directly returns through ret_from_fork() or
1217 * ret_from_kernel_thread(). See copy_thread() for details.
1219 restore_sprs(old_thread, new_thread);
1221 last = _switch(old_thread, new_thread);
1223 #ifdef CONFIG_PPC_BOOK3S_64
1224 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1225 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1226 batch = this_cpu_ptr(&ppc64_tlb_batch);
1230 if (current->thread.regs) {
1231 restore_math(current->thread.regs);
1234 * The copy-paste buffer can only store into foreign real
1235 * addresses, so unprivileged processes can not see the
1236 * data or use it in any way unless they have foreign real
1237 * mappings. If the new process has the foreign real address
1238 * mappings, we must issue a cp_abort to clear any state and
1239 * prevent snooping, corruption or a covert channel.
1242 atomic_read(¤t->mm->context.vas_windows))
1243 asm volatile(PPC_CP_ABORT);
1245 #endif /* CONFIG_PPC_BOOK3S_64 */
1250 #define NR_INSN_TO_PRINT 16
1252 static void show_instructions(struct pt_regs *regs)
1255 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1257 printk("Instruction dump:");
1259 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1265 #if !defined(CONFIG_BOOKE)
1266 /* If executing with the IMMU off, adjust pc rather
1267 * than print XXXXXXXX.
1269 if (!(regs->msr & MSR_IR))
1270 pc = (unsigned long)phys_to_virt(pc);
1273 if (!__kernel_text_address(pc) ||
1274 probe_kernel_address((const void *)pc, instr)) {
1275 pr_cont("XXXXXXXX ");
1277 if (regs->nip == pc)
1278 pr_cont("<%08x> ", instr);
1280 pr_cont("%08x ", instr);
1289 void show_user_instructions(struct pt_regs *regs)
1292 int n = NR_INSN_TO_PRINT;
1294 char buf[96]; /* enough for 8 times 9 + 2 chars */
1296 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1298 seq_buf_init(&s, buf, sizeof(buf));
1305 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1308 if (probe_user_read(&instr, (void __user *)pc, sizeof(instr))) {
1309 seq_buf_printf(&s, "XXXXXXXX ");
1312 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1315 if (!seq_buf_has_overflowed(&s))
1316 pr_info("%s[%d]: code: %s\n", current->comm,
1317 current->pid, s.buffer);
1326 static struct regbit msr_bits[] = {
1327 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1349 #ifndef CONFIG_BOOKE
1356 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1360 for (; bits->bit; ++bits)
1361 if (val & bits->bit) {
1362 pr_cont("%s%s", s, bits->name);
1367 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1368 static struct regbit msr_tm_bits[] = {
1375 static void print_tm_bits(unsigned long val)
1378 * This only prints something if at least one of the TM bit is set.
1379 * Inside the TM[], the output means:
1380 * E: Enabled (bit 32)
1381 * S: Suspended (bit 33)
1382 * T: Transactional (bit 34)
1384 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1386 print_bits(val, msr_tm_bits, "");
1391 static void print_tm_bits(unsigned long val) {}
1394 static void print_msr_bits(unsigned long val)
1397 print_bits(val, msr_bits, ",");
1403 #define REG "%016lx"
1404 #define REGS_PER_LINE 4
1405 #define LAST_VOLATILE 13
1408 #define REGS_PER_LINE 8
1409 #define LAST_VOLATILE 12
1412 void show_regs(struct pt_regs * regs)
1416 show_regs_print_info(KERN_DEFAULT);
1418 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1419 regs->nip, regs->link, regs->ctr);
1420 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1421 regs, regs->trap, print_tainted(), init_utsname()->release);
1422 printk("MSR: "REG" ", regs->msr);
1423 print_msr_bits(regs->msr);
1424 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1426 if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
1427 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1428 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1429 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1430 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1432 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1435 pr_cont("IRQMASK: %lx ", regs->softe);
1437 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1438 if (MSR_TM_ACTIVE(regs->msr))
1439 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1442 for (i = 0; i < 32; i++) {
1443 if ((i % REGS_PER_LINE) == 0)
1444 pr_cont("\nGPR%02d: ", i);
1445 pr_cont(REG " ", regs->gpr[i]);
1446 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1450 #ifdef CONFIG_KALLSYMS
1452 * Lookup NIP late so we have the best change of getting the
1453 * above info out without failing
1455 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1456 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1458 show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT);
1459 if (!user_mode(regs))
1460 show_instructions(regs);
1463 void flush_thread(void)
1465 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1466 flush_ptrace_hw_breakpoint(current);
1467 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1468 set_debug_reg_defaults(¤t->thread);
1469 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1472 #ifdef CONFIG_PPC_BOOK3S_64
1473 void arch_setup_new_exec(void)
1475 if (radix_enabled())
1477 hash__setup_new_exec();
1483 * Assign a TIDR (thread ID) for task @t and set it in the thread
1484 * structure. For now, we only support setting TIDR for 'current' task.
1486 * Since the TID value is a truncated form of it PID, it is possible
1487 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1488 * that 2 threads share the same TID and are waiting, one of the following
1489 * cases will happen:
1491 * 1. The correct thread is running, the wrong thread is not
1492 * In this situation, the correct thread is woken and proceeds to pass it's
1495 * 2. Neither threads are running
1496 * In this situation, neither thread will be woken. When scheduled, the waiting
1497 * threads will execute either a wait, which will return immediately, followed
1498 * by a condition check, which will pass for the correct thread and fail
1499 * for the wrong thread, or they will execute the condition check immediately.
1501 * 3. The wrong thread is running, the correct thread is not
1502 * The wrong thread will be woken, but will fail it's condition check and
1503 * re-execute wait. The correct thread, when scheduled, will execute either
1504 * it's condition check (which will pass), or wait, which returns immediately
1505 * when called the first time after the thread is scheduled, followed by it's
1506 * condition check (which will pass).
1508 * 4. Both threads are running
1509 * Both threads will be woken. The wrong thread will fail it's condition check
1510 * and execute another wait, while the correct thread will pass it's condition
1513 * @t: the task to set the thread ID for
1515 int set_thread_tidr(struct task_struct *t)
1517 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1526 t->thread.tidr = (u16)task_pid_nr(t);
1527 mtspr(SPRN_TIDR, t->thread.tidr);
1531 EXPORT_SYMBOL_GPL(set_thread_tidr);
1533 #endif /* CONFIG_PPC64 */
1536 release_thread(struct task_struct *t)
1541 * this gets called so that we can store coprocessor state into memory and
1542 * copy the current task into the new thread.
1544 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1546 flush_all_to_thread(src);
1548 * Flush TM state out so we can copy it. __switch_to_tm() does this
1549 * flush but it removes the checkpointed state from the current CPU and
1550 * transitions the CPU out of TM mode. Hence we need to call
1551 * tm_recheckpoint_new_task() (on the same task) to restore the
1552 * checkpointed state back and the TM mode.
1554 * Can't pass dst because it isn't ready. Doesn't matter, passing
1555 * dst is only important for __switch_to()
1557 __switch_to_tm(src, src);
1561 clear_task_ebb(dst);
1566 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1568 #ifdef CONFIG_PPC_BOOK3S_64
1569 unsigned long sp_vsid;
1570 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1572 if (radix_enabled())
1575 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1576 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1577 << SLB_VSID_SHIFT_1T;
1579 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1581 sp_vsid |= SLB_VSID_KERNEL | llp;
1582 p->thread.ksp_vsid = sp_vsid;
1591 * Copy architecture-specific thread state
1593 int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
1594 unsigned long kthread_arg, struct task_struct *p,
1597 struct pt_regs *childregs, *kregs;
1598 extern void ret_from_fork(void);
1599 extern void ret_from_kernel_thread(void);
1601 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1602 struct thread_info *ti = task_thread_info(p);
1603 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1607 klp_init_thread_info(p);
1609 /* Copy registers */
1610 sp -= sizeof(struct pt_regs);
1611 childregs = (struct pt_regs *) sp;
1612 if (unlikely(p->flags & PF_KTHREAD)) {
1614 memset(childregs, 0, sizeof(struct pt_regs));
1615 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1618 childregs->gpr[14] = ppc_function_entry((void *)usp);
1620 clear_tsk_thread_flag(p, TIF_32BIT);
1621 childregs->softe = IRQS_ENABLED;
1623 childregs->gpr[15] = kthread_arg;
1624 p->thread.regs = NULL; /* no user register state */
1625 ti->flags |= _TIF_RESTOREALL;
1626 f = ret_from_kernel_thread;
1629 struct pt_regs *regs = current_pt_regs();
1630 CHECK_FULL_REGS(regs);
1633 childregs->gpr[1] = usp;
1634 p->thread.regs = childregs;
1635 childregs->gpr[3] = 0; /* Result from fork() */
1636 if (clone_flags & CLONE_SETTLS) {
1637 if (!is_32bit_task())
1638 childregs->gpr[13] = tls;
1640 childregs->gpr[2] = tls;
1645 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1646 sp -= STACK_FRAME_OVERHEAD;
1649 * The way this works is that at some point in the future
1650 * some task will call _switch to switch to the new task.
1651 * That will pop off the stack frame created below and start
1652 * the new task running at ret_from_fork. The new task will
1653 * do some house keeping and then return from the fork or clone
1654 * system call, using the stack frame created above.
1656 ((unsigned long *)sp)[0] = 0;
1657 sp -= sizeof(struct pt_regs);
1658 kregs = (struct pt_regs *) sp;
1659 sp -= STACK_FRAME_OVERHEAD;
1662 p->thread.ksp_limit = (unsigned long)end_of_stack(p);
1664 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1665 for (i = 0; i < nr_wp_slots(); i++)
1666 p->thread.ptrace_bps[i] = NULL;
1669 p->thread.fp_save_area = NULL;
1670 #ifdef CONFIG_ALTIVEC
1671 p->thread.vr_save_area = NULL;
1674 setup_ksp_vsid(p, sp);
1677 if (cpu_has_feature(CPU_FTR_DSCR)) {
1678 p->thread.dscr_inherit = current->thread.dscr_inherit;
1679 p->thread.dscr = mfspr(SPRN_DSCR);
1681 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1682 childregs->ppr = DEFAULT_PPR;
1686 kregs->nip = ppc_function_entry(f);
1690 void preload_new_slb_context(unsigned long start, unsigned long sp);
1693 * Set up a thread for executing a new program
1695 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1698 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1700 #ifdef CONFIG_PPC_BOOK3S_64
1701 if (!radix_enabled())
1702 preload_new_slb_context(start, sp);
1707 * If we exec out of a kernel thread then thread.regs will not be
1710 if (!current->thread.regs) {
1711 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1712 current->thread.regs = regs - 1;
1715 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1717 * Clear any transactional state, we're exec()ing. The cause is
1718 * not important as there will never be a recheckpoint so it's not
1721 if (MSR_TM_SUSPENDED(mfmsr()))
1722 tm_reclaim_current(0);
1725 memset(regs->gpr, 0, sizeof(regs->gpr));
1733 * We have just cleared all the nonvolatile GPRs, so make
1734 * FULL_REGS(regs) return true. This is necessary to allow
1735 * ptrace to examine the thread immediately after exec.
1737 SET_FULL_REGS(regs);
1742 regs->msr = MSR_USER;
1744 if (!is_32bit_task()) {
1745 unsigned long entry;
1747 if (is_elf2_task()) {
1748 /* Look ma, no function descriptors! */
1753 * The latest iteration of the ABI requires that when
1754 * calling a function (at its global entry point),
1755 * the caller must ensure r12 holds the entry point
1756 * address (so that the function can quickly
1757 * establish addressability).
1759 regs->gpr[12] = start;
1760 /* Make sure that's restored on entry to userspace. */
1761 set_thread_flag(TIF_RESTOREALL);
1765 /* start is a relocated pointer to the function
1766 * descriptor for the elf _start routine. The first
1767 * entry in the function descriptor is the entry
1768 * address of _start and the second entry is the TOC
1769 * value we need to use.
1771 __get_user(entry, (unsigned long __user *)start);
1772 __get_user(toc, (unsigned long __user *)start+1);
1774 /* Check whether the e_entry function descriptor entries
1775 * need to be relocated before we can use them.
1777 if (load_addr != 0) {
1784 regs->msr = MSR_USER64;
1788 regs->msr = MSR_USER32;
1792 current->thread.used_vsr = 0;
1794 current->thread.load_slb = 0;
1795 current->thread.load_fp = 0;
1796 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1797 current->thread.fp_save_area = NULL;
1798 #ifdef CONFIG_ALTIVEC
1799 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1800 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1801 current->thread.vr_save_area = NULL;
1802 current->thread.vrsave = 0;
1803 current->thread.used_vr = 0;
1804 current->thread.load_vec = 0;
1805 #endif /* CONFIG_ALTIVEC */
1807 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1808 current->thread.acc = 0;
1809 current->thread.spefscr = 0;
1810 current->thread.used_spe = 0;
1811 #endif /* CONFIG_SPE */
1812 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1813 current->thread.tm_tfhar = 0;
1814 current->thread.tm_texasr = 0;
1815 current->thread.tm_tfiar = 0;
1816 current->thread.load_tm = 0;
1817 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1819 thread_pkey_regs_init(¤t->thread);
1821 EXPORT_SYMBOL(start_thread);
1823 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1824 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1826 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1828 struct pt_regs *regs = tsk->thread.regs;
1830 /* This is a bit hairy. If we are an SPE enabled processor
1831 * (have embedded fp) we store the IEEE exception enable flags in
1832 * fpexc_mode. fpexc_mode is also used for setting FP exception
1833 * mode (asyn, precise, disabled) for 'Classic' FP. */
1834 if (val & PR_FP_EXC_SW_ENABLE) {
1836 if (cpu_has_feature(CPU_FTR_SPE)) {
1838 * When the sticky exception bits are set
1839 * directly by userspace, it must call prctl
1840 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1841 * in the existing prctl settings) or
1842 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1843 * the bits being set). <fenv.h> functions
1844 * saving and restoring the whole
1845 * floating-point environment need to do so
1846 * anyway to restore the prctl settings from
1847 * the saved environment.
1849 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1850 tsk->thread.fpexc_mode = val &
1851 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1861 /* on a CONFIG_SPE this does not hurt us. The bits that
1862 * __pack_fe01 use do not overlap with bits used for
1863 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1864 * on CONFIG_SPE implementations are reserved so writing to
1865 * them does not change anything */
1866 if (val > PR_FP_EXC_PRECISE)
1868 tsk->thread.fpexc_mode = __pack_fe01(val);
1869 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1870 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1871 | tsk->thread.fpexc_mode;
1875 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1879 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1881 if (cpu_has_feature(CPU_FTR_SPE)) {
1883 * When the sticky exception bits are set
1884 * directly by userspace, it must call prctl
1885 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1886 * in the existing prctl settings) or
1887 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1888 * the bits being set). <fenv.h> functions
1889 * saving and restoring the whole
1890 * floating-point environment need to do so
1891 * anyway to restore the prctl settings from
1892 * the saved environment.
1894 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1895 val = tsk->thread.fpexc_mode;
1902 val = __unpack_fe01(tsk->thread.fpexc_mode);
1903 return put_user(val, (unsigned int __user *) adr);
1906 int set_endian(struct task_struct *tsk, unsigned int val)
1908 struct pt_regs *regs = tsk->thread.regs;
1910 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1911 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1917 if (val == PR_ENDIAN_BIG)
1918 regs->msr &= ~MSR_LE;
1919 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1920 regs->msr |= MSR_LE;
1927 int get_endian(struct task_struct *tsk, unsigned long adr)
1929 struct pt_regs *regs = tsk->thread.regs;
1932 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1933 !cpu_has_feature(CPU_FTR_REAL_LE))
1939 if (regs->msr & MSR_LE) {
1940 if (cpu_has_feature(CPU_FTR_REAL_LE))
1941 val = PR_ENDIAN_LITTLE;
1943 val = PR_ENDIAN_PPC_LITTLE;
1945 val = PR_ENDIAN_BIG;
1947 return put_user(val, (unsigned int __user *)adr);
1950 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1952 tsk->thread.align_ctl = val;
1956 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1958 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1961 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1962 unsigned long nbytes)
1964 unsigned long stack_page;
1965 unsigned long cpu = task_cpu(p);
1967 stack_page = (unsigned long)hardirq_ctx[cpu];
1968 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1971 stack_page = (unsigned long)softirq_ctx[cpu];
1972 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1978 static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p,
1979 unsigned long nbytes)
1982 unsigned long stack_page;
1983 unsigned long cpu = task_cpu(p);
1985 stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE;
1986 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1989 # ifdef CONFIG_PPC_BOOK3S_64
1990 stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE;
1991 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1994 stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE;
1995 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2004 int validate_sp(unsigned long sp, struct task_struct *p,
2005 unsigned long nbytes)
2007 unsigned long stack_page = (unsigned long)task_stack_page(p);
2009 if (sp < THREAD_SIZE)
2012 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2015 if (valid_irq_stack(sp, p, nbytes))
2018 return valid_emergency_stack(sp, p, nbytes);
2021 EXPORT_SYMBOL(validate_sp);
2023 static unsigned long __get_wchan(struct task_struct *p)
2025 unsigned long ip, sp;
2028 if (!p || p == current || p->state == TASK_RUNNING)
2032 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2036 sp = *(unsigned long *)sp;
2037 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2038 p->state == TASK_RUNNING)
2041 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2042 if (!in_sched_functions(ip))
2045 } while (count++ < 16);
2049 unsigned long get_wchan(struct task_struct *p)
2053 if (!try_get_task_stack(p))
2056 ret = __get_wchan(p);
2063 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2065 void show_stack(struct task_struct *tsk, unsigned long *stack,
2068 unsigned long sp, ip, lr, newsp;
2071 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2072 unsigned long ret_addr;
2079 if (!try_get_task_stack(tsk))
2082 sp = (unsigned long) stack;
2085 sp = current_stack_frame();
2087 sp = tsk->thread.ksp;
2091 printk("%sCall Trace:\n", loglvl);
2093 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2096 stack = (unsigned long *) sp;
2098 ip = stack[STACK_FRAME_LR_SAVE];
2099 if (!firstframe || ip != lr) {
2100 printk("%s["REG"] ["REG"] %pS",
2101 loglvl, sp, ip, (void *)ip);
2102 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2103 ret_addr = ftrace_graph_ret_addr(current,
2104 &ftrace_idx, ip, stack);
2106 pr_cont(" (%pS)", (void *)ret_addr);
2109 pr_cont(" (unreliable)");
2115 * See if this is an exception frame.
2116 * We look for the "regshere" marker in the current frame.
2118 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2119 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2120 struct pt_regs *regs = (struct pt_regs *)
2121 (sp + STACK_FRAME_OVERHEAD);
2123 printk("%s--- interrupt: %lx at %pS\n LR = %pS\n",
2125 (void *)regs->nip, (void *)lr);
2130 } while (count++ < kstack_depth_to_print);
2132 put_task_stack(tsk);
2136 /* Called with hard IRQs off */
2137 void notrace __ppc64_runlatch_on(void)
2139 struct thread_info *ti = current_thread_info();
2141 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2143 * Least significant bit (RUN) is the only writable bit of
2144 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2145 * earliest ISA where this is the case, but it's convenient.
2147 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2152 * Some architectures (e.g., Cell) have writable fields other
2153 * than RUN, so do the read-modify-write.
2155 ctrl = mfspr(SPRN_CTRLF);
2156 ctrl |= CTRL_RUNLATCH;
2157 mtspr(SPRN_CTRLT, ctrl);
2160 ti->local_flags |= _TLF_RUNLATCH;
2163 /* Called with hard IRQs off */
2164 void notrace __ppc64_runlatch_off(void)
2166 struct thread_info *ti = current_thread_info();
2168 ti->local_flags &= ~_TLF_RUNLATCH;
2170 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2171 mtspr(SPRN_CTRLT, 0);
2175 ctrl = mfspr(SPRN_CTRLF);
2176 ctrl &= ~CTRL_RUNLATCH;
2177 mtspr(SPRN_CTRLT, ctrl);
2180 #endif /* CONFIG_PPC64 */
2182 unsigned long arch_align_stack(unsigned long sp)
2184 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2185 sp -= get_random_int() & ~PAGE_MASK;
2189 static inline unsigned long brk_rnd(void)
2191 unsigned long rnd = 0;
2193 /* 8MB for 32bit, 1GB for 64bit */
2194 if (is_32bit_task())
2195 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2197 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2199 return rnd << PAGE_SHIFT;
2202 unsigned long arch_randomize_brk(struct mm_struct *mm)
2204 unsigned long base = mm->brk;
2207 #ifdef CONFIG_PPC_BOOK3S_64
2209 * If we are using 1TB segments and we are allowed to randomise
2210 * the heap, we can put it above 1TB so it is backed by a 1TB
2211 * segment. Otherwise the heap will be in the bottom 1TB
2212 * which always uses 256MB segments and this may result in a
2213 * performance penalty. We don't need to worry about radix. For
2214 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2216 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2217 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2220 ret = PAGE_ALIGN(base + brk_rnd());