1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/random.h>
38 #include <linux/hw_breakpoint.h>
39 #include <linux/uaccess.h>
40 #include <linux/elf-randomize.h>
41 #include <linux/pkeys.h>
42 #include <linux/seq_buf.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
57 #include <asm/hw_irq.h>
59 #include <asm/code-patching.h>
61 #include <asm/livepatch.h>
62 #include <asm/cpu_has_feature.h>
63 #include <asm/asm-prototypes.h>
64 #include <asm/stacktrace.h>
65 #include <asm/hw_breakpoint.h>
67 #include <linux/kprobes.h>
68 #include <linux/kdebug.h>
70 /* Transactional Memory debug */
72 #define TM_DEBUG(x...) printk(KERN_INFO x)
74 #define TM_DEBUG(x...) do { } while(0)
77 extern unsigned long _get_SP(void);
79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
81 * Are we running in "Suspend disabled" mode? If so we have to block any
82 * sigreturn that would get us into suspended state, and we also warn in some
83 * other paths that we should never reach with suspend disabled.
85 bool tm_suspend_disabled __ro_after_init = false;
87 static void check_if_tm_restore_required(struct task_struct *tsk)
90 * If we are saving the current thread's registers, and the
91 * thread is in a transactional state, set the TIF_RESTORE_TM
92 * bit so that we know to restore the registers before
93 * returning to userspace.
95 if (tsk == current && tsk->thread.regs &&
96 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
97 !test_thread_flag(TIF_RESTORE_TM)) {
98 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
99 set_thread_flag(TIF_RESTORE_TM);
104 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
105 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
107 bool strict_msr_control;
108 EXPORT_SYMBOL(strict_msr_control);
110 static int __init enable_strict_msr_control(char *str)
112 strict_msr_control = true;
113 pr_info("Enabling strict facility control\n");
117 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
119 /* notrace because it's called by restore_math */
120 unsigned long notrace msr_check_and_set(unsigned long bits)
122 unsigned long oldmsr = mfmsr();
123 unsigned long newmsr;
125 newmsr = oldmsr | bits;
128 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
132 if (oldmsr != newmsr)
137 EXPORT_SYMBOL_GPL(msr_check_and_set);
139 /* notrace because it's called by restore_math */
140 void notrace __msr_check_and_clear(unsigned long bits)
142 unsigned long oldmsr = mfmsr();
143 unsigned long newmsr;
145 newmsr = oldmsr & ~bits;
148 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
152 if (oldmsr != newmsr)
155 EXPORT_SYMBOL(__msr_check_and_clear);
157 #ifdef CONFIG_PPC_FPU
158 static void __giveup_fpu(struct task_struct *tsk)
163 msr = tsk->thread.regs->msr;
164 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
166 if (cpu_has_feature(CPU_FTR_VSX))
169 tsk->thread.regs->msr = msr;
172 void giveup_fpu(struct task_struct *tsk)
174 check_if_tm_restore_required(tsk);
176 msr_check_and_set(MSR_FP);
178 msr_check_and_clear(MSR_FP);
180 EXPORT_SYMBOL(giveup_fpu);
183 * Make sure the floating-point register state in the
184 * the thread_struct is up to date for task tsk.
186 void flush_fp_to_thread(struct task_struct *tsk)
188 if (tsk->thread.regs) {
190 * We need to disable preemption here because if we didn't,
191 * another process could get scheduled after the regs->msr
192 * test but before we have finished saving the FP registers
193 * to the thread_struct. That process could take over the
194 * FPU, and then when we get scheduled again we would store
195 * bogus values for the remaining FP registers.
198 if (tsk->thread.regs->msr & MSR_FP) {
200 * This should only ever be called for current or
201 * for a stopped child process. Since we save away
202 * the FP register state on context switch,
203 * there is something wrong if a stopped child appears
204 * to still have its FP state in the CPU registers.
206 BUG_ON(tsk != current);
212 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
214 void enable_kernel_fp(void)
216 unsigned long cpumsr;
218 WARN_ON(preemptible());
220 cpumsr = msr_check_and_set(MSR_FP);
222 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
223 check_if_tm_restore_required(current);
225 * If a thread has already been reclaimed then the
226 * checkpointed registers are on the CPU but have definitely
227 * been saved by the reclaim code. Don't need to and *cannot*
228 * giveup as this would save to the 'live' structure not the
229 * checkpointed structure.
231 if (!MSR_TM_ACTIVE(cpumsr) &&
232 MSR_TM_ACTIVE(current->thread.regs->msr))
234 __giveup_fpu(current);
237 EXPORT_SYMBOL(enable_kernel_fp);
238 #endif /* CONFIG_PPC_FPU */
240 #ifdef CONFIG_ALTIVEC
241 static void __giveup_altivec(struct task_struct *tsk)
246 msr = tsk->thread.regs->msr;
249 if (cpu_has_feature(CPU_FTR_VSX))
252 tsk->thread.regs->msr = msr;
255 void giveup_altivec(struct task_struct *tsk)
257 check_if_tm_restore_required(tsk);
259 msr_check_and_set(MSR_VEC);
260 __giveup_altivec(tsk);
261 msr_check_and_clear(MSR_VEC);
263 EXPORT_SYMBOL(giveup_altivec);
265 void enable_kernel_altivec(void)
267 unsigned long cpumsr;
269 WARN_ON(preemptible());
271 cpumsr = msr_check_and_set(MSR_VEC);
273 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
274 check_if_tm_restore_required(current);
276 * If a thread has already been reclaimed then the
277 * checkpointed registers are on the CPU but have definitely
278 * been saved by the reclaim code. Don't need to and *cannot*
279 * giveup as this would save to the 'live' structure not the
280 * checkpointed structure.
282 if (!MSR_TM_ACTIVE(cpumsr) &&
283 MSR_TM_ACTIVE(current->thread.regs->msr))
285 __giveup_altivec(current);
288 EXPORT_SYMBOL(enable_kernel_altivec);
291 * Make sure the VMX/Altivec register state in the
292 * the thread_struct is up to date for task tsk.
294 void flush_altivec_to_thread(struct task_struct *tsk)
296 if (tsk->thread.regs) {
298 if (tsk->thread.regs->msr & MSR_VEC) {
299 BUG_ON(tsk != current);
305 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
306 #endif /* CONFIG_ALTIVEC */
309 static void __giveup_vsx(struct task_struct *tsk)
311 unsigned long msr = tsk->thread.regs->msr;
314 * We should never be ssetting MSR_VSX without also setting
317 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
319 /* __giveup_fpu will clear MSR_VSX */
323 __giveup_altivec(tsk);
326 static void giveup_vsx(struct task_struct *tsk)
328 check_if_tm_restore_required(tsk);
330 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
332 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
335 void enable_kernel_vsx(void)
337 unsigned long cpumsr;
339 WARN_ON(preemptible());
341 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
343 if (current->thread.regs &&
344 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
345 check_if_tm_restore_required(current);
347 * If a thread has already been reclaimed then the
348 * checkpointed registers are on the CPU but have definitely
349 * been saved by the reclaim code. Don't need to and *cannot*
350 * giveup as this would save to the 'live' structure not the
351 * checkpointed structure.
353 if (!MSR_TM_ACTIVE(cpumsr) &&
354 MSR_TM_ACTIVE(current->thread.regs->msr))
356 __giveup_vsx(current);
359 EXPORT_SYMBOL(enable_kernel_vsx);
361 void flush_vsx_to_thread(struct task_struct *tsk)
363 if (tsk->thread.regs) {
365 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
366 BUG_ON(tsk != current);
372 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
373 #endif /* CONFIG_VSX */
376 void giveup_spe(struct task_struct *tsk)
378 check_if_tm_restore_required(tsk);
380 msr_check_and_set(MSR_SPE);
382 msr_check_and_clear(MSR_SPE);
384 EXPORT_SYMBOL(giveup_spe);
386 void enable_kernel_spe(void)
388 WARN_ON(preemptible());
390 msr_check_and_set(MSR_SPE);
392 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
393 check_if_tm_restore_required(current);
394 __giveup_spe(current);
397 EXPORT_SYMBOL(enable_kernel_spe);
399 void flush_spe_to_thread(struct task_struct *tsk)
401 if (tsk->thread.regs) {
403 if (tsk->thread.regs->msr & MSR_SPE) {
404 BUG_ON(tsk != current);
405 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
411 #endif /* CONFIG_SPE */
413 static unsigned long msr_all_available;
415 static int __init init_msr_all_available(void)
417 #ifdef CONFIG_PPC_FPU
418 msr_all_available |= MSR_FP;
420 #ifdef CONFIG_ALTIVEC
421 if (cpu_has_feature(CPU_FTR_ALTIVEC))
422 msr_all_available |= MSR_VEC;
425 if (cpu_has_feature(CPU_FTR_VSX))
426 msr_all_available |= MSR_VSX;
429 if (cpu_has_feature(CPU_FTR_SPE))
430 msr_all_available |= MSR_SPE;
435 early_initcall(init_msr_all_available);
437 void giveup_all(struct task_struct *tsk)
439 unsigned long usermsr;
441 if (!tsk->thread.regs)
444 check_if_tm_restore_required(tsk);
446 usermsr = tsk->thread.regs->msr;
448 if ((usermsr & msr_all_available) == 0)
451 msr_check_and_set(msr_all_available);
453 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
455 #ifdef CONFIG_PPC_FPU
456 if (usermsr & MSR_FP)
459 #ifdef CONFIG_ALTIVEC
460 if (usermsr & MSR_VEC)
461 __giveup_altivec(tsk);
464 if (usermsr & MSR_SPE)
468 msr_check_and_clear(msr_all_available);
470 EXPORT_SYMBOL(giveup_all);
472 #ifdef CONFIG_PPC_BOOK3S_64
473 #ifdef CONFIG_PPC_FPU
474 static int restore_fp(struct task_struct *tsk)
476 if (tsk->thread.load_fp) {
477 load_fp_state(¤t->thread.fp_state);
478 current->thread.load_fp++;
484 static int restore_fp(struct task_struct *tsk) { return 0; }
485 #endif /* CONFIG_PPC_FPU */
487 #ifdef CONFIG_ALTIVEC
488 #define loadvec(thr) ((thr).load_vec)
489 static int restore_altivec(struct task_struct *tsk)
491 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) {
492 load_vr_state(&tsk->thread.vr_state);
493 tsk->thread.used_vr = 1;
494 tsk->thread.load_vec++;
501 #define loadvec(thr) 0
502 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
503 #endif /* CONFIG_ALTIVEC */
506 static int restore_vsx(struct task_struct *tsk)
508 if (cpu_has_feature(CPU_FTR_VSX)) {
509 tsk->thread.used_vsr = 1;
516 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
517 #endif /* CONFIG_VSX */
520 * The exception exit path calls restore_math() with interrupts hard disabled
521 * but the soft irq state not "reconciled". ftrace code that calls
522 * local_irq_save/restore causes warnings.
524 * Rather than complicate the exit path, just don't trace restore_math. This
525 * could be done by having ftrace entry code check for this un-reconciled
526 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
527 * temporarily fix it up for the duration of the ftrace call.
529 void notrace restore_math(struct pt_regs *regs)
533 if (!current->thread.load_fp && !loadvec(current->thread))
537 msr_check_and_set(msr_all_available);
540 * Only reload if the bit is not set in the user MSR, the bit BEING set
541 * indicates that the registers are hot
543 if ((!(msr & MSR_FP)) && restore_fp(current))
544 msr |= MSR_FP | current->thread.fpexc_mode;
546 if ((!(msr & MSR_VEC)) && restore_altivec(current))
549 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
550 restore_vsx(current)) {
554 msr_check_and_clear(msr_all_available);
560 static void save_all(struct task_struct *tsk)
562 unsigned long usermsr;
564 if (!tsk->thread.regs)
567 usermsr = tsk->thread.regs->msr;
569 if ((usermsr & msr_all_available) == 0)
572 msr_check_and_set(msr_all_available);
574 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
576 if (usermsr & MSR_FP)
579 if (usermsr & MSR_VEC)
582 if (usermsr & MSR_SPE)
585 msr_check_and_clear(msr_all_available);
586 thread_pkey_regs_save(&tsk->thread);
589 void flush_all_to_thread(struct task_struct *tsk)
591 if (tsk->thread.regs) {
593 BUG_ON(tsk != current);
595 if (tsk->thread.regs->msr & MSR_SPE)
596 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
603 EXPORT_SYMBOL(flush_all_to_thread);
605 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
606 void do_send_trap(struct pt_regs *regs, unsigned long address,
607 unsigned long error_code, int breakpt)
609 current->thread.trap_nr = TRAP_HWBKPT;
610 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
611 11, SIGSEGV) == NOTIFY_STOP)
614 /* Deliver the signal to userspace */
615 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
616 (void __user *)address);
618 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
619 void do_break (struct pt_regs *regs, unsigned long address,
620 unsigned long error_code)
622 current->thread.trap_nr = TRAP_HWBKPT;
623 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
624 11, SIGSEGV) == NOTIFY_STOP)
627 if (debugger_break_match(regs))
630 /* Deliver the signal to userspace */
631 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address);
633 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
635 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]);
637 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
639 * Set the debug registers back to their default "safe" values.
641 static void set_debug_reg_defaults(struct thread_struct *thread)
643 thread->debug.iac1 = thread->debug.iac2 = 0;
644 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
645 thread->debug.iac3 = thread->debug.iac4 = 0;
647 thread->debug.dac1 = thread->debug.dac2 = 0;
648 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
649 thread->debug.dvc1 = thread->debug.dvc2 = 0;
651 thread->debug.dbcr0 = 0;
654 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
656 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
657 DBCR1_IAC3US | DBCR1_IAC4US;
659 * Force Data Address Compare User/Supervisor bits to be User-only
660 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
662 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
664 thread->debug.dbcr1 = 0;
668 static void prime_debug_regs(struct debug_reg *debug)
671 * We could have inherited MSR_DE from userspace, since
672 * it doesn't get cleared on exception entry. Make sure
673 * MSR_DE is clear before we enable any debug events.
675 mtmsr(mfmsr() & ~MSR_DE);
677 mtspr(SPRN_IAC1, debug->iac1);
678 mtspr(SPRN_IAC2, debug->iac2);
679 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
680 mtspr(SPRN_IAC3, debug->iac3);
681 mtspr(SPRN_IAC4, debug->iac4);
683 mtspr(SPRN_DAC1, debug->dac1);
684 mtspr(SPRN_DAC2, debug->dac2);
685 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
686 mtspr(SPRN_DVC1, debug->dvc1);
687 mtspr(SPRN_DVC2, debug->dvc2);
689 mtspr(SPRN_DBCR0, debug->dbcr0);
690 mtspr(SPRN_DBCR1, debug->dbcr1);
692 mtspr(SPRN_DBCR2, debug->dbcr2);
696 * Unless neither the old or new thread are making use of the
697 * debug registers, set the debug registers from the values
698 * stored in the new thread.
700 void switch_booke_debug_regs(struct debug_reg *new_debug)
702 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
703 || (new_debug->dbcr0 & DBCR0_IDM))
704 prime_debug_regs(new_debug);
706 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
707 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
708 #ifndef CONFIG_HAVE_HW_BREAKPOINT
709 static void set_breakpoint(int i, struct arch_hw_breakpoint *brk)
712 __set_breakpoint(i, brk);
716 static void set_debug_reg_defaults(struct thread_struct *thread)
719 struct arch_hw_breakpoint null_brk = {0};
721 for (i = 0; i < nr_wp_slots(); i++) {
722 thread->hw_brk[i] = null_brk;
723 if (ppc_breakpoint_available())
724 set_breakpoint(i, &thread->hw_brk[i]);
728 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
729 struct arch_hw_breakpoint *b)
731 if (a->address != b->address)
733 if (a->type != b->type)
735 if (a->len != b->len)
737 /* no need to check hw_len. it's calculated from address and len */
741 static void switch_hw_breakpoint(struct task_struct *new)
745 for (i = 0; i < nr_wp_slots(); i++) {
746 if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]),
747 &new->thread.hw_brk[i])))
750 __set_breakpoint(i, &new->thread.hw_brk[i]);
753 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
754 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
756 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
757 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
759 mtspr(SPRN_DAC1, dabr);
760 #ifdef CONFIG_PPC_47x
765 #elif defined(CONFIG_PPC_BOOK3S)
766 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
768 mtspr(SPRN_DABR, dabr);
769 if (cpu_has_feature(CPU_FTR_DABRX))
770 mtspr(SPRN_DABRX, dabrx);
774 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
780 static inline int set_dabr(struct arch_hw_breakpoint *brk)
782 unsigned long dabr, dabrx;
784 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
785 dabrx = ((brk->type >> 3) & 0x7);
788 return ppc_md.set_dabr(dabr, dabrx);
790 return __set_dabr(dabr, dabrx);
793 static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk)
795 unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW |
797 unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN;
798 unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE);
799 unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE);
802 lctrl2 |= LCTRL2_LW0LA_F;
803 else if (end_addr == 0)
804 lctrl2 |= LCTRL2_LW0LA_E;
806 lctrl2 |= LCTRL2_LW0LA_EandF;
808 mtspr(SPRN_LCTRL2, 0);
810 if ((brk->type & HW_BRK_TYPE_RDWR) == 0)
813 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
814 lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO;
815 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
816 lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO;
818 mtspr(SPRN_CMPE, start_addr - 1);
819 mtspr(SPRN_CMPF, end_addr);
820 mtspr(SPRN_LCTRL1, lctrl1);
821 mtspr(SPRN_LCTRL2, lctrl2);
826 void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk)
828 memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk));
833 else if (IS_ENABLED(CONFIG_PPC_8xx))
834 set_breakpoint_8xx(brk);
835 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
839 // Shouldn't happen due to higher level checks
843 /* Check if we have DAWR or DABR hardware */
844 bool ppc_breakpoint_available(void)
847 return true; /* POWER8 DAWR or POWER9 forced DAWR */
848 if (cpu_has_feature(CPU_FTR_ARCH_207S))
849 return false; /* POWER9 with DAWR disabled */
850 /* DABR: Everything but POWER8 and POWER9 */
853 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
855 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
857 static inline bool tm_enabled(struct task_struct *tsk)
859 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
862 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
865 * Use the current MSR TM suspended bit to track if we have
866 * checkpointed state outstanding.
867 * On signal delivery, we'd normally reclaim the checkpointed
868 * state to obtain stack pointer (see:get_tm_stackpointer()).
869 * This will then directly return to userspace without going
870 * through __switch_to(). However, if the stack frame is bad,
871 * we need to exit this thread which calls __switch_to() which
872 * will again attempt to reclaim the already saved tm state.
873 * Hence we need to check that we've not already reclaimed
875 * We do this using the current MSR, rather tracking it in
876 * some specific thread_struct bit, as it has the additional
877 * benefit of checking for a potential TM bad thing exception.
879 if (!MSR_TM_SUSPENDED(mfmsr()))
882 giveup_all(container_of(thr, struct task_struct, thread));
884 tm_reclaim(thr, cause);
887 * If we are in a transaction and FP is off then we can't have
888 * used FP inside that transaction. Hence the checkpointed
889 * state is the same as the live state. We need to copy the
890 * live state to the checkpointed state so that when the
891 * transaction is restored, the checkpointed state is correct
892 * and the aborted transaction sees the correct state. We use
893 * ckpt_regs.msr here as that's what tm_reclaim will use to
894 * determine if it's going to write the checkpointed state or
895 * not. So either this will write the checkpointed registers,
896 * or reclaim will. Similarly for VMX.
898 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
899 memcpy(&thr->ckfp_state, &thr->fp_state,
900 sizeof(struct thread_fp_state));
901 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
902 memcpy(&thr->ckvr_state, &thr->vr_state,
903 sizeof(struct thread_vr_state));
906 void tm_reclaim_current(uint8_t cause)
909 tm_reclaim_thread(¤t->thread, cause);
912 static inline void tm_reclaim_task(struct task_struct *tsk)
914 /* We have to work out if we're switching from/to a task that's in the
915 * middle of a transaction.
917 * In switching we need to maintain a 2nd register state as
918 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
919 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
922 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
924 struct thread_struct *thr = &tsk->thread;
929 if (!MSR_TM_ACTIVE(thr->regs->msr))
930 goto out_and_saveregs;
932 WARN_ON(tm_suspend_disabled);
934 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
935 "ccr=%lx, msr=%lx, trap=%lx)\n",
936 tsk->pid, thr->regs->nip,
937 thr->regs->ccr, thr->regs->msr,
940 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
942 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
946 /* Always save the regs here, even if a transaction's not active.
947 * This context-switches a thread's TM info SPRs. We do it here to
948 * be consistent with the restore path (in recheckpoint) which
949 * cannot happen later in _switch().
954 extern void __tm_recheckpoint(struct thread_struct *thread);
956 void tm_recheckpoint(struct thread_struct *thread)
960 if (!(thread->regs->msr & MSR_TM))
963 /* We really can't be interrupted here as the TEXASR registers can't
964 * change and later in the trecheckpoint code, we have a userspace R1.
965 * So let's hard disable over this region.
967 local_irq_save(flags);
970 /* The TM SPRs are restored here, so that TEXASR.FS can be set
971 * before the trecheckpoint and no explosion occurs.
973 tm_restore_sprs(thread);
975 __tm_recheckpoint(thread);
977 local_irq_restore(flags);
980 static inline void tm_recheckpoint_new_task(struct task_struct *new)
982 if (!cpu_has_feature(CPU_FTR_TM))
985 /* Recheckpoint the registers of the thread we're about to switch to.
987 * If the task was using FP, we non-lazily reload both the original and
988 * the speculative FP register states. This is because the kernel
989 * doesn't see if/when a TM rollback occurs, so if we take an FP
990 * unavailable later, we are unable to determine which set of FP regs
991 * need to be restored.
993 if (!tm_enabled(new))
996 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
997 tm_restore_sprs(&new->thread);
1000 /* Recheckpoint to restore original checkpointed register state. */
1001 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1002 new->pid, new->thread.regs->msr);
1004 tm_recheckpoint(&new->thread);
1007 * The checkpointed state has been restored but the live state has
1008 * not, ensure all the math functionality is turned off to trigger
1009 * restore_math() to reload.
1011 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1013 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1014 "(kernel msr 0x%lx)\n",
1018 static inline void __switch_to_tm(struct task_struct *prev,
1019 struct task_struct *new)
1021 if (cpu_has_feature(CPU_FTR_TM)) {
1022 if (tm_enabled(prev) || tm_enabled(new))
1025 if (tm_enabled(prev)) {
1026 prev->thread.load_tm++;
1027 tm_reclaim_task(prev);
1028 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1029 prev->thread.regs->msr &= ~MSR_TM;
1032 tm_recheckpoint_new_task(new);
1037 * This is called if we are on the way out to userspace and the
1038 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1039 * FP and/or vector state and does so if necessary.
1040 * If userspace is inside a transaction (whether active or
1041 * suspended) and FP/VMX/VSX instructions have ever been enabled
1042 * inside that transaction, then we have to keep them enabled
1043 * and keep the FP/VMX/VSX state loaded while ever the transaction
1044 * continues. The reason is that if we didn't, and subsequently
1045 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1046 * we don't know whether it's the same transaction, and thus we
1047 * don't know which of the checkpointed state and the transactional
1050 void restore_tm_state(struct pt_regs *regs)
1052 unsigned long msr_diff;
1055 * This is the only moment we should clear TIF_RESTORE_TM as
1056 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1057 * again, anything else could lead to an incorrect ckpt_msr being
1058 * saved and therefore incorrect signal contexts.
1060 clear_thread_flag(TIF_RESTORE_TM);
1061 if (!MSR_TM_ACTIVE(regs->msr))
1064 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1065 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1067 /* Ensure that restore_math() will restore */
1068 if (msr_diff & MSR_FP)
1069 current->thread.load_fp = 1;
1070 #ifdef CONFIG_ALTIVEC
1071 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1072 current->thread.load_vec = 1;
1076 regs->msr |= msr_diff;
1080 #define tm_recheckpoint_new_task(new)
1081 #define __switch_to_tm(prev, new)
1082 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1084 static inline void save_sprs(struct thread_struct *t)
1086 #ifdef CONFIG_ALTIVEC
1087 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1088 t->vrsave = mfspr(SPRN_VRSAVE);
1090 #ifdef CONFIG_PPC_BOOK3S_64
1091 if (cpu_has_feature(CPU_FTR_DSCR))
1092 t->dscr = mfspr(SPRN_DSCR);
1094 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1095 t->bescr = mfspr(SPRN_BESCR);
1096 t->ebbhr = mfspr(SPRN_EBBHR);
1097 t->ebbrr = mfspr(SPRN_EBBRR);
1099 t->fscr = mfspr(SPRN_FSCR);
1102 * Note that the TAR is not available for use in the kernel.
1103 * (To provide this, the TAR should be backed up/restored on
1104 * exception entry/exit instead, and be in pt_regs. FIXME,
1105 * this should be in pt_regs anyway (for debug).)
1107 t->tar = mfspr(SPRN_TAR);
1111 thread_pkey_regs_save(t);
1114 static inline void restore_sprs(struct thread_struct *old_thread,
1115 struct thread_struct *new_thread)
1117 #ifdef CONFIG_ALTIVEC
1118 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1119 old_thread->vrsave != new_thread->vrsave)
1120 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1122 #ifdef CONFIG_PPC_BOOK3S_64
1123 if (cpu_has_feature(CPU_FTR_DSCR)) {
1124 u64 dscr = get_paca()->dscr_default;
1125 if (new_thread->dscr_inherit)
1126 dscr = new_thread->dscr;
1128 if (old_thread->dscr != dscr)
1129 mtspr(SPRN_DSCR, dscr);
1132 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1133 if (old_thread->bescr != new_thread->bescr)
1134 mtspr(SPRN_BESCR, new_thread->bescr);
1135 if (old_thread->ebbhr != new_thread->ebbhr)
1136 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1137 if (old_thread->ebbrr != new_thread->ebbrr)
1138 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1140 if (old_thread->fscr != new_thread->fscr)
1141 mtspr(SPRN_FSCR, new_thread->fscr);
1143 if (old_thread->tar != new_thread->tar)
1144 mtspr(SPRN_TAR, new_thread->tar);
1147 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1148 old_thread->tidr != new_thread->tidr)
1149 mtspr(SPRN_TIDR, new_thread->tidr);
1152 thread_pkey_regs_restore(new_thread, old_thread);
1155 struct task_struct *__switch_to(struct task_struct *prev,
1156 struct task_struct *new)
1158 struct thread_struct *new_thread, *old_thread;
1159 struct task_struct *last;
1160 #ifdef CONFIG_PPC_BOOK3S_64
1161 struct ppc64_tlb_batch *batch;
1164 new_thread = &new->thread;
1165 old_thread = ¤t->thread;
1167 WARN_ON(!irqs_disabled());
1169 #ifdef CONFIG_PPC_BOOK3S_64
1170 batch = this_cpu_ptr(&ppc64_tlb_batch);
1171 if (batch->active) {
1172 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1174 __flush_tlb_pending(batch);
1177 #endif /* CONFIG_PPC_BOOK3S_64 */
1179 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1180 switch_booke_debug_regs(&new->thread.debug);
1183 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1186 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1187 switch_hw_breakpoint(new);
1188 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1192 * We need to save SPRs before treclaim/trecheckpoint as these will
1193 * change a number of them.
1195 save_sprs(&prev->thread);
1197 /* Save FPU, Altivec, VSX and SPE state */
1200 __switch_to_tm(prev, new);
1202 if (!radix_enabled()) {
1204 * We can't take a PMU exception inside _switch() since there
1205 * is a window where the kernel stack SLB and the kernel stack
1206 * are out of sync. Hard disable here.
1212 * Call restore_sprs() before calling _switch(). If we move it after
1213 * _switch() then we miss out on calling it for new tasks. The reason
1214 * for this is we manually create a stack frame for new tasks that
1215 * directly returns through ret_from_fork() or
1216 * ret_from_kernel_thread(). See copy_thread() for details.
1218 restore_sprs(old_thread, new_thread);
1220 last = _switch(old_thread, new_thread);
1222 #ifdef CONFIG_PPC_BOOK3S_64
1223 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1224 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1225 batch = this_cpu_ptr(&ppc64_tlb_batch);
1229 if (current->thread.regs) {
1230 restore_math(current->thread.regs);
1233 * The copy-paste buffer can only store into foreign real
1234 * addresses, so unprivileged processes can not see the
1235 * data or use it in any way unless they have foreign real
1236 * mappings. If the new process has the foreign real address
1237 * mappings, we must issue a cp_abort to clear any state and
1238 * prevent snooping, corruption or a covert channel.
1241 atomic_read(¤t->mm->context.vas_windows))
1242 asm volatile(PPC_CP_ABORT);
1244 #endif /* CONFIG_PPC_BOOK3S_64 */
1249 #define NR_INSN_TO_PRINT 16
1251 static void show_instructions(struct pt_regs *regs)
1254 unsigned long nip = regs->nip;
1255 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1257 printk("Instruction dump:");
1260 * If we were executing with the MMU off for instructions, adjust pc
1261 * rather than printing XXXXXXXX.
1263 if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) {
1264 pc = (unsigned long)phys_to_virt(pc);
1265 nip = (unsigned long)phys_to_virt(regs->nip);
1268 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1274 if (!__kernel_text_address(pc) ||
1275 get_kernel_nofault(instr, (const void *)pc)) {
1276 pr_cont("XXXXXXXX ");
1279 pr_cont("<%08x> ", instr);
1281 pr_cont("%08x ", instr);
1290 void show_user_instructions(struct pt_regs *regs)
1293 int n = NR_INSN_TO_PRINT;
1295 char buf[96]; /* enough for 8 times 9 + 2 chars */
1297 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1299 seq_buf_init(&s, buf, sizeof(buf));
1306 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1309 if (copy_from_user_nofault(&instr, (void __user *)pc,
1311 seq_buf_printf(&s, "XXXXXXXX ");
1314 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1317 if (!seq_buf_has_overflowed(&s))
1318 pr_info("%s[%d]: code: %s\n", current->comm,
1319 current->pid, s.buffer);
1328 static struct regbit msr_bits[] = {
1329 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1351 #ifndef CONFIG_BOOKE
1358 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1362 for (; bits->bit; ++bits)
1363 if (val & bits->bit) {
1364 pr_cont("%s%s", s, bits->name);
1369 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1370 static struct regbit msr_tm_bits[] = {
1377 static void print_tm_bits(unsigned long val)
1380 * This only prints something if at least one of the TM bit is set.
1381 * Inside the TM[], the output means:
1382 * E: Enabled (bit 32)
1383 * S: Suspended (bit 33)
1384 * T: Transactional (bit 34)
1386 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1388 print_bits(val, msr_tm_bits, "");
1393 static void print_tm_bits(unsigned long val) {}
1396 static void print_msr_bits(unsigned long val)
1399 print_bits(val, msr_bits, ",");
1405 #define REG "%016lx"
1406 #define REGS_PER_LINE 4
1407 #define LAST_VOLATILE 13
1410 #define REGS_PER_LINE 8
1411 #define LAST_VOLATILE 12
1414 void show_regs(struct pt_regs * regs)
1418 show_regs_print_info(KERN_DEFAULT);
1420 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1421 regs->nip, regs->link, regs->ctr);
1422 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1423 regs, regs->trap, print_tainted(), init_utsname()->release);
1424 printk("MSR: "REG" ", regs->msr);
1425 print_msr_bits(regs->msr);
1426 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1428 if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
1429 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1430 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1431 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1432 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1434 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1437 pr_cont("IRQMASK: %lx ", regs->softe);
1439 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1440 if (MSR_TM_ACTIVE(regs->msr))
1441 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1444 for (i = 0; i < 32; i++) {
1445 if ((i % REGS_PER_LINE) == 0)
1446 pr_cont("\nGPR%02d: ", i);
1447 pr_cont(REG " ", regs->gpr[i]);
1448 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1452 #ifdef CONFIG_KALLSYMS
1454 * Lookup NIP late so we have the best change of getting the
1455 * above info out without failing
1457 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1458 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1460 show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT);
1461 if (!user_mode(regs))
1462 show_instructions(regs);
1465 void flush_thread(void)
1467 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1468 flush_ptrace_hw_breakpoint(current);
1469 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1470 set_debug_reg_defaults(¤t->thread);
1471 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1474 #ifdef CONFIG_PPC_BOOK3S_64
1475 void arch_setup_new_exec(void)
1477 if (radix_enabled())
1479 hash__setup_new_exec();
1485 * Assign a TIDR (thread ID) for task @t and set it in the thread
1486 * structure. For now, we only support setting TIDR for 'current' task.
1488 * Since the TID value is a truncated form of it PID, it is possible
1489 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1490 * that 2 threads share the same TID and are waiting, one of the following
1491 * cases will happen:
1493 * 1. The correct thread is running, the wrong thread is not
1494 * In this situation, the correct thread is woken and proceeds to pass it's
1497 * 2. Neither threads are running
1498 * In this situation, neither thread will be woken. When scheduled, the waiting
1499 * threads will execute either a wait, which will return immediately, followed
1500 * by a condition check, which will pass for the correct thread and fail
1501 * for the wrong thread, or they will execute the condition check immediately.
1503 * 3. The wrong thread is running, the correct thread is not
1504 * The wrong thread will be woken, but will fail it's condition check and
1505 * re-execute wait. The correct thread, when scheduled, will execute either
1506 * it's condition check (which will pass), or wait, which returns immediately
1507 * when called the first time after the thread is scheduled, followed by it's
1508 * condition check (which will pass).
1510 * 4. Both threads are running
1511 * Both threads will be woken. The wrong thread will fail it's condition check
1512 * and execute another wait, while the correct thread will pass it's condition
1515 * @t: the task to set the thread ID for
1517 int set_thread_tidr(struct task_struct *t)
1519 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1528 t->thread.tidr = (u16)task_pid_nr(t);
1529 mtspr(SPRN_TIDR, t->thread.tidr);
1533 EXPORT_SYMBOL_GPL(set_thread_tidr);
1535 #endif /* CONFIG_PPC64 */
1538 release_thread(struct task_struct *t)
1543 * this gets called so that we can store coprocessor state into memory and
1544 * copy the current task into the new thread.
1546 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1548 flush_all_to_thread(src);
1550 * Flush TM state out so we can copy it. __switch_to_tm() does this
1551 * flush but it removes the checkpointed state from the current CPU and
1552 * transitions the CPU out of TM mode. Hence we need to call
1553 * tm_recheckpoint_new_task() (on the same task) to restore the
1554 * checkpointed state back and the TM mode.
1556 * Can't pass dst because it isn't ready. Doesn't matter, passing
1557 * dst is only important for __switch_to()
1559 __switch_to_tm(src, src);
1563 clear_task_ebb(dst);
1568 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1570 #ifdef CONFIG_PPC_BOOK3S_64
1571 unsigned long sp_vsid;
1572 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1574 if (radix_enabled())
1577 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1578 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1579 << SLB_VSID_SHIFT_1T;
1581 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1583 sp_vsid |= SLB_VSID_KERNEL | llp;
1584 p->thread.ksp_vsid = sp_vsid;
1593 * Copy architecture-specific thread state
1595 int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
1596 unsigned long kthread_arg, struct task_struct *p,
1599 struct pt_regs *childregs, *kregs;
1600 extern void ret_from_fork(void);
1601 extern void ret_from_kernel_thread(void);
1603 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1604 struct thread_info *ti = task_thread_info(p);
1605 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1609 klp_init_thread_info(p);
1611 /* Copy registers */
1612 sp -= sizeof(struct pt_regs);
1613 childregs = (struct pt_regs *) sp;
1614 if (unlikely(p->flags & PF_KTHREAD)) {
1616 memset(childregs, 0, sizeof(struct pt_regs));
1617 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1620 childregs->gpr[14] = ppc_function_entry((void *)usp);
1622 clear_tsk_thread_flag(p, TIF_32BIT);
1623 childregs->softe = IRQS_ENABLED;
1625 childregs->gpr[15] = kthread_arg;
1626 p->thread.regs = NULL; /* no user register state */
1627 ti->flags |= _TIF_RESTOREALL;
1628 f = ret_from_kernel_thread;
1631 struct pt_regs *regs = current_pt_regs();
1632 CHECK_FULL_REGS(regs);
1635 childregs->gpr[1] = usp;
1636 p->thread.regs = childregs;
1637 childregs->gpr[3] = 0; /* Result from fork() */
1638 if (clone_flags & CLONE_SETTLS) {
1639 if (!is_32bit_task())
1640 childregs->gpr[13] = tls;
1642 childregs->gpr[2] = tls;
1647 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1648 sp -= STACK_FRAME_OVERHEAD;
1651 * The way this works is that at some point in the future
1652 * some task will call _switch to switch to the new task.
1653 * That will pop off the stack frame created below and start
1654 * the new task running at ret_from_fork. The new task will
1655 * do some house keeping and then return from the fork or clone
1656 * system call, using the stack frame created above.
1658 ((unsigned long *)sp)[0] = 0;
1659 sp -= sizeof(struct pt_regs);
1660 kregs = (struct pt_regs *) sp;
1661 sp -= STACK_FRAME_OVERHEAD;
1664 p->thread.ksp_limit = (unsigned long)end_of_stack(p);
1666 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1667 for (i = 0; i < nr_wp_slots(); i++)
1668 p->thread.ptrace_bps[i] = NULL;
1671 p->thread.fp_save_area = NULL;
1672 #ifdef CONFIG_ALTIVEC
1673 p->thread.vr_save_area = NULL;
1676 setup_ksp_vsid(p, sp);
1679 if (cpu_has_feature(CPU_FTR_DSCR)) {
1680 p->thread.dscr_inherit = current->thread.dscr_inherit;
1681 p->thread.dscr = mfspr(SPRN_DSCR);
1683 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1684 childregs->ppr = DEFAULT_PPR;
1688 kregs->nip = ppc_function_entry(f);
1692 void preload_new_slb_context(unsigned long start, unsigned long sp);
1695 * Set up a thread for executing a new program
1697 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1700 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1702 #ifdef CONFIG_PPC_BOOK3S_64
1703 if (!radix_enabled())
1704 preload_new_slb_context(start, sp);
1709 * If we exec out of a kernel thread then thread.regs will not be
1712 if (!current->thread.regs) {
1713 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1714 current->thread.regs = regs - 1;
1717 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1719 * Clear any transactional state, we're exec()ing. The cause is
1720 * not important as there will never be a recheckpoint so it's not
1723 if (MSR_TM_SUSPENDED(mfmsr()))
1724 tm_reclaim_current(0);
1727 memset(regs->gpr, 0, sizeof(regs->gpr));
1735 * We have just cleared all the nonvolatile GPRs, so make
1736 * FULL_REGS(regs) return true. This is necessary to allow
1737 * ptrace to examine the thread immediately after exec.
1739 SET_FULL_REGS(regs);
1744 regs->msr = MSR_USER;
1746 if (!is_32bit_task()) {
1747 unsigned long entry;
1749 if (is_elf2_task()) {
1750 /* Look ma, no function descriptors! */
1755 * The latest iteration of the ABI requires that when
1756 * calling a function (at its global entry point),
1757 * the caller must ensure r12 holds the entry point
1758 * address (so that the function can quickly
1759 * establish addressability).
1761 regs->gpr[12] = start;
1762 /* Make sure that's restored on entry to userspace. */
1763 set_thread_flag(TIF_RESTOREALL);
1767 /* start is a relocated pointer to the function
1768 * descriptor for the elf _start routine. The first
1769 * entry in the function descriptor is the entry
1770 * address of _start and the second entry is the TOC
1771 * value we need to use.
1773 __get_user(entry, (unsigned long __user *)start);
1774 __get_user(toc, (unsigned long __user *)start+1);
1776 /* Check whether the e_entry function descriptor entries
1777 * need to be relocated before we can use them.
1779 if (load_addr != 0) {
1786 regs->msr = MSR_USER64;
1790 regs->msr = MSR_USER32;
1794 current->thread.used_vsr = 0;
1796 current->thread.load_slb = 0;
1797 current->thread.load_fp = 0;
1798 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1799 current->thread.fp_save_area = NULL;
1800 #ifdef CONFIG_ALTIVEC
1801 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1802 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1803 current->thread.vr_save_area = NULL;
1804 current->thread.vrsave = 0;
1805 current->thread.used_vr = 0;
1806 current->thread.load_vec = 0;
1807 #endif /* CONFIG_ALTIVEC */
1809 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1810 current->thread.acc = 0;
1811 current->thread.spefscr = 0;
1812 current->thread.used_spe = 0;
1813 #endif /* CONFIG_SPE */
1814 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1815 current->thread.tm_tfhar = 0;
1816 current->thread.tm_texasr = 0;
1817 current->thread.tm_tfiar = 0;
1818 current->thread.load_tm = 0;
1819 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1821 thread_pkey_regs_init(¤t->thread);
1823 EXPORT_SYMBOL(start_thread);
1825 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1826 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1828 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1830 struct pt_regs *regs = tsk->thread.regs;
1832 /* This is a bit hairy. If we are an SPE enabled processor
1833 * (have embedded fp) we store the IEEE exception enable flags in
1834 * fpexc_mode. fpexc_mode is also used for setting FP exception
1835 * mode (asyn, precise, disabled) for 'Classic' FP. */
1836 if (val & PR_FP_EXC_SW_ENABLE) {
1838 if (cpu_has_feature(CPU_FTR_SPE)) {
1840 * When the sticky exception bits are set
1841 * directly by userspace, it must call prctl
1842 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1843 * in the existing prctl settings) or
1844 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1845 * the bits being set). <fenv.h> functions
1846 * saving and restoring the whole
1847 * floating-point environment need to do so
1848 * anyway to restore the prctl settings from
1849 * the saved environment.
1851 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1852 tsk->thread.fpexc_mode = val &
1853 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1863 /* on a CONFIG_SPE this does not hurt us. The bits that
1864 * __pack_fe01 use do not overlap with bits used for
1865 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1866 * on CONFIG_SPE implementations are reserved so writing to
1867 * them does not change anything */
1868 if (val > PR_FP_EXC_PRECISE)
1870 tsk->thread.fpexc_mode = __pack_fe01(val);
1871 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1872 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1873 | tsk->thread.fpexc_mode;
1877 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1881 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1883 if (cpu_has_feature(CPU_FTR_SPE)) {
1885 * When the sticky exception bits are set
1886 * directly by userspace, it must call prctl
1887 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1888 * in the existing prctl settings) or
1889 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1890 * the bits being set). <fenv.h> functions
1891 * saving and restoring the whole
1892 * floating-point environment need to do so
1893 * anyway to restore the prctl settings from
1894 * the saved environment.
1896 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1897 val = tsk->thread.fpexc_mode;
1904 val = __unpack_fe01(tsk->thread.fpexc_mode);
1905 return put_user(val, (unsigned int __user *) adr);
1908 int set_endian(struct task_struct *tsk, unsigned int val)
1910 struct pt_regs *regs = tsk->thread.regs;
1912 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1913 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1919 if (val == PR_ENDIAN_BIG)
1920 regs->msr &= ~MSR_LE;
1921 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1922 regs->msr |= MSR_LE;
1929 int get_endian(struct task_struct *tsk, unsigned long adr)
1931 struct pt_regs *regs = tsk->thread.regs;
1934 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1935 !cpu_has_feature(CPU_FTR_REAL_LE))
1941 if (regs->msr & MSR_LE) {
1942 if (cpu_has_feature(CPU_FTR_REAL_LE))
1943 val = PR_ENDIAN_LITTLE;
1945 val = PR_ENDIAN_PPC_LITTLE;
1947 val = PR_ENDIAN_BIG;
1949 return put_user(val, (unsigned int __user *)adr);
1952 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1954 tsk->thread.align_ctl = val;
1958 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1960 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1963 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1964 unsigned long nbytes)
1966 unsigned long stack_page;
1967 unsigned long cpu = task_cpu(p);
1969 stack_page = (unsigned long)hardirq_ctx[cpu];
1970 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1973 stack_page = (unsigned long)softirq_ctx[cpu];
1974 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1980 static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p,
1981 unsigned long nbytes)
1984 unsigned long stack_page;
1985 unsigned long cpu = task_cpu(p);
1987 stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE;
1988 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1991 # ifdef CONFIG_PPC_BOOK3S_64
1992 stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE;
1993 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1996 stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE;
1997 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2006 int validate_sp(unsigned long sp, struct task_struct *p,
2007 unsigned long nbytes)
2009 unsigned long stack_page = (unsigned long)task_stack_page(p);
2011 if (sp < THREAD_SIZE)
2014 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2017 if (valid_irq_stack(sp, p, nbytes))
2020 return valid_emergency_stack(sp, p, nbytes);
2023 EXPORT_SYMBOL(validate_sp);
2025 static unsigned long __get_wchan(struct task_struct *p)
2027 unsigned long ip, sp;
2030 if (!p || p == current || p->state == TASK_RUNNING)
2034 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2038 sp = *(unsigned long *)sp;
2039 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2040 p->state == TASK_RUNNING)
2043 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2044 if (!in_sched_functions(ip))
2047 } while (count++ < 16);
2051 unsigned long get_wchan(struct task_struct *p)
2055 if (!try_get_task_stack(p))
2058 ret = __get_wchan(p);
2065 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2067 void show_stack(struct task_struct *tsk, unsigned long *stack,
2070 unsigned long sp, ip, lr, newsp;
2073 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2074 unsigned long ret_addr;
2081 if (!try_get_task_stack(tsk))
2084 sp = (unsigned long) stack;
2087 sp = current_stack_frame();
2089 sp = tsk->thread.ksp;
2093 printk("%sCall Trace:\n", loglvl);
2095 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2098 stack = (unsigned long *) sp;
2100 ip = stack[STACK_FRAME_LR_SAVE];
2101 if (!firstframe || ip != lr) {
2102 printk("%s["REG"] ["REG"] %pS",
2103 loglvl, sp, ip, (void *)ip);
2104 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2105 ret_addr = ftrace_graph_ret_addr(current,
2106 &ftrace_idx, ip, stack);
2108 pr_cont(" (%pS)", (void *)ret_addr);
2111 pr_cont(" (unreliable)");
2117 * See if this is an exception frame.
2118 * We look for the "regshere" marker in the current frame.
2120 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2121 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2122 struct pt_regs *regs = (struct pt_regs *)
2123 (sp + STACK_FRAME_OVERHEAD);
2125 printk("%s--- interrupt: %lx at %pS\n LR = %pS\n",
2127 (void *)regs->nip, (void *)lr);
2132 } while (count++ < kstack_depth_to_print);
2134 put_task_stack(tsk);
2138 /* Called with hard IRQs off */
2139 void notrace __ppc64_runlatch_on(void)
2141 struct thread_info *ti = current_thread_info();
2143 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2145 * Least significant bit (RUN) is the only writable bit of
2146 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2147 * earliest ISA where this is the case, but it's convenient.
2149 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2154 * Some architectures (e.g., Cell) have writable fields other
2155 * than RUN, so do the read-modify-write.
2157 ctrl = mfspr(SPRN_CTRLF);
2158 ctrl |= CTRL_RUNLATCH;
2159 mtspr(SPRN_CTRLT, ctrl);
2162 ti->local_flags |= _TLF_RUNLATCH;
2165 /* Called with hard IRQs off */
2166 void notrace __ppc64_runlatch_off(void)
2168 struct thread_info *ti = current_thread_info();
2170 ti->local_flags &= ~_TLF_RUNLATCH;
2172 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2173 mtspr(SPRN_CTRLT, 0);
2177 ctrl = mfspr(SPRN_CTRLF);
2178 ctrl &= ~CTRL_RUNLATCH;
2179 mtspr(SPRN_CTRLT, ctrl);
2182 #endif /* CONFIG_PPC64 */
2184 unsigned long arch_align_stack(unsigned long sp)
2186 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2187 sp -= get_random_int() & ~PAGE_MASK;
2191 static inline unsigned long brk_rnd(void)
2193 unsigned long rnd = 0;
2195 /* 8MB for 32bit, 1GB for 64bit */
2196 if (is_32bit_task())
2197 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2199 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2201 return rnd << PAGE_SHIFT;
2204 unsigned long arch_randomize_brk(struct mm_struct *mm)
2206 unsigned long base = mm->brk;
2209 #ifdef CONFIG_PPC_BOOK3S_64
2211 * If we are using 1TB segments and we are allowed to randomise
2212 * the heap, we can put it above 1TB so it is backed by a 1TB
2213 * segment. Otherwise the heap will be in the bottom 1TB
2214 * which always uses 256MB segments and this may result in a
2215 * performance penalty. We don't need to worry about radix. For
2216 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2218 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2219 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2222 ret = PAGE_ALIGN(base + brk_rnd());