1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from arch/i386/kernel/irq.c
4 * Copyright (C) 1992 Linus Torvalds
5 * Adapted from arch/i386 by Gary Thomas
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Updated and modified by Cort Dougan <cort@fsmlabs.com>
8 * Copyright (C) 1996-2001 Cort Dougan
9 * Adapted for Power Macintosh by Paul Mackerras
10 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
12 * This file contains the code used by various IRQ handling routines:
13 * asking for different IRQ's should be done through these routines
14 * instead of just grabbing them. Thus setups with different IRQ numbers
15 * shouldn't result in any weird surprises, and installing new handlers
18 * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the
19 * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit
20 * mask register (of which only 16 are defined), hence the weird shifting
21 * and complement of the cached_irq_mask. I want to be able to stuff
22 * this right into the SIU SMASK register.
23 * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx
24 * to reduce code space and undefined function references.
29 #include <linux/export.h>
30 #include <linux/threads.h>
31 #include <linux/kernel_stat.h>
32 #include <linux/signal.h>
33 #include <linux/sched.h>
34 #include <linux/ptrace.h>
35 #include <linux/ioport.h>
36 #include <linux/interrupt.h>
37 #include <linux/timex.h>
38 #include <linux/init.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
41 #include <linux/irq.h>
42 #include <linux/seq_file.h>
43 #include <linux/cpumask.h>
44 #include <linux/profile.h>
45 #include <linux/bitops.h>
46 #include <linux/list.h>
47 #include <linux/radix-tree.h>
48 #include <linux/mutex.h>
49 #include <linux/pci.h>
50 #include <linux/debugfs.h>
52 #include <linux/of_irq.h>
53 #include <linux/vmalloc.h>
54 #include <linux/pgtable.h>
56 #include <linux/uaccess.h>
57 #include <asm/interrupt.h>
60 #include <asm/cache.h>
62 #include <asm/ptrace.h>
63 #include <asm/machdep.h>
66 #include <asm/livepatch.h>
67 #include <asm/asm-prototypes.h>
68 #include <asm/hw_irq.h>
69 #include <asm/softirq_stack.h>
73 #include <asm/firmware.h>
74 #include <asm/lv1call.h>
75 #include <asm/dbell.h>
77 #define CREATE_TRACE_POINTS
78 #include <asm/trace.h>
79 #include <asm/cpu_has_feature.h>
81 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
82 EXPORT_PER_CPU_SYMBOL(irq_stat);
85 atomic_t ppc_n_lost_interrupts;
88 extern int tau_initialized;
89 u32 tau_interrupts(unsigned long cpu);
91 #endif /* CONFIG_PPC32 */
95 int distribute_irqs = 1;
97 static inline notrace unsigned long get_irq_happened(void)
99 unsigned long happened;
101 __asm__ __volatile__("lbz %0,%1(13)"
102 : "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened)));
107 #ifdef CONFIG_PPC_BOOK3E
109 /* This is called whenever we are re-enabling interrupts
110 * and returns either 0 (nothing to do) or 500/900/280 if
111 * there's an EE, DEC or DBELL to generate.
113 * This is called in two contexts: From arch_local_irq_restore()
114 * before soft-enabling interrupts, and from the exception exit
115 * path when returning from an interrupt from a soft-disabled to
116 * a soft enabled context. In both case we have interrupts hard
119 * We take care of only clearing the bits we handled in the
120 * PACA irq_happened field since we can only re-emit one at a
121 * time and we don't want to "lose" one.
123 notrace unsigned int __check_irq_replay(void)
126 * We use local_paca rather than get_paca() to avoid all
127 * the debug_smp_processor_id() business in this low level
130 unsigned char happened = local_paca->irq_happened;
133 * We are responding to the next interrupt, so interrupt-off
134 * latencies should be reset here.
137 trace_hardirqs_off();
139 if (happened & PACA_IRQ_DEC) {
140 local_paca->irq_happened &= ~PACA_IRQ_DEC;
144 if (happened & PACA_IRQ_EE) {
145 local_paca->irq_happened &= ~PACA_IRQ_EE;
149 if (happened & PACA_IRQ_DBELL) {
150 local_paca->irq_happened &= ~PACA_IRQ_DBELL;
154 if (happened & PACA_IRQ_HARD_DIS)
155 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
157 /* There should be nothing left ! */
158 BUG_ON(local_paca->irq_happened != 0);
164 * This is specifically called by assembly code to re-enable interrupts
165 * if they are currently disabled. This is typically called before
166 * schedule() or do_signal() when returning to userspace. We do it
167 * in C to avoid the burden of dealing with lockdep etc...
169 * NOTE: This is called with interrupts hard disabled but not marked
170 * as such in paca->irq_happened, so we need to resync this.
172 void notrace restore_interrupts(void)
174 if (irqs_disabled()) {
175 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
181 #endif /* CONFIG_PPC_BOOK3E */
183 void replay_soft_interrupts(void)
188 * Be careful here, calling these interrupt handlers can cause
189 * softirqs to be raised, which they may run when calling irq_exit,
190 * which will cause local_irq_enable() to be run, which can then
191 * recurse into this function. Don't keep any state across
192 * interrupt handler calls which may change underneath us.
194 * We use local_paca rather than get_paca() to avoid all the
195 * debug_smp_processor_id() business in this low level function.
198 ppc_save_regs(®s);
199 regs.softe = IRQS_ENABLED;
202 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
203 WARN_ON_ONCE(mfmsr() & MSR_EE);
206 * Force the delivery of pending soft-disabled interrupts on PS3.
207 * Any HV call will have this side effect.
209 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
211 lv1_get_version_info(&tmp, &tmp2);
215 * Check if an hypervisor Maintenance interrupt happened.
216 * This is a higher priority interrupt than the others, so
219 if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_HMI)) {
220 local_paca->irq_happened &= ~PACA_IRQ_HMI;
222 handle_hmi_exception(®s);
223 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
227 if (local_paca->irq_happened & PACA_IRQ_DEC) {
228 local_paca->irq_happened &= ~PACA_IRQ_DEC;
230 timer_interrupt(®s);
231 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
235 if (local_paca->irq_happened & PACA_IRQ_EE) {
236 local_paca->irq_happened &= ~PACA_IRQ_EE;
239 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
243 if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (local_paca->irq_happened & PACA_IRQ_DBELL)) {
244 local_paca->irq_happened &= ~PACA_IRQ_DBELL;
245 if (IS_ENABLED(CONFIG_PPC_BOOK3E))
249 doorbell_exception(®s);
250 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
254 /* Book3E does not support soft-masking PMI interrupts */
255 if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_PMI)) {
256 local_paca->irq_happened &= ~PACA_IRQ_PMI;
258 performance_monitor_exception(®s);
259 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
263 if (local_paca->irq_happened & ~PACA_IRQ_HARD_DIS) {
265 * We are responding to the next interrupt, so interrupt-off
266 * latencies should be reset here.
269 trace_hardirqs_off();
274 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_KUAP)
275 static inline void replay_soft_interrupts_irqrestore(void)
277 unsigned long kuap_state = get_kuap();
280 * Check if anything calls local_irq_enable/restore() when KUAP is
281 * disabled (user access enabled). We handle that case here by saving
282 * and re-locking AMR but we shouldn't get here in the first place,
287 if (kuap_state != AMR_KUAP_BLOCKED)
288 set_kuap(AMR_KUAP_BLOCKED);
290 replay_soft_interrupts();
292 if (kuap_state != AMR_KUAP_BLOCKED)
293 set_kuap(kuap_state);
296 #define replay_soft_interrupts_irqrestore() replay_soft_interrupts()
299 notrace void arch_local_irq_restore(unsigned long mask)
301 unsigned char irq_happened;
303 /* Write the new soft-enabled value */
304 irq_soft_mask_set(mask);
309 * From this point onward, we can take interrupts, preempt,
310 * etc... unless we got hard-disabled. We check if an event
311 * happened. If none happened, we know we can just return.
313 * We may have preempted before the check below, in which case
314 * we are checking the "new" CPU instead of the old one. This
315 * is only a problem if an event happened on the "old" CPU.
317 * External interrupt events will have caused interrupts to
318 * be hard-disabled, so there is no problem, we
319 * cannot have preempted.
321 irq_happened = get_irq_happened();
323 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
324 WARN_ON_ONCE(!(mfmsr() & MSR_EE));
328 /* We need to hard disable to replay. */
329 if (!(irq_happened & PACA_IRQ_HARD_DIS)) {
330 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
331 WARN_ON_ONCE(!(mfmsr() & MSR_EE));
332 __hard_irq_disable();
333 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
336 * We should already be hard disabled here. We had bugs
337 * where that wasn't the case so let's dbl check it and
338 * warn if we are wrong. Only do that when IRQ tracing
339 * is enabled as mfmsr() can be costly.
341 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) {
342 if (WARN_ON_ONCE(mfmsr() & MSR_EE))
343 __hard_irq_disable();
346 if (irq_happened == PACA_IRQ_HARD_DIS) {
347 local_paca->irq_happened = 0;
354 * Disable preempt here, so that the below preempt_enable will
355 * perform resched if required (a replayed interrupt may set
359 irq_soft_mask_set(IRQS_ALL_DISABLED);
360 trace_hardirqs_off();
362 replay_soft_interrupts_irqrestore();
363 local_paca->irq_happened = 0;
366 irq_soft_mask_set(IRQS_ENABLED);
370 EXPORT_SYMBOL(arch_local_irq_restore);
373 * This is a helper to use when about to go into idle low-power
374 * when the latter has the side effect of re-enabling interrupts
375 * (such as calling H_CEDE under pHyp).
377 * You call this function with interrupts soft-disabled (this is
378 * already the case when ppc_md.power_save is called). The function
379 * will return whether to enter power save or just return.
381 * In the former case, it will have notified lockdep of interrupts
382 * being re-enabled and generally sanitized the lazy irq state,
383 * and in the latter case it will leave with interrupts hard
384 * disabled and marked as such, so the local_irq_enable() call
385 * in arch_cpu_idle() will properly re-enable everything.
387 bool prep_irq_for_idle(void)
390 * First we need to hard disable to ensure no interrupt
391 * occurs before we effectively enter the low power state
393 __hard_irq_disable();
394 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
397 * If anything happened while we were soft-disabled,
398 * we return now and do not enter the low power state.
400 if (lazy_irq_pending())
403 /* Tell lockdep we are about to re-enable */
407 * Mark interrupts as soft-enabled and clear the
408 * PACA_IRQ_HARD_DIS from the pending mask since we
409 * are about to hard enable as well as a side effect
410 * of entering the low power state.
412 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
413 irq_soft_mask_set(IRQS_ENABLED);
415 /* Tell the caller to enter the low power state */
419 #ifdef CONFIG_PPC_BOOK3S
421 * This is for idle sequences that return with IRQs off, but the
422 * idle state itself wakes on interrupt. Tell the irq tracer that
423 * IRQs are enabled for the duration of idle so it does not get long
424 * off times. Must be paired with fini_irq_for_idle_irqsoff.
426 bool prep_irq_for_idle_irqsoff(void)
428 WARN_ON(!irqs_disabled());
431 * First we need to hard disable to ensure no interrupt
432 * occurs before we effectively enter the low power state
434 __hard_irq_disable();
435 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
438 * If anything happened while we were soft-disabled,
439 * we return now and do not enter the low power state.
441 if (lazy_irq_pending())
444 /* Tell lockdep we are about to re-enable */
451 * Take the SRR1 wakeup reason, index into this table to find the
452 * appropriate irq_happened bit.
454 * Sytem reset exceptions taken in idle state also come through here,
455 * but they are NMI interrupts so do not need to wait for IRQs to be
456 * restored, and should be taken as early as practical. These are marked
457 * with 0xff in the table. The Power ISA specifies 0100b as the system
458 * reset interrupt reason.
460 #define IRQ_SYSTEM_RESET 0xff
462 static const u8 srr1_to_lazyirq[0x10] = {
474 void replay_system_reset(void)
478 ppc_save_regs(®s);
480 get_paca()->in_nmi = 1;
481 system_reset_exception(®s);
482 get_paca()->in_nmi = 0;
484 EXPORT_SYMBOL_GPL(replay_system_reset);
486 void irq_set_pending_from_srr1(unsigned long srr1)
488 unsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18;
489 u8 reason = srr1_to_lazyirq[idx];
492 * Take the system reset now, which is immediately after registers
493 * are restored from idle. It's an NMI, so interrupts need not be
494 * re-enabled before it is taken.
496 if (unlikely(reason == IRQ_SYSTEM_RESET)) {
497 replay_system_reset();
501 if (reason == PACA_IRQ_DBELL) {
503 * When doorbell triggers a system reset wakeup, the message
504 * is not cleared, so if the doorbell interrupt is replayed
505 * and the IPI handled, the doorbell interrupt would still
506 * fire when EE is enabled.
508 * To avoid taking the superfluous doorbell interrupt,
509 * execute a msgclr here before the interrupt is replayed.
511 ppc_msgclr(PPC_DBELL_MSGTYPE);
515 * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,
516 * so this can be called unconditionally with the SRR1 wake
517 * reason as returned by the idle code, which uses 0 to mean no
520 * If a future CPU was to designate this as an interrupt reason,
521 * then a new index for no interrupt must be assigned.
523 local_paca->irq_happened |= reason;
525 #endif /* CONFIG_PPC_BOOK3S */
528 * Force a replay of the external interrupt handler on this CPU.
530 void force_external_irq_replay(void)
533 * This must only be called with interrupts soft-disabled,
534 * the replay will happen when re-enabling.
536 WARN_ON(!arch_irqs_disabled());
539 * Interrupts must always be hard disabled before irq_happened is
540 * modified (to prevent lost update in case of interrupt between
543 __hard_irq_disable();
544 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
546 /* Indicate in the PACA that we have an interrupt to replay */
547 local_paca->irq_happened |= PACA_IRQ_EE;
550 #endif /* CONFIG_PPC64 */
552 int arch_show_interrupts(struct seq_file *p, int prec)
556 #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
557 if (tau_initialized) {
558 seq_printf(p, "%*s: ", prec, "TAU");
559 for_each_online_cpu(j)
560 seq_printf(p, "%10u ", tau_interrupts(j));
561 seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n");
563 #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
565 seq_printf(p, "%*s: ", prec, "LOC");
566 for_each_online_cpu(j)
567 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event);
568 seq_printf(p, " Local timer interrupts for timer event device\n");
570 seq_printf(p, "%*s: ", prec, "BCT");
571 for_each_online_cpu(j)
572 seq_printf(p, "%10u ", per_cpu(irq_stat, j).broadcast_irqs_event);
573 seq_printf(p, " Broadcast timer interrupts for timer event device\n");
575 seq_printf(p, "%*s: ", prec, "LOC");
576 for_each_online_cpu(j)
577 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others);
578 seq_printf(p, " Local timer interrupts for others\n");
580 seq_printf(p, "%*s: ", prec, "SPU");
581 for_each_online_cpu(j)
582 seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs);
583 seq_printf(p, " Spurious interrupts\n");
585 seq_printf(p, "%*s: ", prec, "PMI");
586 for_each_online_cpu(j)
587 seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs);
588 seq_printf(p, " Performance monitoring interrupts\n");
590 seq_printf(p, "%*s: ", prec, "MCE");
591 for_each_online_cpu(j)
592 seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
593 seq_printf(p, " Machine check exceptions\n");
595 #ifdef CONFIG_PPC_BOOK3S_64
596 if (cpu_has_feature(CPU_FTR_HVMODE)) {
597 seq_printf(p, "%*s: ", prec, "HMI");
598 for_each_online_cpu(j)
599 seq_printf(p, "%10u ", paca_ptrs[j]->hmi_irqs);
600 seq_printf(p, " Hypervisor Maintenance Interrupts\n");
604 seq_printf(p, "%*s: ", prec, "NMI");
605 for_each_online_cpu(j)
606 seq_printf(p, "%10u ", per_cpu(irq_stat, j).sreset_irqs);
607 seq_printf(p, " System Reset interrupts\n");
609 #ifdef CONFIG_PPC_WATCHDOG
610 seq_printf(p, "%*s: ", prec, "WDG");
611 for_each_online_cpu(j)
612 seq_printf(p, "%10u ", per_cpu(irq_stat, j).soft_nmi_irqs);
613 seq_printf(p, " Watchdog soft-NMI interrupts\n");
616 #ifdef CONFIG_PPC_DOORBELL
617 if (cpu_has_feature(CPU_FTR_DBELL)) {
618 seq_printf(p, "%*s: ", prec, "DBL");
619 for_each_online_cpu(j)
620 seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
621 seq_printf(p, " Doorbell interrupts\n");
631 u64 arch_irq_stat_cpu(unsigned int cpu)
633 u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
635 sum += per_cpu(irq_stat, cpu).broadcast_irqs_event;
636 sum += per_cpu(irq_stat, cpu).pmu_irqs;
637 sum += per_cpu(irq_stat, cpu).mce_exceptions;
638 sum += per_cpu(irq_stat, cpu).spurious_irqs;
639 sum += per_cpu(irq_stat, cpu).timer_irqs_others;
640 #ifdef CONFIG_PPC_BOOK3S_64
641 sum += paca_ptrs[cpu]->hmi_irqs;
643 sum += per_cpu(irq_stat, cpu).sreset_irqs;
644 #ifdef CONFIG_PPC_WATCHDOG
645 sum += per_cpu(irq_stat, cpu).soft_nmi_irqs;
647 #ifdef CONFIG_PPC_DOORBELL
648 sum += per_cpu(irq_stat, cpu).doorbell_irqs;
654 static inline void check_stack_overflow(void)
658 if (!IS_ENABLED(CONFIG_DEBUG_STACKOVERFLOW))
661 sp = current_stack_pointer & (THREAD_SIZE - 1);
663 /* check for stack overflow: is there less than 2KB free? */
664 if (unlikely(sp < 2048)) {
665 pr_err("do_IRQ: stack overflow: %ld\n", sp);
670 void __do_irq(struct pt_regs *regs)
674 trace_irq_entry(regs);
677 * Query the platform PIC for the interrupt & ack it.
679 * This will typically lower the interrupt line to the CPU
681 irq = ppc_md.get_irq();
683 /* We can hard enable interrupts now to allow perf interrupts */
684 may_hard_irq_enable();
686 /* And finally process it */
688 __this_cpu_inc(irq_stat.spurious_irqs);
690 generic_handle_irq(irq);
692 trace_irq_exit(regs);
695 DEFINE_INTERRUPT_HANDLER_ASYNC(do_IRQ)
697 struct pt_regs *old_regs = set_irq_regs(regs);
698 void *cursp, *irqsp, *sirqsp;
700 /* Switch to the irq stack to handle this */
701 cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
702 irqsp = hardirq_ctx[raw_smp_processor_id()];
703 sirqsp = softirq_ctx[raw_smp_processor_id()];
705 check_stack_overflow();
707 /* Already there ? */
708 if (unlikely(cursp == irqsp || cursp == sirqsp)) {
710 set_irq_regs(old_regs);
713 /* Switch stack and call */
714 call_do_irq(regs, irqsp);
716 set_irq_regs(old_regs);
719 static void *__init alloc_vm_stack(void)
721 return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP,
722 NUMA_NO_NODE, (void *)_RET_IP_);
725 static void __init vmap_irqstack_init(void)
729 for_each_possible_cpu(i) {
730 softirq_ctx[i] = alloc_vm_stack();
731 hardirq_ctx[i] = alloc_vm_stack();
736 void __init init_IRQ(void)
738 if (IS_ENABLED(CONFIG_VMAP_STACK))
739 vmap_irqstack_init();
745 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
746 void *critirq_ctx[NR_CPUS] __read_mostly;
747 void *dbgirq_ctx[NR_CPUS] __read_mostly;
748 void *mcheckirq_ctx[NR_CPUS] __read_mostly;
751 void *softirq_ctx[NR_CPUS] __read_mostly;
752 void *hardirq_ctx[NR_CPUS] __read_mostly;
754 void do_softirq_own_stack(void)
756 call_do_softirq(softirq_ctx[smp_processor_id()]);
759 irq_hw_number_t virq_to_hw(unsigned int virq)
761 struct irq_data *irq_data = irq_get_irq_data(virq);
762 return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
764 EXPORT_SYMBOL_GPL(virq_to_hw);
767 int irq_choose_cpu(const struct cpumask *mask)
771 if (cpumask_equal(mask, cpu_online_mask)) {
772 static int irq_rover;
773 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
776 /* Round-robin distribution... */
778 raw_spin_lock_irqsave(&irq_rover_lock, flags);
780 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
781 if (irq_rover >= nr_cpu_ids)
782 irq_rover = cpumask_first(cpu_online_mask);
786 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
788 cpuid = cpumask_first_and(mask, cpu_online_mask);
789 if (cpuid >= nr_cpu_ids)
793 return get_hard_smp_processor_id(cpuid);
796 int irq_choose_cpu(const struct cpumask *mask)
798 return hard_smp_processor_id();
803 static int __init setup_noirqdistrib(char *str)
809 __setup("noirqdistrib", setup_noirqdistrib);
810 #endif /* CONFIG_PPC64 */