1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from arch/i386/kernel/irq.c
4 * Copyright (C) 1992 Linus Torvalds
5 * Adapted from arch/i386 by Gary Thomas
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Updated and modified by Cort Dougan <cort@fsmlabs.com>
8 * Copyright (C) 1996-2001 Cort Dougan
9 * Adapted for Power Macintosh by Paul Mackerras
10 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
12 * This file contains the code used by various IRQ handling routines:
13 * asking for different IRQ's should be done through these routines
14 * instead of just grabbing them. Thus setups with different IRQ numbers
15 * shouldn't result in any weird surprises, and installing new handlers
18 * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the
19 * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit
20 * mask register (of which only 16 are defined), hence the weird shifting
21 * and complement of the cached_irq_mask. I want to be able to stuff
22 * this right into the SIU SMASK register.
23 * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx
24 * to reduce code space and undefined function references.
29 #include <linux/export.h>
30 #include <linux/threads.h>
31 #include <linux/kernel_stat.h>
32 #include <linux/signal.h>
33 #include <linux/sched.h>
34 #include <linux/ptrace.h>
35 #include <linux/ioport.h>
36 #include <linux/interrupt.h>
37 #include <linux/timex.h>
38 #include <linux/init.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
41 #include <linux/irq.h>
42 #include <linux/seq_file.h>
43 #include <linux/cpumask.h>
44 #include <linux/profile.h>
45 #include <linux/bitops.h>
46 #include <linux/list.h>
47 #include <linux/radix-tree.h>
48 #include <linux/mutex.h>
49 #include <linux/pci.h>
50 #include <linux/debugfs.h>
52 #include <linux/of_irq.h>
53 #include <linux/vmalloc.h>
54 #include <linux/pgtable.h>
56 #include <linux/uaccess.h>
59 #include <asm/cache.h>
61 #include <asm/ptrace.h>
62 #include <asm/machdep.h>
65 #include <asm/livepatch.h>
66 #include <asm/asm-prototypes.h>
67 #include <asm/hw_irq.h>
71 #include <asm/firmware.h>
72 #include <asm/lv1call.h>
73 #include <asm/dbell.h>
75 #define CREATE_TRACE_POINTS
76 #include <asm/trace.h>
77 #include <asm/cpu_has_feature.h>
79 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
80 EXPORT_PER_CPU_SYMBOL(irq_stat);
83 atomic_t ppc_n_lost_interrupts;
86 extern int tau_initialized;
87 u32 tau_interrupts(unsigned long cpu);
89 #endif /* CONFIG_PPC32 */
93 int distribute_irqs = 1;
95 static inline notrace unsigned long get_irq_happened(void)
97 unsigned long happened;
99 __asm__ __volatile__("lbz %0,%1(13)"
100 : "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened)));
105 static inline notrace int decrementer_check_overflow(void)
107 u64 now = get_tb_or_rtc();
108 u64 *next_tb = this_cpu_ptr(&decrementers_next_tb);
110 return now >= *next_tb;
113 #ifdef CONFIG_PPC_BOOK3E
115 /* This is called whenever we are re-enabling interrupts
116 * and returns either 0 (nothing to do) or 500/900/280 if
117 * there's an EE, DEC or DBELL to generate.
119 * This is called in two contexts: From arch_local_irq_restore()
120 * before soft-enabling interrupts, and from the exception exit
121 * path when returning from an interrupt from a soft-disabled to
122 * a soft enabled context. In both case we have interrupts hard
125 * We take care of only clearing the bits we handled in the
126 * PACA irq_happened field since we can only re-emit one at a
127 * time and we don't want to "lose" one.
129 notrace unsigned int __check_irq_replay(void)
132 * We use local_paca rather than get_paca() to avoid all
133 * the debug_smp_processor_id() business in this low level
136 unsigned char happened = local_paca->irq_happened;
139 * We are responding to the next interrupt, so interrupt-off
140 * latencies should be reset here.
143 trace_hardirqs_off();
146 * We are always hard disabled here, but PACA_IRQ_HARD_DIS may
147 * not be set, which means interrupts have only just been hard
148 * disabled as part of the local_irq_restore or interrupt return
149 * code. In that case, skip the decrementr check becaus it's
150 * expensive to read the TB.
152 * HARD_DIS then gets cleared here, but it's reconciled later.
153 * Either local_irq_disable will replay the interrupt and that
154 * will reconcile state like other hard interrupts. Or interrupt
155 * retur will replay the interrupt and in that case it sets
156 * PACA_IRQ_HARD_DIS by hand (see comments in entry_64.S).
158 if (happened & PACA_IRQ_HARD_DIS) {
159 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
162 * We may have missed a decrementer interrupt if hard disabled.
163 * Check the decrementer register in case we had a rollover
164 * while hard disabled.
166 if (!(happened & PACA_IRQ_DEC)) {
167 if (decrementer_check_overflow()) {
168 local_paca->irq_happened |= PACA_IRQ_DEC;
169 happened |= PACA_IRQ_DEC;
174 if (happened & PACA_IRQ_DEC) {
175 local_paca->irq_happened &= ~PACA_IRQ_DEC;
179 if (happened & PACA_IRQ_EE) {
180 local_paca->irq_happened &= ~PACA_IRQ_EE;
184 if (happened & PACA_IRQ_DBELL) {
185 local_paca->irq_happened &= ~PACA_IRQ_DBELL;
189 /* There should be nothing left ! */
190 BUG_ON(local_paca->irq_happened != 0);
194 #endif /* CONFIG_PPC_BOOK3E */
196 void replay_soft_interrupts(void)
199 * We use local_paca rather than get_paca() to avoid all
200 * the debug_smp_processor_id() business in this low level
203 unsigned char happened = local_paca->irq_happened;
206 ppc_save_regs(®s);
207 regs.softe = IRQS_ENABLED;
210 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
211 WARN_ON_ONCE(mfmsr() & MSR_EE);
213 if (happened & PACA_IRQ_HARD_DIS) {
215 * We may have missed a decrementer interrupt if hard disabled.
216 * Check the decrementer register in case we had a rollover
217 * while hard disabled.
219 if (!(happened & PACA_IRQ_DEC)) {
220 if (decrementer_check_overflow())
221 happened |= PACA_IRQ_DEC;
226 * Force the delivery of pending soft-disabled interrupts on PS3.
227 * Any HV call will have this side effect.
229 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
231 lv1_get_version_info(&tmp, &tmp2);
235 * Check if an hypervisor Maintenance interrupt happened.
236 * This is a higher priority interrupt than the others, so
239 if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (happened & PACA_IRQ_HMI)) {
240 local_paca->irq_happened &= ~PACA_IRQ_HMI;
242 handle_hmi_exception(®s);
243 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
247 if (happened & PACA_IRQ_DEC) {
248 local_paca->irq_happened &= ~PACA_IRQ_DEC;
250 timer_interrupt(®s);
251 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
255 if (happened & PACA_IRQ_EE) {
256 local_paca->irq_happened &= ~PACA_IRQ_EE;
259 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
263 if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (happened & PACA_IRQ_DBELL)) {
264 local_paca->irq_happened &= ~PACA_IRQ_DBELL;
265 if (IS_ENABLED(CONFIG_PPC_BOOK3E))
269 doorbell_exception(®s);
270 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
274 /* Book3E does not support soft-masking PMI interrupts */
275 if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (happened & PACA_IRQ_PMI)) {
276 local_paca->irq_happened &= ~PACA_IRQ_PMI;
278 performance_monitor_exception(®s);
279 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
283 happened = local_paca->irq_happened;
284 if (happened & ~PACA_IRQ_HARD_DIS) {
286 * We are responding to the next interrupt, so interrupt-off
287 * latencies should be reset here.
290 trace_hardirqs_off();
295 notrace void arch_local_irq_restore(unsigned long mask)
297 unsigned char irq_happened;
299 /* Write the new soft-enabled value */
300 irq_soft_mask_set(mask);
305 * From this point onward, we can take interrupts, preempt,
306 * etc... unless we got hard-disabled. We check if an event
307 * happened. If none happened, we know we can just return.
309 * We may have preempted before the check below, in which case
310 * we are checking the "new" CPU instead of the old one. This
311 * is only a problem if an event happened on the "old" CPU.
313 * External interrupt events will have caused interrupts to
314 * be hard-disabled, so there is no problem, we
315 * cannot have preempted.
317 irq_happened = get_irq_happened();
319 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
320 WARN_ON_ONCE(!(mfmsr() & MSR_EE));
324 /* We need to hard disable to replay. */
325 if (!(irq_happened & PACA_IRQ_HARD_DIS)) {
326 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
327 WARN_ON_ONCE(!(mfmsr() & MSR_EE));
328 __hard_irq_disable();
331 * We should already be hard disabled here. We had bugs
332 * where that wasn't the case so let's dbl check it and
333 * warn if we are wrong. Only do that when IRQ tracing
334 * is enabled as mfmsr() can be costly.
336 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) {
337 if (WARN_ON_ONCE(mfmsr() & MSR_EE))
338 __hard_irq_disable();
341 if (irq_happened == PACA_IRQ_HARD_DIS) {
342 local_paca->irq_happened = 0;
349 * Disable preempt here, so that the below preempt_enable will
350 * perform resched if required (a replayed interrupt may set
354 irq_soft_mask_set(IRQS_ALL_DISABLED);
355 trace_hardirqs_off();
357 replay_soft_interrupts();
358 local_paca->irq_happened = 0;
361 irq_soft_mask_set(IRQS_ENABLED);
365 EXPORT_SYMBOL(arch_local_irq_restore);
368 * This is specifically called by assembly code to re-enable interrupts
369 * if they are currently disabled. This is typically called before
370 * schedule() or do_signal() when returning to userspace. We do it
371 * in C to avoid the burden of dealing with lockdep etc...
373 * NOTE: This is called with interrupts hard disabled but not marked
374 * as such in paca->irq_happened, so we need to resync this.
376 void notrace restore_interrupts(void)
378 if (irqs_disabled()) {
379 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
386 * This is a helper to use when about to go into idle low-power
387 * when the latter has the side effect of re-enabling interrupts
388 * (such as calling H_CEDE under pHyp).
390 * You call this function with interrupts soft-disabled (this is
391 * already the case when ppc_md.power_save is called). The function
392 * will return whether to enter power save or just return.
394 * In the former case, it will have notified lockdep of interrupts
395 * being re-enabled and generally sanitized the lazy irq state,
396 * and in the latter case it will leave with interrupts hard
397 * disabled and marked as such, so the local_irq_enable() call
398 * in arch_cpu_idle() will properly re-enable everything.
400 bool prep_irq_for_idle(void)
403 * First we need to hard disable to ensure no interrupt
404 * occurs before we effectively enter the low power state
406 __hard_irq_disable();
407 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
410 * If anything happened while we were soft-disabled,
411 * we return now and do not enter the low power state.
413 if (lazy_irq_pending())
416 /* Tell lockdep we are about to re-enable */
420 * Mark interrupts as soft-enabled and clear the
421 * PACA_IRQ_HARD_DIS from the pending mask since we
422 * are about to hard enable as well as a side effect
423 * of entering the low power state.
425 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
426 irq_soft_mask_set(IRQS_ENABLED);
428 /* Tell the caller to enter the low power state */
432 #ifdef CONFIG_PPC_BOOK3S
434 * This is for idle sequences that return with IRQs off, but the
435 * idle state itself wakes on interrupt. Tell the irq tracer that
436 * IRQs are enabled for the duration of idle so it does not get long
437 * off times. Must be paired with fini_irq_for_idle_irqsoff.
439 bool prep_irq_for_idle_irqsoff(void)
441 WARN_ON(!irqs_disabled());
444 * First we need to hard disable to ensure no interrupt
445 * occurs before we effectively enter the low power state
447 __hard_irq_disable();
448 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
451 * If anything happened while we were soft-disabled,
452 * we return now and do not enter the low power state.
454 if (lazy_irq_pending())
457 /* Tell lockdep we are about to re-enable */
464 * Take the SRR1 wakeup reason, index into this table to find the
465 * appropriate irq_happened bit.
467 * Sytem reset exceptions taken in idle state also come through here,
468 * but they are NMI interrupts so do not need to wait for IRQs to be
469 * restored, and should be taken as early as practical. These are marked
470 * with 0xff in the table. The Power ISA specifies 0100b as the system
471 * reset interrupt reason.
473 #define IRQ_SYSTEM_RESET 0xff
475 static const u8 srr1_to_lazyirq[0x10] = {
487 void replay_system_reset(void)
491 ppc_save_regs(®s);
493 get_paca()->in_nmi = 1;
494 system_reset_exception(®s);
495 get_paca()->in_nmi = 0;
497 EXPORT_SYMBOL_GPL(replay_system_reset);
499 void irq_set_pending_from_srr1(unsigned long srr1)
501 unsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18;
502 u8 reason = srr1_to_lazyirq[idx];
505 * Take the system reset now, which is immediately after registers
506 * are restored from idle. It's an NMI, so interrupts need not be
507 * re-enabled before it is taken.
509 if (unlikely(reason == IRQ_SYSTEM_RESET)) {
510 replay_system_reset();
514 if (reason == PACA_IRQ_DBELL) {
516 * When doorbell triggers a system reset wakeup, the message
517 * is not cleared, so if the doorbell interrupt is replayed
518 * and the IPI handled, the doorbell interrupt would still
519 * fire when EE is enabled.
521 * To avoid taking the superfluous doorbell interrupt,
522 * execute a msgclr here before the interrupt is replayed.
524 ppc_msgclr(PPC_DBELL_MSGTYPE);
528 * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,
529 * so this can be called unconditionally with the SRR1 wake
530 * reason as returned by the idle code, which uses 0 to mean no
533 * If a future CPU was to designate this as an interrupt reason,
534 * then a new index for no interrupt must be assigned.
536 local_paca->irq_happened |= reason;
538 #endif /* CONFIG_PPC_BOOK3S */
541 * Force a replay of the external interrupt handler on this CPU.
543 void force_external_irq_replay(void)
546 * This must only be called with interrupts soft-disabled,
547 * the replay will happen when re-enabling.
549 WARN_ON(!arch_irqs_disabled());
552 * Interrupts must always be hard disabled before irq_happened is
553 * modified (to prevent lost update in case of interrupt between
556 __hard_irq_disable();
557 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
559 /* Indicate in the PACA that we have an interrupt to replay */
560 local_paca->irq_happened |= PACA_IRQ_EE;
563 #endif /* CONFIG_PPC64 */
565 int arch_show_interrupts(struct seq_file *p, int prec)
569 #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
570 if (tau_initialized) {
571 seq_printf(p, "%*s: ", prec, "TAU");
572 for_each_online_cpu(j)
573 seq_printf(p, "%10u ", tau_interrupts(j));
574 seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n");
576 #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
578 seq_printf(p, "%*s: ", prec, "LOC");
579 for_each_online_cpu(j)
580 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event);
581 seq_printf(p, " Local timer interrupts for timer event device\n");
583 seq_printf(p, "%*s: ", prec, "BCT");
584 for_each_online_cpu(j)
585 seq_printf(p, "%10u ", per_cpu(irq_stat, j).broadcast_irqs_event);
586 seq_printf(p, " Broadcast timer interrupts for timer event device\n");
588 seq_printf(p, "%*s: ", prec, "LOC");
589 for_each_online_cpu(j)
590 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others);
591 seq_printf(p, " Local timer interrupts for others\n");
593 seq_printf(p, "%*s: ", prec, "SPU");
594 for_each_online_cpu(j)
595 seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs);
596 seq_printf(p, " Spurious interrupts\n");
598 seq_printf(p, "%*s: ", prec, "PMI");
599 for_each_online_cpu(j)
600 seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs);
601 seq_printf(p, " Performance monitoring interrupts\n");
603 seq_printf(p, "%*s: ", prec, "MCE");
604 for_each_online_cpu(j)
605 seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
606 seq_printf(p, " Machine check exceptions\n");
608 #ifdef CONFIG_PPC_BOOK3S_64
609 if (cpu_has_feature(CPU_FTR_HVMODE)) {
610 seq_printf(p, "%*s: ", prec, "HMI");
611 for_each_online_cpu(j)
612 seq_printf(p, "%10u ", paca_ptrs[j]->hmi_irqs);
613 seq_printf(p, " Hypervisor Maintenance Interrupts\n");
617 seq_printf(p, "%*s: ", prec, "NMI");
618 for_each_online_cpu(j)
619 seq_printf(p, "%10u ", per_cpu(irq_stat, j).sreset_irqs);
620 seq_printf(p, " System Reset interrupts\n");
622 #ifdef CONFIG_PPC_WATCHDOG
623 seq_printf(p, "%*s: ", prec, "WDG");
624 for_each_online_cpu(j)
625 seq_printf(p, "%10u ", per_cpu(irq_stat, j).soft_nmi_irqs);
626 seq_printf(p, " Watchdog soft-NMI interrupts\n");
629 #ifdef CONFIG_PPC_DOORBELL
630 if (cpu_has_feature(CPU_FTR_DBELL)) {
631 seq_printf(p, "%*s: ", prec, "DBL");
632 for_each_online_cpu(j)
633 seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
634 seq_printf(p, " Doorbell interrupts\n");
644 u64 arch_irq_stat_cpu(unsigned int cpu)
646 u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
648 sum += per_cpu(irq_stat, cpu).broadcast_irqs_event;
649 sum += per_cpu(irq_stat, cpu).pmu_irqs;
650 sum += per_cpu(irq_stat, cpu).mce_exceptions;
651 sum += per_cpu(irq_stat, cpu).spurious_irqs;
652 sum += per_cpu(irq_stat, cpu).timer_irqs_others;
653 #ifdef CONFIG_PPC_BOOK3S_64
654 sum += paca_ptrs[cpu]->hmi_irqs;
656 sum += per_cpu(irq_stat, cpu).sreset_irqs;
657 #ifdef CONFIG_PPC_WATCHDOG
658 sum += per_cpu(irq_stat, cpu).soft_nmi_irqs;
660 #ifdef CONFIG_PPC_DOORBELL
661 sum += per_cpu(irq_stat, cpu).doorbell_irqs;
667 static inline void check_stack_overflow(void)
671 if (!IS_ENABLED(CONFIG_DEBUG_STACKOVERFLOW))
674 sp = current_stack_pointer & (THREAD_SIZE - 1);
676 /* check for stack overflow: is there less than 2KB free? */
677 if (unlikely(sp < 2048)) {
678 pr_err("do_IRQ: stack overflow: %ld\n", sp);
683 void __do_irq(struct pt_regs *regs)
689 trace_irq_entry(regs);
692 * Query the platform PIC for the interrupt & ack it.
694 * This will typically lower the interrupt line to the CPU
696 irq = ppc_md.get_irq();
698 /* We can hard enable interrupts now to allow perf interrupts */
699 may_hard_irq_enable();
701 /* And finally process it */
703 __this_cpu_inc(irq_stat.spurious_irqs);
705 generic_handle_irq(irq);
707 trace_irq_exit(regs);
712 void do_IRQ(struct pt_regs *regs)
714 struct pt_regs *old_regs = set_irq_regs(regs);
715 void *cursp, *irqsp, *sirqsp;
717 /* Switch to the irq stack to handle this */
718 cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
719 irqsp = hardirq_ctx[raw_smp_processor_id()];
720 sirqsp = softirq_ctx[raw_smp_processor_id()];
722 check_stack_overflow();
724 /* Already there ? */
725 if (unlikely(cursp == irqsp || cursp == sirqsp)) {
727 set_irq_regs(old_regs);
730 /* Switch stack and call */
731 call_do_irq(regs, irqsp);
733 set_irq_regs(old_regs);
736 static void *__init alloc_vm_stack(void)
738 return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP,
739 NUMA_NO_NODE, (void *)_RET_IP_);
742 static void __init vmap_irqstack_init(void)
746 for_each_possible_cpu(i) {
747 softirq_ctx[i] = alloc_vm_stack();
748 hardirq_ctx[i] = alloc_vm_stack();
753 void __init init_IRQ(void)
755 if (IS_ENABLED(CONFIG_VMAP_STACK))
756 vmap_irqstack_init();
762 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
763 void *critirq_ctx[NR_CPUS] __read_mostly;
764 void *dbgirq_ctx[NR_CPUS] __read_mostly;
765 void *mcheckirq_ctx[NR_CPUS] __read_mostly;
768 void *softirq_ctx[NR_CPUS] __read_mostly;
769 void *hardirq_ctx[NR_CPUS] __read_mostly;
771 void do_softirq_own_stack(void)
773 call_do_softirq(softirq_ctx[smp_processor_id()]);
776 irq_hw_number_t virq_to_hw(unsigned int virq)
778 struct irq_data *irq_data = irq_get_irq_data(virq);
779 return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
781 EXPORT_SYMBOL_GPL(virq_to_hw);
784 int irq_choose_cpu(const struct cpumask *mask)
788 if (cpumask_equal(mask, cpu_online_mask)) {
789 static int irq_rover;
790 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
793 /* Round-robin distribution... */
795 raw_spin_lock_irqsave(&irq_rover_lock, flags);
797 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
798 if (irq_rover >= nr_cpu_ids)
799 irq_rover = cpumask_first(cpu_online_mask);
803 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
805 cpuid = cpumask_first_and(mask, cpu_online_mask);
806 if (cpuid >= nr_cpu_ids)
810 return get_hard_smp_processor_id(cpuid);
813 int irq_choose_cpu(const struct cpumask *mask)
815 return hard_smp_processor_id();
820 static int __init setup_noirqdistrib(char *str)
826 __setup("noirqdistrib", setup_noirqdistrib);
827 #endif /* CONFIG_PPC64 */