1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
12 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
19 #include <linux/init.h>
20 #include <linux/pgtable.h>
24 #include <asm/cputable.h>
25 #include <asm/cache.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/ptrace.h>
31 #include <asm/kvm_book3s_asm.h>
32 #include <asm/export.h>
33 #include <asm/feature-fixups.h>
37 #define LOAD_BAT(n, reg, RA, RB) \
38 /* see the comment for clear_bats() -- Cort */ \
40 mtspr SPRN_IBAT##n##U,RA; \
41 mtspr SPRN_DBAT##n##U,RA; \
42 lwz RA,(n*16)+0(reg); \
43 lwz RB,(n*16)+4(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
46 lwz RA,(n*16)+8(reg); \
47 lwz RB,(n*16)+12(reg); \
48 mtspr SPRN_DBAT##n##U,RA; \
49 mtspr SPRN_DBAT##n##L,RB
52 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
53 .stabs "head_book3s_32.S",N_SO,0,0,0f
58 * _start is defined this way because the XCOFF loader in the OpenFirmware
59 * on the powermac expects the entry point to be a procedure descriptor.
63 * These are here for legacy reasons, the kernel used to
64 * need to look like a coff function entry for the pmac
65 * but we're always started by some kind of bootloader now.
68 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
69 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
73 * Enter here with the kernel text, data and bss loaded starting at
74 * 0, running with virtual == physical mapping.
75 * r5 points to the prom entry point (the client interface handler
76 * address). Address translation is turned on, with the prom
77 * managing the hash table. Interrupts are disabled. The stack
78 * pointer (r1) points to just below the end of the half-meg region
79 * from 0x380000 - 0x400000, which is mapped in already.
81 * If we are booted from MacOS via BootX, we enter with the kernel
82 * image loaded somewhere, and the following values in registers:
83 * r3: 'BooX' (0x426f6f58)
84 * r4: virtual address of boot_infos_t
88 * This is jumped to on prep systems right after the kernel is relocated
89 * to its proper place in memory by the boot loader. The expected layout
91 * r3: ptr to residual data
92 * r4: initrd_start or if no initrd then 0
93 * r5: initrd_end - unused if r4 is 0
94 * r6: Start of command line string
95 * r7: End of command line string
97 * This just gets a minimal mmu environment setup so we can call
98 * start_here() to do the real work.
105 * We have to do any OF calls before we map ourselves to KERNELBASE,
106 * because OF may have I/O devices mapped into that area
107 * (particularly on CHRP).
112 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
113 /* find out where we are now */
115 0: mflr r8 /* r8 = runtime addr here */
116 addis r8,r8,(_stext - 0b)@ha
117 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
119 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
121 /* We never return. We also hit that trap if trying to boot
122 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
126 * Check for BootX signature when supporting PowerMac and branch to
127 * appropriate trampoline if it's present
129 #ifdef CONFIG_PPC_PMAC
136 #endif /* CONFIG_PPC_PMAC */
138 1: mr r31,r3 /* save device tree ptr */
142 * early_init() does the early machine identification and does
143 * the necessary low-level setup and clears the BSS
144 * -- Cort <cort@fsmlabs.com>
148 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
149 * the physical address we are running at, returned by early_init()
157 bl load_segment_registers
158 BEGIN_MMU_FTR_SECTION
160 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
161 #if defined(CONFIG_BOOTX_TEXT)
164 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
167 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
168 bl setup_usbgecko_bat
172 * Call setup_cpu for CPU 0 and initialize 6xx Idle
176 bl call_setup_cpu /* Call setup_cpu for this CPU */
182 * We need to run with _start at physical address 0.
183 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
184 * the exception vectors at 0 (and therefore this copy
185 * overwrites OF's exception vectors with our own).
186 * The MMU is off at this point.
190 addis r4,r3,KERNELBASE@h /* current address of _start */
191 lis r5,PHYSICAL_START@h
192 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
195 * we now have the 1st 16M of ram mapped with the bats.
196 * prep needs the mmu to be turned on here, but pmac already has it on.
197 * this shouldn't bother the pmac since it just gets turned on again
198 * as we jump to our code at KERNELBASE. -- Cort
199 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
200 * off, and in other cases, we now turn it off before changing BATs above.
204 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
207 ori r0,r0,start_here@l
209 RFI /* enables MMU */
212 * We need __secondary_hold as a place to hold the other cpus on
213 * an SMP machine, even when we are running a UP kernel.
215 . = 0xc0 /* for prep bootloader */
216 li r3,1 /* MTX only has 1 cpu */
217 .globl __secondary_hold
219 /* tell the master we're here */
220 stw r3,__secondary_hold_acknowledge@l(0)
223 /* wait until we're told to start */
226 /* our cpu # was at addr 0 - go */
227 mr r24,r3 /* cpu # */
231 #endif /* CONFIG_SMP */
233 .globl __secondary_hold_spinloop
234 __secondary_hold_spinloop:
236 .globl __secondary_hold_acknowledge
237 __secondary_hold_acknowledge:
241 /* core99 pmac starts the seconary here by changing the vector, and
242 putting it back to what it was (unknown_exception) when done. */
243 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
247 * On CHRP, this is complicated by the fact that we could get a
248 * machine check inside RTAS, and we have no guarantee that certain
249 * critical registers will have the values we expect. The set of
250 * registers that might have bad values includes all the GPRs
251 * and all the BATs. We indicate that we are in RTAS by putting
252 * a non-zero value, the address of the exception frame to use,
253 * in thread.rtas_sp. The machine check handler checks thread.rtas_sp
254 * and uses its value if it is non-zero.
255 * (Other exception handlers assume that r1 is a valid kernel stack
256 * pointer when we take an exception from supervisor mode.)
263 #ifdef CONFIG_PPC_CHRP
264 mfspr r11, SPRN_SPRG_THREAD
265 lwz r11, RTAS_SP(r11)
268 #endif /* CONFIG_PPC_CHRP */
269 EXCEPTION_PROLOG_1 for_rtas=1
270 7: EXCEPTION_PROLOG_2
271 addi r3,r1,STACK_FRAME_OVERHEAD
272 #ifdef CONFIG_PPC_CHRP
273 #ifdef CONFIG_VMAP_STACK
274 mfspr r4, SPRN_SPRG_THREAD
279 beq cr1, machine_check_tramp
282 b machine_check_tramp
285 /* Data access exception. */
289 #ifdef CONFIG_VMAP_STACK
290 mtspr SPRN_SPRG_SCRATCH0,r10
291 mfspr r10, SPRN_SPRG_THREAD
292 BEGIN_MMU_FTR_SECTION
294 mfspr r10, SPRN_DSISR
296 #ifdef CONFIG_PPC_KUAP
297 andis. r10, r10, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
299 andis. r10, r10, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
301 mfspr r10, SPRN_SPRG_THREAD
303 .Lhash_page_dsi_cont:
306 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
307 mtspr SPRN_SPRG_SCRATCH1,r11
310 mfspr r11, SPRN_DSISR
314 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
317 andi. r11, r11, MSR_PR
320 b handle_page_fault_tramp_1
321 #else /* CONFIG_VMAP_STACK */
322 EXCEPTION_PROLOG handle_dar_dsisr=1
323 get_and_save_dar_dsisr_on_stack r4, r5, r11
324 BEGIN_MMU_FTR_SECTION
325 #ifdef CONFIG_PPC_KUAP
326 andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
328 andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
330 bne handle_page_fault_tramp_2 /* if not, try to put a PTE */
331 rlwinm r3, r5, 32 - 15, 21, 21 /* DSISR_STORE -> _PAGE_RW */
333 b handle_page_fault_tramp_1
335 b handle_page_fault_tramp_2
336 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
337 #endif /* CONFIG_VMAP_STACK */
339 /* Instruction access exception. */
343 #ifdef CONFIG_VMAP_STACK
344 mtspr SPRN_SPRG_SCRATCH0,r10
345 mtspr SPRN_SPRG_SCRATCH1,r11
346 mfspr r10, SPRN_SPRG_THREAD
349 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
352 BEGIN_MMU_FTR_SECTION
353 andis. r11, r11, SRR1_ISI_NOPT@h /* no pte found? */
355 .Lhash_page_isi_cont:
356 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
357 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
358 andi. r11, r11, MSR_PR
362 #else /* CONFIG_VMAP_STACK */
364 andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
365 beq 1f /* if so, try to put a PTE */
366 li r3,0 /* into the hash table */
367 mr r4,r12 /* SRR0 is fault address */
368 BEGIN_MMU_FTR_SECTION
370 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
371 #endif /* CONFIG_VMAP_STACK */
373 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
375 EXC_XFER_LITE(0x400, handle_page_fault)
377 /* External interrupt */
378 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
380 /* Alignment exception */
384 EXCEPTION_PROLOG handle_dar_dsisr=1
385 save_dar_dsisr_on_stack r4, r5, r11
386 addi r3,r1,STACK_FRAME_OVERHEAD
387 b alignment_exception_tramp
389 /* Program check exception */
390 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
392 /* Floating-point unavailable */
398 * Certain Freescale cores don't have a FPU and treat fp instructions
399 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
402 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
405 bl load_up_fpu /* if from user, just load it up */
406 b fast_exception_return
407 1: addi r3,r1,STACK_FRAME_OVERHEAD
408 EXC_XFER_LITE(0x800, kernel_fp_unavailable_exception)
411 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
413 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
414 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
422 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
423 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
426 * The Altivec unavailable trap is at 0x0f20. Foo.
427 * We effectively remap it to 0x3000.
428 * We include an altivec unavailable exception vector even if
429 * not configured for Altivec, so that you can't panic a
430 * non-altivec kernel running on a machine with altivec just
431 * by executing an altivec instruction.
442 * Handle TLB miss for instruction on 603/603e.
443 * Note: we get an alternate set of r0 - r3 to use automatically.
449 * r1: linux style pte ( later becomes ppc hardware pte )
450 * r2: ptr to linux-style pte
453 /* Get PTE (linux-style) and check access */
455 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
456 lis r1, TASK_SIZE@h /* check if kernel address */
459 mfspr r2, SPRN_SPRG_PGDIR
461 li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
463 li r1,_PAGE_PRESENT | _PAGE_EXEC
465 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
467 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
468 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
470 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
471 lwz r2,0(r2) /* get pmd entry */
472 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
473 beq- InstructionAddressInvalid /* return if no mapping */
474 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
475 lwz r0,0(r2) /* get linux-style pte */
476 andc. r1,r1,r0 /* check access & ~permission */
477 bne- InstructionAddressInvalid /* return if access not permitted */
478 /* Convert linux-style PTE to low word of PPC-style PTE */
479 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
480 ori r1, r1, 0xe06 /* clear out reserved bits */
481 andc r1, r0, r1 /* PP = user? 1 : 0 */
483 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
484 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
487 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
490 InstructionAddressInvalid:
492 rlwinm r1,r3,9,6,6 /* Get load/store bit */
495 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
496 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
499 mfspr r1,SPRN_IMISS /* Get failing address */
500 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
501 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
503 mtspr SPRN_DAR,r1 /* Set fault address */
504 mfmsr r0 /* Restore "normal" registers */
505 xoris r0,r0,MSR_TGPR>>16
506 mtcrf 0x80,r3 /* Restore CR0 */
511 * Handle TLB miss for DATA Load operation on 603/603e
517 * r1: linux style pte ( later becomes ppc hardware pte )
518 * r2: ptr to linux-style pte
521 /* Get PTE (linux-style) and check access */
523 lis r1, TASK_SIZE@h /* check if kernel address */
525 mfspr r2, SPRN_SPRG_PGDIR
527 li r1, _PAGE_PRESENT | _PAGE_ACCESSED
532 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
533 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
534 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
535 lwz r2,0(r2) /* get pmd entry */
536 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
537 beq- DataAddressInvalid /* return if no mapping */
538 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
539 lwz r0,0(r2) /* get linux-style pte */
540 andc. r1,r1,r0 /* check access & ~permission */
541 bne- DataAddressInvalid /* return if access not permitted */
543 * NOTE! We are assuming this is not an SMP system, otherwise
544 * we would need to update the pte atomically with lwarx/stwcx.
546 /* Convert linux-style PTE to low word of PPC-style PTE */
547 rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
548 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
549 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
550 ori r1,r1,0xe04 /* clear out reserved bits */
551 andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
553 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
554 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
556 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
558 BEGIN_MMU_FTR_SECTION
560 mfspr r1,SPRN_SPRG_603_LRU
561 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
565 mtspr SPRN_SPRG_603_LRU,r1
567 rlwimi r2,r0,31-14,14,14
569 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
574 rlwinm r1,r3,9,6,6 /* Get load/store bit */
577 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
579 mfspr r1,SPRN_DMISS /* Get failing address */
580 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
581 beq 20f /* Jump if big endian */
583 20: mtspr SPRN_DAR,r1 /* Set fault address */
584 mfmsr r0 /* Restore "normal" registers */
585 xoris r0,r0,MSR_TGPR>>16
586 mtcrf 0x80,r3 /* Restore CR0 */
591 * Handle TLB miss for DATA Store on 603/603e
597 * r1: linux style pte ( later becomes ppc hardware pte )
598 * r2: ptr to linux-style pte
601 /* Get PTE (linux-style) and check access */
603 lis r1, TASK_SIZE@h /* check if kernel address */
605 mfspr r2, SPRN_SPRG_PGDIR
607 li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
609 li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT
612 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
613 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
614 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
615 lwz r2,0(r2) /* get pmd entry */
616 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
617 beq- DataAddressInvalid /* return if no mapping */
618 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
619 lwz r0,0(r2) /* get linux-style pte */
620 andc. r1,r1,r0 /* check access & ~permission */
621 bne- DataAddressInvalid /* return if access not permitted */
623 * NOTE! We are assuming this is not an SMP system, otherwise
624 * we would need to update the pte atomically with lwarx/stwcx.
626 /* Convert linux-style PTE to low word of PPC-style PTE */
627 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
628 li r1,0xe06 /* clear out reserved bits & PP msb */
629 andc r1,r0,r1 /* PP = user? 1: 0 */
631 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
632 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
634 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
636 BEGIN_MMU_FTR_SECTION
638 mfspr r1,SPRN_SPRG_603_LRU
639 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
643 mtspr SPRN_SPRG_603_LRU,r1
645 rlwimi r2,r0,31-14,14,14
647 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
651 #ifndef CONFIG_ALTIVEC
652 #define altivec_assist_exception unknown_exception
655 #ifndef CONFIG_TAU_INT
656 #define TAUException unknown_exception
659 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_STD)
660 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_STD)
661 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
662 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_STD)
663 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
664 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
665 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
666 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
667 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
668 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_STD)
669 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
670 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
671 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
672 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_STD)
673 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_STD)
674 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_STD)
675 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_STD)
676 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_STD)
677 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_STD)
678 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_STD)
679 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_STD)
680 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_STD)
681 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_STD)
682 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_STD)
683 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_STD)
684 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_STD)
685 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_STD)
686 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_STD)
687 EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_STD)
692 EXC_XFER_STD(0x200, machine_check_exception)
694 alignment_exception_tramp:
695 EXC_XFER_STD(0x600, alignment_exception)
697 handle_page_fault_tramp_1:
698 #ifdef CONFIG_VMAP_STACK
699 EXCEPTION_PROLOG_2 handle_dar_dsisr=1
704 handle_page_fault_tramp_2:
705 EXC_XFER_LITE(0x300, handle_page_fault)
707 #ifdef CONFIG_VMAP_STACK
708 .macro save_regs_thread thread
709 stw r0, THR0(\thread)
710 stw r3, THR3(\thread)
711 stw r4, THR4(\thread)
712 stw r5, THR5(\thread)
713 stw r6, THR6(\thread)
714 stw r8, THR8(\thread)
715 stw r9, THR9(\thread)
717 stw r0, THLR(\thread)
719 stw r0, THCTR(\thread)
722 .macro restore_regs_thread thread
723 lwz r0, THLR(\thread)
725 lwz r0, THCTR(\thread)
727 lwz r0, THR0(\thread)
728 lwz r3, THR3(\thread)
729 lwz r4, THR4(\thread)
730 lwz r5, THR5(\thread)
731 lwz r6, THR6(\thread)
732 lwz r8, THR8(\thread)
733 lwz r9, THR9(\thread)
742 rlwinm r3, r3, 32 - 15, _PAGE_RW /* DSISR_STORE -> _PAGE_RW */
744 mfspr r10, SPRN_SPRG_THREAD
745 restore_regs_thread r10
746 b .Lhash_page_dsi_cont
750 mfspr r10, SPRN_SPRG_THREAD
756 mfspr r10, SPRN_SPRG_THREAD
757 restore_regs_thread r10
759 b .Lhash_page_isi_cont
761 .globl fast_hash_page_return
762 fast_hash_page_return:
763 andis. r10, r9, SRR1_ISI_NOPT@h /* Set on ISI, cleared on DSI */
764 mfspr r10, SPRN_SPRG_THREAD
765 restore_regs_thread r10
771 mfspr r10, SPRN_SPRG_SCRATCH0
776 mfspr r11, SPRN_SPRG_SCRATCH1
777 mfspr r10, SPRN_SPRG_SCRATCH0
781 vmap_stack_overflow_exception
786 #ifdef CONFIG_ALTIVEC
788 bl load_up_altivec /* if from user, just load it up */
789 b fast_exception_return
790 #endif /* CONFIG_ALTIVEC */
791 1: addi r3,r1,STACK_FRAME_OVERHEAD
792 EXC_XFER_LITE(0xf20, altivec_unavailable_exception)
796 addi r3,r1,STACK_FRAME_OVERHEAD
797 EXC_XFER_STD(0xf00, performance_monitor_exception)
801 * This code is jumped to from the startup code to copy
802 * the kernel image to physical address PHYSICAL_START.
805 addis r9,r26,klimit@ha /* fetch klimit */
807 addis r25,r25,-KERNELBASE@h
808 lis r3,PHYSICAL_START@h /* Destination base address */
809 li r6,0 /* Destination offset */
810 li r5,0x4000 /* # bytes of memory to copy */
811 bl copy_and_flush /* copy the first 0x4000 bytes */
812 addi r0,r3,4f@l /* jump to the address of 4f */
813 mtctr r0 /* in copy and do the rest. */
814 bctr /* jump to the copy */
816 bl copy_and_flush /* copy the rest */
820 * Copy routine used to copy the kernel to start at physical address 0
821 * and flush and invalidate the caches as needed.
822 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
823 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
825 _ENTRY(copy_and_flush)
828 4: li r0,L1_CACHE_BYTES/4
830 3: addi r6,r6,4 /* copy a cache line */
834 dcbst r6,r3 /* write it to memory */
836 icbi r6,r3 /* flush the icache line */
839 sync /* additional sync needed on g4 */
846 .globl __secondary_start_mpc86xx
847 __secondary_start_mpc86xx:
849 stw r3, __secondary_hold_acknowledge@l(0)
850 mr r24, r3 /* cpu # */
853 .globl __secondary_start_pmac_0
854 __secondary_start_pmac_0:
855 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
864 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
865 set to map the 0xf0000000 - 0xffffffff region */
867 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
871 .globl __secondary_start
873 /* Copy some CPU settings from CPU 0 */
874 bl __restore_cpu_setup
878 bl call_setup_cpu /* Call setup_cpu for this CPU */
882 /* get current's stack and current */
883 lis r2,secondary_current@ha
885 lwz r2,secondary_current@l(r2)
887 lwz r1,TASK_STACK(r1)
890 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
895 /* load up the MMU */
896 bl load_segment_registers
899 /* ptr to phys current thread */
901 addi r4,r4,THREAD /* phys address of our thread_struct */
902 mtspr SPRN_SPRG_THREAD,r4
903 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
904 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
905 mtspr SPRN_SPRG_PGDIR, r4
907 /* enable MMU and jump to start_secondary */
909 lis r3,start_secondary@h
910 ori r3,r3,start_secondary@l
914 #endif /* CONFIG_SMP */
916 #ifdef CONFIG_KVM_BOOK3S_HANDLER
917 #include "../kvm/book3s_rmhandlers.S"
921 * Load stuff into the MMU. Intended to be called with
925 sync /* Force all PTE updates to finish */
927 tlbia /* Clear all TLB entries */
928 sync /* wait for tlbia/tlbie to finish */
929 TLBSYNC /* ... on all CPUs */
930 /* Load the SDR1 register (hash table base & size) */
931 lis r6, early_hash - PAGE_OFFSET@h
932 ori r6, r6, 3 /* 256kB table */
940 sync /* Force all PTE updates to finish */
942 tlbia /* Clear all TLB entries */
943 sync /* wait for tlbia/tlbie to finish */
944 TLBSYNC /* ... on all CPUs */
945 /* Load the SDR1 register (hash table base & size) */
951 /* Load the BAT registers with the values set up by MMU_init. */
959 BEGIN_MMU_FTR_SECTION
964 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
967 _GLOBAL(load_segment_registers)
968 li r0, NUM_USER_SEGMENTS /* load up user segment register values */
969 mtctr r0 /* for context 0 */
970 li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */
971 #ifdef CONFIG_PPC_KUEP
972 oris r3, r3, SR_NX@h /* Set Nx */
974 #ifdef CONFIG_PPC_KUAP
975 oris r3, r3, SR_KS@h /* Set Ks */
979 addi r3, r3, 0x111 /* increment VSID */
980 addis r4, r4, 0x1000 /* address of next segment */
982 li r0, 16 - NUM_USER_SEGMENTS /* load up kernel segment registers */
983 mtctr r0 /* for context 0 */
984 rlwinm r3, r3, 0, ~SR_NX /* Nx = 0 */
985 rlwinm r3, r3, 0, ~SR_KS /* Ks = 0 */
986 oris r3, r3, SR_KP@h /* Kp = 1 */
988 addi r3, r3, 0x111 /* increment VSID */
989 addis r4, r4, 0x1000 /* address of next segment */
994 * This is where the main kernel code starts.
999 ori r2,r2,init_task@l
1000 /* Set up for using our exception vectors */
1001 /* ptr to phys current thread */
1003 addi r4,r4,THREAD /* init task's THREAD */
1004 mtspr SPRN_SPRG_THREAD,r4
1005 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
1006 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
1007 mtspr SPRN_SPRG_PGDIR, r4
1010 lis r1,init_thread_union@ha
1011 addi r1,r1,init_thread_union@l
1013 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1015 * Do early platform-specific initialization,
1016 * and set up the MMU.
1026 bl MMU_init_hw_patch
1029 * Go back to running unmapped so we can load up new values
1030 * for SDR1 (hash table pointer) and the segment registers
1031 * and change to using our exception vectors.
1036 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1042 /* Load up the kernel context */
1045 #ifdef CONFIG_BDI_SWITCH
1046 /* Add helper information for the Abatron bdiGDB debugger.
1047 * We do this here because we know the mmu is disabled, and
1048 * will be enabled for real in just a few instructions.
1050 lis r5, abatron_pteptrs@h
1051 ori r5, r5, abatron_pteptrs@l
1052 stw r5, 0xf0(0) /* This much match your Abatron config */
1053 lis r6, swapper_pg_dir@h
1054 ori r6, r6, swapper_pg_dir@l
1057 #endif /* CONFIG_BDI_SWITCH */
1059 /* Now turn on the MMU for real! */
1061 lis r3,start_kernel@h
1062 ori r3,r3,start_kernel@l
1068 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1070 * Set up the segment registers for a new context.
1072 _ENTRY(switch_mmu_context)
1073 lwz r3,MMCONTEXTID(r4)
1076 mulli r3,r3,897 /* multiply context by skew factor */
1077 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1078 #ifdef CONFIG_PPC_KUEP
1079 oris r3, r3, SR_NX@h /* Set Nx */
1081 #ifdef CONFIG_PPC_KUAP
1082 oris r3, r3, SR_KS@h /* Set Ks */
1084 li r0,NUM_USER_SEGMENTS
1088 #ifdef CONFIG_BDI_SWITCH
1089 /* Context switch the PTE pointer for the Abatron BDI2000.
1090 * The PGDIR is passed as second argument.
1092 lis r5, abatron_pteptrs@ha
1093 stw r4, abatron_pteptrs@l + 0x4(r5)
1096 mtspr SPRN_SPRG_PGDIR, r4
1101 addi r3,r3,0x111 /* next VSID */
1102 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1103 addis r4,r4,0x1000 /* address of next segment */
1109 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1111 EXPORT_SYMBOL(switch_mmu_context)
1114 * An undocumented "feature" of 604e requires that the v bit
1115 * be cleared before changing BAT values.
1117 * Also, newer IBM firmware does not clear bat3 and 4 so
1118 * this makes sure it's done.
1124 mtspr SPRN_DBAT0U,r10
1125 mtspr SPRN_DBAT0L,r10
1126 mtspr SPRN_DBAT1U,r10
1127 mtspr SPRN_DBAT1L,r10
1128 mtspr SPRN_DBAT2U,r10
1129 mtspr SPRN_DBAT2L,r10
1130 mtspr SPRN_DBAT3U,r10
1131 mtspr SPRN_DBAT3L,r10
1132 mtspr SPRN_IBAT0U,r10
1133 mtspr SPRN_IBAT0L,r10
1134 mtspr SPRN_IBAT1U,r10
1135 mtspr SPRN_IBAT1L,r10
1136 mtspr SPRN_IBAT2U,r10
1137 mtspr SPRN_IBAT2L,r10
1138 mtspr SPRN_IBAT3U,r10
1139 mtspr SPRN_IBAT3L,r10
1140 BEGIN_MMU_FTR_SECTION
1141 /* Here's a tweak: at this point, CPU setup have
1142 * not been called yet, so HIGH_BAT_EN may not be
1143 * set in HID0 for the 745x processors. However, it
1144 * seems that doesn't affect our ability to actually
1145 * write to these SPRs.
1147 mtspr SPRN_DBAT4U,r10
1148 mtspr SPRN_DBAT4L,r10
1149 mtspr SPRN_DBAT5U,r10
1150 mtspr SPRN_DBAT5L,r10
1151 mtspr SPRN_DBAT6U,r10
1152 mtspr SPRN_DBAT6L,r10
1153 mtspr SPRN_DBAT7U,r10
1154 mtspr SPRN_DBAT7L,r10
1155 mtspr SPRN_IBAT4U,r10
1156 mtspr SPRN_IBAT4L,r10
1157 mtspr SPRN_IBAT5U,r10
1158 mtspr SPRN_IBAT5L,r10
1159 mtspr SPRN_IBAT6U,r10
1160 mtspr SPRN_IBAT6L,r10
1161 mtspr SPRN_IBAT7U,r10
1162 mtspr SPRN_IBAT7L,r10
1163 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1172 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
1173 rlwinm r0, r6, 0, ~MSR_RI
1174 rlwinm r0, r0, 0, ~MSR_EE
1185 LOAD_BAT(0, r3, r4, r5)
1186 LOAD_BAT(1, r3, r4, r5)
1187 LOAD_BAT(2, r3, r4, r5)
1188 LOAD_BAT(3, r3, r4, r5)
1189 BEGIN_MMU_FTR_SECTION
1190 LOAD_BAT(4, r3, r4, r5)
1191 LOAD_BAT(5, r3, r4, r5)
1192 LOAD_BAT(6, r3, r4, r5)
1193 LOAD_BAT(7, r3, r4, r5)
1194 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1195 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
1203 1: addic. r10, r10, -0x1000
1210 addi r4, r3, __after_mmu_off - _start
1212 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1222 /* We use one BAT to map up to 256M of RAM at _PAGE_OFFSET */
1224 lis r11,PAGE_OFFSET@h
1227 ori r8,r8,0x12 /* R/W access, M=1 */
1229 ori r8,r8,2 /* R/W access */
1230 #endif /* CONFIG_SMP */
1231 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1233 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx have valid */
1234 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1235 mtspr SPRN_IBAT0L,r8
1236 mtspr SPRN_IBAT0U,r11
1240 #ifdef CONFIG_BOOTX_TEXT
1243 * setup the display bat prepared for us in prom.c
1248 addis r8,r3,disp_BAT@ha
1249 addi r8,r8,disp_BAT@l
1254 mtspr SPRN_DBAT3L,r8
1255 mtspr SPRN_DBAT3U,r11
1257 #endif /* CONFIG_BOOTX_TEXT */
1259 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1263 mtspr SPRN_DBAT1L, r8
1266 ori r11, r11, (BL_1M << 2) | 2
1267 mtspr SPRN_DBAT1U, r11
1272 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1274 /* prepare a BAT for early io */
1275 #if defined(CONFIG_GAMECUBE)
1277 #elif defined(CONFIG_WII)
1280 #error Invalid platform for USB Gecko based early debugging.
1283 * The virtual address used must match the virtual address
1284 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1286 lis r11, 0xfffe /* top 128K */
1287 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1288 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1289 mtspr SPRN_DBAT1L, r8
1290 mtspr SPRN_DBAT1U, r11
1295 /* Jump into the system reset for the rom.
1296 * We first disable the MMU, and then jump to the ROM reset address.
1298 * r3 is the board info structure, r4 is the location for starting.
1299 * I use this for building a small kernel that can load other kernels,
1300 * rather than trying to write or rely on a rom monitor that can tftp load.
1305 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1309 mfspr r11, SPRN_HID0
1311 ori r10,r10,HID0_ICE|HID0_DCE
1313 mtspr SPRN_HID0, r11
1315 li r5, MSR_ME|MSR_RI
1317 addis r6,r6,-KERNELBASE@h
1331 * We put a few things here that have to be page-aligned.
1332 * This stuff goes at the beginning of the data segment,
1333 * which is page-aligned.
1338 .globl empty_zero_page
1341 EXPORT_SYMBOL(empty_zero_page)
1343 .globl swapper_pg_dir
1345 .space PGD_TABLE_SIZE
1347 /* Room for two PTE pointers, usually the kernel and current user pointers
1348 * to their respective root page table.