arch/mips/cavium-octeon/smp.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
   7  */
   8 #include <linux/cpu.h>
   9 #include <linux/delay.h>
  10 #include <linux/smp.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/sched.h>
  14 #include <linux/sched/hotplug.h>
  15 #include <linux/sched/task_stack.h>
  16 #include <linux/init.h>
  17 #include <linux/export.h>
  18 #include <linux/kexec.h>
  19
  20 #include <asm/mmu_context.h>
  21 #include <asm/time.h>
  22 #include <asm/setup.h>
  23
  24 #include <asm/octeon/octeon.h>
  25
  26 #include "octeon_boot.h"
  27
  28 volatile unsigned long octeon_processor_boot = 0xff;
  29 volatile unsigned long octeon_processor_sp;
  30 volatile unsigned long octeon_processor_gp;
  31 #ifdef CONFIG_RELOCATABLE
  32 volatile unsigned long octeon_processor_relocated_kernel_entry;
  33 #endif /* CONFIG_RELOCATABLE */
  34
  35 #ifdef CONFIG_HOTPLUG_CPU
  36 uint64_t octeon_bootloader_entry_addr;
  37 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
  38 #endif
  39
  40 extern void kernel_entry(unsigned long arg1, ...);
  41
  42 static void octeon_icache_flush(void)
  43 {
  44         asm volatile ("synci 0($0)\n");
  45 }
  46
  47 static void (*octeon_message_functions[8])(void) = {
  48         scheduler_ipi,
  49         generic_smp_call_function_interrupt,
  50         octeon_icache_flush,
  51 };
  52
  53 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
  54 {
  55         u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num());
  56         u64 action;
  57         int i;
  58
  59         /*
  60          * Make sure the function array initialization remains
  61          * correct.
  62          */
  63         BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0));
  64         BUILD_BUG_ON(SMP_CALL_FUNCTION       != (1 << 1));
  65         BUILD_BUG_ON(SMP_ICACHE_FLUSH        != (1 << 2));
  66
  67         /*
  68          * Load the mailbox register to figure out what we're supposed
  69          * to do.
  70          */
  71         action = cvmx_read_csr(mbox_clrx);
  72
  73         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  74                 action &= 0xff;
  75         else
  76                 action &= 0xffff;
  77
  78         /* Clear the mailbox to clear the interrupt */
  79         cvmx_write_csr(mbox_clrx, action);
  80
  81         for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) {
  82                 if (action & 1) {
  83                         void (*fn)(void) = octeon_message_functions[i];
  84
  85                         if (fn)
  86                                 fn();
  87                 }
  88                 action >>= 1;
  89                 i++;
  90         }
  91         return IRQ_HANDLED;
  92 }
  93
  94 /**
  95  * Cause the function described by call_data to be executed on the passed
  96  * cpu.  When the function has finished, increment the finished field of
  97  * call_data.
  98  */
  99 void octeon_send_ipi_single(int cpu, unsigned int action)
 100 {
 101         int coreid = cpu_logical_map(cpu);
 102         /*
 103         pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
 104                coreid, action);
 105         */
 106         cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
 107 }
 108
 109 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
 110                                         unsigned int action)
 111 {
 112         unsigned int i;
 113
 114         for_each_cpu(i, mask)
 115                 octeon_send_ipi_single(i, action);
 116 }
 117
 118 /**
 119  * Detect available CPUs, populate cpu_possible_mask
 120  */
 121 static void octeon_smp_hotplug_setup(void)
 122 {
 123 #ifdef CONFIG_HOTPLUG_CPU
 124         struct linux_app_boot_info *labi;
 125
 126         if (!setup_max_cpus)
 127                 return;
 128
 129         labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 130         if (labi->labi_signature != LABI_SIGNATURE) {
 131                 pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
 132                 return;
 133         }
 134
 135         octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
 136 #endif
 137 }
 138
 139 static void __init octeon_smp_setup(void)
 140 {
 141         const int coreid = cvmx_get_core_num();
 142         int cpus;
 143         int id;
 144         struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
 145
 146 #ifdef CONFIG_HOTPLUG_CPU
 147         int core_mask = octeon_get_boot_coremask();
 148         unsigned int num_cores = cvmx_octeon_num_cores();
 149 #endif
 150
 151         /* The present CPUs are initially just the boot cpu (CPU 0). */
 152         for (id = 0; id < NR_CPUS; id++) {
 153                 set_cpu_possible(id, id == 0);
 154                 set_cpu_present(id, id == 0);
 155         }
 156
 157         __cpu_number_map[coreid] = 0;
 158         __cpu_logical_map[0] = coreid;
 159
 160         /* The present CPUs get the lowest CPU numbers. */
 161         cpus = 1;
 162         for (id = 0; id < NR_CPUS; id++) {
 163                 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
 164                         set_cpu_possible(cpus, true);
 165                         set_cpu_present(cpus, true);
 166                         __cpu_number_map[id] = cpus;
 167                         __cpu_logical_map[cpus] = id;
 168                         cpus++;
 169                 }
 170         }
 171
 172 #ifdef CONFIG_HOTPLUG_CPU
 173         /*
 174          * The possible CPUs are all those present on the chip.  We
 175          * will assign CPU numbers for possible cores as well.  Cores
 176          * are always consecutively numberd from 0.
 177          */
 178         for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
 179                      id < num_cores && id < NR_CPUS; id++) {
 180                 if (!(core_mask & (1 << id))) {
 181                         set_cpu_possible(cpus, true);
 182                         __cpu_number_map[id] = cpus;
 183                         __cpu_logical_map[cpus] = id;
 184                         cpus++;
 185                 }
 186         }
 187 #endif
 188
 189         octeon_smp_hotplug_setup();
 190 }
 191
 192
 193 #ifdef CONFIG_RELOCATABLE
 194 int plat_post_relocation(long offset)
 195 {
 196         unsigned long entry = (unsigned long)kernel_entry;
 197
 198         /* Send secondaries into relocated kernel */
 199         octeon_processor_relocated_kernel_entry = entry + offset;
 200
 201         return 0;
 202 }
 203 #endif /* CONFIG_RELOCATABLE */
 204
 205 /**
 206  * Firmware CPU startup hook
 207  *
 208  */
 209 static int octeon_boot_secondary(int cpu, struct task_struct *idle)
 210 {
 211         int count;
 212
 213         pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
 214                 cpu_logical_map(cpu));
 215
 216         octeon_processor_sp = __KSTK_TOS(idle);
 217         octeon_processor_gp = (unsigned long)(task_thread_info(idle));
 218         octeon_processor_boot = cpu_logical_map(cpu);
 219         mb();
 220
 221         count = 10000;
 222         while (octeon_processor_sp && count) {
 223                 /* Waiting for processor to get the SP and GP */
 224                 udelay(1);
 225                 count--;
 226         }
 227         if (count == 0) {
 228                 pr_err("Secondary boot timeout\n");
 229                 return -ETIMEDOUT;
 230         }
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * After we've done initial boot, this function is called to allow the
 237  * board code to clean up state, if needed
 238  */
 239 static void octeon_init_secondary(void)
 240 {
 241         unsigned int sr;
 242
 243         sr = set_c0_status(ST0_BEV);
 244         write_c0_ebase((u32)ebase);
 245         write_c0_status(sr);
 246
 247         octeon_check_cpu_bist();
 248         octeon_init_cvmcount();
 249
 250         octeon_irq_setup_secondary();
 251 }
 252
 253 /**
 254  * Callout to firmware before smp_init
 255  *
 256  */
 257 static void __init octeon_prepare_cpus(unsigned int max_cpus)
 258 {
 259         /*
 260          * Only the low order mailbox bits are used for IPIs, leave
 261          * the other bits alone.
 262          */
 263         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
 264         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
 265                         IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
 266                         mailbox_interrupt)) {
 267                 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
 268         }
 269 }
 270
 271 /**
 272  * Last chance for the board code to finish SMP initialization before
 273  * the CPU is "online".
 274  */
 275 static void octeon_smp_finish(void)
 276 {
 277         octeon_user_io_init();
 278
 279         /* to generate the first CPU timer interrupt */
 280         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 281         local_irq_enable();
 282 }
 283
 284 #ifdef CONFIG_HOTPLUG_CPU
 285
 286 /* State of each CPU. */
 287 static DEFINE_PER_CPU(int, cpu_state);
 288
 289 static int octeon_cpu_disable(void)
 290 {
 291         unsigned int cpu = smp_processor_id();
 292
 293         if (!octeon_bootloader_entry_addr)
 294                 return -ENOTSUPP;
 295
 296         set_cpu_online(cpu, false);
 297         calculate_cpu_foreign_map();
 298         octeon_fixup_irqs();
 299
 300         __flush_cache_all();
 301         local_flush_tlb_all();
 302
 303         return 0;
 304 }
 305
 306 static void octeon_cpu_die(unsigned int cpu)
 307 {
 308         int coreid = cpu_logical_map(cpu);
 309         uint32_t mask, new_mask;
 310         const struct cvmx_bootmem_named_block_desc *block_desc;
 311
 312         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
 313                 cpu_relax();
 314
 315         /*
 316          * This is a bit complicated strategics of getting/settig available
 317          * cores mask, copied from bootloader
 318          */
 319
 320         mask = 1 << coreid;
 321         /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
 322         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 323
 324         if (!block_desc) {
 325                 struct linux_app_boot_info *labi;
 326
 327                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 328
 329                 labi->avail_coremask |= mask;
 330                 new_mask = labi->avail_coremask;
 331         } else {                       /* alternative, already initialized */
 332                 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
 333                                                                AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
 334                 *p |= mask;
 335                 new_mask = *p;
 336         }
 337
 338         pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
 339         mb();
 340         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
 341         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 342 }
 343
 344 void play_dead(void)
 345 {
 346         int cpu = cpu_number_map(cvmx_get_core_num());
 347
 348         idle_task_exit();
 349         octeon_processor_boot = 0xff;
 350         per_cpu(cpu_state, cpu) = CPU_DEAD;
 351
 352         mb();
 353
 354         while (1)       /* core will be reset here */
 355                 ;
 356 }
 357
 358 static void start_after_reset(void)
 359 {
 360         kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
 361 }
 362
 363 static int octeon_update_boot_vector(unsigned int cpu)
 364 {
 365
 366         int coreid = cpu_logical_map(cpu);
 367         uint32_t avail_coremask;
 368         const struct cvmx_bootmem_named_block_desc *block_desc;
 369         struct boot_init_vector *boot_vect =
 370                 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
 371
 372         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 373
 374         if (!block_desc) {
 375                 struct linux_app_boot_info *labi;
 376
 377                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 378
 379                 avail_coremask = labi->avail_coremask;
 380                 labi->avail_coremask &= ~(1 << coreid);
 381         } else {                       /* alternative, already initialized */
 382                 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
 383                         block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
 384         }
 385
 386         if (!(avail_coremask & (1 << coreid))) {
 387                 /* core not available, assume, that caught by simple-executive */
 388                 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
 389                 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 390         }
 391
 392         boot_vect[coreid].app_start_func_addr =
 393                 (uint32_t) (unsigned long) start_after_reset;
 394         boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
 395
 396         mb();
 397
 398         cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
 399
 400         return 0;
 401 }
 402
 403 static int register_cavium_notifier(void)
 404 {
 405         return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
 406                                          "mips/cavium:prepare",
 407                                          octeon_update_boot_vector, NULL);
 408 }
 409 late_initcall(register_cavium_notifier);
 410
 411 #endif  /* CONFIG_HOTPLUG_CPU */
 412
 413 static const struct plat_smp_ops octeon_smp_ops = {
 414         .send_ipi_single        = octeon_send_ipi_single,
 415         .send_ipi_mask          = octeon_send_ipi_mask,
 416         .init_secondary         = octeon_init_secondary,
 417         .smp_finish             = octeon_smp_finish,
 418         .boot_secondary         = octeon_boot_secondary,
 419         .smp_setup              = octeon_smp_setup,
 420         .prepare_cpus           = octeon_prepare_cpus,
 421 #ifdef CONFIG_HOTPLUG_CPU
 422         .cpu_disable            = octeon_cpu_disable,
 423         .cpu_die                = octeon_cpu_die,
 424 #endif
 425 #ifdef CONFIG_KEXEC
 426         .kexec_nonboot_cpu      = kexec_nonboot_cpu_jump,
 427 #endif
 428 };
 429
 430 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id)
 431 {
 432         scheduler_ipi();
 433         return IRQ_HANDLED;
 434 }
 435
 436 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id)
 437 {
 438         generic_smp_call_function_interrupt();
 439         return IRQ_HANDLED;
 440 }
 441
 442 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id)
 443 {
 444         octeon_icache_flush();
 445         return IRQ_HANDLED;
 446 }
 447
 448 /*
 449  * Callout to firmware before smp_init
 450  */
 451 static void octeon_78xx_prepare_cpus(unsigned int max_cpus)
 452 {
 453         if (request_irq(OCTEON_IRQ_MBOX0 + 0,
 454                         octeon_78xx_reched_interrupt,
 455                         IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler",
 456                         octeon_78xx_reched_interrupt)) {
 457                 panic("Cannot request_irq for SchedulerIPI");
 458         }
 459         if (request_irq(OCTEON_IRQ_MBOX0 + 1,
 460                         octeon_78xx_call_function_interrupt,
 461                         IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call",
 462                         octeon_78xx_call_function_interrupt)) {
 463                 panic("Cannot request_irq for SMP-Call");
 464         }
 465         if (request_irq(OCTEON_IRQ_MBOX0 + 2,
 466                         octeon_78xx_icache_flush_interrupt,
 467                         IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush",
 468                         octeon_78xx_icache_flush_interrupt)) {
 469                 panic("Cannot request_irq for ICache-Flush");
 470         }
 471 }
 472
 473 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action)
 474 {
 475         int i;
 476
 477         for (i = 0; i < 8; i++) {
 478                 if (action & 1)
 479                         octeon_ciu3_mbox_send(cpu, i);
 480                 action >>= 1;
 481         }
 482 }
 483
 484 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
 485                                       unsigned int action)
 486 {
 487         unsigned int cpu;
 488
 489         for_each_cpu(cpu, mask)
 490                 octeon_78xx_send_ipi_single(cpu, action);
 491 }
 492
 493 static const struct plat_smp_ops octeon_78xx_smp_ops = {
 494         .send_ipi_single        = octeon_78xx_send_ipi_single,
 495         .send_ipi_mask          = octeon_78xx_send_ipi_mask,
 496         .init_secondary         = octeon_init_secondary,
 497         .smp_finish             = octeon_smp_finish,
 498         .boot_secondary         = octeon_boot_secondary,
 499         .smp_setup              = octeon_smp_setup,
 500         .prepare_cpus           = octeon_78xx_prepare_cpus,
 501 #ifdef CONFIG_HOTPLUG_CPU
 502         .cpu_disable            = octeon_cpu_disable,
 503         .cpu_die                = octeon_cpu_die,
 504 #endif
 505 #ifdef CONFIG_KEXEC
 506         .kexec_nonboot_cpu      = kexec_nonboot_cpu_jump,
 507 #endif
 508 };
 509
 510 void __init octeon_setup_smp(void)
 511 {
 512         const struct plat_smp_ops *ops;
 513
 514         if (octeon_has_feature(OCTEON_FEATURE_CIU3))
 515                 ops = &octeon_78xx_smp_ops;
 516         else
 517                 ops = &octeon_smp_ops;
 518
 519         register_smp_ops(ops);
 520 }