arch/mips/boot/dts/mscc/ocelot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2017 Microsemi Corporation */
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "mscc,ocelot";
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         compatible = "mips,mips24KEc";
  15                         device_type = "cpu";
  16                         clocks = <&cpu_clk>;
  17                         reg = <0>;
  18                 };
  19         };
  20
  21         aliases {
  22                 serial0 = &uart0;
  23         };
  24
  25         cpuintc: interrupt-controller {
  26                 #address-cells = <0>;
  27                 #interrupt-cells = <1>;
  28                 interrupt-controller;
  29                 compatible = "mti,cpu-interrupt-controller";
  30         };
  31
  32         cpu_clk: cpu-clock {
  33                 compatible = "fixed-clock";
  34                 #clock-cells = <0>;
  35                 clock-frequency = <500000000>;
  36         };
  37
  38         ahb_clk: ahb-clk {
  39                 compatible = "fixed-factor-clock";
  40                 #clock-cells = <0>;
  41                 clocks = <&cpu_clk>;
  42                 clock-div = <2>;
  43                 clock-mult = <1>;
  44         };
  45
  46         ahb@70000000 {
  47                 compatible = "simple-bus";
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges = <0 0x70000000 0x2000000>;
  51
  52                 interrupt-parent = <&intc>;
  53
  54                 cpu_ctrl: syscon@0 {
  55                         compatible = "mscc,ocelot-cpu-syscon", "syscon";
  56                         reg = <0x0 0x2c>;
  57                 };
  58
  59                 intc: interrupt-controller@70 {
  60                         compatible = "mscc,ocelot-icpu-intr";
  61                         reg = <0x70 0x70>;
  62                         #interrupt-cells = <1>;
  63                         interrupt-controller;
  64                         interrupt-parent = <&cpuintc>;
  65                         interrupts = <2>;
  66                 };
  67
  68                 uart0: serial@100000 {
  69                         pinctrl-0 = <&uart_pins>;
  70                         pinctrl-names = "default";
  71                         compatible = "ns16550a";
  72                         reg = <0x100000 0x20>;
  73                         interrupts = <6>;
  74                         clocks = <&ahb_clk>;
  75                         reg-io-width = <4>;
  76                         reg-shift = <2>;
  77
  78                         status = "disabled";
  79                 };
  80
  81                 i2c: i2c@100400 {
  82                         compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
  83                         pinctrl-0 = <&i2c_pins>;
  84                         pinctrl-names = "default";
  85                         reg = <0x100400 0x100>, <0x198 0x8>;
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                         interrupts = <8>;
  89                         clocks = <&ahb_clk>;
  90
  91                         status = "disabled";
  92                 };
  93
  94                 uart2: serial@100800 {
  95                         pinctrl-0 = <&uart2_pins>;
  96                         pinctrl-names = "default";
  97                         compatible = "ns16550a";
  98                         reg = <0x100800 0x20>;
  99                         interrupts = <7>;
 100                         clocks = <&ahb_clk>;
 101                         reg-io-width = <4>;
 102                         reg-shift = <2>;
 103
 104                         status = "disabled";
 105                 };
 106
 107                 spi: spi@101000 {
 108                         compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         reg = <0x101000 0x100>, <0x3c 0x18>;
 112                         interrupts = <9>;
 113                         clocks = <&ahb_clk>;
 114
 115                         status = "disabled";
 116                 };
 117
 118                 switch@1010000 {
 119                         compatible = "mscc,vsc7514-switch";
 120                         reg = <0x1010000 0x10000>,
 121                               <0x1030000 0x10000>,
 122                               <0x1080000 0x100>,
 123                               <0x10e0000 0x10000>,
 124                               <0x11e0000 0x100>,
 125                               <0x11f0000 0x100>,
 126                               <0x1200000 0x100>,
 127                               <0x1210000 0x100>,
 128                               <0x1220000 0x100>,
 129                               <0x1230000 0x100>,
 130                               <0x1240000 0x100>,
 131                               <0x1250000 0x100>,
 132                               <0x1260000 0x100>,
 133                               <0x1270000 0x100>,
 134                               <0x1280000 0x100>,
 135                               <0x1800000 0x80000>,
 136                               <0x1880000 0x10000>,
 137                               <0x1040000 0x10000>,
 138                               <0x1050000 0x10000>,
 139                               <0x1060000 0x10000>;
 140                         reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
 141                                     "port2", "port3", "port4", "port5", "port6",
 142                                     "port7", "port8", "port9", "port10", "qsys",
 143                                     "ana", "s0", "s1", "s2";
 144                         interrupts = <18 21 22>;
 145                         interrupt-names = "ptp_rdy", "xtr", "inj";
 146
 147                         ethernet-ports {
 148                                 #address-cells = <1>;
 149                                 #size-cells = <0>;
 150
 151                                 port0: port@0 {
 152                                         reg = <0>;
 153                                 };
 154                                 port1: port@1 {
 155                                         reg = <1>;
 156                                 };
 157                                 port2: port@2 {
 158                                         reg = <2>;
 159                                 };
 160                                 port3: port@3 {
 161                                         reg = <3>;
 162                                 };
 163                                 port4: port@4 {
 164                                         reg = <4>;
 165                                 };
 166                                 port5: port@5 {
 167                                         reg = <5>;
 168                                 };
 169                                 port6: port@6 {
 170                                         reg = <6>;
 171                                 };
 172                                 port7: port@7 {
 173                                         reg = <7>;
 174                                 };
 175                                 port8: port@8 {
 176                                         reg = <8>;
 177                                 };
 178                                 port9: port@9 {
 179                                         reg = <9>;
 180                                 };
 181                                 port10: port@10 {
 182                                         reg = <10>;
 183                                 };
 184                         };
 185                 };
 186
 187                 reset@1070008 {
 188                         compatible = "mscc,ocelot-chip-reset";
 189                         reg = <0x1070008 0x4>;
 190                 };
 191
 192                 gpio: pinctrl@1070034 {
 193                         compatible = "mscc,ocelot-pinctrl";
 194                         reg = <0x1070034 0x68>;
 195                         gpio-controller;
 196                         #gpio-cells = <2>;
 197                         gpio-ranges = <&gpio 0 0 22>;
 198                         interrupt-controller;
 199                         interrupts = <13>;
 200                         #interrupt-cells = <2>;
 201
 202                         i2c_pins: i2c-pins {
 203                                 pins = "GPIO_16", "GPIO_17";
 204                                 function = "twi";
 205                         };
 206
 207                         uart_pins: uart-pins {
 208                                 pins = "GPIO_6", "GPIO_7";
 209                                 function = "uart";
 210                         };
 211
 212                         uart2_pins: uart2-pins {
 213                                 pins = "GPIO_12", "GPIO_13";
 214                                 function = "uart2";
 215                         };
 216
 217                         miim1: miim1 {
 218                                 pins = "GPIO_14", "GPIO_15";
 219                                 function = "miim";
 220                         };
 221
 222                 };
 223
 224                 mdio0: mdio@107009c {
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         compatible = "mscc,ocelot-miim";
 228                         reg = <0x107009c 0x24>, <0x10700f0 0x8>;
 229                         interrupts = <14>;
 230                         status = "disabled";
 231
 232                         phy0: ethernet-phy@0 {
 233                                 reg = <0>;
 234                         };
 235                         phy1: ethernet-phy@1 {
 236                                 reg = <1>;
 237                         };
 238                         phy2: ethernet-phy@2 {
 239                                 reg = <2>;
 240                         };
 241                         phy3: ethernet-phy@3 {
 242                                 reg = <3>;
 243                         };
 244                 };
 245
 246                 mdio1: mdio@10700c0 {
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         compatible = "mscc,ocelot-miim";
 250                         reg = <0x10700c0 0x24>;
 251                         interrupts = <15>;
 252                         pinctrl-names = "default";
 253                         pinctrl-0 = <&miim1>;
 254                         status = "disabled";
 255                 };
 256
 257                 hsio: syscon@10d0000 {
 258                         compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
 259                         reg = <0x10d0000 0x10000>;
 260
 261                         serdes: serdes {
 262                                 compatible = "mscc,vsc7514-serdes";
 263                                 #phy-cells = <2>;
 264                         };
 265                 };
 266         };
 267 };