arch/arm64/kvm/sys_regs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012,2013 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  *
   6  * Derived from arch/arm/kvm/coproc.c:
   7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   8  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   9  *          Christoffer Dall <c.dall@virtualopensystems.com>
  10  */
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/bsearch.h>
  14 #include <linux/kvm_host.h>
  15 #include <linux/mm.h>
  16 #include <linux/printk.h>
  17 #include <linux/uaccess.h>
  18
  19 #include <asm/cacheflush.h>
  20 #include <asm/cputype.h>
  21 #include <asm/debug-monitors.h>
  22 #include <asm/esr.h>
  23 #include <asm/kvm_arm.h>
  24 #include <asm/kvm_emulate.h>
  25 #include <asm/kvm_hyp.h>
  26 #include <asm/kvm_mmu.h>
  27 #include <asm/perf_event.h>
  28 #include <asm/sysreg.h>
  29
  30 #include <trace/events/kvm.h>
  31
  32 #include "sys_regs.h"
  33
  34 #include "trace.h"
  35
  36 /*
  37  * All of this file is extremely similar to the ARM coproc.c, but the
  38  * types are different. My gut feeling is that it should be pretty
  39  * easy to merge, but that would be an ABI breakage -- again. VFP
  40  * would also need to be abstracted.
  41  *
  42  * For AArch32, we only take care of what is being trapped. Anything
  43  * that has to do with init and userspace access has to go via the
  44  * 64bit interface.
  45  */
  46
  47 #define reg_to_encoding(x)                                              \
  48         sys_reg((u32)(x)->Op0, (u32)(x)->Op1,                           \
  49                 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
  50
  51 static bool read_from_write_only(struct kvm_vcpu *vcpu,
  52                                  struct sys_reg_params *params,
  53                                  const struct sys_reg_desc *r)
  54 {
  55         WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
  56         print_sys_reg_instr(params);
  57         kvm_inject_undefined(vcpu);
  58         return false;
  59 }
  60
  61 static bool write_to_read_only(struct kvm_vcpu *vcpu,
  62                                struct sys_reg_params *params,
  63                                const struct sys_reg_desc *r)
  64 {
  65         WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
  66         print_sys_reg_instr(params);
  67         kvm_inject_undefined(vcpu);
  68         return false;
  69 }
  70
  71 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
  72 {
  73         u64 val = 0x8badf00d8badf00d;
  74
  75         if (vcpu->arch.sysregs_loaded_on_cpu &&
  76             __vcpu_read_sys_reg_from_cpu(reg, &val))
  77                 return val;
  78
  79         return __vcpu_sys_reg(vcpu, reg);
  80 }
  81
  82 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
  83 {
  84         if (vcpu->arch.sysregs_loaded_on_cpu &&
  85             __vcpu_write_sys_reg_to_cpu(val, reg))
  86                 return;
  87
  88          __vcpu_sys_reg(vcpu, reg) = val;
  89 }
  90
  91 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  92 static u32 cache_levels;
  93
  94 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  95 #define CSSELR_MAX 14
  96
  97 /* Which cache CCSIDR represents depends on CSSELR value. */
  98 static u32 get_ccsidr(u32 csselr)
  99 {
 100         u32 ccsidr;
 101
 102         /* Make sure noone else changes CSSELR during this! */
 103         local_irq_disable();
 104         write_sysreg(csselr, csselr_el1);
 105         isb();
 106         ccsidr = read_sysreg(ccsidr_el1);
 107         local_irq_enable();
 108
 109         return ccsidr;
 110 }
 111
 112 /*
 113  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
 114  */
 115 static bool access_dcsw(struct kvm_vcpu *vcpu,
 116                         struct sys_reg_params *p,
 117                         const struct sys_reg_desc *r)
 118 {
 119         if (!p->is_write)
 120                 return read_from_write_only(vcpu, p, r);
 121
 122         /*
 123          * Only track S/W ops if we don't have FWB. It still indicates
 124          * that the guest is a bit broken (S/W operations should only
 125          * be done by firmware, knowing that there is only a single
 126          * CPU left in the system, and certainly not from non-secure
 127          * software).
 128          */
 129         if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
 130                 kvm_set_way_flush(vcpu);
 131
 132         return true;
 133 }
 134
 135 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
 136 {
 137         switch (r->aarch32_map) {
 138         case AA32_LO:
 139                 *mask = GENMASK_ULL(31, 0);
 140                 *shift = 0;
 141                 break;
 142         case AA32_HI:
 143                 *mask = GENMASK_ULL(63, 32);
 144                 *shift = 32;
 145                 break;
 146         default:
 147                 *mask = GENMASK_ULL(63, 0);
 148                 *shift = 0;
 149                 break;
 150         }
 151 }
 152
 153 /*
 154  * Generic accessor for VM registers. Only called as long as HCR_TVM
 155  * is set. If the guest enables the MMU, we stop trapping the VM
 156  * sys_regs and leave it in complete control of the caches.
 157  */
 158 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 159                           struct sys_reg_params *p,
 160                           const struct sys_reg_desc *r)
 161 {
 162         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 163         u64 val, mask, shift;
 164
 165         BUG_ON(!p->is_write);
 166
 167         get_access_mask(r, &mask, &shift);
 168
 169         if (~mask) {
 170                 val = vcpu_read_sys_reg(vcpu, r->reg);
 171                 val &= ~mask;
 172         } else {
 173                 val = 0;
 174         }
 175
 176         val |= (p->regval & (mask >> shift)) << shift;
 177         vcpu_write_sys_reg(vcpu, val, r->reg);
 178
 179         kvm_toggle_cache(vcpu, was_enabled);
 180         return true;
 181 }
 182
 183 static bool access_actlr(struct kvm_vcpu *vcpu,
 184                          struct sys_reg_params *p,
 185                          const struct sys_reg_desc *r)
 186 {
 187         u64 mask, shift;
 188
 189         if (p->is_write)
 190                 return ignore_write(vcpu, p);
 191
 192         get_access_mask(r, &mask, &shift);
 193         p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
 194
 195         return true;
 196 }
 197
 198 /*
 199  * Trap handler for the GICv3 SGI generation system register.
 200  * Forward the request to the VGIC emulation.
 201  * The cp15_64 code makes sure this automatically works
 202  * for both AArch64 and AArch32 accesses.
 203  */
 204 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 205                            struct sys_reg_params *p,
 206                            const struct sys_reg_desc *r)
 207 {
 208         bool g1;
 209
 210         if (!p->is_write)
 211                 return read_from_write_only(vcpu, p, r);
 212
 213         /*
 214          * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
 215          * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
 216          * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
 217          * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
 218          * group.
 219          */
 220         if (p->Op0 == 0) {              /* AArch32 */
 221                 switch (p->Op1) {
 222                 default:                /* Keep GCC quiet */
 223                 case 0:                 /* ICC_SGI1R */
 224                         g1 = true;
 225                         break;
 226                 case 1:                 /* ICC_ASGI1R */
 227                 case 2:                 /* ICC_SGI0R */
 228                         g1 = false;
 229                         break;
 230                 }
 231         } else {                        /* AArch64 */
 232                 switch (p->Op2) {
 233                 default:                /* Keep GCC quiet */
 234                 case 5:                 /* ICC_SGI1R_EL1 */
 235                         g1 = true;
 236                         break;
 237                 case 6:                 /* ICC_ASGI1R_EL1 */
 238                 case 7:                 /* ICC_SGI0R_EL1 */
 239                         g1 = false;
 240                         break;
 241                 }
 242         }
 243
 244         vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
 245
 246         return true;
 247 }
 248
 249 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 250                            struct sys_reg_params *p,
 251                            const struct sys_reg_desc *r)
 252 {
 253         if (p->is_write)
 254                 return ignore_write(vcpu, p);
 255
 256         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 257         return true;
 258 }
 259
 260 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 261                         struct sys_reg_params *p,
 262                         const struct sys_reg_desc *r)
 263 {
 264         if (p->is_write)
 265                 return ignore_write(vcpu, p);
 266         else
 267                 return read_zero(vcpu, p);
 268 }
 269
 270 /*
 271  * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
 272  * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
 273  * system, these registers should UNDEF. LORID_EL1 being a RO register, we
 274  * treat it separately.
 275  */
 276 static bool trap_loregion(struct kvm_vcpu *vcpu,
 277                           struct sys_reg_params *p,
 278                           const struct sys_reg_desc *r)
 279 {
 280         u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
 281         u32 sr = reg_to_encoding(r);
 282
 283         if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
 284                 kvm_inject_undefined(vcpu);
 285                 return false;
 286         }
 287
 288         if (p->is_write && sr == SYS_LORID_EL1)
 289                 return write_to_read_only(vcpu, p, r);
 290
 291         return trap_raz_wi(vcpu, p, r);
 292 }
 293
 294 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 295                            struct sys_reg_params *p,
 296                            const struct sys_reg_desc *r)
 297 {
 298         if (p->is_write) {
 299                 return ignore_write(vcpu, p);
 300         } else {
 301                 p->regval = (1 << 3);
 302                 return true;
 303         }
 304 }
 305
 306 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 307                                    struct sys_reg_params *p,
 308                                    const struct sys_reg_desc *r)
 309 {
 310         if (p->is_write) {
 311                 return ignore_write(vcpu, p);
 312         } else {
 313                 p->regval = read_sysreg(dbgauthstatus_el1);
 314                 return true;
 315         }
 316 }
 317
 318 /*
 319  * We want to avoid world-switching all the DBG registers all the
 320  * time:
 321  *
 322  * - If we've touched any debug register, it is likely that we're
 323  *   going to touch more of them. It then makes sense to disable the
 324  *   traps and start doing the save/restore dance
 325  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 326  *   then mandatory to save/restore the registers, as the guest
 327  *   depends on them.
 328  *
 329  * For this, we use a DIRTY bit, indicating the guest has modified the
 330  * debug registers, used as follow:
 331  *
 332  * On guest entry:
 333  * - If the dirty bit is set (because we're coming back from trapping),
 334  *   disable the traps, save host registers, restore guest registers.
 335  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 336  *   set the dirty bit, disable the traps, save host registers,
 337  *   restore guest registers.
 338  * - Otherwise, enable the traps
 339  *
 340  * On guest exit:
 341  * - If the dirty bit is set, save guest registers, restore host
 342  *   registers and clear the dirty bit. This ensure that the host can
 343  *   now use the debug registers.
 344  */
 345 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 346                             struct sys_reg_params *p,
 347                             const struct sys_reg_desc *r)
 348 {
 349         if (p->is_write) {
 350                 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
 351                 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
 352         } else {
 353                 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
 354         }
 355
 356         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 357
 358         return true;
 359 }
 360
 361 /*
 362  * reg_to_dbg/dbg_to_reg
 363  *
 364  * A 32 bit write to a debug register leave top bits alone
 365  * A 32 bit read from a debug register only returns the bottom bits
 366  *
 367  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 368  * hyp.S code switches between host and guest values in future.
 369  */
 370 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 371                        struct sys_reg_params *p,
 372                        const struct sys_reg_desc *rd,
 373                        u64 *dbg_reg)
 374 {
 375         u64 mask, shift, val;
 376
 377         get_access_mask(rd, &mask, &shift);
 378
 379         val = *dbg_reg;
 380         val &= ~mask;
 381         val |= (p->regval & (mask >> shift)) << shift;
 382         *dbg_reg = val;
 383
 384         vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
 385 }
 386
 387 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 388                        struct sys_reg_params *p,
 389                        const struct sys_reg_desc *rd,
 390                        u64 *dbg_reg)
 391 {
 392         u64 mask, shift;
 393
 394         get_access_mask(rd, &mask, &shift);
 395         p->regval = (*dbg_reg & mask) >> shift;
 396 }
 397
 398 static bool trap_bvr(struct kvm_vcpu *vcpu,
 399                      struct sys_reg_params *p,
 400                      const struct sys_reg_desc *rd)
 401 {
 402         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
 403
 404         if (p->is_write)
 405                 reg_to_dbg(vcpu, p, rd, dbg_reg);
 406         else
 407                 dbg_to_reg(vcpu, p, rd, dbg_reg);
 408
 409         trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
 410
 411         return true;
 412 }
 413
 414 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 415                 const struct kvm_one_reg *reg, void __user *uaddr)
 416 {
 417         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
 418
 419         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 420                 return -EFAULT;
 421         return 0;
 422 }
 423
 424 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 425         const struct kvm_one_reg *reg, void __user *uaddr)
 426 {
 427         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
 428
 429         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 430                 return -EFAULT;
 431         return 0;
 432 }
 433
 434 static void reset_bvr(struct kvm_vcpu *vcpu,
 435                       const struct sys_reg_desc *rd)
 436 {
 437         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
 438 }
 439
 440 static bool trap_bcr(struct kvm_vcpu *vcpu,
 441                      struct sys_reg_params *p,
 442                      const struct sys_reg_desc *rd)
 443 {
 444         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
 445
 446         if (p->is_write)
 447                 reg_to_dbg(vcpu, p, rd, dbg_reg);
 448         else
 449                 dbg_to_reg(vcpu, p, rd, dbg_reg);
 450
 451         trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
 452
 453         return true;
 454 }
 455
 456 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 457                 const struct kvm_one_reg *reg, void __user *uaddr)
 458 {
 459         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
 460
 461         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 462                 return -EFAULT;
 463
 464         return 0;
 465 }
 466
 467 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 468         const struct kvm_one_reg *reg, void __user *uaddr)
 469 {
 470         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
 471
 472         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 473                 return -EFAULT;
 474         return 0;
 475 }
 476
 477 static void reset_bcr(struct kvm_vcpu *vcpu,
 478                       const struct sys_reg_desc *rd)
 479 {
 480         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
 481 }
 482
 483 static bool trap_wvr(struct kvm_vcpu *vcpu,
 484                      struct sys_reg_params *p,
 485                      const struct sys_reg_desc *rd)
 486 {
 487         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
 488
 489         if (p->is_write)
 490                 reg_to_dbg(vcpu, p, rd, dbg_reg);
 491         else
 492                 dbg_to_reg(vcpu, p, rd, dbg_reg);
 493
 494         trace_trap_reg(__func__, rd->CRm, p->is_write,
 495                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
 496
 497         return true;
 498 }
 499
 500 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 501                 const struct kvm_one_reg *reg, void __user *uaddr)
 502 {
 503         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
 504
 505         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 506                 return -EFAULT;
 507         return 0;
 508 }
 509
 510 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 511         const struct kvm_one_reg *reg, void __user *uaddr)
 512 {
 513         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
 514
 515         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 516                 return -EFAULT;
 517         return 0;
 518 }
 519
 520 static void reset_wvr(struct kvm_vcpu *vcpu,
 521                       const struct sys_reg_desc *rd)
 522 {
 523         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
 524 }
 525
 526 static bool trap_wcr(struct kvm_vcpu *vcpu,
 527                      struct sys_reg_params *p,
 528                      const struct sys_reg_desc *rd)
 529 {
 530         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
 531
 532         if (p->is_write)
 533                 reg_to_dbg(vcpu, p, rd, dbg_reg);
 534         else
 535                 dbg_to_reg(vcpu, p, rd, dbg_reg);
 536
 537         trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
 538
 539         return true;
 540 }
 541
 542 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 543                 const struct kvm_one_reg *reg, void __user *uaddr)
 544 {
 545         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
 546
 547         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 548                 return -EFAULT;
 549         return 0;
 550 }
 551
 552 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 553         const struct kvm_one_reg *reg, void __user *uaddr)
 554 {
 555         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
 556
 557         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 558                 return -EFAULT;
 559         return 0;
 560 }
 561
 562 static void reset_wcr(struct kvm_vcpu *vcpu,
 563                       const struct sys_reg_desc *rd)
 564 {
 565         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
 566 }
 567
 568 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 569 {
 570         u64 amair = read_sysreg(amair_el1);
 571         vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
 572 }
 573
 574 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 575 {
 576         u64 actlr = read_sysreg(actlr_el1);
 577         vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
 578 }
 579
 580 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 581 {
 582         u64 mpidr;
 583
 584         /*
 585          * Map the vcpu_id into the first three affinity level fields of
 586          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 587          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 588          * of the GICv3 to be able to address each CPU directly when
 589          * sending IPIs.
 590          */
 591         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 592         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 593         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 594         vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
 595 }
 596
 597 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
 598                                    const struct sys_reg_desc *r)
 599 {
 600         if (kvm_vcpu_has_pmu(vcpu))
 601                 return 0;
 602
 603         return REG_HIDDEN;
 604 }
 605
 606 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 607 {
 608         u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
 609
 610         /* No PMU available, any PMU reg may UNDEF... */
 611         if (!kvm_arm_support_pmu_v3())
 612                 return;
 613
 614         n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
 615         n &= ARMV8_PMU_PMCR_N_MASK;
 616         if (n)
 617                 mask |= GENMASK(n - 1, 0);
 618
 619         reset_unknown(vcpu, r);
 620         __vcpu_sys_reg(vcpu, r->reg) &= mask;
 621 }
 622
 623 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 624 {
 625         reset_unknown(vcpu, r);
 626         __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
 627 }
 628
 629 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 630 {
 631         reset_unknown(vcpu, r);
 632         __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
 633 }
 634
 635 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 636 {
 637         reset_unknown(vcpu, r);
 638         __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
 639 }
 640
 641 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 642 {
 643         u64 pmcr, val;
 644
 645         /* No PMU available, PMCR_EL0 may UNDEF... */
 646         if (!kvm_arm_support_pmu_v3())
 647                 return;
 648
 649         pmcr = read_sysreg(pmcr_el0);
 650         /*
 651          * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 652          * except PMCR.E resetting to zero.
 653          */
 654         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 655                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 656         if (!system_supports_32bit_el0())
 657                 val |= ARMV8_PMU_PMCR_LC;
 658         __vcpu_sys_reg(vcpu, r->reg) = val;
 659 }
 660
 661 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
 662 {
 663         u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 664         bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
 665
 666         if (!enabled)
 667                 kvm_inject_undefined(vcpu);
 668
 669         return !enabled;
 670 }
 671
 672 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 673 {
 674         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
 675 }
 676
 677 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 678 {
 679         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
 680 }
 681
 682 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 683 {
 684         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
 685 }
 686
 687 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 688 {
 689         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
 690 }
 691
 692 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 693                         const struct sys_reg_desc *r)
 694 {
 695         u64 val;
 696
 697         if (pmu_access_el0_disabled(vcpu))
 698                 return false;
 699
 700         if (p->is_write) {
 701                 /* Only update writeable bits of PMCR */
 702                 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
 703                 val &= ~ARMV8_PMU_PMCR_MASK;
 704                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 705                 if (!system_supports_32bit_el0())
 706                         val |= ARMV8_PMU_PMCR_LC;
 707                 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 708                 kvm_pmu_handle_pmcr(vcpu, val);
 709                 kvm_vcpu_pmu_restore_guest(vcpu);
 710         } else {
 711                 /* PMCR.P & PMCR.C are RAZ */
 712                 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
 713                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 714                 p->regval = val;
 715         }
 716
 717         return true;
 718 }
 719
 720 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 721                           const struct sys_reg_desc *r)
 722 {
 723         if (pmu_access_event_counter_el0_disabled(vcpu))
 724                 return false;
 725
 726         if (p->is_write)
 727                 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 728         else
 729                 /* return PMSELR.SEL field */
 730                 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
 731                             & ARMV8_PMU_COUNTER_MASK;
 732
 733         return true;
 734 }
 735
 736 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 737                           const struct sys_reg_desc *r)
 738 {
 739         u64 pmceid, mask, shift;
 740
 741         BUG_ON(p->is_write);
 742
 743         if (pmu_access_el0_disabled(vcpu))
 744                 return false;
 745
 746         get_access_mask(r, &mask, &shift);
 747
 748         pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
 749         pmceid &= mask;
 750         pmceid >>= shift;
 751
 752         p->regval = pmceid;
 753
 754         return true;
 755 }
 756
 757 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 758 {
 759         u64 pmcr, val;
 760
 761         pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
 762         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 763         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
 764                 kvm_inject_undefined(vcpu);
 765                 return false;
 766         }
 767
 768         return true;
 769 }
 770
 771 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 772                               struct sys_reg_params *p,
 773                               const struct sys_reg_desc *r)
 774 {
 775         u64 idx = ~0UL;
 776
 777         if (r->CRn == 9 && r->CRm == 13) {
 778                 if (r->Op2 == 2) {
 779                         /* PMXEVCNTR_EL0 */
 780                         if (pmu_access_event_counter_el0_disabled(vcpu))
 781                                 return false;
 782
 783                         idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
 784                               & ARMV8_PMU_COUNTER_MASK;
 785                 } else if (r->Op2 == 0) {
 786                         /* PMCCNTR_EL0 */
 787                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 788                                 return false;
 789
 790                         idx = ARMV8_PMU_CYCLE_IDX;
 791                 }
 792         } else if (r->CRn == 0 && r->CRm == 9) {
 793                 /* PMCCNTR */
 794                 if (pmu_access_event_counter_el0_disabled(vcpu))
 795                         return false;
 796
 797                 idx = ARMV8_PMU_CYCLE_IDX;
 798         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 799                 /* PMEVCNTRn_EL0 */
 800                 if (pmu_access_event_counter_el0_disabled(vcpu))
 801                         return false;
 802
 803                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 804         }
 805
 806         /* Catch any decoding mistake */
 807         WARN_ON(idx == ~0UL);
 808
 809         if (!pmu_counter_idx_valid(vcpu, idx))
 810                 return false;
 811
 812         if (p->is_write) {
 813                 if (pmu_access_el0_disabled(vcpu))
 814                         return false;
 815
 816                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 817         } else {
 818                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 819         }
 820
 821         return true;
 822 }
 823
 824 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 825                                const struct sys_reg_desc *r)
 826 {
 827         u64 idx, reg;
 828
 829         if (pmu_access_el0_disabled(vcpu))
 830                 return false;
 831
 832         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 833                 /* PMXEVTYPER_EL0 */
 834                 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 835                 reg = PMEVTYPER0_EL0 + idx;
 836         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 837                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 838                 if (idx == ARMV8_PMU_CYCLE_IDX)
 839                         reg = PMCCFILTR_EL0;
 840                 else
 841                         /* PMEVTYPERn_EL0 */
 842                         reg = PMEVTYPER0_EL0 + idx;
 843         } else {
 844                 BUG();
 845         }
 846
 847         if (!pmu_counter_idx_valid(vcpu, idx))
 848                 return false;
 849
 850         if (p->is_write) {
 851                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 852                 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 853                 kvm_vcpu_pmu_restore_guest(vcpu);
 854         } else {
 855                 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 856         }
 857
 858         return true;
 859 }
 860
 861 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 862                            const struct sys_reg_desc *r)
 863 {
 864         u64 val, mask;
 865
 866         if (pmu_access_el0_disabled(vcpu))
 867                 return false;
 868
 869         mask = kvm_pmu_valid_counter_mask(vcpu);
 870         if (p->is_write) {
 871                 val = p->regval & mask;
 872                 if (r->Op2 & 0x1) {
 873                         /* accessing PMCNTENSET_EL0 */
 874                         __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 875                         kvm_pmu_enable_counter_mask(vcpu, val);
 876                         kvm_vcpu_pmu_restore_guest(vcpu);
 877                 } else {
 878                         /* accessing PMCNTENCLR_EL0 */
 879                         __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 880                         kvm_pmu_disable_counter_mask(vcpu, val);
 881                 }
 882         } else {
 883                 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
 884         }
 885
 886         return true;
 887 }
 888
 889 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 890                            const struct sys_reg_desc *r)
 891 {
 892         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 893
 894         if (check_pmu_access_disabled(vcpu, 0))
 895                 return false;
 896
 897         if (p->is_write) {
 898                 u64 val = p->regval & mask;
 899
 900                 if (r->Op2 & 0x1)
 901                         /* accessing PMINTENSET_EL1 */
 902                         __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 903                 else
 904                         /* accessing PMINTENCLR_EL1 */
 905                         __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 906         } else {
 907                 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
 908         }
 909
 910         return true;
 911 }
 912
 913 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 914                          const struct sys_reg_desc *r)
 915 {
 916         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 917
 918         if (pmu_access_el0_disabled(vcpu))
 919                 return false;
 920
 921         if (p->is_write) {
 922                 if (r->CRm & 0x2)
 923                         /* accessing PMOVSSET_EL0 */
 924                         __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
 925                 else
 926                         /* accessing PMOVSCLR_EL0 */
 927                         __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 928         } else {
 929                 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
 930         }
 931
 932         return true;
 933 }
 934
 935 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 936                            const struct sys_reg_desc *r)
 937 {
 938         u64 mask;
 939
 940         if (!p->is_write)
 941                 return read_from_write_only(vcpu, p, r);
 942
 943         if (pmu_write_swinc_el0_disabled(vcpu))
 944                 return false;
 945
 946         mask = kvm_pmu_valid_counter_mask(vcpu);
 947         kvm_pmu_software_increment(vcpu, p->regval & mask);
 948         return true;
 949 }
 950
 951 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 952                              const struct sys_reg_desc *r)
 953 {
 954         if (p->is_write) {
 955                 if (!vcpu_mode_priv(vcpu)) {
 956                         kvm_inject_undefined(vcpu);
 957                         return false;
 958                 }
 959
 960                 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
 961                                p->regval & ARMV8_PMU_USERENR_MASK;
 962         } else {
 963                 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 964                             & ARMV8_PMU_USERENR_MASK;
 965         }
 966
 967         return true;
 968 }
 969
 970 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 971 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 972         { SYS_DESC(SYS_DBGBVRn_EL1(n)),                                 \
 973           trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr },                \
 974         { SYS_DESC(SYS_DBGBCRn_EL1(n)),                                 \
 975           trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr },                \
 976         { SYS_DESC(SYS_DBGWVRn_EL1(n)),                                 \
 977           trap_wvr, reset_wvr, 0, 0,  get_wvr, set_wvr },               \
 978         { SYS_DESC(SYS_DBGWCRn_EL1(n)),                                 \
 979           trap_wcr, reset_wcr, 0, 0,  get_wcr, set_wcr }
 980
 981 #define PMU_SYS_REG(r)                                          \
 982         SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
 983
 984 /* Macro to expand the PMEVCNTRn_EL0 register */
 985 #define PMU_PMEVCNTR_EL0(n)                                             \
 986         { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)),                            \
 987           .reset = reset_pmevcntr,                                      \
 988           .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
 989
 990 /* Macro to expand the PMEVTYPERn_EL0 register */
 991 #define PMU_PMEVTYPER_EL0(n)                                            \
 992         { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)),                           \
 993           .reset = reset_pmevtyper,                                     \
 994           .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
 995
 996 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 997                          const struct sys_reg_desc *r)
 998 {
 999         kvm_inject_undefined(vcpu);
1000
1001         return false;
1002 }
1003
1004 /* Macro to expand the AMU counter and type registers*/
1005 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1006 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1007 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1008 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1009
1010 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1011                         const struct sys_reg_desc *rd)
1012 {
1013         return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1014 }
1015
1016 /*
1017  * If we land here on a PtrAuth access, that is because we didn't
1018  * fixup the access on exit by allowing the PtrAuth sysregs. The only
1019  * way this happens is when the guest does not have PtrAuth support
1020  * enabled.
1021  */
1022 #define __PTRAUTH_KEY(k)                                                \
1023         { SYS_DESC(SYS_## k), undef_access, reset_unknown, k,           \
1024         .visibility = ptrauth_visibility}
1025
1026 #define PTRAUTH_KEY(k)                                                  \
1027         __PTRAUTH_KEY(k ## KEYLO_EL1),                                  \
1028         __PTRAUTH_KEY(k ## KEYHI_EL1)
1029
1030 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1031                               struct sys_reg_params *p,
1032                               const struct sys_reg_desc *r)
1033 {
1034         enum kvm_arch_timers tmr;
1035         enum kvm_arch_timer_regs treg;
1036         u64 reg = reg_to_encoding(r);
1037
1038         switch (reg) {
1039         case SYS_CNTP_TVAL_EL0:
1040         case SYS_AARCH32_CNTP_TVAL:
1041                 tmr = TIMER_PTIMER;
1042                 treg = TIMER_REG_TVAL;
1043                 break;
1044         case SYS_CNTP_CTL_EL0:
1045         case SYS_AARCH32_CNTP_CTL:
1046                 tmr = TIMER_PTIMER;
1047                 treg = TIMER_REG_CTL;
1048                 break;
1049         case SYS_CNTP_CVAL_EL0:
1050         case SYS_AARCH32_CNTP_CVAL:
1051                 tmr = TIMER_PTIMER;
1052                 treg = TIMER_REG_CVAL;
1053                 break;
1054         default:
1055                 BUG();
1056         }
1057
1058         if (p->is_write)
1059                 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1060         else
1061                 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1062
1063         return true;
1064 }
1065
1066 #define FEATURE(x)      (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
1067
1068 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1069 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1070                 struct sys_reg_desc const *r, bool raz)
1071 {
1072         u32 id = reg_to_encoding(r);
1073         u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1074
1075         switch (id) {
1076         case SYS_ID_AA64PFR0_EL1:
1077                 if (!vcpu_has_sve(vcpu))
1078                         val &= ~FEATURE(ID_AA64PFR0_SVE);
1079                 val &= ~FEATURE(ID_AA64PFR0_AMU);
1080                 val &= ~FEATURE(ID_AA64PFR0_CSV2);
1081                 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
1082                 val &= ~FEATURE(ID_AA64PFR0_CSV3);
1083                 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
1084                 break;
1085         case SYS_ID_AA64PFR1_EL1:
1086                 val &= ~FEATURE(ID_AA64PFR1_MTE);
1087                 if (kvm_has_mte(vcpu->kvm)) {
1088                         u64 pfr, mte;
1089
1090                         pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
1091                         mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
1092                         val |= FIELD_PREP(FEATURE(ID_AA64PFR1_MTE), mte);
1093                 }
1094                 break;
1095         case SYS_ID_AA64ISAR1_EL1:
1096                 if (!vcpu_has_ptrauth(vcpu))
1097                         val &= ~(FEATURE(ID_AA64ISAR1_APA) |
1098                                  FEATURE(ID_AA64ISAR1_API) |
1099                                  FEATURE(ID_AA64ISAR1_GPA) |
1100                                  FEATURE(ID_AA64ISAR1_GPI));
1101                 break;
1102         case SYS_ID_AA64DFR0_EL1:
1103                 /* Limit debug to ARMv8.0 */
1104                 val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
1105                 val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
1106                 /* Limit guests to PMUv3 for ARMv8.4 */
1107                 val = cpuid_feature_cap_perfmon_field(val,
1108                                                       ID_AA64DFR0_PMUVER_SHIFT,
1109                                                       kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
1110                 /* Hide SPE from guests */
1111                 val &= ~FEATURE(ID_AA64DFR0_PMSVER);
1112                 break;
1113         case SYS_ID_DFR0_EL1:
1114                 /* Limit guests to PMUv3 for ARMv8.4 */
1115                 val = cpuid_feature_cap_perfmon_field(val,
1116                                                       ID_DFR0_PERFMON_SHIFT,
1117                                                       kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
1118                 break;
1119         }
1120
1121         return val;
1122 }
1123
1124 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1125                                   const struct sys_reg_desc *r)
1126 {
1127         u32 id = reg_to_encoding(r);
1128
1129         switch (id) {
1130         case SYS_ID_AA64ZFR0_EL1:
1131                 if (!vcpu_has_sve(vcpu))
1132                         return REG_RAZ;
1133                 break;
1134         }
1135
1136         return 0;
1137 }
1138
1139 /* cpufeature ID register access trap handlers */
1140
1141 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1142                             struct sys_reg_params *p,
1143                             const struct sys_reg_desc *r,
1144                             bool raz)
1145 {
1146         if (p->is_write)
1147                 return write_to_read_only(vcpu, p, r);
1148
1149         p->regval = read_id_reg(vcpu, r, raz);
1150         return true;
1151 }
1152
1153 static bool access_id_reg(struct kvm_vcpu *vcpu,
1154                           struct sys_reg_params *p,
1155                           const struct sys_reg_desc *r)
1156 {
1157         bool raz = sysreg_visible_as_raz(vcpu, r);
1158
1159         return __access_id_reg(vcpu, p, r, raz);
1160 }
1161
1162 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1163                               struct sys_reg_params *p,
1164                               const struct sys_reg_desc *r)
1165 {
1166         return __access_id_reg(vcpu, p, r, true);
1167 }
1168
1169 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1170 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1171 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1172
1173 /* Visibility overrides for SVE-specific control registers */
1174 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1175                                    const struct sys_reg_desc *rd)
1176 {
1177         if (vcpu_has_sve(vcpu))
1178                 return 0;
1179
1180         return REG_HIDDEN;
1181 }
1182
1183 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1184                                const struct sys_reg_desc *rd,
1185                                const struct kvm_one_reg *reg, void __user *uaddr)
1186 {
1187         const u64 id = sys_reg_to_index(rd);
1188         u8 csv2, csv3;
1189         int err;
1190         u64 val;
1191
1192         err = reg_from_user(&val, uaddr, id);
1193         if (err)
1194                 return err;
1195
1196         /*
1197          * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1198          * it doesn't promise more than what is actually provided (the
1199          * guest could otherwise be covered in ectoplasmic residue).
1200          */
1201         csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1202         if (csv2 > 1 ||
1203             (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1204                 return -EINVAL;
1205
1206         /* Same thing for CSV3 */
1207         csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT);
1208         if (csv3 > 1 ||
1209             (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
1210                 return -EINVAL;
1211
1212         /* We can only differ with CSV[23], and anything else is an error */
1213         val ^= read_id_reg(vcpu, rd, false);
1214         val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
1215                  (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
1216         if (val)
1217                 return -EINVAL;
1218
1219         vcpu->kvm->arch.pfr0_csv2 = csv2;
1220         vcpu->kvm->arch.pfr0_csv3 = csv3 ;
1221
1222         return 0;
1223 }
1224
1225 /*
1226  * cpufeature ID register user accessors
1227  *
1228  * For now, these registers are immutable for userspace, so no values
1229  * are stored, and for set_id_reg() we don't allow the effective value
1230  * to be changed.
1231  */
1232 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1233                         const struct sys_reg_desc *rd, void __user *uaddr,
1234                         bool raz)
1235 {
1236         const u64 id = sys_reg_to_index(rd);
1237         const u64 val = read_id_reg(vcpu, rd, raz);
1238
1239         return reg_to_user(uaddr, &val, id);
1240 }
1241
1242 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1243                         const struct sys_reg_desc *rd, void __user *uaddr,
1244                         bool raz)
1245 {
1246         const u64 id = sys_reg_to_index(rd);
1247         int err;
1248         u64 val;
1249
1250         err = reg_from_user(&val, uaddr, id);
1251         if (err)
1252                 return err;
1253
1254         /* This is what we mean by invariant: you can't change it. */
1255         if (val != read_id_reg(vcpu, rd, raz))
1256                 return -EINVAL;
1257
1258         return 0;
1259 }
1260
1261 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1262                       const struct kvm_one_reg *reg, void __user *uaddr)
1263 {
1264         bool raz = sysreg_visible_as_raz(vcpu, rd);
1265
1266         return __get_id_reg(vcpu, rd, uaddr, raz);
1267 }
1268
1269 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1270                       const struct kvm_one_reg *reg, void __user *uaddr)
1271 {
1272         bool raz = sysreg_visible_as_raz(vcpu, rd);
1273
1274         return __set_id_reg(vcpu, rd, uaddr, raz);
1275 }
1276
1277 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1278                           const struct kvm_one_reg *reg, void __user *uaddr)
1279 {
1280         return __get_id_reg(vcpu, rd, uaddr, true);
1281 }
1282
1283 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1284                           const struct kvm_one_reg *reg, void __user *uaddr)
1285 {
1286         return __set_id_reg(vcpu, rd, uaddr, true);
1287 }
1288
1289 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1290                       const struct kvm_one_reg *reg, void __user *uaddr)
1291 {
1292         int err;
1293         u64 val;
1294
1295         /* Perform the access even if we are going to ignore the value */
1296         err = reg_from_user(&val, uaddr, sys_reg_to_index(rd));
1297         if (err)
1298                 return err;
1299
1300         return 0;
1301 }
1302
1303 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1304                        const struct sys_reg_desc *r)
1305 {
1306         if (p->is_write)
1307                 return write_to_read_only(vcpu, p, r);
1308
1309         p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1310         return true;
1311 }
1312
1313 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1314                          const struct sys_reg_desc *r)
1315 {
1316         if (p->is_write)
1317                 return write_to_read_only(vcpu, p, r);
1318
1319         p->regval = read_sysreg(clidr_el1);
1320         return true;
1321 }
1322
1323 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1324                           const struct sys_reg_desc *r)
1325 {
1326         int reg = r->reg;
1327
1328         if (p->is_write)
1329                 vcpu_write_sys_reg(vcpu, p->regval, reg);
1330         else
1331                 p->regval = vcpu_read_sys_reg(vcpu, reg);
1332         return true;
1333 }
1334
1335 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1336                           const struct sys_reg_desc *r)
1337 {
1338         u32 csselr;
1339
1340         if (p->is_write)
1341                 return write_to_read_only(vcpu, p, r);
1342
1343         csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1344         p->regval = get_ccsidr(csselr);
1345
1346         /*
1347          * Guests should not be doing cache operations by set/way at all, and
1348          * for this reason, we trap them and attempt to infer the intent, so
1349          * that we can flush the entire guest's address space at the appropriate
1350          * time.
1351          * To prevent this trapping from causing performance problems, let's
1352          * expose the geometry of all data and unified caches (which are
1353          * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1354          * [If guests should attempt to infer aliasing properties from the
1355          * geometry (which is not permitted by the architecture), they would
1356          * only do so for virtually indexed caches.]
1357          */
1358         if (!(csselr & 1)) // data or unified cache
1359                 p->regval &= ~GENMASK(27, 3);
1360         return true;
1361 }
1362
1363 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1364                                    const struct sys_reg_desc *rd)
1365 {
1366         if (kvm_has_mte(vcpu->kvm))
1367                 return 0;
1368
1369         return REG_HIDDEN;
1370 }
1371
1372 #define MTE_REG(name) {                         \
1373         SYS_DESC(SYS_##name),                   \
1374         .access = undef_access,                 \
1375         .reset = reset_unknown,                 \
1376         .reg = name,                            \
1377         .visibility = mte_visibility,           \
1378 }
1379
1380 /* sys_reg_desc initialiser for known cpufeature ID registers */
1381 #define ID_SANITISED(name) {                    \
1382         SYS_DESC(SYS_##name),                   \
1383         .access = access_id_reg,                \
1384         .get_user = get_id_reg,                 \
1385         .set_user = set_id_reg,                 \
1386         .visibility = id_visibility,            \
1387 }
1388
1389 /*
1390  * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1391  * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1392  * (1 <= crm < 8, 0 <= Op2 < 8).
1393  */
1394 #define ID_UNALLOCATED(crm, op2) {                      \
1395         Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),     \
1396         .access = access_raz_id_reg,                    \
1397         .get_user = get_raz_id_reg,                     \
1398         .set_user = set_raz_id_reg,                     \
1399 }
1400
1401 /*
1402  * sys_reg_desc initialiser for known ID registers that we hide from guests.
1403  * For now, these are exposed just like unallocated ID regs: they appear
1404  * RAZ for the guest.
1405  */
1406 #define ID_HIDDEN(name) {                       \
1407         SYS_DESC(SYS_##name),                   \
1408         .access = access_raz_id_reg,            \
1409         .get_user = get_raz_id_reg,             \
1410         .set_user = set_raz_id_reg,             \
1411 }
1412
1413 /*
1414  * Architected system registers.
1415  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1416  *
1417  * Debug handling: We do trap most, if not all debug related system
1418  * registers. The implementation is good enough to ensure that a guest
1419  * can use these with minimal performance degradation. The drawback is
1420  * that we don't implement any of the external debug, none of the
1421  * OSlock protocol. This should be revisited if we ever encounter a
1422  * more demanding guest...
1423  */
1424 static const struct sys_reg_desc sys_reg_descs[] = {
1425         { SYS_DESC(SYS_DC_ISW), access_dcsw },
1426         { SYS_DESC(SYS_DC_CSW), access_dcsw },
1427         { SYS_DESC(SYS_DC_CISW), access_dcsw },
1428
1429         DBG_BCR_BVR_WCR_WVR_EL1(0),
1430         DBG_BCR_BVR_WCR_WVR_EL1(1),
1431         { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1432         { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1433         DBG_BCR_BVR_WCR_WVR_EL1(2),
1434         DBG_BCR_BVR_WCR_WVR_EL1(3),
1435         DBG_BCR_BVR_WCR_WVR_EL1(4),
1436         DBG_BCR_BVR_WCR_WVR_EL1(5),
1437         DBG_BCR_BVR_WCR_WVR_EL1(6),
1438         DBG_BCR_BVR_WCR_WVR_EL1(7),
1439         DBG_BCR_BVR_WCR_WVR_EL1(8),
1440         DBG_BCR_BVR_WCR_WVR_EL1(9),
1441         DBG_BCR_BVR_WCR_WVR_EL1(10),
1442         DBG_BCR_BVR_WCR_WVR_EL1(11),
1443         DBG_BCR_BVR_WCR_WVR_EL1(12),
1444         DBG_BCR_BVR_WCR_WVR_EL1(13),
1445         DBG_BCR_BVR_WCR_WVR_EL1(14),
1446         DBG_BCR_BVR_WCR_WVR_EL1(15),
1447
1448         { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1449         { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1450         { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1451         { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1452         { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1453         { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1454         { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1455         { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1456
1457         { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1458         { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1459         // DBGDTR[TR]X_EL0 share the same encoding
1460         { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1461
1462         { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1463
1464         { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1465
1466         /*
1467          * ID regs: all ID_SANITISED() entries here must have corresponding
1468          * entries in arm64_ftr_regs[].
1469          */
1470
1471         /* AArch64 mappings of the AArch32 ID registers */
1472         /* CRm=1 */
1473         ID_SANITISED(ID_PFR0_EL1),
1474         ID_SANITISED(ID_PFR1_EL1),
1475         ID_SANITISED(ID_DFR0_EL1),
1476         ID_HIDDEN(ID_AFR0_EL1),
1477         ID_SANITISED(ID_MMFR0_EL1),
1478         ID_SANITISED(ID_MMFR1_EL1),
1479         ID_SANITISED(ID_MMFR2_EL1),
1480         ID_SANITISED(ID_MMFR3_EL1),
1481
1482         /* CRm=2 */
1483         ID_SANITISED(ID_ISAR0_EL1),
1484         ID_SANITISED(ID_ISAR1_EL1),
1485         ID_SANITISED(ID_ISAR2_EL1),
1486         ID_SANITISED(ID_ISAR3_EL1),
1487         ID_SANITISED(ID_ISAR4_EL1),
1488         ID_SANITISED(ID_ISAR5_EL1),
1489         ID_SANITISED(ID_MMFR4_EL1),
1490         ID_SANITISED(ID_ISAR6_EL1),
1491
1492         /* CRm=3 */
1493         ID_SANITISED(MVFR0_EL1),
1494         ID_SANITISED(MVFR1_EL1),
1495         ID_SANITISED(MVFR2_EL1),
1496         ID_UNALLOCATED(3,3),
1497         ID_SANITISED(ID_PFR2_EL1),
1498         ID_HIDDEN(ID_DFR1_EL1),
1499         ID_SANITISED(ID_MMFR5_EL1),
1500         ID_UNALLOCATED(3,7),
1501
1502         /* AArch64 ID registers */
1503         /* CRm=4 */
1504         { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1505           .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1506         ID_SANITISED(ID_AA64PFR1_EL1),
1507         ID_UNALLOCATED(4,2),
1508         ID_UNALLOCATED(4,3),
1509         ID_SANITISED(ID_AA64ZFR0_EL1),
1510         ID_UNALLOCATED(4,5),
1511         ID_UNALLOCATED(4,6),
1512         ID_UNALLOCATED(4,7),
1513
1514         /* CRm=5 */
1515         ID_SANITISED(ID_AA64DFR0_EL1),
1516         ID_SANITISED(ID_AA64DFR1_EL1),
1517         ID_UNALLOCATED(5,2),
1518         ID_UNALLOCATED(5,3),
1519         ID_HIDDEN(ID_AA64AFR0_EL1),
1520         ID_HIDDEN(ID_AA64AFR1_EL1),
1521         ID_UNALLOCATED(5,6),
1522         ID_UNALLOCATED(5,7),
1523
1524         /* CRm=6 */
1525         ID_SANITISED(ID_AA64ISAR0_EL1),
1526         ID_SANITISED(ID_AA64ISAR1_EL1),
1527         ID_UNALLOCATED(6,2),
1528         ID_UNALLOCATED(6,3),
1529         ID_UNALLOCATED(6,4),
1530         ID_UNALLOCATED(6,5),
1531         ID_UNALLOCATED(6,6),
1532         ID_UNALLOCATED(6,7),
1533
1534         /* CRm=7 */
1535         ID_SANITISED(ID_AA64MMFR0_EL1),
1536         ID_SANITISED(ID_AA64MMFR1_EL1),
1537         ID_SANITISED(ID_AA64MMFR2_EL1),
1538         ID_UNALLOCATED(7,3),
1539         ID_UNALLOCATED(7,4),
1540         ID_UNALLOCATED(7,5),
1541         ID_UNALLOCATED(7,6),
1542         ID_UNALLOCATED(7,7),
1543
1544         { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1545         { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1546         { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1547
1548         MTE_REG(RGSR_EL1),
1549         MTE_REG(GCR_EL1),
1550
1551         { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1552         { SYS_DESC(SYS_TRFCR_EL1), undef_access },
1553         { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1554         { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1555         { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1556
1557         PTRAUTH_KEY(APIA),
1558         PTRAUTH_KEY(APIB),
1559         PTRAUTH_KEY(APDA),
1560         PTRAUTH_KEY(APDB),
1561         PTRAUTH_KEY(APGA),
1562
1563         { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1564         { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1565         { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1566
1567         { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1568         { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1569         { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1570         { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1571         { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1572         { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1573         { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1574         { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1575
1576         MTE_REG(TFSR_EL1),
1577         MTE_REG(TFSRE0_EL1),
1578
1579         { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1580         { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1581
1582         { SYS_DESC(SYS_PMSCR_EL1), undef_access },
1583         { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
1584         { SYS_DESC(SYS_PMSICR_EL1), undef_access },
1585         { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
1586         { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
1587         { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
1588         { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
1589         { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
1590         { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
1591         { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
1592         { SYS_DESC(SYS_PMBSR_EL1), undef_access },
1593         /* PMBIDR_EL1 is not trapped */
1594
1595         { PMU_SYS_REG(SYS_PMINTENSET_EL1),
1596           .access = access_pminten, .reg = PMINTENSET_EL1 },
1597         { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
1598           .access = access_pminten, .reg = PMINTENSET_EL1 },
1599         { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
1600
1601         { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1602         { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1603
1604         { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1605         { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1606         { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1607         { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1608         { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1609
1610         { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1611         { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1612
1613         { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1614         { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1615         { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1616         { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1617         { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1618         { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1619         { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1620         { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1621         { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1622         { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1623         { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1624         { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1625
1626         { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1627         { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1628
1629         { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1630
1631         { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1632
1633         { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1634         { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1635         { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1636         { SYS_DESC(SYS_CTR_EL0), access_ctr },
1637
1638         { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
1639           .reset = reset_pmcr, .reg = PMCR_EL0 },
1640         { PMU_SYS_REG(SYS_PMCNTENSET_EL0),
1641           .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1642         { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),
1643           .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1644         { PMU_SYS_REG(SYS_PMOVSCLR_EL0),
1645           .access = access_pmovs, .reg = PMOVSSET_EL0 },
1646         /*
1647          * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
1648          * previously (and pointlessly) advertised in the past...
1649          */
1650         { PMU_SYS_REG(SYS_PMSWINC_EL0),
1651           .get_user = get_raz_id_reg, .set_user = set_wi_reg,
1652           .access = access_pmswinc, .reset = NULL },
1653         { PMU_SYS_REG(SYS_PMSELR_EL0),
1654           .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
1655         { PMU_SYS_REG(SYS_PMCEID0_EL0),
1656           .access = access_pmceid, .reset = NULL },
1657         { PMU_SYS_REG(SYS_PMCEID1_EL0),
1658           .access = access_pmceid, .reset = NULL },
1659         { PMU_SYS_REG(SYS_PMCCNTR_EL0),
1660           .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 },
1661         { PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
1662           .access = access_pmu_evtyper, .reset = NULL },
1663         { PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
1664           .access = access_pmu_evcntr, .reset = NULL },
1665         /*
1666          * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1667          * in 32bit mode. Here we choose to reset it as zero for consistency.
1668          */
1669         { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr,
1670           .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
1671         { PMU_SYS_REG(SYS_PMOVSSET_EL0),
1672           .access = access_pmovs, .reg = PMOVSSET_EL0 },
1673
1674         { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1675         { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1676
1677         { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1678
1679         { SYS_DESC(SYS_AMCR_EL0), undef_access },
1680         { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1681         { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1682         { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1683         { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1684         { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1685         { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1686         { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1687         AMU_AMEVCNTR0_EL0(0),
1688         AMU_AMEVCNTR0_EL0(1),
1689         AMU_AMEVCNTR0_EL0(2),
1690         AMU_AMEVCNTR0_EL0(3),
1691         AMU_AMEVCNTR0_EL0(4),
1692         AMU_AMEVCNTR0_EL0(5),
1693         AMU_AMEVCNTR0_EL0(6),
1694         AMU_AMEVCNTR0_EL0(7),
1695         AMU_AMEVCNTR0_EL0(8),
1696         AMU_AMEVCNTR0_EL0(9),
1697         AMU_AMEVCNTR0_EL0(10),
1698         AMU_AMEVCNTR0_EL0(11),
1699         AMU_AMEVCNTR0_EL0(12),
1700         AMU_AMEVCNTR0_EL0(13),
1701         AMU_AMEVCNTR0_EL0(14),
1702         AMU_AMEVCNTR0_EL0(15),
1703         AMU_AMEVTYPER0_EL0(0),
1704         AMU_AMEVTYPER0_EL0(1),
1705         AMU_AMEVTYPER0_EL0(2),
1706         AMU_AMEVTYPER0_EL0(3),
1707         AMU_AMEVTYPER0_EL0(4),
1708         AMU_AMEVTYPER0_EL0(5),
1709         AMU_AMEVTYPER0_EL0(6),
1710         AMU_AMEVTYPER0_EL0(7),
1711         AMU_AMEVTYPER0_EL0(8),
1712         AMU_AMEVTYPER0_EL0(9),
1713         AMU_AMEVTYPER0_EL0(10),
1714         AMU_AMEVTYPER0_EL0(11),
1715         AMU_AMEVTYPER0_EL0(12),
1716         AMU_AMEVTYPER0_EL0(13),
1717         AMU_AMEVTYPER0_EL0(14),
1718         AMU_AMEVTYPER0_EL0(15),
1719         AMU_AMEVCNTR1_EL0(0),
1720         AMU_AMEVCNTR1_EL0(1),
1721         AMU_AMEVCNTR1_EL0(2),
1722         AMU_AMEVCNTR1_EL0(3),
1723         AMU_AMEVCNTR1_EL0(4),
1724         AMU_AMEVCNTR1_EL0(5),
1725         AMU_AMEVCNTR1_EL0(6),
1726         AMU_AMEVCNTR1_EL0(7),
1727         AMU_AMEVCNTR1_EL0(8),
1728         AMU_AMEVCNTR1_EL0(9),
1729         AMU_AMEVCNTR1_EL0(10),
1730         AMU_AMEVCNTR1_EL0(11),
1731         AMU_AMEVCNTR1_EL0(12),
1732         AMU_AMEVCNTR1_EL0(13),
1733         AMU_AMEVCNTR1_EL0(14),
1734         AMU_AMEVCNTR1_EL0(15),
1735         AMU_AMEVTYPER1_EL0(0),
1736         AMU_AMEVTYPER1_EL0(1),
1737         AMU_AMEVTYPER1_EL0(2),
1738         AMU_AMEVTYPER1_EL0(3),
1739         AMU_AMEVTYPER1_EL0(4),
1740         AMU_AMEVTYPER1_EL0(5),
1741         AMU_AMEVTYPER1_EL0(6),
1742         AMU_AMEVTYPER1_EL0(7),
1743         AMU_AMEVTYPER1_EL0(8),
1744         AMU_AMEVTYPER1_EL0(9),
1745         AMU_AMEVTYPER1_EL0(10),
1746         AMU_AMEVTYPER1_EL0(11),
1747         AMU_AMEVTYPER1_EL0(12),
1748         AMU_AMEVTYPER1_EL0(13),
1749         AMU_AMEVTYPER1_EL0(14),
1750         AMU_AMEVTYPER1_EL0(15),
1751
1752         { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1753         { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1754         { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1755
1756         /* PMEVCNTRn_EL0 */
1757         PMU_PMEVCNTR_EL0(0),
1758         PMU_PMEVCNTR_EL0(1),
1759         PMU_PMEVCNTR_EL0(2),
1760         PMU_PMEVCNTR_EL0(3),
1761         PMU_PMEVCNTR_EL0(4),
1762         PMU_PMEVCNTR_EL0(5),
1763         PMU_PMEVCNTR_EL0(6),
1764         PMU_PMEVCNTR_EL0(7),
1765         PMU_PMEVCNTR_EL0(8),
1766         PMU_PMEVCNTR_EL0(9),
1767         PMU_PMEVCNTR_EL0(10),
1768         PMU_PMEVCNTR_EL0(11),
1769         PMU_PMEVCNTR_EL0(12),
1770         PMU_PMEVCNTR_EL0(13),
1771         PMU_PMEVCNTR_EL0(14),
1772         PMU_PMEVCNTR_EL0(15),
1773         PMU_PMEVCNTR_EL0(16),
1774         PMU_PMEVCNTR_EL0(17),
1775         PMU_PMEVCNTR_EL0(18),
1776         PMU_PMEVCNTR_EL0(19),
1777         PMU_PMEVCNTR_EL0(20),
1778         PMU_PMEVCNTR_EL0(21),
1779         PMU_PMEVCNTR_EL0(22),
1780         PMU_PMEVCNTR_EL0(23),
1781         PMU_PMEVCNTR_EL0(24),
1782         PMU_PMEVCNTR_EL0(25),
1783         PMU_PMEVCNTR_EL0(26),
1784         PMU_PMEVCNTR_EL0(27),
1785         PMU_PMEVCNTR_EL0(28),
1786         PMU_PMEVCNTR_EL0(29),
1787         PMU_PMEVCNTR_EL0(30),
1788         /* PMEVTYPERn_EL0 */
1789         PMU_PMEVTYPER_EL0(0),
1790         PMU_PMEVTYPER_EL0(1),
1791         PMU_PMEVTYPER_EL0(2),
1792         PMU_PMEVTYPER_EL0(3),
1793         PMU_PMEVTYPER_EL0(4),
1794         PMU_PMEVTYPER_EL0(5),
1795         PMU_PMEVTYPER_EL0(6),
1796         PMU_PMEVTYPER_EL0(7),
1797         PMU_PMEVTYPER_EL0(8),
1798         PMU_PMEVTYPER_EL0(9),
1799         PMU_PMEVTYPER_EL0(10),
1800         PMU_PMEVTYPER_EL0(11),
1801         PMU_PMEVTYPER_EL0(12),
1802         PMU_PMEVTYPER_EL0(13),
1803         PMU_PMEVTYPER_EL0(14),
1804         PMU_PMEVTYPER_EL0(15),
1805         PMU_PMEVTYPER_EL0(16),
1806         PMU_PMEVTYPER_EL0(17),
1807         PMU_PMEVTYPER_EL0(18),
1808         PMU_PMEVTYPER_EL0(19),
1809         PMU_PMEVTYPER_EL0(20),
1810         PMU_PMEVTYPER_EL0(21),
1811         PMU_PMEVTYPER_EL0(22),
1812         PMU_PMEVTYPER_EL0(23),
1813         PMU_PMEVTYPER_EL0(24),
1814         PMU_PMEVTYPER_EL0(25),
1815         PMU_PMEVTYPER_EL0(26),
1816         PMU_PMEVTYPER_EL0(27),
1817         PMU_PMEVTYPER_EL0(28),
1818         PMU_PMEVTYPER_EL0(29),
1819         PMU_PMEVTYPER_EL0(30),
1820         /*
1821          * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1822          * in 32bit mode. Here we choose to reset it as zero for consistency.
1823          */
1824         { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper,
1825           .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
1826
1827         { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1828         { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1829         { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1830 };
1831
1832 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
1833                         struct sys_reg_params *p,
1834                         const struct sys_reg_desc *r)
1835 {
1836         if (p->is_write) {
1837                 return ignore_write(vcpu, p);
1838         } else {
1839                 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1840                 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1841                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1842
1843                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1844                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1845                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1846                              | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
1847                 return true;
1848         }
1849 }
1850
1851 /*
1852  * AArch32 debug register mappings
1853  *
1854  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1855  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1856  *
1857  * None of the other registers share their location, so treat them as
1858  * if they were 64bit.
1859  */
1860 #define DBG_BCR_BVR_WCR_WVR(n)                                                \
1861         /* DBGBVRn */                                                         \
1862         { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1863         /* DBGBCRn */                                                         \
1864         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },           \
1865         /* DBGWVRn */                                                         \
1866         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },           \
1867         /* DBGWCRn */                                                         \
1868         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1869
1870 #define DBGBXVR(n)                                                            \
1871         { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1872
1873 /*
1874  * Trapped cp14 registers. We generally ignore most of the external
1875  * debug, on the principle that they don't really make sense to a
1876  * guest. Revisit this one day, would this principle change.
1877  */
1878 static const struct sys_reg_desc cp14_regs[] = {
1879         /* DBGDIDR */
1880         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1881         /* DBGDTRRXext */
1882         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1883
1884         DBG_BCR_BVR_WCR_WVR(0),
1885         /* DBGDSCRint */
1886         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1887         DBG_BCR_BVR_WCR_WVR(1),
1888         /* DBGDCCINT */
1889         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
1890         /* DBGDSCRext */
1891         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
1892         DBG_BCR_BVR_WCR_WVR(2),
1893         /* DBGDTR[RT]Xint */
1894         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1895         /* DBGDTR[RT]Xext */
1896         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1897         DBG_BCR_BVR_WCR_WVR(3),
1898         DBG_BCR_BVR_WCR_WVR(4),
1899         DBG_BCR_BVR_WCR_WVR(5),
1900         /* DBGWFAR */
1901         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1902         /* DBGOSECCR */
1903         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1904         DBG_BCR_BVR_WCR_WVR(6),
1905         /* DBGVCR */
1906         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
1907         DBG_BCR_BVR_WCR_WVR(7),
1908         DBG_BCR_BVR_WCR_WVR(8),
1909         DBG_BCR_BVR_WCR_WVR(9),
1910         DBG_BCR_BVR_WCR_WVR(10),
1911         DBG_BCR_BVR_WCR_WVR(11),
1912         DBG_BCR_BVR_WCR_WVR(12),
1913         DBG_BCR_BVR_WCR_WVR(13),
1914         DBG_BCR_BVR_WCR_WVR(14),
1915         DBG_BCR_BVR_WCR_WVR(15),
1916
1917         /* DBGDRAR (32bit) */
1918         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1919
1920         DBGBXVR(0),
1921         /* DBGOSLAR */
1922         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1923         DBGBXVR(1),
1924         /* DBGOSLSR */
1925         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1926         DBGBXVR(2),
1927         DBGBXVR(3),
1928         /* DBGOSDLR */
1929         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1930         DBGBXVR(4),
1931         /* DBGPRCR */
1932         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1933         DBGBXVR(5),
1934         DBGBXVR(6),
1935         DBGBXVR(7),
1936         DBGBXVR(8),
1937         DBGBXVR(9),
1938         DBGBXVR(10),
1939         DBGBXVR(11),
1940         DBGBXVR(12),
1941         DBGBXVR(13),
1942         DBGBXVR(14),
1943         DBGBXVR(15),
1944
1945         /* DBGDSAR (32bit) */
1946         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1947
1948         /* DBGDEVID2 */
1949         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1950         /* DBGDEVID1 */
1951         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1952         /* DBGDEVID */
1953         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1954         /* DBGCLAIMSET */
1955         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1956         /* DBGCLAIMCLR */
1957         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1958         /* DBGAUTHSTATUS */
1959         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1960 };
1961
1962 /* Trapped cp14 64bit registers */
1963 static const struct sys_reg_desc cp14_64_regs[] = {
1964         /* DBGDRAR (64bit) */
1965         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1966
1967         /* DBGDSAR (64bit) */
1968         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1969 };
1970
1971 /* Macro to expand the PMEVCNTRn register */
1972 #define PMU_PMEVCNTR(n)                                                 \
1973         /* PMEVCNTRn */                                                 \
1974         { Op1(0), CRn(0b1110),                                          \
1975           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1976           access_pmu_evcntr }
1977
1978 /* Macro to expand the PMEVTYPERn register */
1979 #define PMU_PMEVTYPER(n)                                                \
1980         /* PMEVTYPERn */                                                \
1981         { Op1(0), CRn(0b1110),                                          \
1982           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1983           access_pmu_evtyper }
1984
1985 /*
1986  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1987  * depending on the way they are accessed (as a 32bit or a 64bit
1988  * register).
1989  */
1990 static const struct sys_reg_desc cp15_regs[] = {
1991         { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1992         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1993         /* ACTLR */
1994         { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1995         /* ACTLR2 */
1996         { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1997         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1998         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
1999         /* TTBCR */
2000         { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2001         /* TTBCR2 */
2002         { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2003         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2004         /* DFSR */
2005         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2006         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2007         /* ADFSR */
2008         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2009         /* AIFSR */
2010         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2011         /* DFAR */
2012         { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2013         /* IFAR */
2014         { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2015
2016         /*
2017          * DC{C,I,CI}SW operations:
2018          */
2019         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2020         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2021         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2022
2023         /* PMU */
2024         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
2025         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
2026         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
2027         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
2028         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
2029         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
2030         { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
2031         { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
2032         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
2033         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
2034         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
2035         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
2036         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
2037         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
2038         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
2039         { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
2040         { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
2041         /* PMMIR */
2042         { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
2043
2044         /* PRRR/MAIR0 */
2045         { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2046         /* NMRR/MAIR1 */
2047         { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2048         /* AMAIR0 */
2049         { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2050         /* AMAIR1 */
2051         { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2052
2053         /* ICC_SRE */
2054         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2055
2056         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2057
2058         /* Arch Tmers */
2059         { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2060         { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2061
2062         /* PMEVCNTRn */
2063         PMU_PMEVCNTR(0),
2064         PMU_PMEVCNTR(1),
2065         PMU_PMEVCNTR(2),
2066         PMU_PMEVCNTR(3),
2067         PMU_PMEVCNTR(4),
2068         PMU_PMEVCNTR(5),
2069         PMU_PMEVCNTR(6),
2070         PMU_PMEVCNTR(7),
2071         PMU_PMEVCNTR(8),
2072         PMU_PMEVCNTR(9),
2073         PMU_PMEVCNTR(10),
2074         PMU_PMEVCNTR(11),
2075         PMU_PMEVCNTR(12),
2076         PMU_PMEVCNTR(13),
2077         PMU_PMEVCNTR(14),
2078         PMU_PMEVCNTR(15),
2079         PMU_PMEVCNTR(16),
2080         PMU_PMEVCNTR(17),
2081         PMU_PMEVCNTR(18),
2082         PMU_PMEVCNTR(19),
2083         PMU_PMEVCNTR(20),
2084         PMU_PMEVCNTR(21),
2085         PMU_PMEVCNTR(22),
2086         PMU_PMEVCNTR(23),
2087         PMU_PMEVCNTR(24),
2088         PMU_PMEVCNTR(25),
2089         PMU_PMEVCNTR(26),
2090         PMU_PMEVCNTR(27),
2091         PMU_PMEVCNTR(28),
2092         PMU_PMEVCNTR(29),
2093         PMU_PMEVCNTR(30),
2094         /* PMEVTYPERn */
2095         PMU_PMEVTYPER(0),
2096         PMU_PMEVTYPER(1),
2097         PMU_PMEVTYPER(2),
2098         PMU_PMEVTYPER(3),
2099         PMU_PMEVTYPER(4),
2100         PMU_PMEVTYPER(5),
2101         PMU_PMEVTYPER(6),
2102         PMU_PMEVTYPER(7),
2103         PMU_PMEVTYPER(8),
2104         PMU_PMEVTYPER(9),
2105         PMU_PMEVTYPER(10),
2106         PMU_PMEVTYPER(11),
2107         PMU_PMEVTYPER(12),
2108         PMU_PMEVTYPER(13),
2109         PMU_PMEVTYPER(14),
2110         PMU_PMEVTYPER(15),
2111         PMU_PMEVTYPER(16),
2112         PMU_PMEVTYPER(17),
2113         PMU_PMEVTYPER(18),
2114         PMU_PMEVTYPER(19),
2115         PMU_PMEVTYPER(20),
2116         PMU_PMEVTYPER(21),
2117         PMU_PMEVTYPER(22),
2118         PMU_PMEVTYPER(23),
2119         PMU_PMEVTYPER(24),
2120         PMU_PMEVTYPER(25),
2121         PMU_PMEVTYPER(26),
2122         PMU_PMEVTYPER(27),
2123         PMU_PMEVTYPER(28),
2124         PMU_PMEVTYPER(29),
2125         PMU_PMEVTYPER(30),
2126         /* PMCCFILTR */
2127         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2128
2129         { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2130         { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2131         { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2132 };
2133
2134 static const struct sys_reg_desc cp15_64_regs[] = {
2135         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2136         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2137         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2138         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2139         { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2140         { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2141         { SYS_DESC(SYS_AARCH32_CNTP_CVAL),    access_arch_timer },
2142 };
2143
2144 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2145                               bool is_32)
2146 {
2147         unsigned int i;
2148
2149         for (i = 0; i < n; i++) {
2150                 if (!is_32 && table[i].reg && !table[i].reset) {
2151                         kvm_err("sys_reg table %p entry %d has lacks reset\n",
2152                                 table, i);
2153                         return 1;
2154                 }
2155
2156                 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2157                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2158                         return 1;
2159                 }
2160         }
2161
2162         return 0;
2163 }
2164
2165 static int match_sys_reg(const void *key, const void *elt)
2166 {
2167         const unsigned long pval = (unsigned long)key;
2168         const struct sys_reg_desc *r = elt;
2169
2170         return pval - reg_to_encoding(r);
2171 }
2172
2173 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2174                                          const struct sys_reg_desc table[],
2175                                          unsigned int num)
2176 {
2177         unsigned long pval = reg_to_encoding(params);
2178
2179         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
2180 }
2181
2182 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2183 {
2184         kvm_inject_undefined(vcpu);
2185         return 1;
2186 }
2187
2188 static void perform_access(struct kvm_vcpu *vcpu,
2189                            struct sys_reg_params *params,
2190                            const struct sys_reg_desc *r)
2191 {
2192         trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2193
2194         /* Check for regs disabled by runtime config */
2195         if (sysreg_hidden(vcpu, r)) {
2196                 kvm_inject_undefined(vcpu);
2197                 return;
2198         }
2199
2200         /*
2201          * Not having an accessor means that we have configured a trap
2202          * that we don't know how to handle. This certainly qualifies
2203          * as a gross bug that should be fixed right away.
2204          */
2205         BUG_ON(!r->access);
2206
2207         /* Skip instruction if instructed so */
2208         if (likely(r->access(vcpu, params, r)))
2209                 kvm_incr_pc(vcpu);
2210 }
2211
2212 /*
2213  * emulate_cp --  tries to match a sys_reg access in a handling table, and
2214  *                call the corresponding trap handler.
2215  *
2216  * @params: pointer to the descriptor of the access
2217  * @table: array of trap descriptors
2218  * @num: size of the trap descriptor array
2219  *
2220  * Return 0 if the access has been handled, and -1 if not.
2221  */
2222 static int emulate_cp(struct kvm_vcpu *vcpu,
2223                       struct sys_reg_params *params,
2224                       const struct sys_reg_desc *table,
2225                       size_t num)
2226 {
2227         const struct sys_reg_desc *r;
2228
2229         if (!table)
2230                 return -1;      /* Not handled */
2231
2232         r = find_reg(params, table, num);
2233
2234         if (r) {
2235                 perform_access(vcpu, params, r);
2236                 return 0;
2237         }
2238
2239         /* Not handled */
2240         return -1;
2241 }
2242
2243 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2244                                 struct sys_reg_params *params)
2245 {
2246         u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2247         int cp = -1;
2248
2249         switch (esr_ec) {
2250         case ESR_ELx_EC_CP15_32:
2251         case ESR_ELx_EC_CP15_64:
2252                 cp = 15;
2253                 break;
2254         case ESR_ELx_EC_CP14_MR:
2255         case ESR_ELx_EC_CP14_64:
2256                 cp = 14;
2257                 break;
2258         default:
2259                 WARN_ON(1);
2260         }
2261
2262         print_sys_reg_msg(params,
2263                           "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2264                           cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2265         kvm_inject_undefined(vcpu);
2266 }
2267
2268 /**
2269  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2270  * @vcpu: The VCPU pointer
2271  * @run:  The kvm_run struct
2272  */
2273 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2274                             const struct sys_reg_desc *global,
2275                             size_t nr_global)
2276 {
2277         struct sys_reg_params params;
2278         u32 esr = kvm_vcpu_get_esr(vcpu);
2279         int Rt = kvm_vcpu_sys_get_rt(vcpu);
2280         int Rt2 = (esr >> 10) & 0x1f;
2281
2282         params.CRm = (esr >> 1) & 0xf;
2283         params.is_write = ((esr & 1) == 0);
2284
2285         params.Op0 = 0;
2286         params.Op1 = (esr >> 16) & 0xf;
2287         params.Op2 = 0;
2288         params.CRn = 0;
2289
2290         /*
2291          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2292          * backends between AArch32 and AArch64, we get away with it.
2293          */
2294         if (params.is_write) {
2295                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2296                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2297         }
2298
2299         /*
2300          * If the table contains a handler, handle the
2301          * potential register operation in the case of a read and return
2302          * with success.
2303          */
2304         if (!emulate_cp(vcpu, &params, global, nr_global)) {
2305                 /* Split up the value between registers for the read side */
2306                 if (!params.is_write) {
2307                         vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2308                         vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2309                 }
2310
2311                 return 1;
2312         }
2313
2314         unhandled_cp_access(vcpu, &params);
2315         return 1;
2316 }
2317
2318 /**
2319  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2320  * @vcpu: The VCPU pointer
2321  * @run:  The kvm_run struct
2322  */
2323 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2324                             const struct sys_reg_desc *global,
2325                             size_t nr_global)
2326 {
2327         struct sys_reg_params params;
2328         u32 esr = kvm_vcpu_get_esr(vcpu);
2329         int Rt  = kvm_vcpu_sys_get_rt(vcpu);
2330
2331         params.CRm = (esr >> 1) & 0xf;
2332         params.regval = vcpu_get_reg(vcpu, Rt);
2333         params.is_write = ((esr & 1) == 0);
2334         params.CRn = (esr >> 10) & 0xf;
2335         params.Op0 = 0;
2336         params.Op1 = (esr >> 14) & 0x7;
2337         params.Op2 = (esr >> 17) & 0x7;
2338
2339         if (!emulate_cp(vcpu, &params, global, nr_global)) {
2340                 if (!params.is_write)
2341                         vcpu_set_reg(vcpu, Rt, params.regval);
2342                 return 1;
2343         }
2344
2345         unhandled_cp_access(vcpu, &params);
2346         return 1;
2347 }
2348
2349 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2350 {
2351         return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2352 }
2353
2354 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2355 {
2356         return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
2357 }
2358
2359 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2360 {
2361         return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2362 }
2363
2364 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2365 {
2366         return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
2367 }
2368
2369 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2370 {
2371         // See ARM DDI 0487E.a, section D12.3.2
2372         return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2373 }
2374
2375 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2376                            struct sys_reg_params *params)
2377 {
2378         const struct sys_reg_desc *r;
2379
2380         r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2381
2382         if (likely(r)) {
2383                 perform_access(vcpu, params, r);
2384         } else if (is_imp_def_sys_reg(params)) {
2385                 kvm_inject_undefined(vcpu);
2386         } else {
2387                 print_sys_reg_msg(params,
2388                                   "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2389                                   *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2390                 kvm_inject_undefined(vcpu);
2391         }
2392         return 1;
2393 }
2394
2395 /**
2396  * kvm_reset_sys_regs - sets system registers to reset value
2397  * @vcpu: The VCPU pointer
2398  *
2399  * This function finds the right table above and sets the registers on the
2400  * virtual CPU struct to their architecturally defined reset values.
2401  */
2402 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2403 {
2404         unsigned long i;
2405
2406         for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2407                 if (sys_reg_descs[i].reset)
2408                         sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2409 }
2410
2411 /**
2412  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2413  * @vcpu: The VCPU pointer
2414  */
2415 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2416 {
2417         struct sys_reg_params params;
2418         unsigned long esr = kvm_vcpu_get_esr(vcpu);
2419         int Rt = kvm_vcpu_sys_get_rt(vcpu);
2420         int ret;
2421
2422         trace_kvm_handle_sys_reg(esr);
2423
2424         params.Op0 = (esr >> 20) & 3;
2425         params.Op1 = (esr >> 14) & 0x7;
2426         params.CRn = (esr >> 10) & 0xf;
2427         params.CRm = (esr >> 1) & 0xf;
2428         params.Op2 = (esr >> 17) & 0x7;
2429         params.regval = vcpu_get_reg(vcpu, Rt);
2430         params.is_write = !(esr & 1);
2431
2432         ret = emulate_sys_reg(vcpu, &params);
2433
2434         if (!params.is_write)
2435                 vcpu_set_reg(vcpu, Rt, params.regval);
2436         return ret;
2437 }
2438
2439 /******************************************************************************
2440  * Userspace API
2441  *****************************************************************************/
2442
2443 static bool index_to_params(u64 id, struct sys_reg_params *params)
2444 {
2445         switch (id & KVM_REG_SIZE_MASK) {
2446         case KVM_REG_SIZE_U64:
2447                 /* Any unused index bits means it's not valid. */
2448                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2449                               | KVM_REG_ARM_COPROC_MASK
2450                               | KVM_REG_ARM64_SYSREG_OP0_MASK
2451                               | KVM_REG_ARM64_SYSREG_OP1_MASK
2452                               | KVM_REG_ARM64_SYSREG_CRN_MASK
2453                               | KVM_REG_ARM64_SYSREG_CRM_MASK
2454                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
2455                         return false;
2456                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2457                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2458                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2459                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2460                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2461                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2462                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2463                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2464                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2465                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2466                 return true;
2467         default:
2468                 return false;
2469         }
2470 }
2471
2472 const struct sys_reg_desc *find_reg_by_id(u64 id,
2473                                           struct sys_reg_params *params,
2474                                           const struct sys_reg_desc table[],
2475                                           unsigned int num)
2476 {
2477         if (!index_to_params(id, params))
2478                 return NULL;
2479
2480         return find_reg(params, table, num);
2481 }
2482
2483 /* Decode an index value, and find the sys_reg_desc entry. */
2484 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2485                                                     u64 id)
2486 {
2487         const struct sys_reg_desc *r;
2488         struct sys_reg_params params;
2489
2490         /* We only do sys_reg for now. */
2491         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2492                 return NULL;
2493
2494         if (!index_to_params(id, &params))
2495                 return NULL;
2496
2497         r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2498
2499         /* Not saved in the sys_reg array and not otherwise accessible? */
2500         if (r && !(r->reg || r->get_user))
2501                 r = NULL;
2502
2503         return r;
2504 }
2505
2506 /*
2507  * These are the invariant sys_reg registers: we let the guest see the
2508  * host versions of these, so they're part of the guest state.
2509  *
2510  * A future CPU may provide a mechanism to present different values to
2511  * the guest, or a future kvm may trap them.
2512  */
2513
2514 #define FUNCTION_INVARIANT(reg)                                         \
2515         static void get_##reg(struct kvm_vcpu *v,                       \
2516                               const struct sys_reg_desc *r)             \
2517         {                                                               \
2518                 ((struct sys_reg_desc *)r)->val = read_sysreg(reg);     \
2519         }
2520
2521 FUNCTION_INVARIANT(midr_el1)
2522 FUNCTION_INVARIANT(revidr_el1)
2523 FUNCTION_INVARIANT(clidr_el1)
2524 FUNCTION_INVARIANT(aidr_el1)
2525
2526 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2527 {
2528         ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2529 }
2530
2531 /* ->val is filled in by kvm_sys_reg_table_init() */
2532 static struct sys_reg_desc invariant_sys_regs[] = {
2533         { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2534         { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2535         { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2536         { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2537         { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2538 };
2539
2540 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2541 {
2542         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2543                 return -EFAULT;
2544         return 0;
2545 }
2546
2547 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2548 {
2549         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2550                 return -EFAULT;
2551         return 0;
2552 }
2553
2554 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2555 {
2556         struct sys_reg_params params;
2557         const struct sys_reg_desc *r;
2558
2559         r = find_reg_by_id(id, &params, invariant_sys_regs,
2560                            ARRAY_SIZE(invariant_sys_regs));
2561         if (!r)
2562                 return -ENOENT;
2563
2564         return reg_to_user(uaddr, &r->val, id);
2565 }
2566
2567 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2568 {
2569         struct sys_reg_params params;
2570         const struct sys_reg_desc *r;
2571         int err;
2572         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2573
2574         r = find_reg_by_id(id, &params, invariant_sys_regs,
2575                            ARRAY_SIZE(invariant_sys_regs));
2576         if (!r)
2577                 return -ENOENT;
2578
2579         err = reg_from_user(&val, uaddr, id);
2580         if (err)
2581                 return err;
2582
2583         /* This is what we mean by invariant: you can't change it. */
2584         if (r->val != val)
2585                 return -EINVAL;
2586
2587         return 0;
2588 }
2589
2590 static bool is_valid_cache(u32 val)
2591 {
2592         u32 level, ctype;
2593
2594         if (val >= CSSELR_MAX)
2595                 return false;
2596
2597         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
2598         level = (val >> 1);
2599         ctype = (cache_levels >> (level * 3)) & 7;
2600
2601         switch (ctype) {
2602         case 0: /* No cache */
2603                 return false;
2604         case 1: /* Instruction cache only */
2605                 return (val & 1);
2606         case 2: /* Data cache only */
2607         case 4: /* Unified cache */
2608                 return !(val & 1);
2609         case 3: /* Separate instruction and data caches */
2610                 return true;
2611         default: /* Reserved: we can't know instruction or data. */
2612                 return false;
2613         }
2614 }
2615
2616 static int demux_c15_get(u64 id, void __user *uaddr)
2617 {
2618         u32 val;
2619         u32 __user *uval = uaddr;
2620
2621         /* Fail if we have unknown bits set. */
2622         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2623                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2624                 return -ENOENT;
2625
2626         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2627         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2628                 if (KVM_REG_SIZE(id) != 4)
2629                         return -ENOENT;
2630                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2631                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2632                 if (!is_valid_cache(val))
2633                         return -ENOENT;
2634
2635                 return put_user(get_ccsidr(val), uval);
2636         default:
2637                 return -ENOENT;
2638         }
2639 }
2640
2641 static int demux_c15_set(u64 id, void __user *uaddr)
2642 {
2643         u32 val, newval;
2644         u32 __user *uval = uaddr;
2645
2646         /* Fail if we have unknown bits set. */
2647         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2648                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2649                 return -ENOENT;
2650
2651         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2652         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2653                 if (KVM_REG_SIZE(id) != 4)
2654                         return -ENOENT;
2655                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2656                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2657                 if (!is_valid_cache(val))
2658                         return -ENOENT;
2659
2660                 if (get_user(newval, uval))
2661                         return -EFAULT;
2662
2663                 /* This is also invariant: you can't change it. */
2664                 if (newval != get_ccsidr(val))
2665                         return -EINVAL;
2666                 return 0;
2667         default:
2668                 return -ENOENT;
2669         }
2670 }
2671
2672 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2673 {
2674         const struct sys_reg_desc *r;
2675         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2676
2677         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2678                 return demux_c15_get(reg->id, uaddr);
2679
2680         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2681                 return -ENOENT;
2682
2683         r = index_to_sys_reg_desc(vcpu, reg->id);
2684         if (!r)
2685                 return get_invariant_sys_reg(reg->id, uaddr);
2686
2687         /* Check for regs disabled by runtime config */
2688         if (sysreg_hidden(vcpu, r))
2689                 return -ENOENT;
2690
2691         if (r->get_user)
2692                 return (r->get_user)(vcpu, r, reg, uaddr);
2693
2694         return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2695 }
2696
2697 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2698 {
2699         const struct sys_reg_desc *r;
2700         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2701
2702         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2703                 return demux_c15_set(reg->id, uaddr);
2704
2705         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2706                 return -ENOENT;
2707
2708         r = index_to_sys_reg_desc(vcpu, reg->id);
2709         if (!r)
2710                 return set_invariant_sys_reg(reg->id, uaddr);
2711
2712         /* Check for regs disabled by runtime config */
2713         if (sysreg_hidden(vcpu, r))
2714                 return -ENOENT;
2715
2716         if (r->set_user)
2717                 return (r->set_user)(vcpu, r, reg, uaddr);
2718
2719         return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2720 }
2721
2722 static unsigned int num_demux_regs(void)
2723 {
2724         unsigned int i, count = 0;
2725
2726         for (i = 0; i < CSSELR_MAX; i++)
2727                 if (is_valid_cache(i))
2728                         count++;
2729
2730         return count;
2731 }
2732
2733 static int write_demux_regids(u64 __user *uindices)
2734 {
2735         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2736         unsigned int i;
2737
2738         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2739         for (i = 0; i < CSSELR_MAX; i++) {
2740                 if (!is_valid_cache(i))
2741                         continue;
2742                 if (put_user(val | i, uindices))
2743                         return -EFAULT;
2744                 uindices++;
2745         }
2746         return 0;
2747 }
2748
2749 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2750 {
2751         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2752                 KVM_REG_ARM64_SYSREG |
2753                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2754                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2755                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2756                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2757                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2758 }
2759
2760 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2761 {
2762         if (!*uind)
2763                 return true;
2764
2765         if (put_user(sys_reg_to_index(reg), *uind))
2766                 return false;
2767
2768         (*uind)++;
2769         return true;
2770 }
2771
2772 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2773                             const struct sys_reg_desc *rd,
2774                             u64 __user **uind,
2775                             unsigned int *total)
2776 {
2777         /*
2778          * Ignore registers we trap but don't save,
2779          * and for which no custom user accessor is provided.
2780          */
2781         if (!(rd->reg || rd->get_user))
2782                 return 0;
2783
2784         if (sysreg_hidden(vcpu, rd))
2785                 return 0;
2786
2787         if (!copy_reg_to_user(rd, uind))
2788                 return -EFAULT;
2789
2790         (*total)++;
2791         return 0;
2792 }
2793
2794 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2795 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2796 {
2797         const struct sys_reg_desc *i2, *end2;
2798         unsigned int total = 0;
2799         int err;
2800
2801         i2 = sys_reg_descs;
2802         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2803
2804         while (i2 != end2) {
2805                 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2806                 if (err)
2807                         return err;
2808         }
2809         return total;
2810 }
2811
2812 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2813 {
2814         return ARRAY_SIZE(invariant_sys_regs)
2815                 + num_demux_regs()
2816                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2817 }
2818
2819 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2820 {
2821         unsigned int i;
2822         int err;
2823
2824         /* Then give them all the invariant registers' indices. */
2825         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2826                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2827                         return -EFAULT;
2828                 uindices++;
2829         }
2830
2831         err = walk_sys_regs(vcpu, uindices);
2832         if (err < 0)
2833                 return err;
2834         uindices += err;
2835
2836         return write_demux_regids(uindices);
2837 }
2838
2839 void kvm_sys_reg_table_init(void)
2840 {
2841         unsigned int i;
2842         struct sys_reg_desc clidr;
2843
2844         /* Make sure tables are unique and in order. */
2845         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2846         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2847         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2848         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2849         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2850         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
2851
2852         /* We abuse the reset function to overwrite the table itself. */
2853         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2854                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2855
2856         /*
2857          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2858          *
2859          *   If software reads the Cache Type fields from Ctype1
2860          *   upwards, once it has seen a value of 0b000, no caches
2861          *   exist at further-out levels of the hierarchy. So, for
2862          *   example, if Ctype3 is the first Cache Type field with a
2863          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2864          *   ignored.
2865          */
2866         get_clidr_el1(NULL, &clidr); /* Ugly... */
2867         cache_levels = clidr.val;
2868         for (i = 0; i < 7; i++)
2869                 if (((cache_levels >> (i*3)) & 7) == 0)
2870                         break;
2871         /* Clear all higher bits. */
2872         cache_levels &= (1 << (i*3))-1;
2873 }