1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <hyp/switch.h>
9 #include <linux/arm-smccc.h>
10 #include <linux/kvm_host.h>
11 #include <linux/types.h>
12 #include <linux/jump_label.h>
13 #include <uapi/linux/psci.h>
15 #include <kvm/arm_psci.h>
17 #include <asm/barrier.h>
18 #include <asm/cpufeature.h>
19 #include <asm/kprobes.h>
20 #include <asm/kvm_asm.h>
21 #include <asm/kvm_emulate.h>
22 #include <asm/kvm_hyp.h>
23 #include <asm/kvm_mmu.h>
24 #include <asm/fpsimd.h>
25 #include <asm/debug-monitors.h>
26 #include <asm/processor.h>
27 #include <asm/thread_info.h>
29 /* VHE specific context */
30 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
31 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
32 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
34 static void __activate_traps(struct kvm_vcpu *vcpu)
38 ___activate_traps(vcpu);
40 val = read_sysreg(cpacr_el1);
42 val &= ~CPACR_EL1_ZEN;
45 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
46 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
47 * except for some missing controls, such as TAM.
48 * In this case, CPTR_EL2.TAM has the same position with or without
49 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
50 * shift value for trapping the AMU accesses.
55 if (update_fp_enabled(vcpu)) {
56 if (vcpu_has_sve(vcpu))
59 val &= ~CPACR_EL1_FPEN;
60 __activate_traps_fpsimd32(vcpu);
63 write_sysreg(val, cpacr_el1);
65 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
67 NOKPROBE_SYMBOL(__activate_traps);
69 static void __deactivate_traps(struct kvm_vcpu *vcpu)
71 extern char vectors[]; /* kernel exception vectors */
73 ___deactivate_traps(vcpu);
75 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
78 * ARM errata 1165522 and 1530923 require the actual execution of the
79 * above before we can switch to the EL2/EL0 translation regime used by
82 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
84 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
85 write_sysreg(vectors, vbar_el1);
87 NOKPROBE_SYMBOL(__deactivate_traps);
89 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
91 __activate_traps_common(vcpu);
94 void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu)
96 __deactivate_traps_common(vcpu);
99 /* Switch to the guest for VHE systems running in EL2 */
100 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
102 struct kvm_cpu_context *host_ctxt;
103 struct kvm_cpu_context *guest_ctxt;
106 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
107 host_ctxt->__hyp_running_vcpu = vcpu;
108 guest_ctxt = &vcpu->arch.ctxt;
110 sysreg_save_host_state_vhe(host_ctxt);
113 * ARM erratum 1165522 requires us to configure both stage 1 and
114 * stage 2 translation for the guest context before we clear
117 * We have already configured the guest's stage 1 translation in
118 * kvm_vcpu_load_sysregs_vhe above. We must now call
119 * __load_stage2 before __activate_traps, because
120 * __load_stage2 configures stage 2 translation, and
121 * __activate_traps clear HCR_EL2.TGE (among other things).
123 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
124 __activate_traps(vcpu);
126 __kvm_adjust_pc(vcpu);
128 sysreg_restore_guest_state_vhe(guest_ctxt);
129 __debug_switch_to_guest(vcpu);
132 /* Jump in the fire! */
133 exit_code = __guest_enter(vcpu);
135 /* And we're baaack! */
136 } while (fixup_guest_exit(vcpu, &exit_code));
138 sysreg_save_guest_state_vhe(guest_ctxt);
140 __deactivate_traps(vcpu);
142 sysreg_restore_host_state_vhe(host_ctxt);
144 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
145 __fpsimd_save_fpexc32(vcpu);
147 __debug_switch_to_host(vcpu);
151 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
153 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
160 * Having IRQs masked via PMR when entering the guest means the GIC
161 * will not signal the CPU of interrupts of lower priority, and the
162 * only way to get out will be via guest exceptions.
163 * Naturally, we want to avoid this.
165 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
166 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
170 ret = __kvm_vcpu_run_vhe(vcpu);
173 * local_daif_restore() takes care to properly restore PSTATE.DAIF
174 * and the GIC PMR if the host is using IRQ priorities.
176 local_daif_restore(DAIF_PROCCTX_NOIRQ);
179 * When we exit from the guest we change a number of CPU configuration
180 * parameters, such as traps. Make sure these changes take effect
181 * before running the host or additional guests.
188 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par)
190 struct kvm_cpu_context *host_ctxt;
191 struct kvm_vcpu *vcpu;
193 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
194 vcpu = host_ctxt->__hyp_running_vcpu;
196 __deactivate_traps(vcpu);
197 sysreg_restore_host_state_vhe(host_ctxt);
199 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n",
201 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
202 read_sysreg(hpfar_el2), par, vcpu);
204 NOKPROBE_SYMBOL(__hyp_call_panic);
206 void __noreturn hyp_panic(void)
208 u64 spsr = read_sysreg_el2(SYS_SPSR);
209 u64 elr = read_sysreg_el2(SYS_ELR);
210 u64 par = read_sysreg_par();
212 __hyp_call_panic(spsr, elr, par);
216 asmlinkage void kvm_unexpected_el2_exception(void)
218 return __kvm_unexpected_el2_exception();