1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * A stand-alone ticket spinlock implementation for use by the non-VHE
4 * KVM hypervisor code running at EL2.
6 * Copyright (C) 2020 Google LLC
7 * Author: Will Deacon <will@kernel.org>
9 * Heavily based on the implementation removed by c11090474d70 which was:
10 * Copyright (C) 2012 ARM Ltd.
13 #ifndef __ARM64_KVM_NVHE_SPINLOCK_H__
14 #define __ARM64_KVM_NVHE_SPINLOCK_H__
16 #include <asm/alternative.h>
19 typedef union hyp_spinlock {
30 #define hyp_spin_lock_init(l) \
32 *(l) = (hyp_spinlock_t){ .__val = 0 }; \
35 static inline void hyp_spin_lock(hyp_spinlock_t *lock)
38 hyp_spinlock_t lockval, newval;
41 /* Atomically increment the next ticket. */
42 ARM64_LSE_ATOMIC_INSN(
44 " prfm pstl1strm, %3\n"
46 " add %w1, %w0, #(1 << 16)\n"
47 " stxr %w2, %w1, %3\n"
50 " mov %w2, #(1 << 16)\n"
51 " ldadda %w2, %w0, %3\n"
54 /* Did we get the lock? */
55 " eor %w1, %w0, %w0, ror #16\n"
58 * No: spin on the owner. Send a local event to avoid missing an
59 * unlock before the exclusive load.
64 " eor %w1, %w2, %w0, lsr #16\n"
66 /* We got the lock. Critical section starts here. */
68 : "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock)
73 static inline void hyp_spin_unlock(hyp_spinlock_t *lock)
78 ARM64_LSE_ATOMIC_INSN(
87 : "=Q" (lock->owner), "=&r" (tmp)
92 #endif /* __ARM64_KVM_NVHE_SPINLOCK_H__ */