1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2015, Linaro Limited
5 #include <linux/linkage.h>
6 #include <linux/arm-smccc.h>
8 #include <asm/asm-offsets.h>
9 #include <asm/assembler.h>
10 #include <asm/thread_info.h>
13 * If we have SMCCC v1.3 and (as is likely) no SVE state in
14 * the registers then set the SMCCC hint bit to say there's no
15 * need to preserve it. Do this by directly adjusting the SMCCC
16 * function value which is already stored in x0 ready to be called.
18 SYM_FUNC_START(__arm_smccc_sve_check)
20 ldr_l x16, smccc_has_sve_hint
24 ldr x16, [x16, #TSK_TI_FLAGS]
25 tbnz x16, #TIF_FOREIGN_FPSTATE, 1f // Any live FP state?
26 tbnz x16, #TIF_SVE, 2f // Does that state include SVE?
28 1: orr x0, x0, ARM_SMCCC_1_3_SVE_HINT
31 SYM_FUNC_END(__arm_smccc_sve_check)
32 EXPORT_SYMBOL(__arm_smccc_sve_check)
35 alternative_if ARM64_SVE
36 bl __arm_smccc_sve_check
37 alternative_else_nop_endif
40 stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
41 stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
43 cbz x4, 1f /* no quirk structure */
44 ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
45 cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
47 str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
52 * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
53 * unsigned long a3, unsigned long a4, unsigned long a5,
54 * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
55 * struct arm_smccc_quirk *quirk)
57 SYM_FUNC_START(__arm_smccc_smc)
59 SYM_FUNC_END(__arm_smccc_smc)
60 EXPORT_SYMBOL(__arm_smccc_smc)
63 * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
64 * unsigned long a3, unsigned long a4, unsigned long a5,
65 * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
66 * struct arm_smccc_quirk *quirk)
68 SYM_FUNC_START(__arm_smccc_hvc)
70 SYM_FUNC_END(__arm_smccc_hvc)
71 EXPORT_SYMBOL(__arm_smccc_hvc)
73 .macro SMCCC_1_2 instr
74 /* Save `res` and free a GPR that won't be clobbered */
75 stp x1, x19, [sp, #-16]!
77 /* Ensure `args` won't be clobbered while loading regs in next step */
80 /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
81 ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
82 ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
83 ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
84 ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
85 ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
86 ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
87 ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
88 ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
89 ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
93 /* Load the `res` from the stack */
96 /* Store the registers x0 - x17 into the result structure */
97 stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
98 stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
99 stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
100 stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
101 stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
102 stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
103 stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
104 stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
105 stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
107 /* Restore original x19 */
108 ldp xzr, x19, [sp], #16
113 * void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args,
114 * struct arm_smccc_1_2_regs *res);
116 SYM_FUNC_START(arm_smccc_1_2_hvc)
118 SYM_FUNC_END(arm_smccc_1_2_hvc)
119 EXPORT_SYMBOL(arm_smccc_1_2_hvc)
122 * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
123 * struct arm_smccc_1_2_regs *res);
125 SYM_FUNC_START(arm_smccc_1_2_smc)
127 SYM_FUNC_END(arm_smccc_1_2_smc)
128 EXPORT_SYMBOL(arm_smccc_1_2_smc)