arch/arm64/kernel/perf_event.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARMv8 PMUv3 Performance Events handling code.
   4  *
   5  * Copyright (C) 2012 ARM Limited
   6  * Author: Will Deacon <will.deacon@arm.com>
   7  *
   8  * This code is based heavily on the ARMv7 perf event code.
   9  */
  10
  11 #include <asm/irq_regs.h>
  12 #include <asm/perf_event.h>
  13 #include <asm/sysreg.h>
  14 #include <asm/virt.h>
  15
  16 #include <clocksource/arm_arch_timer.h>
  17
  18 #include <linux/acpi.h>
  19 #include <linux/clocksource.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/of.h>
  22 #include <linux/perf/arm_pmu.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched_clock.h>
  25 #include <linux/smp.h>
  26
  27 /* ARMv8 Cortex-A53 specific event types. */
  28 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
  29
  30 /* ARMv8 Cavium ThunderX specific event types. */
  31 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
  32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
  33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
  34 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
  35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
  36
  37 /*
  38  * ARMv8 Architectural defined events, not all of these may
  39  * be supported on any given implementation. Unsupported events will
  40  * be disabled at run-time based on the PMCEID registers.
  41  */
  42 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
  43         PERF_MAP_ALL_UNSUPPORTED,
  44         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
  45         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
  46         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  47         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  48         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
  49         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  50         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
  51         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
  52         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
  53 };
  54
  55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  56                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  58         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  59
  60         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  61         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  62
  63         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
  64         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
  65
  66         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
  67         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
  68
  69         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
  70         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
  71
  72         [C(LL)][C(OP_READ)][C(RESULT_MISS)]     = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
  73         [C(LL)][C(OP_READ)][C(RESULT_ACCESS)]   = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
  74
  75         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
  76         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  77 };
  78
  79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  80                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  81                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  82         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  83
  84         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
  85
  86         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  87         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  88 };
  89
  90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  91                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  92                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  93         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  94
  95         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  96         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  97         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  98         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
  99
 100         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 101         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 102
 103         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 104         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 105 };
 106
 107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 108                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 109                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 110         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 111
 112         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 113         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 114 };
 115
 116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 117                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 118                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 119         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 120
 121         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 122         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 123         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 124         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 125         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 126         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 127
 128         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 129         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 130
 131         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 132         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 133         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 134         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 135 };
 136
 137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 138                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 139                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 140         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 141
 142         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 143         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 144         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 145         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 146
 147         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 148         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 149         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 150         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 151
 152         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 153         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 154 };
 155
 156 static ssize_t
 157 armv8pmu_events_sysfs_show(struct device *dev,
 158                            struct device_attribute *attr, char *page)
 159 {
 160         struct perf_pmu_events_attr *pmu_attr;
 161
 162         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 163
 164         return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
 165 }
 166
 167 #define ARMV8_EVENT_ATTR(name, config)                                          \
 168         (&((struct perf_pmu_events_attr) {                                      \
 169                 .attr = __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL),   \
 170                 .id = config,                                                   \
 171         }).attr.attr)
 172
 173 static struct attribute *armv8_pmuv3_event_attrs[] = {
 174         ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
 175         ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
 176         ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
 177         ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
 178         ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
 179         ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
 180         ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
 181         ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
 182         ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
 183         ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
 184         ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
 185         ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
 186         ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
 187         ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
 188         ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
 189         ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
 190         ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
 191         ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
 192         ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
 193         ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
 194         ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
 195         ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
 196         ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
 197         ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
 198         ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
 199         ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
 200         ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
 201         ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
 202         ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
 203         ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
 204         /* Don't expose the chain event in /sys, since it's useless in isolation */
 205         ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
 206         ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
 207         ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
 208         ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
 209         ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
 210         ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
 211         ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
 212         ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
 213         ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
 214         ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
 215         ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
 216         ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
 217         ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
 218         ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
 219         ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
 220         ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
 221         ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
 222         ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
 223         ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
 224         ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
 225         ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
 226         ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
 227         ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
 228         ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
 229         ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
 230         ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
 231         ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
 232         ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
 233         ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
 234         ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
 235         ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
 236         ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
 237         ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
 238         ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
 239         ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
 240         ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
 241         ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
 242         ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
 243         ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
 244         ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
 245         ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
 246         ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
 247         ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
 248         ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
 249         ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
 250         ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
 251         ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
 252         ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
 253         ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
 254         NULL,
 255 };
 256
 257 static umode_t
 258 armv8pmu_event_attr_is_visible(struct kobject *kobj,
 259                                struct attribute *attr, int unused)
 260 {
 261         struct device *dev = kobj_to_dev(kobj);
 262         struct pmu *pmu = dev_get_drvdata(dev);
 263         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 264         struct perf_pmu_events_attr *pmu_attr;
 265
 266         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 267
 268         if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 269             test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 270                 return attr->mode;
 271
 272         if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
 273                 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
 274
 275                 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 276                     test_bit(id, cpu_pmu->pmceid_ext_bitmap))
 277                         return attr->mode;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static struct attribute_group armv8_pmuv3_events_attr_group = {
 284         .name = "events",
 285         .attrs = armv8_pmuv3_event_attrs,
 286         .is_visible = armv8pmu_event_attr_is_visible,
 287 };
 288
 289 PMU_FORMAT_ATTR(event, "config:0-15");
 290 PMU_FORMAT_ATTR(long, "config1:0");
 291
 292 static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
 293 {
 294         return event->attr.config1 & 0x1;
 295 }
 296
 297 static struct attribute *armv8_pmuv3_format_attrs[] = {
 298         &format_attr_event.attr,
 299         &format_attr_long.attr,
 300         NULL,
 301 };
 302
 303 static struct attribute_group armv8_pmuv3_format_attr_group = {
 304         .name = "format",
 305         .attrs = armv8_pmuv3_format_attrs,
 306 };
 307
 308 static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
 309                           char *page)
 310 {
 311         struct pmu *pmu = dev_get_drvdata(dev);
 312         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 313         u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
 314
 315         return snprintf(page, PAGE_SIZE, "0x%08x\n", slots);
 316 }
 317
 318 static DEVICE_ATTR_RO(slots);
 319
 320 static struct attribute *armv8_pmuv3_caps_attrs[] = {
 321         &dev_attr_slots.attr,
 322         NULL,
 323 };
 324
 325 static struct attribute_group armv8_pmuv3_caps_attr_group = {
 326         .name = "caps",
 327         .attrs = armv8_pmuv3_caps_attrs,
 328 };
 329
 330 /*
 331  * Perf Events' indices
 332  */
 333 #define ARMV8_IDX_CYCLE_COUNTER 0
 334 #define ARMV8_IDX_COUNTER0      1
 335
 336
 337 /*
 338  * We unconditionally enable ARMv8.5-PMU long event counter support
 339  * (64-bit events) where supported. Indicate if this arm_pmu has long
 340  * event counter support.
 341  */
 342 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
 343 {
 344         return (cpu_pmu->pmuver >= ID_AA64DFR0_PMUVER_8_5);
 345 }
 346
 347 /*
 348  * We must chain two programmable counters for 64 bit events,
 349  * except when we have allocated the 64bit cycle counter (for CPU
 350  * cycles event). This must be called only when the event has
 351  * a counter allocated.
 352  */
 353 static inline bool armv8pmu_event_is_chained(struct perf_event *event)
 354 {
 355         int idx = event->hw.idx;
 356         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 357
 358         return !WARN_ON(idx < 0) &&
 359                armv8pmu_event_is_64bit(event) &&
 360                !armv8pmu_has_long_event(cpu_pmu) &&
 361                (idx != ARMV8_IDX_CYCLE_COUNTER);
 362 }
 363
 364 /*
 365  * ARMv8 low level PMU access
 366  */
 367
 368 /*
 369  * Perf Event to low level counters mapping
 370  */
 371 #define ARMV8_IDX_TO_COUNTER(x) \
 372         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 373
 374 /*
 375  * This code is really good
 376  */
 377
 378 #define PMEVN_CASE(n, case_macro) \
 379         case n: case_macro(n); break
 380
 381 #define PMEVN_SWITCH(x, case_macro)                             \
 382         do {                                                    \
 383                 switch (x) {                                    \
 384                 PMEVN_CASE(0,  case_macro);                     \
 385                 PMEVN_CASE(1,  case_macro);                     \
 386                 PMEVN_CASE(2,  case_macro);                     \
 387                 PMEVN_CASE(3,  case_macro);                     \
 388                 PMEVN_CASE(4,  case_macro);                     \
 389                 PMEVN_CASE(5,  case_macro);                     \
 390                 PMEVN_CASE(6,  case_macro);                     \
 391                 PMEVN_CASE(7,  case_macro);                     \
 392                 PMEVN_CASE(8,  case_macro);                     \
 393                 PMEVN_CASE(9,  case_macro);                     \
 394                 PMEVN_CASE(10, case_macro);                     \
 395                 PMEVN_CASE(11, case_macro);                     \
 396                 PMEVN_CASE(12, case_macro);                     \
 397                 PMEVN_CASE(13, case_macro);                     \
 398                 PMEVN_CASE(14, case_macro);                     \
 399                 PMEVN_CASE(15, case_macro);                     \
 400                 PMEVN_CASE(16, case_macro);                     \
 401                 PMEVN_CASE(17, case_macro);                     \
 402                 PMEVN_CASE(18, case_macro);                     \
 403                 PMEVN_CASE(19, case_macro);                     \
 404                 PMEVN_CASE(20, case_macro);                     \
 405                 PMEVN_CASE(21, case_macro);                     \
 406                 PMEVN_CASE(22, case_macro);                     \
 407                 PMEVN_CASE(23, case_macro);                     \
 408                 PMEVN_CASE(24, case_macro);                     \
 409                 PMEVN_CASE(25, case_macro);                     \
 410                 PMEVN_CASE(26, case_macro);                     \
 411                 PMEVN_CASE(27, case_macro);                     \
 412                 PMEVN_CASE(28, case_macro);                     \
 413                 PMEVN_CASE(29, case_macro);                     \
 414                 PMEVN_CASE(30, case_macro);                     \
 415                 default: WARN(1, "Invalid PMEV* index\n");      \
 416                 }                                               \
 417         } while (0)
 418
 419 #define RETURN_READ_PMEVCNTRN(n) \
 420         return read_sysreg(pmevcntr##n##_el0)
 421 static unsigned long read_pmevcntrn(int n)
 422 {
 423         PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
 424         return 0;
 425 }
 426
 427 #define WRITE_PMEVCNTRN(n) \
 428         write_sysreg(val, pmevcntr##n##_el0)
 429 static void write_pmevcntrn(int n, unsigned long val)
 430 {
 431         PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
 432 }
 433
 434 #define WRITE_PMEVTYPERN(n) \
 435         write_sysreg(val, pmevtyper##n##_el0)
 436 static void write_pmevtypern(int n, unsigned long val)
 437 {
 438         PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
 439 }
 440
 441 static inline u32 armv8pmu_pmcr_read(void)
 442 {
 443         return read_sysreg(pmcr_el0);
 444 }
 445
 446 static inline void armv8pmu_pmcr_write(u32 val)
 447 {
 448         val &= ARMV8_PMU_PMCR_MASK;
 449         isb();
 450         write_sysreg(val, pmcr_el0);
 451 }
 452
 453 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 454 {
 455         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 456 }
 457
 458 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 459 {
 460         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 461 }
 462
 463 static inline u32 armv8pmu_read_evcntr(int idx)
 464 {
 465         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 466
 467         return read_pmevcntrn(counter);
 468 }
 469
 470 static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
 471 {
 472         int idx = event->hw.idx;
 473         u64 val = 0;
 474
 475         val = armv8pmu_read_evcntr(idx);
 476         if (armv8pmu_event_is_chained(event))
 477                 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
 478         return val;
 479 }
 480
 481 /*
 482  * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
 483  * is set the event counters also become 64-bit counters. Unless the
 484  * user has requested a long counter (attr.config1) then we want to
 485  * interrupt upon 32-bit overflow - we achieve this by applying a bias.
 486  */
 487 static bool armv8pmu_event_needs_bias(struct perf_event *event)
 488 {
 489         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 490         struct hw_perf_event *hwc = &event->hw;
 491         int idx = hwc->idx;
 492
 493         if (armv8pmu_event_is_64bit(event))
 494                 return false;
 495
 496         if (armv8pmu_has_long_event(cpu_pmu) ||
 497             idx == ARMV8_IDX_CYCLE_COUNTER)
 498                 return true;
 499
 500         return false;
 501 }
 502
 503 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
 504 {
 505         if (armv8pmu_event_needs_bias(event))
 506                 value |= GENMASK(63, 32);
 507
 508         return value;
 509 }
 510
 511 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
 512 {
 513         if (armv8pmu_event_needs_bias(event))
 514                 value &= ~GENMASK(63, 32);
 515
 516         return value;
 517 }
 518
 519 static u64 armv8pmu_read_counter(struct perf_event *event)
 520 {
 521         struct hw_perf_event *hwc = &event->hw;
 522         int idx = hwc->idx;
 523         u64 value = 0;
 524
 525         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 526                 value = read_sysreg(pmccntr_el0);
 527         else
 528                 value = armv8pmu_read_hw_counter(event);
 529
 530         return  armv8pmu_unbias_long_counter(event, value);
 531 }
 532
 533 static inline void armv8pmu_write_evcntr(int idx, u64 value)
 534 {
 535         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 536
 537         write_pmevcntrn(counter, value);
 538 }
 539
 540 static inline void armv8pmu_write_hw_counter(struct perf_event *event,
 541                                              u64 value)
 542 {
 543         int idx = event->hw.idx;
 544
 545         if (armv8pmu_event_is_chained(event)) {
 546                 armv8pmu_write_evcntr(idx, upper_32_bits(value));
 547                 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
 548         } else {
 549                 armv8pmu_write_evcntr(idx, value);
 550         }
 551 }
 552
 553 static void armv8pmu_write_counter(struct perf_event *event, u64 value)
 554 {
 555         struct hw_perf_event *hwc = &event->hw;
 556         int idx = hwc->idx;
 557
 558         value = armv8pmu_bias_long_counter(event, value);
 559
 560         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 561                 write_sysreg(value, pmccntr_el0);
 562         else
 563                 armv8pmu_write_hw_counter(event, value);
 564 }
 565
 566 static inline void armv8pmu_write_evtype(int idx, u32 val)
 567 {
 568         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 569
 570         val &= ARMV8_PMU_EVTYPE_MASK;
 571         write_pmevtypern(counter, val);
 572 }
 573
 574 static inline void armv8pmu_write_event_type(struct perf_event *event)
 575 {
 576         struct hw_perf_event *hwc = &event->hw;
 577         int idx = hwc->idx;
 578
 579         /*
 580          * For chained events, the low counter is programmed to count
 581          * the event of interest and the high counter is programmed
 582          * with CHAIN event code with filters set to count at all ELs.
 583          */
 584         if (armv8pmu_event_is_chained(event)) {
 585                 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
 586                                 ARMV8_PMU_INCLUDE_EL2;
 587
 588                 armv8pmu_write_evtype(idx - 1, hwc->config_base);
 589                 armv8pmu_write_evtype(idx, chain_evt);
 590         } else {
 591                 if (idx == ARMV8_IDX_CYCLE_COUNTER)
 592                         write_sysreg(hwc->config_base, pmccfiltr_el0);
 593                 else
 594                         armv8pmu_write_evtype(idx, hwc->config_base);
 595         }
 596 }
 597
 598 static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
 599 {
 600         int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 601         u32 mask = BIT(counter);
 602
 603         if (armv8pmu_event_is_chained(event))
 604                 mask |= BIT(counter - 1);
 605         return mask;
 606 }
 607
 608 static inline void armv8pmu_enable_counter(u32 mask)
 609 {
 610         /*
 611          * Make sure event configuration register writes are visible before we
 612          * enable the counter.
 613          * */
 614         isb();
 615         write_sysreg(mask, pmcntenset_el0);
 616 }
 617
 618 static inline void armv8pmu_enable_event_counter(struct perf_event *event)
 619 {
 620         struct perf_event_attr *attr = &event->attr;
 621         u32 mask = armv8pmu_event_cnten_mask(event);
 622
 623         kvm_set_pmu_events(mask, attr);
 624
 625         /* We rely on the hypervisor switch code to enable guest counters */
 626         if (!kvm_pmu_counter_deferred(attr))
 627                 armv8pmu_enable_counter(mask);
 628 }
 629
 630 static inline void armv8pmu_disable_counter(u32 mask)
 631 {
 632         write_sysreg(mask, pmcntenclr_el0);
 633         /*
 634          * Make sure the effects of disabling the counter are visible before we
 635          * start configuring the event.
 636          */
 637         isb();
 638 }
 639
 640 static inline void armv8pmu_disable_event_counter(struct perf_event *event)
 641 {
 642         struct perf_event_attr *attr = &event->attr;
 643         u32 mask = armv8pmu_event_cnten_mask(event);
 644
 645         kvm_clr_pmu_events(mask);
 646
 647         /* We rely on the hypervisor switch code to disable guest counters */
 648         if (!kvm_pmu_counter_deferred(attr))
 649                 armv8pmu_disable_counter(mask);
 650 }
 651
 652 static inline void armv8pmu_enable_intens(u32 mask)
 653 {
 654         write_sysreg(mask, pmintenset_el1);
 655 }
 656
 657 static inline void armv8pmu_enable_event_irq(struct perf_event *event)
 658 {
 659         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 660         armv8pmu_enable_intens(BIT(counter));
 661 }
 662
 663 static inline void armv8pmu_disable_intens(u32 mask)
 664 {
 665         write_sysreg(mask, pmintenclr_el1);
 666         isb();
 667         /* Clear the overflow flag in case an interrupt is pending. */
 668         write_sysreg(mask, pmovsclr_el0);
 669         isb();
 670 }
 671
 672 static inline void armv8pmu_disable_event_irq(struct perf_event *event)
 673 {
 674         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 675         armv8pmu_disable_intens(BIT(counter));
 676 }
 677
 678 static inline u32 armv8pmu_getreset_flags(void)
 679 {
 680         u32 value;
 681
 682         /* Read */
 683         value = read_sysreg(pmovsclr_el0);
 684
 685         /* Write to clear flags */
 686         value &= ARMV8_PMU_OVSR_MASK;
 687         write_sysreg(value, pmovsclr_el0);
 688
 689         return value;
 690 }
 691
 692 static void armv8pmu_enable_event(struct perf_event *event)
 693 {
 694         /*
 695          * Enable counter and interrupt, and set the counter to count
 696          * the event that we're interested in.
 697          */
 698
 699         /*
 700          * Disable counter
 701          */
 702         armv8pmu_disable_event_counter(event);
 703
 704         /*
 705          * Set event.
 706          */
 707         armv8pmu_write_event_type(event);
 708
 709         /*
 710          * Enable interrupt for this counter
 711          */
 712         armv8pmu_enable_event_irq(event);
 713
 714         /*
 715          * Enable counter
 716          */
 717         armv8pmu_enable_event_counter(event);
 718 }
 719
 720 static void armv8pmu_disable_event(struct perf_event *event)
 721 {
 722         /*
 723          * Disable counter
 724          */
 725         armv8pmu_disable_event_counter(event);
 726
 727         /*
 728          * Disable interrupt for this counter
 729          */
 730         armv8pmu_disable_event_irq(event);
 731 }
 732
 733 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 734 {
 735         /* Enable all counters */
 736         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 737 }
 738
 739 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 740 {
 741         /* Disable all counters */
 742         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 743 }
 744
 745 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
 746 {
 747         u32 pmovsr;
 748         struct perf_sample_data data;
 749         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 750         struct pt_regs *regs;
 751         int idx;
 752
 753         /*
 754          * Get and reset the IRQ flags
 755          */
 756         pmovsr = armv8pmu_getreset_flags();
 757
 758         /*
 759          * Did an overflow occur?
 760          */
 761         if (!armv8pmu_has_overflowed(pmovsr))
 762                 return IRQ_NONE;
 763
 764         /*
 765          * Handle the counter(s) overflow(s)
 766          */
 767         regs = get_irq_regs();
 768
 769         /*
 770          * Stop the PMU while processing the counter overflows
 771          * to prevent skews in group events.
 772          */
 773         armv8pmu_stop(cpu_pmu);
 774         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 775                 struct perf_event *event = cpuc->events[idx];
 776                 struct hw_perf_event *hwc;
 777
 778                 /* Ignore if we don't have an event. */
 779                 if (!event)
 780                         continue;
 781
 782                 /*
 783                  * We have a single interrupt for all counters. Check that
 784                  * each counter has overflowed before we process it.
 785                  */
 786                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 787                         continue;
 788
 789                 hwc = &event->hw;
 790                 armpmu_event_update(event);
 791                 perf_sample_data_init(&data, 0, hwc->last_period);
 792                 if (!armpmu_event_set_period(event))
 793                         continue;
 794
 795                 /*
 796                  * Perf event overflow will queue the processing of the event as
 797                  * an irq_work which will be taken care of in the handling of
 798                  * IPI_IRQ_WORK.
 799                  */
 800                 if (perf_event_overflow(event, &data, regs))
 801                         cpu_pmu->disable(event);
 802         }
 803         armv8pmu_start(cpu_pmu);
 804
 805         return IRQ_HANDLED;
 806 }
 807
 808 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
 809                                     struct arm_pmu *cpu_pmu)
 810 {
 811         int idx;
 812
 813         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx ++) {
 814                 if (!test_and_set_bit(idx, cpuc->used_mask))
 815                         return idx;
 816         }
 817         return -EAGAIN;
 818 }
 819
 820 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
 821                                    struct arm_pmu *cpu_pmu)
 822 {
 823         int idx;
 824
 825         /*
 826          * Chaining requires two consecutive event counters, where
 827          * the lower idx must be even.
 828          */
 829         for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
 830                 if (!test_and_set_bit(idx, cpuc->used_mask)) {
 831                         /* Check if the preceding even counter is available */
 832                         if (!test_and_set_bit(idx - 1, cpuc->used_mask))
 833                                 return idx;
 834                         /* Release the Odd counter */
 835                         clear_bit(idx, cpuc->used_mask);
 836                 }
 837         }
 838         return -EAGAIN;
 839 }
 840
 841 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 842                                   struct perf_event *event)
 843 {
 844         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 845         struct hw_perf_event *hwc = &event->hw;
 846         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 847
 848         /* Always prefer to place a cycle counter into the cycle counter. */
 849         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 850                 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 851                         return ARMV8_IDX_CYCLE_COUNTER;
 852         }
 853
 854         /*
 855          * Otherwise use events counters
 856          */
 857         if (armv8pmu_event_is_64bit(event) &&
 858             !armv8pmu_has_long_event(cpu_pmu))
 859                 return  armv8pmu_get_chain_idx(cpuc, cpu_pmu);
 860         else
 861                 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
 862 }
 863
 864 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
 865                                      struct perf_event *event)
 866 {
 867         int idx = event->hw.idx;
 868
 869         clear_bit(idx, cpuc->used_mask);
 870         if (armv8pmu_event_is_chained(event))
 871                 clear_bit(idx - 1, cpuc->used_mask);
 872 }
 873
 874 /*
 875  * Add an event filter to a given event.
 876  */
 877 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 878                                      struct perf_event_attr *attr)
 879 {
 880         unsigned long config_base = 0;
 881
 882         if (attr->exclude_idle)
 883                 return -EPERM;
 884
 885         /*
 886          * If we're running in hyp mode, then we *are* the hypervisor.
 887          * Therefore we ignore exclude_hv in this configuration, since
 888          * there's no hypervisor to sample anyway. This is consistent
 889          * with other architectures (x86 and Power).
 890          */
 891         if (is_kernel_in_hyp_mode()) {
 892                 if (!attr->exclude_kernel && !attr->exclude_host)
 893                         config_base |= ARMV8_PMU_INCLUDE_EL2;
 894                 if (attr->exclude_guest)
 895                         config_base |= ARMV8_PMU_EXCLUDE_EL1;
 896                 if (attr->exclude_host)
 897                         config_base |= ARMV8_PMU_EXCLUDE_EL0;
 898         } else {
 899                 if (!attr->exclude_hv && !attr->exclude_host)
 900                         config_base |= ARMV8_PMU_INCLUDE_EL2;
 901         }
 902
 903         /*
 904          * Filter out !VHE kernels and guest kernels
 905          */
 906         if (attr->exclude_kernel)
 907                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
 908
 909         if (attr->exclude_user)
 910                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
 911
 912         /*
 913          * Install the filter into config_base as this is used to
 914          * construct the event type.
 915          */
 916         event->config_base = config_base;
 917
 918         return 0;
 919 }
 920
 921 static int armv8pmu_filter_match(struct perf_event *event)
 922 {
 923         unsigned long evtype = event->hw.config_base & ARMV8_PMU_EVTYPE_EVENT;
 924         return evtype != ARMV8_PMUV3_PERFCTR_CHAIN;
 925 }
 926
 927 static void armv8pmu_reset(void *info)
 928 {
 929         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 930         u32 pmcr;
 931
 932         /* The counter and interrupt enable registers are unknown at reset. */
 933         armv8pmu_disable_counter(U32_MAX);
 934         armv8pmu_disable_intens(U32_MAX);
 935
 936         /* Clear the counters we flip at guest entry/exit */
 937         kvm_clr_pmu_events(U32_MAX);
 938
 939         /*
 940          * Initialize & Reset PMNC. Request overflow interrupt for
 941          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 942          */
 943         pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
 944
 945         /* Enable long event counter support where available */
 946         if (armv8pmu_has_long_event(cpu_pmu))
 947                 pmcr |= ARMV8_PMU_PMCR_LP;
 948
 949         armv8pmu_pmcr_write(pmcr);
 950 }
 951
 952 static int __armv8_pmuv3_map_event(struct perf_event *event,
 953                                    const unsigned (*extra_event_map)
 954                                                   [PERF_COUNT_HW_MAX],
 955                                    const unsigned (*extra_cache_map)
 956                                                   [PERF_COUNT_HW_CACHE_MAX]
 957                                                   [PERF_COUNT_HW_CACHE_OP_MAX]
 958                                                   [PERF_COUNT_HW_CACHE_RESULT_MAX])
 959 {
 960         int hw_event_id;
 961         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 962
 963         hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
 964                                        &armv8_pmuv3_perf_cache_map,
 965                                        ARMV8_PMU_EVTYPE_EVENT);
 966
 967         if (armv8pmu_event_is_64bit(event))
 968                 event->hw.flags |= ARMPMU_EVT_64BIT;
 969
 970         /* Only expose micro/arch events supported by this PMU */
 971         if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
 972             && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
 973                 return hw_event_id;
 974         }
 975
 976         return armpmu_map_event(event, extra_event_map, extra_cache_map,
 977                                 ARMV8_PMU_EVTYPE_EVENT);
 978 }
 979
 980 static int armv8_pmuv3_map_event(struct perf_event *event)
 981 {
 982         return __armv8_pmuv3_map_event(event, NULL, NULL);
 983 }
 984
 985 static int armv8_a53_map_event(struct perf_event *event)
 986 {
 987         return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
 988 }
 989
 990 static int armv8_a57_map_event(struct perf_event *event)
 991 {
 992         return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
 993 }
 994
 995 static int armv8_a73_map_event(struct perf_event *event)
 996 {
 997         return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
 998 }
 999
1000 static int armv8_thunder_map_event(struct perf_event *event)
1001 {
1002         return __armv8_pmuv3_map_event(event, NULL,
1003                                        &armv8_thunder_perf_cache_map);
1004 }
1005
1006 static int armv8_vulcan_map_event(struct perf_event *event)
1007 {
1008         return __armv8_pmuv3_map_event(event, NULL,
1009                                        &armv8_vulcan_perf_cache_map);
1010 }
1011
1012 struct armv8pmu_probe_info {
1013         struct arm_pmu *pmu;
1014         bool present;
1015 };
1016
1017 static void __armv8pmu_probe_pmu(void *info)
1018 {
1019         struct armv8pmu_probe_info *probe = info;
1020         struct arm_pmu *cpu_pmu = probe->pmu;
1021         u64 dfr0;
1022         u64 pmceid_raw[2];
1023         u32 pmceid[2];
1024         int pmuver;
1025
1026         dfr0 = read_sysreg(id_aa64dfr0_el1);
1027         pmuver = cpuid_feature_extract_unsigned_field(dfr0,
1028                         ID_AA64DFR0_PMUVER_SHIFT);
1029         if (pmuver == 0xf || pmuver == 0)
1030                 return;
1031
1032         cpu_pmu->pmuver = pmuver;
1033         probe->present = true;
1034
1035         /* Read the nb of CNTx counters supported from PMNC */
1036         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1037                 & ARMV8_PMU_PMCR_N_MASK;
1038
1039         /* Add the CPU cycles counter */
1040         cpu_pmu->num_events += 1;
1041
1042         pmceid[0] = pmceid_raw[0] = read_sysreg(pmceid0_el0);
1043         pmceid[1] = pmceid_raw[1] = read_sysreg(pmceid1_el0);
1044
1045         bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1046                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1047
1048         pmceid[0] = pmceid_raw[0] >> 32;
1049         pmceid[1] = pmceid_raw[1] >> 32;
1050
1051         bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1052                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1053
1054         /* store PMMIR_EL1 register for sysfs */
1055         if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid_raw[1] & BIT(31)))
1056                 cpu_pmu->reg_pmmir = read_cpuid(PMMIR_EL1);
1057         else
1058                 cpu_pmu->reg_pmmir = 0;
1059 }
1060
1061 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1062 {
1063         struct armv8pmu_probe_info probe = {
1064                 .pmu = cpu_pmu,
1065                 .present = false,
1066         };
1067         int ret;
1068
1069         ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1070                                     __armv8pmu_probe_pmu,
1071                                     &probe, 1);
1072         if (ret)
1073                 return ret;
1074
1075         return probe.present ? 0 : -ENODEV;
1076 }
1077
1078 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1079                           int (*map_event)(struct perf_event *event),
1080                           const struct attribute_group *events,
1081                           const struct attribute_group *format,
1082                           const struct attribute_group *caps)
1083 {
1084         int ret = armv8pmu_probe_pmu(cpu_pmu);
1085         if (ret)
1086                 return ret;
1087
1088         cpu_pmu->handle_irq             = armv8pmu_handle_irq;
1089         cpu_pmu->enable                 = armv8pmu_enable_event;
1090         cpu_pmu->disable                = armv8pmu_disable_event;
1091         cpu_pmu->read_counter           = armv8pmu_read_counter;
1092         cpu_pmu->write_counter          = armv8pmu_write_counter;
1093         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx;
1094         cpu_pmu->clear_event_idx        = armv8pmu_clear_event_idx;
1095         cpu_pmu->start                  = armv8pmu_start;
1096         cpu_pmu->stop                   = armv8pmu_stop;
1097         cpu_pmu->reset                  = armv8pmu_reset;
1098         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1099         cpu_pmu->filter_match           = armv8pmu_filter_match;
1100
1101         cpu_pmu->name                   = name;
1102         cpu_pmu->map_event              = map_event;
1103         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1104                         events : &armv8_pmuv3_events_attr_group;
1105         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1106                         format : &armv8_pmuv3_format_attr_group;
1107         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1108                         caps : &armv8_pmuv3_caps_attr_group;
1109
1110         return 0;
1111 }
1112
1113 static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1114                                    int (*map_event)(struct perf_event *event))
1115 {
1116         return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1117 }
1118
1119 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
1120 {
1121         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
1122                                        armv8_pmuv3_map_event);
1123 }
1124
1125 static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
1126 {
1127         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
1128                                        armv8_pmuv3_map_event);
1129 }
1130
1131 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1132 {
1133         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1134                                        armv8_a53_map_event);
1135 }
1136
1137 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1138 {
1139         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1140                                        armv8_a53_map_event);
1141 }
1142
1143 static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
1144 {
1145         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
1146                                        armv8_pmuv3_map_event);
1147 }
1148
1149 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1150 {
1151         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1152                                        armv8_a57_map_event);
1153 }
1154
1155 static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
1156 {
1157         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
1158                                        armv8_pmuv3_map_event);
1159 }
1160
1161 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1162 {
1163         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1164                                        armv8_a57_map_event);
1165 }
1166
1167 static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1168 {
1169         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1170                                        armv8_a73_map_event);
1171 }
1172
1173 static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
1174 {
1175         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
1176                                        armv8_pmuv3_map_event);
1177 }
1178
1179 static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
1180 {
1181         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
1182                                        armv8_pmuv3_map_event);
1183 }
1184
1185 static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
1186 {
1187         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
1188                                        armv8_pmuv3_map_event);
1189 }
1190
1191 static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
1192 {
1193         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
1194                                        armv8_pmuv3_map_event);
1195 }
1196
1197 static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
1198 {
1199         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
1200                                        armv8_pmuv3_map_event);
1201 }
1202
1203 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1204 {
1205         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1206                                        armv8_thunder_map_event);
1207 }
1208
1209 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1210 {
1211         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1212                                        armv8_vulcan_map_event);
1213 }
1214
1215 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1216         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
1217         {.compatible = "arm,cortex-a34-pmu",    .data = armv8_a34_pmu_init},
1218         {.compatible = "arm,cortex-a35-pmu",    .data = armv8_a35_pmu_init},
1219         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1220         {.compatible = "arm,cortex-a55-pmu",    .data = armv8_a55_pmu_init},
1221         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1222         {.compatible = "arm,cortex-a65-pmu",    .data = armv8_a65_pmu_init},
1223         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1224         {.compatible = "arm,cortex-a73-pmu",    .data = armv8_a73_pmu_init},
1225         {.compatible = "arm,cortex-a75-pmu",    .data = armv8_a75_pmu_init},
1226         {.compatible = "arm,cortex-a76-pmu",    .data = armv8_a76_pmu_init},
1227         {.compatible = "arm,cortex-a77-pmu",    .data = armv8_a77_pmu_init},
1228         {.compatible = "arm,neoverse-e1-pmu",   .data = armv8_e1_pmu_init},
1229         {.compatible = "arm,neoverse-n1-pmu",   .data = armv8_n1_pmu_init},
1230         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1231         {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1232         {},
1233 };
1234
1235 static int armv8_pmu_device_probe(struct platform_device *pdev)
1236 {
1237         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1238 }
1239
1240 static struct platform_driver armv8_pmu_driver = {
1241         .driver         = {
1242                 .name   = ARMV8_PMU_PDEV_NAME,
1243                 .of_match_table = armv8_pmu_of_device_ids,
1244                 .suppress_bind_attrs = true,
1245         },
1246         .probe          = armv8_pmu_device_probe,
1247 };
1248
1249 static int __init armv8_pmu_driver_init(void)
1250 {
1251         if (acpi_disabled)
1252                 return platform_driver_register(&armv8_pmu_driver);
1253         else
1254                 return arm_pmu_acpi_probe(armv8_pmuv3_init);
1255 }
1256 device_initcall(armv8_pmu_driver_init)
1257
1258 void arch_perf_update_userpage(struct perf_event *event,
1259                                struct perf_event_mmap_page *userpg, u64 now)
1260 {
1261         struct clock_read_data *rd;
1262         unsigned int seq;
1263         u64 ns;
1264
1265         userpg->cap_user_time = 0;
1266         userpg->cap_user_time_zero = 0;
1267         userpg->cap_user_time_short = 0;
1268
1269         do {
1270                 rd = sched_clock_read_begin(&seq);
1271
1272                 if (rd->read_sched_clock != arch_timer_read_counter)
1273                         return;
1274
1275                 userpg->time_mult = rd->mult;
1276                 userpg->time_shift = rd->shift;
1277                 userpg->time_zero = rd->epoch_ns;
1278                 userpg->time_cycles = rd->epoch_cyc;
1279                 userpg->time_mask = rd->sched_clock_mask;
1280
1281                 /*
1282                  * Subtract the cycle base, such that software that
1283                  * doesn't know about cap_user_time_short still 'works'
1284                  * assuming no wraps.
1285                  */
1286                 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1287                 userpg->time_zero -= ns;
1288
1289         } while (sched_clock_read_retry(seq));
1290
1291         userpg->time_offset = userpg->time_zero - now;
1292
1293         /*
1294          * time_shift is not expected to be greater than 31 due to
1295          * the original published conversion algorithm shifting a
1296          * 32-bit value (now specifies a 64-bit value) - refer
1297          * perf_event_mmap_page documentation in perf_event.h.
1298          */
1299         if (userpg->time_shift == 32) {
1300                 userpg->time_shift = 31;
1301                 userpg->time_mult >>= 1;
1302         }
1303
1304         /*
1305          * Internal timekeeping for enabled/running/stopped times
1306          * is always computed with the sched_clock.
1307          */
1308         userpg->cap_user_time = 1;
1309         userpg->cap_user_time_zero = 1;
1310         userpg->cap_user_time_short = 1;
1311 }