arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/sort.h>
  14 #include <linux/stop_machine.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/cpu.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/cpu_ops.h>
  21 #include <asm/fpsimd.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/processor.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/traps.h>
  26 #include <asm/virt.h>
  27
  28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  29 static unsigned long elf_hwcap __read_mostly;
  30
  31 #ifdef CONFIG_COMPAT
  32 #define COMPAT_ELF_HWCAP_DEFAULT        \
  33                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  34                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  35                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  36                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  37                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  38                                  COMPAT_HWCAP_LPAE)
  39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  40 unsigned int compat_elf_hwcap2 __read_mostly;
  41 #endif
  42
  43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  44 EXPORT_SYMBOL(cpu_hwcaps);
  45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  46
  47 /* Need also bit for ARM64_CB_PATCH */
  48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  49
  50 /*
  51  * Flag to indicate if we have computed the system wide
  52  * capabilities based on the boot time active CPUs. This
  53  * will be used to determine if a new booting CPU should
  54  * go through the verification process to make sure that it
  55  * supports the system capabilities, without using a hotplug
  56  * notifier.
  57  */
  58 static bool sys_caps_initialised;
  59
  60 static inline void set_sys_caps_initialised(void)
  61 {
  62         sys_caps_initialised = true;
  63 }
  64
  65 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  66 {
  67         /* file-wide pr_fmt adds "CPU features: " prefix */
  68         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  69         return 0;
  70 }
  71
  72 static struct notifier_block cpu_hwcaps_notifier = {
  73         .notifier_call = dump_cpu_hwcaps
  74 };
  75
  76 static int __init register_cpu_hwcaps_dumper(void)
  77 {
  78         atomic_notifier_chain_register(&panic_notifier_list,
  79                                        &cpu_hwcaps_notifier);
  80         return 0;
  81 }
  82 __initcall(register_cpu_hwcaps_dumper);
  83
  84 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  85 EXPORT_SYMBOL(cpu_hwcap_keys);
  86
  87 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  88         {                                               \
  89                 .sign = SIGNED,                         \
  90                 .visible = VISIBLE,                     \
  91                 .strict = STRICT,                       \
  92                 .type = TYPE,                           \
  93                 .shift = SHIFT,                         \
  94                 .width = WIDTH,                         \
  95                 .safe_val = SAFE_VAL,                   \
  96         }
  97
  98 /* Define a feature with unsigned values */
  99 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 100         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 101
 102 /* Define a feature with a signed value */
 103 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 104         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 105
 106 #define ARM64_FTR_END                                   \
 107         {                                               \
 108                 .width = 0,                             \
 109         }
 110
 111 /* meta feature for alternatives */
 112 static bool __maybe_unused
 113 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 114
 115 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 116
 117 /*
 118  * NOTE: Any changes to the visibility of features should be kept in
 119  * sync with the documentation of the CPU feature register ABI.
 120  */
 121 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 134         ARM64_FTR_END,
 135 };
 136
 137 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 145                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 147                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 151         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 152                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 153         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 154                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 155         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 156         ARM64_FTR_END,
 157 };
 158
 159 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 162         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 163         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 164                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 167         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 168         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 169         /* Linux doesn't care about the EL3 */
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 172         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 173         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 174         ARM64_FTR_END,
 175 };
 176
 177 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 178         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 179         ARM64_FTR_END,
 180 };
 181
 182 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 183         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 184                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 186                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 188                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 190                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 192                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 194                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 196                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 198                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 199         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 200                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 201         ARM64_FTR_END,
 202 };
 203
 204 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 205         /*
 206          * We already refuse to boot CPUs that don't support our configured
 207          * page size, so we can only detect mismatches for a page size other
 208          * than the one we're currently using. Unfortunately, SoCs like this
 209          * exist in the wild so, even though we don't like it, we'll have to go
 210          * along with it and treat them as non-strict.
 211          */
 212         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 213         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 214         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 215
 216         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 217         /* Linux shouldn't care about secure memory */
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 221         /*
 222          * Differing PARange is fine as long as all peripherals and memory are mapped
 223          * within the minimum PARange of all CPUs
 224          */
 225         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 226         ARM64_FTR_END,
 227 };
 228
 229 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 234         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 235         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 236         ARM64_FTR_END,
 237 };
 238
 239 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 243         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 244         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 245         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 246         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 247         ARM64_FTR_END,
 248 };
 249
 250 static const struct arm64_ftr_bits ftr_ctr[] = {
 251         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 252         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 253         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 254         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 255         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 256         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 257         /*
 258          * Linux can handle differing I-cache policies. Userspace JITs will
 259          * make use of *minLine.
 260          * If we have differing I-cache policies, report it as the weakest - VIPT.
 261          */
 262         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 263         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 264         ARM64_FTR_END,
 265 };
 266
 267 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 268         .name           = "SYS_CTR_EL0",
 269         .ftr_bits       = ftr_ctr
 270 };
 271
 272 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 273         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 278         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 281         ARM64_FTR_END,
 282 };
 283
 284 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 286         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 287         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 288         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 289         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 290         /*
 291          * We can instantiate multiple PMU instances with different levels
 292          * of support.
 293          */
 294         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 295         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 296         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 297         ARM64_FTR_END,
 298 };
 299
 300 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 302         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 303         ARM64_FTR_END,
 304 };
 305
 306 static const struct arm64_ftr_bits ftr_dczid[] = {
 307         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 308         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 309         ARM64_FTR_END,
 310 };
 311
 312
 313 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 314         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 320         ARM64_FTR_END,
 321 };
 322
 323 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 325         ARM64_FTR_END,
 326 };
 327
 328 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 330         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 331         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 332         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 333         ARM64_FTR_END,
 334 };
 335
 336 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 338         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 342         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 343         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 344         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 345         ARM64_FTR_END,
 346 };
 347
 348 static const struct arm64_ftr_bits ftr_zcr[] = {
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 350                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 351         ARM64_FTR_END,
 352 };
 353
 354 /*
 355  * Common ftr bits for a 32bit register with all hidden, strict
 356  * attributes, with 4bit feature fields and a default safe value of
 357  * 0. Covers the following 32bit registers:
 358  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 359  */
 360 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 361         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 362         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 363         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 364         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 365         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 366         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 367         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 368         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 369         ARM64_FTR_END,
 370 };
 371
 372 /* Table for a single 32bit feature value */
 373 static const struct arm64_ftr_bits ftr_single32[] = {
 374         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 375         ARM64_FTR_END,
 376 };
 377
 378 static const struct arm64_ftr_bits ftr_raz[] = {
 379         ARM64_FTR_END,
 380 };
 381
 382 #define ARM64_FTR_REG(id, table) {              \
 383         .sys_id = id,                           \
 384         .reg =  &(struct arm64_ftr_reg){        \
 385                 .name = #id,                    \
 386                 .ftr_bits = &((table)[0]),      \
 387         }}
 388
 389 static const struct __ftr_reg_entry {
 390         u32                     sys_id;
 391         struct arm64_ftr_reg    *reg;
 392 } arm64_ftr_regs[] = {
 393
 394         /* Op1 = 0, CRn = 0, CRm = 1 */
 395         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 396         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 397         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 398         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 399         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 400         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 401         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 402
 403         /* Op1 = 0, CRn = 0, CRm = 2 */
 404         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 405         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 406         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 407         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 408         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 409         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 410         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 411
 412         /* Op1 = 0, CRn = 0, CRm = 3 */
 413         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 414         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 415         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 416
 417         /* Op1 = 0, CRn = 0, CRm = 4 */
 418         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 419         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 420         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 421
 422         /* Op1 = 0, CRn = 0, CRm = 5 */
 423         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 424         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 425
 426         /* Op1 = 0, CRn = 0, CRm = 6 */
 427         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 428         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 429
 430         /* Op1 = 0, CRn = 0, CRm = 7 */
 431         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 432         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 433         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 434
 435         /* Op1 = 0, CRn = 1, CRm = 2 */
 436         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 437
 438         /* Op1 = 3, CRn = 0, CRm = 0 */
 439         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 440         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 441
 442         /* Op1 = 3, CRn = 14, CRm = 0 */
 443         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 444 };
 445
 446 static int search_cmp_ftr_reg(const void *id, const void *regp)
 447 {
 448         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 449 }
 450
 451 /*
 452  * get_arm64_ftr_reg - Lookup a feature register entry using its
 453  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 454  * ascending order of sys_id , we use binary search to find a matching
 455  * entry.
 456  *
 457  * returns - Upon success,  matching ftr_reg entry for id.
 458  *         - NULL on failure. It is upto the caller to decide
 459  *           the impact of a failure.
 460  */
 461 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 462 {
 463         const struct __ftr_reg_entry *ret;
 464
 465         ret = bsearch((const void *)(unsigned long)sys_id,
 466                         arm64_ftr_regs,
 467                         ARRAY_SIZE(arm64_ftr_regs),
 468                         sizeof(arm64_ftr_regs[0]),
 469                         search_cmp_ftr_reg);
 470         if (ret)
 471                 return ret->reg;
 472         return NULL;
 473 }
 474
 475 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 476                                s64 ftr_val)
 477 {
 478         u64 mask = arm64_ftr_mask(ftrp);
 479
 480         reg &= ~mask;
 481         reg |= (ftr_val << ftrp->shift) & mask;
 482         return reg;
 483 }
 484
 485 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 486                                 s64 cur)
 487 {
 488         s64 ret = 0;
 489
 490         switch (ftrp->type) {
 491         case FTR_EXACT:
 492                 ret = ftrp->safe_val;
 493                 break;
 494         case FTR_LOWER_SAFE:
 495                 ret = new < cur ? new : cur;
 496                 break;
 497         case FTR_HIGHER_OR_ZERO_SAFE:
 498                 if (!cur || !new)
 499                         break;
 500                 /* Fallthrough */
 501         case FTR_HIGHER_SAFE:
 502                 ret = new > cur ? new : cur;
 503                 break;
 504         default:
 505                 BUG();
 506         }
 507
 508         return ret;
 509 }
 510
 511 static void __init sort_ftr_regs(void)
 512 {
 513         int i;
 514
 515         /* Check that the array is sorted so that we can do the binary search */
 516         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 517                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 518 }
 519
 520 /*
 521  * Initialise the CPU feature register from Boot CPU values.
 522  * Also initiliases the strict_mask for the register.
 523  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 524  * RES0 for the system-wide value, and must strictly match.
 525  */
 526 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 527 {
 528         u64 val = 0;
 529         u64 strict_mask = ~0x0ULL;
 530         u64 user_mask = 0;
 531         u64 valid_mask = 0;
 532
 533         const struct arm64_ftr_bits *ftrp;
 534         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 535
 536         BUG_ON(!reg);
 537
 538         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 539                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 540                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 541
 542                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 543
 544                 valid_mask |= ftr_mask;
 545                 if (!ftrp->strict)
 546                         strict_mask &= ~ftr_mask;
 547                 if (ftrp->visible)
 548                         user_mask |= ftr_mask;
 549                 else
 550                         reg->user_val = arm64_ftr_set_value(ftrp,
 551                                                             reg->user_val,
 552                                                             ftrp->safe_val);
 553         }
 554
 555         val &= valid_mask;
 556
 557         reg->sys_val = val;
 558         reg->strict_mask = strict_mask;
 559         reg->user_mask = user_mask;
 560 }
 561
 562 extern const struct arm64_cpu_capabilities arm64_errata[];
 563 static const struct arm64_cpu_capabilities arm64_features[];
 564
 565 static void __init
 566 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 567 {
 568         for (; caps->matches; caps++) {
 569                 if (WARN(caps->capability >= ARM64_NCAPS,
 570                         "Invalid capability %d\n", caps->capability))
 571                         continue;
 572                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 573                         "Duplicate entry for capability %d\n",
 574                         caps->capability))
 575                         continue;
 576                 cpu_hwcaps_ptrs[caps->capability] = caps;
 577         }
 578 }
 579
 580 static void __init init_cpu_hwcaps_indirect_list(void)
 581 {
 582         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 583         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 584 }
 585
 586 static void __init setup_boot_cpu_capabilities(void);
 587
 588 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 589 {
 590         /* Before we start using the tables, make sure it is sorted */
 591         sort_ftr_regs();
 592
 593         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 594         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 595         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 596         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 597         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 598         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 599         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 600         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 601         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 602         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 603         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 604         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 605         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 606
 607         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 608                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 609                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 610                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 611                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 612                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 613                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 614                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 615                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 616                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 617                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 618                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 619                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 620                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 621                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 622                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 623                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 624         }
 625
 626         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 627                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 628                 sve_init_vq_map();
 629         }
 630
 631         /*
 632          * Initialize the indirect array of CPU hwcaps capabilities pointers
 633          * before we handle the boot CPU below.
 634          */
 635         init_cpu_hwcaps_indirect_list();
 636
 637         /*
 638          * Detect and enable early CPU capabilities based on the boot CPU,
 639          * after we have initialised the CPU feature infrastructure.
 640          */
 641         setup_boot_cpu_capabilities();
 642 }
 643
 644 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 645 {
 646         const struct arm64_ftr_bits *ftrp;
 647
 648         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 649                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 650                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 651
 652                 if (ftr_cur == ftr_new)
 653                         continue;
 654                 /* Find a safe value */
 655                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 656                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 657         }
 658
 659 }
 660
 661 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 662 {
 663         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 664
 665         BUG_ON(!regp);
 666         update_cpu_ftr_reg(regp, val);
 667         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 668                 return 0;
 669         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 670                         regp->name, boot, cpu, val);
 671         return 1;
 672 }
 673
 674 /*
 675  * Update system wide CPU feature registers with the values from a
 676  * non-boot CPU. Also performs SANITY checks to make sure that there
 677  * aren't any insane variations from that of the boot CPU.
 678  */
 679 void update_cpu_features(int cpu,
 680                          struct cpuinfo_arm64 *info,
 681                          struct cpuinfo_arm64 *boot)
 682 {
 683         int taint = 0;
 684
 685         /*
 686          * The kernel can handle differing I-cache policies, but otherwise
 687          * caches should look identical. Userspace JITs will make use of
 688          * *minLine.
 689          */
 690         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 691                                       info->reg_ctr, boot->reg_ctr);
 692
 693         /*
 694          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 695          * could result in too much or too little memory being zeroed if a
 696          * process is preempted and migrated between CPUs.
 697          */
 698         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 699                                       info->reg_dczid, boot->reg_dczid);
 700
 701         /* If different, timekeeping will be broken (especially with KVM) */
 702         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 703                                       info->reg_cntfrq, boot->reg_cntfrq);
 704
 705         /*
 706          * The kernel uses self-hosted debug features and expects CPUs to
 707          * support identical debug features. We presently need CTX_CMPs, WRPs,
 708          * and BRPs to be identical.
 709          * ID_AA64DFR1 is currently RES0.
 710          */
 711         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 712                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 713         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 714                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 715         /*
 716          * Even in big.LITTLE, processors should be identical instruction-set
 717          * wise.
 718          */
 719         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 720                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 721         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 722                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 723
 724         /*
 725          * Differing PARange support is fine as long as all peripherals and
 726          * memory are mapped within the minimum PARange of all CPUs.
 727          * Linux should not care about secure memory.
 728          */
 729         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 730                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 731         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 732                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 733         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 734                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 735
 736         /*
 737          * EL3 is not our concern.
 738          */
 739         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 740                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 741         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 742                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 743
 744         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 745                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 746
 747         /*
 748          * If we have AArch32, we care about 32-bit features for compat.
 749          * If the system doesn't support AArch32, don't update them.
 750          */
 751         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 752                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 753
 754                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 755                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 756                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 757                                         info->reg_id_isar0, boot->reg_id_isar0);
 758                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 759                                         info->reg_id_isar1, boot->reg_id_isar1);
 760                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 761                                         info->reg_id_isar2, boot->reg_id_isar2);
 762                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 763                                         info->reg_id_isar3, boot->reg_id_isar3);
 764                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 765                                         info->reg_id_isar4, boot->reg_id_isar4);
 766                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 767                                         info->reg_id_isar5, boot->reg_id_isar5);
 768
 769                 /*
 770                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 771                  * ACTLR formats could differ across CPUs and therefore would have to
 772                  * be trapped for virtualization anyway.
 773                  */
 774                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 775                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 776                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 777                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 778                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 779                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 780                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 781                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 782                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 783                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 784                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 785                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 786                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 787                                         info->reg_mvfr0, boot->reg_mvfr0);
 788                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 789                                         info->reg_mvfr1, boot->reg_mvfr1);
 790                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 791                                         info->reg_mvfr2, boot->reg_mvfr2);
 792         }
 793
 794         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 795                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 796                                         info->reg_zcr, boot->reg_zcr);
 797
 798                 /* Probe vector lengths, unless we already gave up on SVE */
 799                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 800                     !sys_caps_initialised)
 801                         sve_update_vq_map();
 802         }
 803
 804         /*
 805          * Mismatched CPU features are a recipe for disaster. Don't even
 806          * pretend to support them.
 807          */
 808         if (taint) {
 809                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 810                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 811         }
 812 }
 813
 814 u64 read_sanitised_ftr_reg(u32 id)
 815 {
 816         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 817
 818         /* We shouldn't get a request for an unsupported register */
 819         BUG_ON(!regp);
 820         return regp->sys_val;
 821 }
 822
 823 #define read_sysreg_case(r)     \
 824         case r:         return read_sysreg_s(r)
 825
 826 /*
 827  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 828  * Read the system register on the current CPU
 829  */
 830 static u64 __read_sysreg_by_encoding(u32 sys_id)
 831 {
 832         switch (sys_id) {
 833         read_sysreg_case(SYS_ID_PFR0_EL1);
 834         read_sysreg_case(SYS_ID_PFR1_EL1);
 835         read_sysreg_case(SYS_ID_DFR0_EL1);
 836         read_sysreg_case(SYS_ID_MMFR0_EL1);
 837         read_sysreg_case(SYS_ID_MMFR1_EL1);
 838         read_sysreg_case(SYS_ID_MMFR2_EL1);
 839         read_sysreg_case(SYS_ID_MMFR3_EL1);
 840         read_sysreg_case(SYS_ID_ISAR0_EL1);
 841         read_sysreg_case(SYS_ID_ISAR1_EL1);
 842         read_sysreg_case(SYS_ID_ISAR2_EL1);
 843         read_sysreg_case(SYS_ID_ISAR3_EL1);
 844         read_sysreg_case(SYS_ID_ISAR4_EL1);
 845         read_sysreg_case(SYS_ID_ISAR5_EL1);
 846         read_sysreg_case(SYS_MVFR0_EL1);
 847         read_sysreg_case(SYS_MVFR1_EL1);
 848         read_sysreg_case(SYS_MVFR2_EL1);
 849
 850         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 851         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 852         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 853         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 854         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 855         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 856         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 857         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 858         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 859         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 860
 861         read_sysreg_case(SYS_CNTFRQ_EL0);
 862         read_sysreg_case(SYS_CTR_EL0);
 863         read_sysreg_case(SYS_DCZID_EL0);
 864
 865         default:
 866                 BUG();
 867                 return 0;
 868         }
 869 }
 870
 871 #include <linux/irqchip/arm-gic-v3.h>
 872
 873 static bool
 874 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 875 {
 876         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 877
 878         return val >= entry->min_field_value;
 879 }
 880
 881 static bool
 882 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 883 {
 884         u64 val;
 885
 886         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 887         if (scope == SCOPE_SYSTEM)
 888                 val = read_sanitised_ftr_reg(entry->sys_reg);
 889         else
 890                 val = __read_sysreg_by_encoding(entry->sys_reg);
 891
 892         return feature_matches(val, entry);
 893 }
 894
 895 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 896 {
 897         bool has_sre;
 898
 899         if (!has_cpuid_feature(entry, scope))
 900                 return false;
 901
 902         has_sre = gic_enable_sre();
 903         if (!has_sre)
 904                 pr_warn_once("%s present but disabled by higher exception level\n",
 905                              entry->desc);
 906
 907         return has_sre;
 908 }
 909
 910 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 911 {
 912         u32 midr = read_cpuid_id();
 913
 914         /* Cavium ThunderX pass 1.x and 2.x */
 915         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 916                 MIDR_CPU_VAR_REV(0, 0),
 917                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 918 }
 919
 920 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 921 {
 922         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 923
 924         return cpuid_feature_extract_signed_field(pfr0,
 925                                         ID_AA64PFR0_FP_SHIFT) < 0;
 926 }
 927
 928 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 929                           int scope)
 930 {
 931         u64 ctr;
 932
 933         if (scope == SCOPE_SYSTEM)
 934                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 935         else
 936                 ctr = read_cpuid_effective_cachetype();
 937
 938         return ctr & BIT(CTR_IDC_SHIFT);
 939 }
 940
 941 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 942 {
 943         /*
 944          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 945          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 946          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 947          * value.
 948          */
 949         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 950                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 951 }
 952
 953 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 954                           int scope)
 955 {
 956         u64 ctr;
 957
 958         if (scope == SCOPE_SYSTEM)
 959                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 960         else
 961                 ctr = read_cpuid_cachetype();
 962
 963         return ctr & BIT(CTR_DIC_SHIFT);
 964 }
 965
 966 static bool __maybe_unused
 967 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 968 {
 969         /*
 970          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 971          * may share TLB entries with a CPU stuck in the crashed
 972          * kernel.
 973          */
 974          if (is_kdump_kernel())
 975                 return false;
 976
 977         return has_cpuid_feature(entry, scope);
 978 }
 979
 980 static bool __meltdown_safe = true;
 981 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 982
 983 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 984                                 int scope)
 985 {
 986         /* List of CPUs that are not vulnerable and don't need KPTI */
 987         static const struct midr_range kpti_safe_list[] = {
 988                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 989                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 990                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 991                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 992                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 993                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 994                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 995                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 996                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 997                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
 998                 { /* sentinel */ }
 999         };
1000         char const *str = "kpti command line option";
1001         bool meltdown_safe;
1002
1003         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1004
1005         /* Defer to CPU feature registers */
1006         if (has_cpuid_feature(entry, scope))
1007                 meltdown_safe = true;
1008
1009         if (!meltdown_safe)
1010                 __meltdown_safe = false;
1011
1012         /*
1013          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1014          * ThunderX leads to apparent I-cache corruption of kernel text, which
1015          * ends as well as you might imagine. Don't even try.
1016          */
1017         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1018                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1019                 __kpti_forced = -1;
1020         }
1021
1022         /* Useful for KASLR robustness */
1023         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1024                 if (!__kpti_forced) {
1025                         str = "KASLR";
1026                         __kpti_forced = 1;
1027                 }
1028         }
1029
1030         if (cpu_mitigations_off() && !__kpti_forced) {
1031                 str = "mitigations=off";
1032                 __kpti_forced = -1;
1033         }
1034
1035         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1036                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1037                 return false;
1038         }
1039
1040         /* Forced? */
1041         if (__kpti_forced) {
1042                 pr_info_once("kernel page table isolation forced %s by %s\n",
1043                              __kpti_forced > 0 ? "ON" : "OFF", str);
1044                 return __kpti_forced > 0;
1045         }
1046
1047         return !meltdown_safe;
1048 }
1049
1050 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1051 static void
1052 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1053 {
1054         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1055         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1056         kpti_remap_fn *remap_fn;
1057
1058         static bool kpti_applied = false;
1059         int cpu = smp_processor_id();
1060
1061         /*
1062          * We don't need to rewrite the page-tables if either we've done
1063          * it already or we have KASLR enabled and therefore have not
1064          * created any global mappings at all.
1065          */
1066         if (kpti_applied || kaslr_offset() > 0)
1067                 return;
1068
1069         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1070
1071         cpu_install_idmap();
1072         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1073         cpu_uninstall_idmap();
1074
1075         if (!cpu)
1076                 kpti_applied = true;
1077
1078         return;
1079 }
1080 #else
1081 static void
1082 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1083 {
1084 }
1085 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1086
1087 static int __init parse_kpti(char *str)
1088 {
1089         bool enabled;
1090         int ret = strtobool(str, &enabled);
1091
1092         if (ret)
1093                 return ret;
1094
1095         __kpti_forced = enabled ? 1 : -1;
1096         return 0;
1097 }
1098 early_param("kpti", parse_kpti);
1099
1100 #ifdef CONFIG_ARM64_HW_AFDBM
1101 static inline void __cpu_enable_hw_dbm(void)
1102 {
1103         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1104
1105         write_sysreg(tcr, tcr_el1);
1106         isb();
1107 }
1108
1109 static bool cpu_has_broken_dbm(void)
1110 {
1111         /* List of CPUs which have broken DBM support. */
1112         static const struct midr_range cpus[] = {
1113 #ifdef CONFIG_ARM64_ERRATUM_1024718
1114                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1115 #endif
1116                 {},
1117         };
1118
1119         return is_midr_in_range_list(read_cpuid_id(), cpus);
1120 }
1121
1122 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1123 {
1124         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1125                !cpu_has_broken_dbm();
1126 }
1127
1128 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1129 {
1130         if (cpu_can_use_dbm(cap))
1131                 __cpu_enable_hw_dbm();
1132 }
1133
1134 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1135                        int __unused)
1136 {
1137         static bool detected = false;
1138         /*
1139          * DBM is a non-conflicting feature. i.e, the kernel can safely
1140          * run a mix of CPUs with and without the feature. So, we
1141          * unconditionally enable the capability to allow any late CPU
1142          * to use the feature. We only enable the control bits on the
1143          * CPU, if it actually supports.
1144          *
1145          * We have to make sure we print the "feature" detection only
1146          * when at least one CPU actually uses it. So check if this CPU
1147          * can actually use it and print the message exactly once.
1148          *
1149          * This is safe as all CPUs (including secondary CPUs - due to the
1150          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1151          * goes through the "matches" check exactly once. Also if a CPU
1152          * matches the criteria, it is guaranteed that the CPU will turn
1153          * the DBM on, as the capability is unconditionally enabled.
1154          */
1155         if (!detected && cpu_can_use_dbm(cap)) {
1156                 detected = true;
1157                 pr_info("detected: Hardware dirty bit management\n");
1158         }
1159
1160         return true;
1161 }
1162
1163 #endif
1164
1165 #ifdef CONFIG_ARM64_VHE
1166 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1167 {
1168         return is_kernel_in_hyp_mode();
1169 }
1170
1171 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1172 {
1173         /*
1174          * Copy register values that aren't redirected by hardware.
1175          *
1176          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1177          * this value to tpidr_el2 before we patch the code. Once we've done
1178          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1179          * do anything here.
1180          */
1181         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1182                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1183 }
1184 #endif
1185
1186 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1187 {
1188         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1189
1190         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1191         WARN_ON(val & (7 << 27 | 7 << 21));
1192 }
1193
1194 #ifdef CONFIG_ARM64_SSBD
1195 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1196 {
1197         if (user_mode(regs))
1198                 return 1;
1199
1200         if (instr & BIT(PSTATE_Imm_shift))
1201                 regs->pstate |= PSR_SSBS_BIT;
1202         else
1203                 regs->pstate &= ~PSR_SSBS_BIT;
1204
1205         arm64_skip_faulting_instruction(regs, 4);
1206         return 0;
1207 }
1208
1209 static struct undef_hook ssbs_emulation_hook = {
1210         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1211         .instr_val      = 0xd500401f | PSTATE_SSBS,
1212         .fn             = ssbs_emulation_handler,
1213 };
1214
1215 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1216 {
1217         static bool undef_hook_registered = false;
1218         static DEFINE_RAW_SPINLOCK(hook_lock);
1219
1220         raw_spin_lock(&hook_lock);
1221         if (!undef_hook_registered) {
1222                 register_undef_hook(&ssbs_emulation_hook);
1223                 undef_hook_registered = true;
1224         }
1225         raw_spin_unlock(&hook_lock);
1226
1227         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1228                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1229                 arm64_set_ssbd_mitigation(false);
1230         } else {
1231                 arm64_set_ssbd_mitigation(true);
1232         }
1233 }
1234 #endif /* CONFIG_ARM64_SSBD */
1235
1236 #ifdef CONFIG_ARM64_PAN
1237 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1238 {
1239         /*
1240          * We modify PSTATE. This won't work from irq context as the PSTATE
1241          * is discarded once we return from the exception.
1242          */
1243         WARN_ON_ONCE(in_interrupt());
1244
1245         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1246         asm(SET_PSTATE_PAN(1));
1247 }
1248 #endif /* CONFIG_ARM64_PAN */
1249
1250 #ifdef CONFIG_ARM64_RAS_EXTN
1251 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1252 {
1253         /* Firmware may have left a deferred SError in this register. */
1254         write_sysreg_s(0, SYS_DISR_EL1);
1255 }
1256 #endif /* CONFIG_ARM64_RAS_EXTN */
1257
1258 #ifdef CONFIG_ARM64_PTR_AUTH
1259 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1260 {
1261         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1262                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1263 }
1264 #endif /* CONFIG_ARM64_PTR_AUTH */
1265
1266 #ifdef CONFIG_ARM64_PSEUDO_NMI
1267 static bool enable_pseudo_nmi;
1268
1269 static int __init early_enable_pseudo_nmi(char *p)
1270 {
1271         return strtobool(p, &enable_pseudo_nmi);
1272 }
1273 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1274
1275 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1276                                    int scope)
1277 {
1278         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1279 }
1280 #endif
1281
1282 static const struct arm64_cpu_capabilities arm64_features[] = {
1283         {
1284                 .desc = "GIC system register CPU interface",
1285                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1286                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1287                 .matches = has_useable_gicv3_cpuif,
1288                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1289                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1290                 .sign = FTR_UNSIGNED,
1291                 .min_field_value = 1,
1292         },
1293 #ifdef CONFIG_ARM64_PAN
1294         {
1295                 .desc = "Privileged Access Never",
1296                 .capability = ARM64_HAS_PAN,
1297                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1298                 .matches = has_cpuid_feature,
1299                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1300                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1301                 .sign = FTR_UNSIGNED,
1302                 .min_field_value = 1,
1303                 .cpu_enable = cpu_enable_pan,
1304         },
1305 #endif /* CONFIG_ARM64_PAN */
1306 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1307         {
1308                 .desc = "LSE atomic instructions",
1309                 .capability = ARM64_HAS_LSE_ATOMICS,
1310                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1311                 .matches = has_cpuid_feature,
1312                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1313                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1314                 .sign = FTR_UNSIGNED,
1315                 .min_field_value = 2,
1316         },
1317 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1318         {
1319                 .desc = "Software prefetching using PRFM",
1320                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1321                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1322                 .matches = has_no_hw_prefetch,
1323         },
1324 #ifdef CONFIG_ARM64_UAO
1325         {
1326                 .desc = "User Access Override",
1327                 .capability = ARM64_HAS_UAO,
1328                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1329                 .matches = has_cpuid_feature,
1330                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1331                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1332                 .min_field_value = 1,
1333                 /*
1334                  * We rely on stop_machine() calling uao_thread_switch() to set
1335                  * UAO immediately after patching.
1336                  */
1337         },
1338 #endif /* CONFIG_ARM64_UAO */
1339 #ifdef CONFIG_ARM64_PAN
1340         {
1341                 .capability = ARM64_ALT_PAN_NOT_UAO,
1342                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1343                 .matches = cpufeature_pan_not_uao,
1344         },
1345 #endif /* CONFIG_ARM64_PAN */
1346 #ifdef CONFIG_ARM64_VHE
1347         {
1348                 .desc = "Virtualization Host Extensions",
1349                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1350                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1351                 .matches = runs_at_el2,
1352                 .cpu_enable = cpu_copy_el2regs,
1353         },
1354 #endif  /* CONFIG_ARM64_VHE */
1355         {
1356                 .desc = "32-bit EL0 Support",
1357                 .capability = ARM64_HAS_32BIT_EL0,
1358                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1359                 .matches = has_cpuid_feature,
1360                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1361                 .sign = FTR_UNSIGNED,
1362                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1363                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1364         },
1365         {
1366                 .desc = "Kernel page table isolation (KPTI)",
1367                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1368                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1369                 /*
1370                  * The ID feature fields below are used to indicate that
1371                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1372                  * more details.
1373                  */
1374                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1375                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1376                 .min_field_value = 1,
1377                 .matches = unmap_kernel_at_el0,
1378                 .cpu_enable = kpti_install_ng_mappings,
1379         },
1380         {
1381                 /* FP/SIMD is not implemented */
1382                 .capability = ARM64_HAS_NO_FPSIMD,
1383                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1384                 .min_field_value = 0,
1385                 .matches = has_no_fpsimd,
1386         },
1387 #ifdef CONFIG_ARM64_PMEM
1388         {
1389                 .desc = "Data cache clean to Point of Persistence",
1390                 .capability = ARM64_HAS_DCPOP,
1391                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1392                 .matches = has_cpuid_feature,
1393                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1394                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1395                 .min_field_value = 1,
1396         },
1397         {
1398                 .desc = "Data cache clean to Point of Deep Persistence",
1399                 .capability = ARM64_HAS_DCPODP,
1400                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1401                 .matches = has_cpuid_feature,
1402                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1403                 .sign = FTR_UNSIGNED,
1404                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1405                 .min_field_value = 2,
1406         },
1407 #endif
1408 #ifdef CONFIG_ARM64_SVE
1409         {
1410                 .desc = "Scalable Vector Extension",
1411                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1412                 .capability = ARM64_SVE,
1413                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1414                 .sign = FTR_UNSIGNED,
1415                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1416                 .min_field_value = ID_AA64PFR0_SVE,
1417                 .matches = has_cpuid_feature,
1418                 .cpu_enable = sve_kernel_enable,
1419         },
1420 #endif /* CONFIG_ARM64_SVE */
1421 #ifdef CONFIG_ARM64_RAS_EXTN
1422         {
1423                 .desc = "RAS Extension Support",
1424                 .capability = ARM64_HAS_RAS_EXTN,
1425                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1426                 .matches = has_cpuid_feature,
1427                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1428                 .sign = FTR_UNSIGNED,
1429                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1430                 .min_field_value = ID_AA64PFR0_RAS_V1,
1431                 .cpu_enable = cpu_clear_disr,
1432         },
1433 #endif /* CONFIG_ARM64_RAS_EXTN */
1434         {
1435                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1436                 .capability = ARM64_HAS_CACHE_IDC,
1437                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1438                 .matches = has_cache_idc,
1439                 .cpu_enable = cpu_emulate_effective_ctr,
1440         },
1441         {
1442                 .desc = "Instruction cache invalidation not required for I/D coherence",
1443                 .capability = ARM64_HAS_CACHE_DIC,
1444                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1445                 .matches = has_cache_dic,
1446         },
1447         {
1448                 .desc = "Stage-2 Force Write-Back",
1449                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1450                 .capability = ARM64_HAS_STAGE2_FWB,
1451                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1452                 .sign = FTR_UNSIGNED,
1453                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1454                 .min_field_value = 1,
1455                 .matches = has_cpuid_feature,
1456                 .cpu_enable = cpu_has_fwb,
1457         },
1458 #ifdef CONFIG_ARM64_HW_AFDBM
1459         {
1460                 /*
1461                  * Since we turn this on always, we don't want the user to
1462                  * think that the feature is available when it may not be.
1463                  * So hide the description.
1464                  *
1465                  * .desc = "Hardware pagetable Dirty Bit Management",
1466                  *
1467                  */
1468                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1469                 .capability = ARM64_HW_DBM,
1470                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1471                 .sign = FTR_UNSIGNED,
1472                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1473                 .min_field_value = 2,
1474                 .matches = has_hw_dbm,
1475                 .cpu_enable = cpu_enable_hw_dbm,
1476         },
1477 #endif
1478         {
1479                 .desc = "CRC32 instructions",
1480                 .capability = ARM64_HAS_CRC32,
1481                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1482                 .matches = has_cpuid_feature,
1483                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1484                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1485                 .min_field_value = 1,
1486         },
1487 #ifdef CONFIG_ARM64_SSBD
1488         {
1489                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1490                 .capability = ARM64_SSBS,
1491                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1492                 .matches = has_cpuid_feature,
1493                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1494                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1495                 .sign = FTR_UNSIGNED,
1496                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1497                 .cpu_enable = cpu_enable_ssbs,
1498         },
1499 #endif
1500 #ifdef CONFIG_ARM64_CNP
1501         {
1502                 .desc = "Common not Private translations",
1503                 .capability = ARM64_HAS_CNP,
1504                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1505                 .matches = has_useable_cnp,
1506                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1507                 .sign = FTR_UNSIGNED,
1508                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1509                 .min_field_value = 1,
1510                 .cpu_enable = cpu_enable_cnp,
1511         },
1512 #endif
1513         {
1514                 .desc = "Speculation barrier (SB)",
1515                 .capability = ARM64_HAS_SB,
1516                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1517                 .matches = has_cpuid_feature,
1518                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1519                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1520                 .sign = FTR_UNSIGNED,
1521                 .min_field_value = 1,
1522         },
1523 #ifdef CONFIG_ARM64_PTR_AUTH
1524         {
1525                 .desc = "Address authentication (architected algorithm)",
1526                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1527                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1528                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1529                 .sign = FTR_UNSIGNED,
1530                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1531                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1532                 .matches = has_cpuid_feature,
1533                 .cpu_enable = cpu_enable_address_auth,
1534         },
1535         {
1536                 .desc = "Address authentication (IMP DEF algorithm)",
1537                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1538                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1539                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1540                 .sign = FTR_UNSIGNED,
1541                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1542                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1543                 .matches = has_cpuid_feature,
1544                 .cpu_enable = cpu_enable_address_auth,
1545         },
1546         {
1547                 .desc = "Generic authentication (architected algorithm)",
1548                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1549                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1550                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1551                 .sign = FTR_UNSIGNED,
1552                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1553                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1554                 .matches = has_cpuid_feature,
1555         },
1556         {
1557                 .desc = "Generic authentication (IMP DEF algorithm)",
1558                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1559                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1560                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1561                 .sign = FTR_UNSIGNED,
1562                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1563                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1564                 .matches = has_cpuid_feature,
1565         },
1566 #endif /* CONFIG_ARM64_PTR_AUTH */
1567 #ifdef CONFIG_ARM64_PSEUDO_NMI
1568         {
1569                 /*
1570                  * Depends on having GICv3
1571                  */
1572                 .desc = "IRQ priority masking",
1573                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1574                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1575                 .matches = can_use_gic_priorities,
1576                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1577                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1578                 .sign = FTR_UNSIGNED,
1579                 .min_field_value = 1,
1580         },
1581 #endif
1582         {},
1583 };
1584
1585 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1586                 .matches = has_cpuid_feature,                                   \
1587                 .sys_reg = reg,                                                 \
1588                 .field_pos = field,                                             \
1589                 .sign = s,                                                      \
1590                 .min_field_value = min_value,
1591
1592 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1593                 .desc = name,                                                   \
1594                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1595                 .hwcap_type = cap_type,                                         \
1596                 .hwcap = cap,                                                   \
1597
1598 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1599         {                                                                       \
1600                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1601                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1602         }
1603
1604 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1605         {                                                                       \
1606                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1607                 .matches = cpucap_multi_entry_cap_matches,                      \
1608                 .match_list = list,                                             \
1609         }
1610
1611 #ifdef CONFIG_ARM64_PTR_AUTH
1612 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1613         {
1614                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1615                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1616         },
1617         {
1618                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1619                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1620         },
1621         {},
1622 };
1623
1624 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1625         {
1626                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1627                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1628         },
1629         {
1630                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1631                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1632         },
1633         {},
1634 };
1635 #endif
1636
1637 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1638         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1639         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1640         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1641         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1642         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1643         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1644         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1645         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1646         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1647         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1648         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1649         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1650         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1651         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1652         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1653         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1654         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1655         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1656         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1657         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1658         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1659         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1660         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1661         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1662         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1663         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1664         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1665         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1666         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
1667         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
1668         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
1669         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1670 #ifdef CONFIG_ARM64_SVE
1671         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1672         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1673         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1674         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1675         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1676         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
1677         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1678         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1679         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
1680         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
1681         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
1682 #endif
1683         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1684 #ifdef CONFIG_ARM64_PTR_AUTH
1685         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1686         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1687 #endif
1688         {},
1689 };
1690
1691 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1692 #ifdef CONFIG_COMPAT
1693         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1694         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1695         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1696         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1697         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1698 #endif
1699         {},
1700 };
1701
1702 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1703 {
1704         switch (cap->hwcap_type) {
1705         case CAP_HWCAP:
1706                 cpu_set_feature(cap->hwcap);
1707                 break;
1708 #ifdef CONFIG_COMPAT
1709         case CAP_COMPAT_HWCAP:
1710                 compat_elf_hwcap |= (u32)cap->hwcap;
1711                 break;
1712         case CAP_COMPAT_HWCAP2:
1713                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1714                 break;
1715 #endif
1716         default:
1717                 WARN_ON(1);
1718                 break;
1719         }
1720 }
1721
1722 /* Check if we have a particular HWCAP enabled */
1723 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1724 {
1725         bool rc;
1726
1727         switch (cap->hwcap_type) {
1728         case CAP_HWCAP:
1729                 rc = cpu_have_feature(cap->hwcap);
1730                 break;
1731 #ifdef CONFIG_COMPAT
1732         case CAP_COMPAT_HWCAP:
1733                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1734                 break;
1735         case CAP_COMPAT_HWCAP2:
1736                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1737                 break;
1738 #endif
1739         default:
1740                 WARN_ON(1);
1741                 rc = false;
1742         }
1743
1744         return rc;
1745 }
1746
1747 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1748 {
1749         /* We support emulation of accesses to CPU ID feature registers */
1750         cpu_set_named_feature(CPUID);
1751         for (; hwcaps->matches; hwcaps++)
1752                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1753                         cap_set_elf_hwcap(hwcaps);
1754 }
1755
1756 static void update_cpu_capabilities(u16 scope_mask)
1757 {
1758         int i;
1759         const struct arm64_cpu_capabilities *caps;
1760
1761         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1762         for (i = 0; i < ARM64_NCAPS; i++) {
1763                 caps = cpu_hwcaps_ptrs[i];
1764                 if (!caps || !(caps->type & scope_mask) ||
1765                     cpus_have_cap(caps->capability) ||
1766                     !caps->matches(caps, cpucap_default_scope(caps)))
1767                         continue;
1768
1769                 if (caps->desc)
1770                         pr_info("detected: %s\n", caps->desc);
1771                 cpus_set_cap(caps->capability);
1772
1773                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1774                         set_bit(caps->capability, boot_capabilities);
1775         }
1776 }
1777
1778 /*
1779  * Enable all the available capabilities on this CPU. The capabilities
1780  * with BOOT_CPU scope are handled separately and hence skipped here.
1781  */
1782 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1783 {
1784         int i;
1785         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1786
1787         for_each_available_cap(i) {
1788                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1789
1790                 if (WARN_ON(!cap))
1791                         continue;
1792
1793                 if (!(cap->type & non_boot_scope))
1794                         continue;
1795
1796                 if (cap->cpu_enable)
1797                         cap->cpu_enable(cap);
1798         }
1799         return 0;
1800 }
1801
1802 /*
1803  * Run through the enabled capabilities and enable() it on all active
1804  * CPUs
1805  */
1806 static void __init enable_cpu_capabilities(u16 scope_mask)
1807 {
1808         int i;
1809         const struct arm64_cpu_capabilities *caps;
1810         bool boot_scope;
1811
1812         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1813         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1814
1815         for (i = 0; i < ARM64_NCAPS; i++) {
1816                 unsigned int num;
1817
1818                 caps = cpu_hwcaps_ptrs[i];
1819                 if (!caps || !(caps->type & scope_mask))
1820                         continue;
1821                 num = caps->capability;
1822                 if (!cpus_have_cap(num))
1823                         continue;
1824
1825                 /* Ensure cpus_have_const_cap(num) works */
1826                 static_branch_enable(&cpu_hwcap_keys[num]);
1827
1828                 if (boot_scope && caps->cpu_enable)
1829                         /*
1830                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1831                          * before any secondary CPU boots. Thus, each secondary
1832                          * will enable the capability as appropriate via
1833                          * check_local_cpu_capabilities(). The only exception is
1834                          * the boot CPU, for which the capability must be
1835                          * enabled here. This approach avoids costly
1836                          * stop_machine() calls for this case.
1837                          */
1838                         caps->cpu_enable(caps);
1839         }
1840
1841         /*
1842          * For all non-boot scope capabilities, use stop_machine()
1843          * as it schedules the work allowing us to modify PSTATE,
1844          * instead of on_each_cpu() which uses an IPI, giving us a
1845          * PSTATE that disappears when we return.
1846          */
1847         if (!boot_scope)
1848                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1849                              NULL, cpu_online_mask);
1850 }
1851
1852 /*
1853  * Run through the list of capabilities to check for conflicts.
1854  * If the system has already detected a capability, take necessary
1855  * action on this CPU.
1856  *
1857  * Returns "false" on conflicts.
1858  */
1859 static bool verify_local_cpu_caps(u16 scope_mask)
1860 {
1861         int i;
1862         bool cpu_has_cap, system_has_cap;
1863         const struct arm64_cpu_capabilities *caps;
1864
1865         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1866
1867         for (i = 0; i < ARM64_NCAPS; i++) {
1868                 caps = cpu_hwcaps_ptrs[i];
1869                 if (!caps || !(caps->type & scope_mask))
1870                         continue;
1871
1872                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1873                 system_has_cap = cpus_have_cap(caps->capability);
1874
1875                 if (system_has_cap) {
1876                         /*
1877                          * Check if the new CPU misses an advertised feature,
1878                          * which is not safe to miss.
1879                          */
1880                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1881                                 break;
1882                         /*
1883                          * We have to issue cpu_enable() irrespective of
1884                          * whether the CPU has it or not, as it is enabeld
1885                          * system wide. It is upto the call back to take
1886                          * appropriate action on this CPU.
1887                          */
1888                         if (caps->cpu_enable)
1889                                 caps->cpu_enable(caps);
1890                 } else {
1891                         /*
1892                          * Check if the CPU has this capability if it isn't
1893                          * safe to have when the system doesn't.
1894                          */
1895                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1896                                 break;
1897                 }
1898         }
1899
1900         if (i < ARM64_NCAPS) {
1901                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1902                         smp_processor_id(), caps->capability,
1903                         caps->desc, system_has_cap, cpu_has_cap);
1904                 return false;
1905         }
1906
1907         return true;
1908 }
1909
1910 /*
1911  * Check for CPU features that are used in early boot
1912  * based on the Boot CPU value.
1913  */
1914 static void check_early_cpu_features(void)
1915 {
1916         verify_cpu_asid_bits();
1917         /*
1918          * Early features are used by the kernel already. If there
1919          * is a conflict, we cannot proceed further.
1920          */
1921         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1922                 cpu_panic_kernel();
1923 }
1924
1925 static void
1926 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1927 {
1928
1929         for (; caps->matches; caps++)
1930                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1931                         pr_crit("CPU%d: missing HWCAP: %s\n",
1932                                         smp_processor_id(), caps->desc);
1933                         cpu_die_early();
1934                 }
1935 }
1936
1937 static void verify_sve_features(void)
1938 {
1939         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1940         u64 zcr = read_zcr_features();
1941
1942         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1943         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1944
1945         if (len < safe_len || sve_verify_vq_map()) {
1946                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1947                         smp_processor_id());
1948                 cpu_die_early();
1949         }
1950
1951         /* Add checks on other ZCR bits here if necessary */
1952 }
1953
1954
1955 /*
1956  * Run through the enabled system capabilities and enable() it on this CPU.
1957  * The capabilities were decided based on the available CPUs at the boot time.
1958  * Any new CPU should match the system wide status of the capability. If the
1959  * new CPU doesn't have a capability which the system now has enabled, we
1960  * cannot do anything to fix it up and could cause unexpected failures. So
1961  * we park the CPU.
1962  */
1963 static void verify_local_cpu_capabilities(void)
1964 {
1965         /*
1966          * The capabilities with SCOPE_BOOT_CPU are checked from
1967          * check_early_cpu_features(), as they need to be verified
1968          * on all secondary CPUs.
1969          */
1970         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1971                 cpu_die_early();
1972
1973         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1974
1975         if (system_supports_32bit_el0())
1976                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1977
1978         if (system_supports_sve())
1979                 verify_sve_features();
1980 }
1981
1982 void check_local_cpu_capabilities(void)
1983 {
1984         /*
1985          * All secondary CPUs should conform to the early CPU features
1986          * in use by the kernel based on boot CPU.
1987          */
1988         check_early_cpu_features();
1989
1990         /*
1991          * If we haven't finalised the system capabilities, this CPU gets
1992          * a chance to update the errata work arounds and local features.
1993          * Otherwise, this CPU should verify that it has all the system
1994          * advertised capabilities.
1995          */
1996         if (!sys_caps_initialised)
1997                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1998         else
1999                 verify_local_cpu_capabilities();
2000 }
2001
2002 static void __init setup_boot_cpu_capabilities(void)
2003 {
2004         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2005         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2006         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2007         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2008 }
2009
2010 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
2011 EXPORT_SYMBOL(arm64_const_caps_ready);
2012
2013 static void __init mark_const_caps_ready(void)
2014 {
2015         static_branch_enable(&arm64_const_caps_ready);
2016 }
2017
2018 bool this_cpu_has_cap(unsigned int n)
2019 {
2020         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2021                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2022
2023                 if (cap)
2024                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2025         }
2026
2027         return false;
2028 }
2029
2030 void cpu_set_feature(unsigned int num)
2031 {
2032         WARN_ON(num >= MAX_CPU_FEATURES);
2033         elf_hwcap |= BIT(num);
2034 }
2035 EXPORT_SYMBOL_GPL(cpu_set_feature);
2036
2037 bool cpu_have_feature(unsigned int num)
2038 {
2039         WARN_ON(num >= MAX_CPU_FEATURES);
2040         return elf_hwcap & BIT(num);
2041 }
2042 EXPORT_SYMBOL_GPL(cpu_have_feature);
2043
2044 unsigned long cpu_get_elf_hwcap(void)
2045 {
2046         /*
2047          * We currently only populate the first 32 bits of AT_HWCAP. Please
2048          * note that for userspace compatibility we guarantee that bits 62
2049          * and 63 will always be returned as 0.
2050          */
2051         return lower_32_bits(elf_hwcap);
2052 }
2053
2054 unsigned long cpu_get_elf_hwcap2(void)
2055 {
2056         return upper_32_bits(elf_hwcap);
2057 }
2058
2059 static void __init setup_system_capabilities(void)
2060 {
2061         /*
2062          * We have finalised the system-wide safe feature
2063          * registers, finalise the capabilities that depend
2064          * on it. Also enable all the available capabilities,
2065          * that are not enabled already.
2066          */
2067         update_cpu_capabilities(SCOPE_SYSTEM);
2068         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2069 }
2070
2071 void __init setup_cpu_features(void)
2072 {
2073         u32 cwg;
2074
2075         setup_system_capabilities();
2076         mark_const_caps_ready();
2077         setup_elf_hwcaps(arm64_elf_hwcaps);
2078
2079         if (system_supports_32bit_el0())
2080                 setup_elf_hwcaps(compat_elf_hwcaps);
2081
2082         if (system_uses_ttbr0_pan())
2083                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2084
2085         sve_setup();
2086         minsigstksz_setup();
2087
2088         /* Advertise that we have computed the system capabilities */
2089         set_sys_caps_initialised();
2090
2091         /*
2092          * Check for sane CTR_EL0.CWG value.
2093          */
2094         cwg = cache_type_cwg();
2095         if (!cwg)
2096                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2097                         ARCH_DMA_MINALIGN);
2098 }
2099
2100 static bool __maybe_unused
2101 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2102 {
2103         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2104 }
2105
2106 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2107 {
2108         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2109 }
2110
2111 /*
2112  * We emulate only the following system register space.
2113  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2114  * See Table C5-6 System instruction encodings for System register accesses,
2115  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2116  */
2117 static inline bool __attribute_const__ is_emulated(u32 id)
2118 {
2119         return (sys_reg_Op0(id) == 0x3 &&
2120                 sys_reg_CRn(id) == 0x0 &&
2121                 sys_reg_Op1(id) == 0x0 &&
2122                 (sys_reg_CRm(id) == 0 ||
2123                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2124 }
2125
2126 /*
2127  * With CRm == 0, reg should be one of :
2128  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2129  */
2130 static inline int emulate_id_reg(u32 id, u64 *valp)
2131 {
2132         switch (id) {
2133         case SYS_MIDR_EL1:
2134                 *valp = read_cpuid_id();
2135                 break;
2136         case SYS_MPIDR_EL1:
2137                 *valp = SYS_MPIDR_SAFE_VAL;
2138                 break;
2139         case SYS_REVIDR_EL1:
2140                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2141                 *valp = 0;
2142                 break;
2143         default:
2144                 return -EINVAL;
2145         }
2146
2147         return 0;
2148 }
2149
2150 static int emulate_sys_reg(u32 id, u64 *valp)
2151 {
2152         struct arm64_ftr_reg *regp;
2153
2154         if (!is_emulated(id))
2155                 return -EINVAL;
2156
2157         if (sys_reg_CRm(id) == 0)
2158                 return emulate_id_reg(id, valp);
2159
2160         regp = get_arm64_ftr_reg(id);
2161         if (regp)
2162                 *valp = arm64_ftr_reg_user_value(regp);
2163         else
2164                 /*
2165                  * The untracked registers are either IMPLEMENTATION DEFINED
2166                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2167                  */
2168                 *valp = 0;
2169         return 0;
2170 }
2171
2172 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2173 {
2174         int rc;
2175         u64 val;
2176
2177         rc = emulate_sys_reg(sys_reg, &val);
2178         if (!rc) {
2179                 pt_regs_write_reg(regs, rt, val);
2180                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2181         }
2182         return rc;
2183 }
2184
2185 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2186 {
2187         u32 sys_reg, rt;
2188
2189         /*
2190          * sys_reg values are defined as used in mrs/msr instruction.
2191          * shift the imm value to get the encoding.
2192          */
2193         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2194         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2195         return do_emulate_mrs(regs, sys_reg, rt);
2196 }
2197
2198 static struct undef_hook mrs_hook = {
2199         .instr_mask = 0xfff00000,
2200         .instr_val  = 0xd5300000,
2201         .pstate_mask = PSR_AA32_MODE_MASK,
2202         .pstate_val = PSR_MODE_EL0t,
2203         .fn = emulate_mrs,
2204 };
2205
2206 static int __init enable_mrs_emulation(void)
2207 {
2208         register_undef_hook(&mrs_hook);
2209         return 0;
2210 }
2211
2212 core_initcall(enable_mrs_emulation);
2213
2214 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2215                           char *buf)
2216 {
2217         if (__meltdown_safe)
2218                 return sprintf(buf, "Not affected\n");
2219
2220         if (arm64_kernel_unmapped_at_el0())
2221                 return sprintf(buf, "Mitigation: PTI\n");
2222
2223         return sprintf(buf, "Vulnerable\n");
2224 }