1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
9 #include <asm/proc-fns.h>
11 #include <asm/memory.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
24 #define VMALLOC_START (MODULES_END)
25 #define VMALLOC_END (VMEMMAP_START - SZ_256M)
27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
29 #define FIRST_USER_ADDRESS 0UL
33 #include <asm/cmpxchg.h>
34 #include <asm/fixmap.h>
35 #include <linux/mmdebug.h>
36 #include <linux/mm_types.h>
37 #include <linux/sched.h>
39 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
40 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
42 /* Set stride and tlb_level in flush_*_tlb_range */
43 #define flush_pmd_tlb_range(vma, addr, end) \
44 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
45 #define flush_pud_tlb_range(vma, addr, end) \
46 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
47 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
50 * Outside of a few very special situations (e.g. hibernation), we always
51 * use broadcast TLB invalidation instructions, therefore a spurious page
52 * fault on one CPU which has been handled concurrently by another CPU
53 * does not need to perform additional invalidation.
55 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
58 * ZERO_PAGE is a global shared page that is always zero: used
59 * for zero-mapped memory areas etc..
61 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
62 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
64 #define pte_ERROR(e) \
65 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
68 * Macros to convert between a physical address and its placement in a
69 * page table entry, taking care of 52-bit addresses.
71 #ifdef CONFIG_ARM64_PA_BITS_52
72 #define __pte_to_phys(pte) \
73 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
74 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
76 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
77 #define __phys_to_pte_val(phys) (phys)
80 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
81 #define pfn_pte(pfn,prot) \
82 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
84 #define pte_none(pte) (!pte_val(pte))
85 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
86 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
89 * The following only work if pte_present(). Undefined behaviour otherwise.
91 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
92 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
93 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
94 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
95 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
96 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
97 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
98 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
99 PTE_ATTRINDX(MT_NORMAL_TAGGED))
101 #define pte_cont_addr_end(addr, end) \
102 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
103 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
106 #define pmd_cont_addr_end(addr, end) \
107 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
108 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
111 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
112 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
113 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
115 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
117 * Execute-only user mappings do not have the PTE_USER bit set. All valid
118 * kernel mappings have the PTE_UXN bit set.
120 #define pte_valid_not_user(pte) \
121 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
123 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
124 * so that we don't erroneously return false for pages that have been
125 * remapped as PROT_NONE but are yet to be flushed from the TLB.
126 * Note that we can't make any assumptions based on the state of the access
127 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
130 #define pte_accessible(mm, pte) \
131 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
134 * p??_access_permitted() is true for valid user mappings (PTE_USER
135 * bit set, subject to the write permission check). For execute-only
136 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
137 * not set) must return false. PROT_NONE mappings do not have the
140 #define pte_access_permitted(pte, write) \
141 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
142 #define pmd_access_permitted(pmd, write) \
143 (pte_access_permitted(pmd_pte(pmd), (write)))
144 #define pud_access_permitted(pud, write) \
145 (pte_access_permitted(pud_pte(pud), (write)))
147 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
149 pte_val(pte) &= ~pgprot_val(prot);
153 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
155 pte_val(pte) |= pgprot_val(prot);
159 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
161 pmd_val(pmd) &= ~pgprot_val(prot);
165 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
167 pmd_val(pmd) |= pgprot_val(prot);
171 static inline pte_t pte_mkwrite(pte_t pte)
173 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
174 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
178 static inline pte_t pte_mkclean(pte_t pte)
180 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
181 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
186 static inline pte_t pte_mkdirty(pte_t pte)
188 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
191 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
196 static inline pte_t pte_wrprotect(pte_t pte)
199 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
200 * clear), set the PTE_DIRTY bit.
202 if (pte_hw_dirty(pte))
203 pte = pte_mkdirty(pte);
205 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
206 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
210 static inline pte_t pte_mkold(pte_t pte)
212 return clear_pte_bit(pte, __pgprot(PTE_AF));
215 static inline pte_t pte_mkyoung(pte_t pte)
217 return set_pte_bit(pte, __pgprot(PTE_AF));
220 static inline pte_t pte_mkspecial(pte_t pte)
222 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
225 static inline pte_t pte_mkcont(pte_t pte)
227 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
228 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
231 static inline pte_t pte_mknoncont(pte_t pte)
233 return clear_pte_bit(pte, __pgprot(PTE_CONT));
236 static inline pte_t pte_mkpresent(pte_t pte)
238 return set_pte_bit(pte, __pgprot(PTE_VALID));
241 static inline pmd_t pmd_mkcont(pmd_t pmd)
243 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
246 static inline pte_t pte_mkdevmap(pte_t pte)
248 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
251 static inline void set_pte(pte_t *ptep, pte_t pte)
253 WRITE_ONCE(*ptep, pte);
256 * Only if the new pte is valid and kernel, otherwise TLB maintenance
257 * or update_mmu_cache() have the necessary barriers.
259 if (pte_valid_not_user(pte)) {
265 extern void __sync_icache_dcache(pte_t pteval);
268 * PTE bits configuration in the presence of hardware Dirty Bit Management
269 * (PTE_WRITE == PTE_DBM):
271 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
277 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
278 * the page fault mechanism. Checking the dirty status of a pte becomes:
280 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
283 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
288 if (!IS_ENABLED(CONFIG_DEBUG_VM))
291 old_pte = READ_ONCE(*ptep);
293 if (!pte_valid(old_pte) || !pte_valid(pte))
295 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
299 * Check for potential race with hardware updates of the pte
300 * (ptep_set_access_flags safely changes valid ptes without going
301 * through an invalid entry).
303 VM_WARN_ONCE(!pte_young(pte),
304 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
305 __func__, pte_val(old_pte), pte_val(pte));
306 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
307 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
308 __func__, pte_val(old_pte), pte_val(pte));
311 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
312 pte_t *ptep, pte_t pte)
314 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
315 __sync_icache_dcache(pte);
317 if (system_supports_mte() &&
318 pte_present(pte) && pte_tagged(pte) && !pte_special(pte))
319 mte_sync_tags(ptep, pte);
321 __check_racy_pte_update(mm, ptep, pte);
327 * Huge pte definitions.
329 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
332 * Hugetlb definitions.
334 #define HUGE_MAX_HSTATE 4
335 #define HPAGE_SHIFT PMD_SHIFT
336 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
337 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
338 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
340 static inline pte_t pgd_pte(pgd_t pgd)
342 return __pte(pgd_val(pgd));
345 static inline pte_t p4d_pte(p4d_t p4d)
347 return __pte(p4d_val(p4d));
350 static inline pte_t pud_pte(pud_t pud)
352 return __pte(pud_val(pud));
355 static inline pud_t pte_pud(pte_t pte)
357 return __pud(pte_val(pte));
360 static inline pmd_t pud_pmd(pud_t pud)
362 return __pmd(pud_val(pud));
365 static inline pte_t pmd_pte(pmd_t pmd)
367 return __pte(pmd_val(pmd));
370 static inline pmd_t pte_pmd(pte_t pte)
372 return __pmd(pte_val(pte));
375 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
377 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
380 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
382 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
385 #ifdef CONFIG_NUMA_BALANCING
387 * See the comment in include/linux/pgtable.h
389 static inline int pte_protnone(pte_t pte)
391 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
394 static inline int pmd_protnone(pmd_t pmd)
396 return pte_protnone(pmd_pte(pmd));
400 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
402 static inline int pmd_present(pmd_t pmd)
404 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
411 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
412 static inline int pmd_trans_huge(pmd_t pmd)
414 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
416 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
418 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
419 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
420 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
421 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
422 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
423 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
424 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
425 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
426 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
427 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
429 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
431 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
432 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
437 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
439 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
441 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
443 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
444 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
446 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
448 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
451 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
452 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
453 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
454 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
455 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
457 #define pud_young(pud) pte_young(pud_pte(pud))
458 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
459 #define pud_write(pud) pte_write(pud_pte(pud))
461 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
463 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
464 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
465 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
466 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
468 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
469 #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud))
471 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
472 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
474 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
475 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
477 #define __pgprot_modify(prot,mask,bits) \
478 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
480 #define pgprot_nx(prot) \
481 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
484 * Mark the prot value as uncacheable and unbufferable.
486 #define pgprot_noncached(prot) \
487 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
488 #define pgprot_writecombine(prot) \
489 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
490 #define pgprot_device(prot) \
491 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
492 #define pgprot_tagged(prot) \
493 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
494 #define pgprot_mhp pgprot_tagged
496 * DMA allocations for non-coherent devices use what the Arm architecture calls
497 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
498 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
499 * is intended for MMIO and thus forbids speculation, preserves access size,
500 * requires strict alignment and can also force write responses to come from the
503 #define pgprot_dmacoherent(prot) \
504 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
505 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
507 #define __HAVE_PHYS_MEM_ACCESS_PROT
509 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
510 unsigned long size, pgprot_t vma_prot);
512 #define pmd_none(pmd) (!pmd_val(pmd))
514 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
516 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
518 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
520 #define pmd_leaf(pmd) pmd_sect(pmd)
522 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
523 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
525 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
526 static inline bool pud_sect(pud_t pud) { return false; }
527 static inline bool pud_table(pud_t pud) { return true; }
529 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
531 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
535 extern pgd_t init_pg_dir[PTRS_PER_PGD];
536 extern pgd_t init_pg_end[];
537 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
538 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
539 extern pgd_t idmap_pg_end[];
540 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
541 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
543 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
545 static inline bool in_swapper_pgdir(void *addr)
547 return ((unsigned long)addr & PAGE_MASK) ==
548 ((unsigned long)swapper_pg_dir & PAGE_MASK);
551 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
553 #ifdef __PAGETABLE_PMD_FOLDED
554 if (in_swapper_pgdir(pmdp)) {
555 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
558 #endif /* __PAGETABLE_PMD_FOLDED */
560 WRITE_ONCE(*pmdp, pmd);
562 if (pmd_valid(pmd)) {
568 static inline void pmd_clear(pmd_t *pmdp)
570 set_pmd(pmdp, __pmd(0));
573 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
575 return __pmd_to_phys(pmd);
578 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
580 return (unsigned long)__va(pmd_page_paddr(pmd));
583 /* Find an entry in the third-level page table. */
584 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
586 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
587 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
588 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
590 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
592 /* use ONLY for statically allocated translation tables */
593 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
596 * Conversion functions: convert a page and protection to a page entry,
597 * and a page entry and page directory to the page they refer to.
599 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
601 #if CONFIG_PGTABLE_LEVELS > 2
603 #define pmd_ERROR(e) \
604 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
606 #define pud_none(pud) (!pud_val(pud))
607 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
608 #define pud_present(pud) pte_present(pud_pte(pud))
609 #define pud_leaf(pud) pud_sect(pud)
610 #define pud_valid(pud) pte_valid(pud_pte(pud))
612 static inline void set_pud(pud_t *pudp, pud_t pud)
614 #ifdef __PAGETABLE_PUD_FOLDED
615 if (in_swapper_pgdir(pudp)) {
616 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
619 #endif /* __PAGETABLE_PUD_FOLDED */
621 WRITE_ONCE(*pudp, pud);
623 if (pud_valid(pud)) {
629 static inline void pud_clear(pud_t *pudp)
631 set_pud(pudp, __pud(0));
634 static inline phys_addr_t pud_page_paddr(pud_t pud)
636 return __pud_to_phys(pud);
639 static inline unsigned long pud_page_vaddr(pud_t pud)
641 return (unsigned long)__va(pud_page_paddr(pud));
644 /* Find an entry in the second-level page table. */
645 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
647 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
648 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
649 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
651 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
653 /* use ONLY for statically allocated translation tables */
654 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
658 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
660 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
661 #define pmd_set_fixmap(addr) NULL
662 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
663 #define pmd_clear_fixmap()
665 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
667 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
669 #if CONFIG_PGTABLE_LEVELS > 3
671 #define pud_ERROR(e) \
672 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
674 #define p4d_none(p4d) (!p4d_val(p4d))
675 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
676 #define p4d_present(p4d) (p4d_val(p4d))
678 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
680 if (in_swapper_pgdir(p4dp)) {
681 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
685 WRITE_ONCE(*p4dp, p4d);
690 static inline void p4d_clear(p4d_t *p4dp)
692 set_p4d(p4dp, __p4d(0));
695 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
697 return __p4d_to_phys(p4d);
700 static inline unsigned long p4d_page_vaddr(p4d_t p4d)
702 return (unsigned long)__va(p4d_page_paddr(p4d));
705 /* Find an entry in the frst-level page table. */
706 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
708 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
709 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
710 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
712 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
714 /* use ONLY for statically allocated translation tables */
715 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
719 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
720 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
722 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
723 #define pud_set_fixmap(addr) NULL
724 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
725 #define pud_clear_fixmap()
727 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
729 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
731 #define pgd_ERROR(e) \
732 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
734 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
735 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
737 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
740 * Normal and Normal-Tagged are two different memory types and indices
741 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
743 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
744 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
746 /* preserve the hardware dirty information */
747 if (pte_hw_dirty(pte))
748 pte = pte_mkdirty(pte);
749 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
753 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
755 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
758 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
759 extern int ptep_set_access_flags(struct vm_area_struct *vma,
760 unsigned long address, pte_t *ptep,
761 pte_t entry, int dirty);
763 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
764 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
765 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
766 unsigned long address, pmd_t *pmdp,
767 pmd_t entry, int dirty)
769 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
772 static inline int pud_devmap(pud_t pud)
777 static inline int pgd_devmap(pgd_t pgd)
784 * Atomic pte/pmd modifications.
786 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
787 static inline int __ptep_test_and_clear_young(pte_t *ptep)
791 pte = READ_ONCE(*ptep);
794 pte = pte_mkold(pte);
795 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
796 pte_val(old_pte), pte_val(pte));
797 } while (pte_val(pte) != pte_val(old_pte));
799 return pte_young(pte);
802 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
803 unsigned long address,
806 return __ptep_test_and_clear_young(ptep);
809 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
810 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
811 unsigned long address, pte_t *ptep)
813 int young = ptep_test_and_clear_young(vma, address, ptep);
817 * We can elide the trailing DSB here since the worst that can
818 * happen is that a CPU continues to use the young entry in its
819 * TLB and we mistakenly reclaim the associated page. The
820 * window for such an event is bounded by the next
821 * context-switch, which provides a DSB to complete the TLB
824 flush_tlb_page_nosync(vma, address);
830 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
831 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
832 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
833 unsigned long address,
836 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
838 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
840 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
841 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
842 unsigned long address, pte_t *ptep)
844 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
847 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
848 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
849 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
850 unsigned long address, pmd_t *pmdp)
852 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
854 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
857 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
858 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
860 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
861 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
865 pte = READ_ONCE(*ptep);
868 pte = pte_wrprotect(pte);
869 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
870 pte_val(old_pte), pte_val(pte));
871 } while (pte_val(pte) != pte_val(old_pte));
874 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
875 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
876 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
877 unsigned long address, pmd_t *pmdp)
879 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
882 #define pmdp_establish pmdp_establish
883 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
884 unsigned long address, pmd_t *pmdp, pmd_t pmd)
886 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
891 * Encode and decode a swap entry:
892 * bits 0-1: present (must be zero)
893 * bits 2-7: swap type
894 * bits 8-57: swap offset
895 * bit 58: PTE_PROT_NONE (must be zero)
897 #define __SWP_TYPE_SHIFT 2
898 #define __SWP_TYPE_BITS 6
899 #define __SWP_OFFSET_BITS 50
900 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
901 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
902 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
904 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
905 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
906 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
908 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
909 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
911 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
912 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
913 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
914 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
917 * Ensure that there are not more swap files than can be encoded in the kernel
920 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
922 extern int kern_addr_valid(unsigned long addr);
924 #ifdef CONFIG_ARM64_MTE
926 #define __HAVE_ARCH_PREPARE_TO_SWAP
927 static inline int arch_prepare_to_swap(struct page *page)
929 if (system_supports_mte())
930 return mte_save_tags(page);
934 #define __HAVE_ARCH_SWAP_INVALIDATE
935 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
937 if (system_supports_mte())
938 mte_invalidate_tags(type, offset);
941 static inline void arch_swap_invalidate_area(int type)
943 if (system_supports_mte())
944 mte_invalidate_tags_area(type);
947 #define __HAVE_ARCH_SWAP_RESTORE
948 static inline void arch_swap_restore(swp_entry_t entry, struct page *page)
950 if (system_supports_mte() && mte_restore_tags(entry, page))
951 set_bit(PG_mte_tagged, &page->flags);
954 #endif /* CONFIG_ARM64_MTE */
957 * On AArch64, the cache coherency is handled via the set_pte_at() function.
959 static inline void update_mmu_cache(struct vm_area_struct *vma,
960 unsigned long addr, pte_t *ptep)
963 * We don't do anything here, so there's a very small chance of
964 * us retaking a user fault which we just fixed up. The alternative
965 * is doing a dsb(ishst), but that penalises the fastpath.
969 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
971 #ifdef CONFIG_ARM64_PA_BITS_52
972 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
974 #define phys_to_ttbr(addr) (addr)
978 * On arm64 without hardware Access Flag, copying from user will fail because
979 * the pte is old and cannot be marked young. So we always end up with zeroed
980 * page after fork() + CoW for pfn mappings. We don't always have a
981 * hardware-managed access flag on arm64.
983 static inline bool arch_faults_on_old_pte(void)
985 WARN_ON(preemptible());
987 return !cpu_has_hw_af();
989 #define arch_faults_on_old_pte arch_faults_on_old_pte
992 * Experimentally, it's cheap to set the access flag in hardware and we
993 * benefit from prefaulting mappings as 'old' to start with.
995 static inline bool arch_wants_old_prefaulted_pte(void)
997 return !arch_faults_on_old_pte();
999 #define arch_wants_old_prefaulted_pte arch_wants_old_prefaulted_pte
1001 static inline pgprot_t arch_filter_pgprot(pgprot_t prot)
1003 if (cpus_have_const_cap(ARM64_HAS_EPAN))
1006 if (pgprot_val(prot) != pgprot_val(PAGE_EXECONLY))
1009 return PAGE_READONLY_EXEC;
1013 #endif /* !__ASSEMBLY__ */
1015 #endif /* __ASM_PGTABLE_H */