arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721E SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy.h>
   8 #include <dt-bindings/mux/mux.h>
   9 #include <dt-bindings/mux/ti-serdes.h>
  10
  11 &cbass_main {
  12         msmc_ram: sram@70000000 {
  13                 compatible = "mmio-sram";
  14                 reg = <0x0 0x70000000 0x0 0x800000>;
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x0 0x0 0x70000000 0x800000>;
  18
  19                 atf-sram@0 {
  20                         reg = <0x0 0x20000>;
  21                 };
  22         };
  23
  24         scm_conf: scm-conf@100000 {
  25                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  26                 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges = <0x0 0x0 0x00100000 0x1c000>;
  30
  31                 serdes_ln_ctrl: mux@4080 {
  32                         compatible = "mmio-mux";
  33                         reg = <0x00004080 0x50>;
  34                         #mux-control-cells = <1>;
  35                         mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
  36                                         <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
  37                                         <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
  38                                         <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
  39                                         <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
  40                                         /* SERDES4 lane0/1/2/3 select */
  41                         idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
  42                                       <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
  43                                       <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
  44                                       <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
  45                                       <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
  46                                       <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
  47                 };
  48
  49                 usb_serdes_mux: mux-controller@4000 {
  50                         compatible = "mmio-mux";
  51                         #mux-control-cells = <1>;
  52                         mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
  53                                         <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
  54             };
  55         };
  56
  57         gic500: interrupt-controller@1800000 {
  58                 compatible = "arm,gic-v3";
  59                 #address-cells = <2>;
  60                 #size-cells = <2>;
  61                 ranges;
  62                 #interrupt-cells = <3>;
  63                 interrupt-controller;
  64                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  65                       <0x00 0x01900000 0x00 0x100000>;  /* GICR */
  66
  67                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  68                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  69
  70                 gic_its: msi-controller@1820000 {
  71                         compatible = "arm,gic-v3-its";
  72                         reg = <0x00 0x01820000 0x00 0x10000>;
  73                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  74                         msi-controller;
  75                         #msi-cells = <1>;
  76                 };
  77         };
  78
  79         main_gpio_intr: interrupt-controller@a00000 {
  80                 compatible = "ti,sci-intr";
  81                 reg = <0x00 0x00a00000 0x00 0x800>;
  82                 ti,intr-trigger-type = <1>;
  83                 interrupt-controller;
  84                 interrupt-parent = <&gic500>;
  85                 #interrupt-cells = <1>;
  86                 ti,sci = <&dmsc>;
  87                 ti,sci-dev-id = <131>;
  88                 ti,interrupt-ranges = <8 392 56>;
  89         };
  90
  91         main_navss: bus@30000000 {
  92                 compatible = "simple-mfd";
  93                 #address-cells = <2>;
  94                 #size-cells = <2>;
  95                 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
  96                 dma-coherent;
  97                 dma-ranges;
  98
  99                 ti,sci-dev-id = <199>;
 100
 101                 main_navss_intr: interrupt-controller@310e0000 {
 102                         compatible = "ti,sci-intr";
 103                         reg = <0x0 0x310e0000 0x0 0x4000>;
 104                         ti,intr-trigger-type = <4>;
 105                         interrupt-controller;
 106                         interrupt-parent = <&gic500>;
 107                         #interrupt-cells = <1>;
 108                         ti,sci = <&dmsc>;
 109                         ti,sci-dev-id = <213>;
 110                         ti,interrupt-ranges = <0 64 64>,
 111                                               <64 448 64>,
 112                                               <128 672 64>;
 113                 };
 114
 115                 main_udmass_inta: interrupt-controller@33d00000 {
 116                         compatible = "ti,sci-inta";
 117                         reg = <0x0 0x33d00000 0x0 0x100000>;
 118                         interrupt-controller;
 119                         interrupt-parent = <&main_navss_intr>;
 120                         msi-controller;
 121                         #interrupt-cells = <0>;
 122                         ti,sci = <&dmsc>;
 123                         ti,sci-dev-id = <209>;
 124                         ti,interrupt-ranges = <0 0 256>;
 125                 };
 126
 127                 secure_proxy_main: mailbox@32c00000 {
 128                         compatible = "ti,am654-secure-proxy";
 129                         #mbox-cells = <1>;
 130                         reg-names = "target_data", "rt", "scfg";
 131                         reg = <0x00 0x32c00000 0x00 0x100000>,
 132                               <0x00 0x32400000 0x00 0x100000>,
 133                               <0x00 0x32800000 0x00 0x100000>;
 134                         interrupt-names = "rx_011";
 135                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 136                 };
 137
 138                 smmu0: iommu@36600000 {
 139                         compatible = "arm,smmu-v3";
 140                         reg = <0x0 0x36600000 0x0 0x100000>;
 141                         interrupt-parent = <&gic500>;
 142                         interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
 143                                      <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
 144                         interrupt-names = "eventq", "gerror";
 145                         #iommu-cells = <1>;
 146                 };
 147
 148                 hwspinlock: spinlock@30e00000 {
 149                         compatible = "ti,am654-hwspinlock";
 150                         reg = <0x00 0x30e00000 0x00 0x1000>;
 151                         #hwlock-cells = <1>;
 152                 };
 153
 154                 mailbox0_cluster0: mailbox@31f80000 {
 155                         compatible = "ti,am654-mailbox";
 156                         reg = <0x00 0x31f80000 0x00 0x200>;
 157                         #mbox-cells = <1>;
 158                         ti,mbox-num-users = <4>;
 159                         ti,mbox-num-fifos = <16>;
 160                         interrupt-parent = <&main_navss_intr>;
 161                 };
 162
 163                 mailbox0_cluster1: mailbox@31f81000 {
 164                         compatible = "ti,am654-mailbox";
 165                         reg = <0x00 0x31f81000 0x00 0x200>;
 166                         #mbox-cells = <1>;
 167                         ti,mbox-num-users = <4>;
 168                         ti,mbox-num-fifos = <16>;
 169                         interrupt-parent = <&main_navss_intr>;
 170                 };
 171
 172                 mailbox0_cluster2: mailbox@31f82000 {
 173                         compatible = "ti,am654-mailbox";
 174                         reg = <0x00 0x31f82000 0x00 0x200>;
 175                         #mbox-cells = <1>;
 176                         ti,mbox-num-users = <4>;
 177                         ti,mbox-num-fifos = <16>;
 178                         interrupt-parent = <&main_navss_intr>;
 179                 };
 180
 181                 mailbox0_cluster3: mailbox@31f83000 {
 182                         compatible = "ti,am654-mailbox";
 183                         reg = <0x00 0x31f83000 0x00 0x200>;
 184                         #mbox-cells = <1>;
 185                         ti,mbox-num-users = <4>;
 186                         ti,mbox-num-fifos = <16>;
 187                         interrupt-parent = <&main_navss_intr>;
 188                 };
 189
 190                 mailbox0_cluster4: mailbox@31f84000 {
 191                         compatible = "ti,am654-mailbox";
 192                         reg = <0x00 0x31f84000 0x00 0x200>;
 193                         #mbox-cells = <1>;
 194                         ti,mbox-num-users = <4>;
 195                         ti,mbox-num-fifos = <16>;
 196                         interrupt-parent = <&main_navss_intr>;
 197                 };
 198
 199                 mailbox0_cluster5: mailbox@31f85000 {
 200                         compatible = "ti,am654-mailbox";
 201                         reg = <0x00 0x31f85000 0x00 0x200>;
 202                         #mbox-cells = <1>;
 203                         ti,mbox-num-users = <4>;
 204                         ti,mbox-num-fifos = <16>;
 205                         interrupt-parent = <&main_navss_intr>;
 206                 };
 207
 208                 mailbox0_cluster6: mailbox@31f86000 {
 209                         compatible = "ti,am654-mailbox";
 210                         reg = <0x00 0x31f86000 0x00 0x200>;
 211                         #mbox-cells = <1>;
 212                         ti,mbox-num-users = <4>;
 213                         ti,mbox-num-fifos = <16>;
 214                         interrupt-parent = <&main_navss_intr>;
 215                 };
 216
 217                 mailbox0_cluster7: mailbox@31f87000 {
 218                         compatible = "ti,am654-mailbox";
 219                         reg = <0x00 0x31f87000 0x00 0x200>;
 220                         #mbox-cells = <1>;
 221                         ti,mbox-num-users = <4>;
 222                         ti,mbox-num-fifos = <16>;
 223                         interrupt-parent = <&main_navss_intr>;
 224                 };
 225
 226                 mailbox0_cluster8: mailbox@31f88000 {
 227                         compatible = "ti,am654-mailbox";
 228                         reg = <0x00 0x31f88000 0x00 0x200>;
 229                         #mbox-cells = <1>;
 230                         ti,mbox-num-users = <4>;
 231                         ti,mbox-num-fifos = <16>;
 232                         interrupt-parent = <&main_navss_intr>;
 233                 };
 234
 235                 mailbox0_cluster9: mailbox@31f89000 {
 236                         compatible = "ti,am654-mailbox";
 237                         reg = <0x00 0x31f89000 0x00 0x200>;
 238                         #mbox-cells = <1>;
 239                         ti,mbox-num-users = <4>;
 240                         ti,mbox-num-fifos = <16>;
 241                         interrupt-parent = <&main_navss_intr>;
 242                 };
 243
 244                 mailbox0_cluster10: mailbox@31f8a000 {
 245                         compatible = "ti,am654-mailbox";
 246                         reg = <0x00 0x31f8a000 0x00 0x200>;
 247                         #mbox-cells = <1>;
 248                         ti,mbox-num-users = <4>;
 249                         ti,mbox-num-fifos = <16>;
 250                         interrupt-parent = <&main_navss_intr>;
 251                 };
 252
 253                 mailbox0_cluster11: mailbox@31f8b000 {
 254                         compatible = "ti,am654-mailbox";
 255                         reg = <0x00 0x31f8b000 0x00 0x200>;
 256                         #mbox-cells = <1>;
 257                         ti,mbox-num-users = <4>;
 258                         ti,mbox-num-fifos = <16>;
 259                         interrupt-parent = <&main_navss_intr>;
 260                 };
 261
 262                 main_ringacc: ringacc@3c000000 {
 263                         compatible = "ti,am654-navss-ringacc";
 264                         reg =   <0x0 0x3c000000 0x0 0x400000>,
 265                                 <0x0 0x38000000 0x0 0x400000>,
 266                                 <0x0 0x31120000 0x0 0x100>,
 267                                 <0x0 0x33000000 0x0 0x40000>;
 268                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 269                         ti,num-rings = <1024>;
 270                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 271                         ti,sci = <&dmsc>;
 272                         ti,sci-dev-id = <211>;
 273                         msi-parent = <&main_udmass_inta>;
 274                 };
 275
 276                 main_udmap: dma-controller@31150000 {
 277                         compatible = "ti,j721e-navss-main-udmap";
 278                         reg =   <0x0 0x31150000 0x0 0x100>,
 279                                 <0x0 0x34000000 0x0 0x100000>,
 280                                 <0x0 0x35000000 0x0 0x100000>;
 281                         reg-names = "gcfg", "rchanrt", "tchanrt";
 282                         msi-parent = <&main_udmass_inta>;
 283                         #dma-cells = <1>;
 284
 285                         ti,sci = <&dmsc>;
 286                         ti,sci-dev-id = <212>;
 287                         ti,ringacc = <&main_ringacc>;
 288
 289                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 290                                                 <0x0f>, /* TX_HCHAN */
 291                                                 <0x10>; /* TX_UHCHAN */
 292                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 293                                                 <0x0b>, /* RX_HCHAN */
 294                                                 <0x0c>; /* RX_UHCHAN */
 295                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 296                 };
 297
 298                 cpts@310d0000 {
 299                         compatible = "ti,j721e-cpts";
 300                         reg = <0x0 0x310d0000 0x0 0x400>;
 301                         reg-names = "cpts";
 302                         clocks = <&k3_clks 201 1>;
 303                         clock-names = "cpts";
 304                         interrupts-extended = <&main_navss_intr 391>;
 305                         interrupt-names = "cpts";
 306                         ti,cpts-periodic-outputs = <6>;
 307                         ti,cpts-ext-ts-inputs = <8>;
 308                 };
 309         };
 310
 311         main_crypto: crypto@4e00000 {
 312                 compatible = "ti,j721e-sa2ul";
 313                 reg = <0x0 0x4e00000 0x0 0x1200>;
 314                 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
 315                 #address-cells = <2>;
 316                 #size-cells = <2>;
 317                 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
 318
 319                 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
 320                                 <&main_udmap 0x4001>;
 321                 dma-names = "tx", "rx1", "rx2";
 322                 dma-coherent;
 323
 324                 rng: rng@4e10000 {
 325                         compatible = "inside-secure,safexcel-eip76";
 326                         reg = <0x0 0x4e10000 0x0 0x7d>;
 327                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 328                         clocks = <&k3_clks 264 1>;
 329                 };
 330         };
 331
 332         main_pmx0: pinctrl@11c000 {
 333                 compatible = "pinctrl-single";
 334                 /* Proxy 0 addressing */
 335                 reg = <0x0 0x11c000 0x0 0x2b4>;
 336                 #pinctrl-cells = <1>;
 337                 pinctrl-single,register-width = <32>;
 338                 pinctrl-single,function-mask = <0xffffffff>;
 339         };
 340
 341         dummy_cmn_refclk: dummy-cmn-refclk {
 342                 #clock-cells = <0>;
 343                 compatible = "fixed-clock";
 344                 clock-frequency = <100000000>;
 345         };
 346
 347         dummy_cmn_refclk1: dummy-cmn-refclk1 {
 348                 #clock-cells = <0>;
 349                 compatible = "fixed-clock";
 350                 clock-frequency = <100000000>;
 351         };
 352
 353         serdes_wiz0: wiz@5000000 {
 354                 compatible = "ti,j721e-wiz-16g";
 355                 #address-cells = <1>;
 356                 #size-cells = <1>;
 357                 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
 358                 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
 359                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 360                 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
 361                 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
 362                 num-lanes = <2>;
 363                 #reset-cells = <1>;
 364                 ranges = <0x5000000 0x0 0x5000000 0x10000>;
 365
 366                 wiz0_pll0_refclk: pll0-refclk {
 367                         clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
 368                         #clock-cells = <0>;
 369                         assigned-clocks = <&wiz0_pll0_refclk>;
 370                         assigned-clock-parents = <&k3_clks 292 11>;
 371                 };
 372
 373                 wiz0_pll1_refclk: pll1-refclk {
 374                         clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
 375                         #clock-cells = <0>;
 376                         assigned-clocks = <&wiz0_pll1_refclk>;
 377                         assigned-clock-parents = <&k3_clks 292 0>;
 378                 };
 379
 380                 wiz0_refclk_dig: refclk-dig {
 381                         clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 382                         #clock-cells = <0>;
 383                         assigned-clocks = <&wiz0_refclk_dig>;
 384                         assigned-clock-parents = <&k3_clks 292 11>;
 385                 };
 386
 387                 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
 388                         clocks = <&wiz0_refclk_dig>;
 389                         #clock-cells = <0>;
 390                 };
 391
 392                 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 393                         clocks = <&wiz0_pll1_refclk>;
 394                         #clock-cells = <0>;
 395                 };
 396
 397                 serdes0: serdes@5000000 {
 398                         compatible = "ti,sierra-phy-t0";
 399                         reg-names = "serdes";
 400                         reg = <0x5000000 0x10000>;
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         resets = <&serdes_wiz0 0>;
 404                         reset-names = "sierra_reset";
 405                         clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
 406                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 407                 };
 408         };
 409
 410         serdes_wiz1: wiz@5010000 {
 411                 compatible = "ti,j721e-wiz-16g";
 412                 #address-cells = <1>;
 413                 #size-cells = <1>;
 414                 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
 415                 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
 416                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 417                 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
 418                 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
 419                 num-lanes = <2>;
 420                 #reset-cells = <1>;
 421                 ranges = <0x5010000 0x0 0x5010000 0x10000>;
 422
 423                 wiz1_pll0_refclk: pll0-refclk {
 424                         clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
 425                         #clock-cells = <0>;
 426                         assigned-clocks = <&wiz1_pll0_refclk>;
 427                         assigned-clock-parents = <&k3_clks 293 13>;
 428                 };
 429
 430                 wiz1_pll1_refclk: pll1-refclk {
 431                         clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
 432                         #clock-cells = <0>;
 433                         assigned-clocks = <&wiz1_pll1_refclk>;
 434                         assigned-clock-parents = <&k3_clks 293 0>;
 435                 };
 436
 437                 wiz1_refclk_dig: refclk-dig {
 438                         clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 439                         #clock-cells = <0>;
 440                         assigned-clocks = <&wiz1_refclk_dig>;
 441                         assigned-clock-parents = <&k3_clks 293 13>;
 442                 };
 443
 444                 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
 445                         clocks = <&wiz1_refclk_dig>;
 446                         #clock-cells = <0>;
 447                 };
 448
 449                 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 450                         clocks = <&wiz1_pll1_refclk>;
 451                         #clock-cells = <0>;
 452                 };
 453
 454                 serdes1: serdes@5010000 {
 455                         compatible = "ti,sierra-phy-t0";
 456                         reg-names = "serdes";
 457                         reg = <0x5010000 0x10000>;
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         resets = <&serdes_wiz1 0>;
 461                         reset-names = "sierra_reset";
 462                         clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
 463                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 464                 };
 465         };
 466
 467         serdes_wiz2: wiz@5020000 {
 468                 compatible = "ti,j721e-wiz-16g";
 469                 #address-cells = <1>;
 470                 #size-cells = <1>;
 471                 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
 472                 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
 473                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 474                 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
 475                 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
 476                 num-lanes = <2>;
 477                 #reset-cells = <1>;
 478                 ranges = <0x5020000 0x0 0x5020000 0x10000>;
 479
 480                 wiz2_pll0_refclk: pll0-refclk {
 481                         clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
 482                         #clock-cells = <0>;
 483                         assigned-clocks = <&wiz2_pll0_refclk>;
 484                         assigned-clock-parents = <&k3_clks 294 11>;
 485                 };
 486
 487                 wiz2_pll1_refclk: pll1-refclk {
 488                         clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
 489                         #clock-cells = <0>;
 490                         assigned-clocks = <&wiz2_pll1_refclk>;
 491                         assigned-clock-parents = <&k3_clks 294 0>;
 492                 };
 493
 494                 wiz2_refclk_dig: refclk-dig {
 495                         clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 496                         #clock-cells = <0>;
 497                         assigned-clocks = <&wiz2_refclk_dig>;
 498                         assigned-clock-parents = <&k3_clks 294 11>;
 499                 };
 500
 501                 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
 502                         clocks = <&wiz2_refclk_dig>;
 503                         #clock-cells = <0>;
 504                 };
 505
 506                 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 507                         clocks = <&wiz2_pll1_refclk>;
 508                         #clock-cells = <0>;
 509                 };
 510
 511                 serdes2: serdes@5020000 {
 512                         compatible = "ti,sierra-phy-t0";
 513                         reg-names = "serdes";
 514                         reg = <0x5020000 0x10000>;
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         resets = <&serdes_wiz2 0>;
 518                         reset-names = "sierra_reset";
 519                         clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
 520                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 521                 };
 522         };
 523
 524         serdes_wiz3: wiz@5030000 {
 525                 compatible = "ti,j721e-wiz-16g";
 526                 #address-cells = <1>;
 527                 #size-cells = <1>;
 528                 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
 529                 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
 530                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 531                 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
 532                 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
 533                 num-lanes = <2>;
 534                 #reset-cells = <1>;
 535                 ranges = <0x5030000 0x0 0x5030000 0x10000>;
 536
 537                 wiz3_pll0_refclk: pll0-refclk {
 538                         clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
 539                         #clock-cells = <0>;
 540                         assigned-clocks = <&wiz3_pll0_refclk>;
 541                         assigned-clock-parents = <&k3_clks 295 9>;
 542                 };
 543
 544                 wiz3_pll1_refclk: pll1-refclk {
 545                         clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
 546                         #clock-cells = <0>;
 547                         assigned-clocks = <&wiz3_pll1_refclk>;
 548                         assigned-clock-parents = <&k3_clks 295 0>;
 549                 };
 550
 551                 wiz3_refclk_dig: refclk-dig {
 552                         clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 553                         #clock-cells = <0>;
 554                         assigned-clocks = <&wiz3_refclk_dig>;
 555                         assigned-clock-parents = <&k3_clks 295 9>;
 556                 };
 557
 558                 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
 559                         clocks = <&wiz3_refclk_dig>;
 560                         #clock-cells = <0>;
 561                 };
 562
 563                 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 564                         clocks = <&wiz3_pll1_refclk>;
 565                         #clock-cells = <0>;
 566                 };
 567
 568                 serdes3: serdes@5030000 {
 569                         compatible = "ti,sierra-phy-t0";
 570                         reg-names = "serdes";
 571                         reg = <0x5030000 0x10000>;
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         resets = <&serdes_wiz3 0>;
 575                         reset-names = "sierra_reset";
 576                         clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
 577                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 578                 };
 579         };
 580
 581         pcie0_rc: pcie@2900000 {
 582                 compatible = "ti,j721e-pcie-host";
 583                 reg = <0x00 0x02900000 0x00 0x1000>,
 584                       <0x00 0x02907000 0x00 0x400>,
 585                       <0x00 0x0d000000 0x00 0x00800000>,
 586                       <0x00 0x10000000 0x00 0x00001000>;
 587                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 588                 interrupt-names = "link_state";
 589                 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
 590                 device_type = "pci";
 591                 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
 592                 max-link-speed = <3>;
 593                 num-lanes = <2>;
 594                 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
 595                 clocks = <&k3_clks 239 1>;
 596                 clock-names = "fck";
 597                 #address-cells = <3>;
 598                 #size-cells = <2>;
 599                 bus-range = <0x0 0xf>;
 600                 vendor-id = <0x104c>;
 601                 device-id = <0xb00d>;
 602                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 603                 dma-coherent;
 604                 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
 605                          <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
 606                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 607         };
 608
 609         pcie0_ep: pcie-ep@2900000 {
 610                 compatible = "ti,j721e-pcie-ep";
 611                 reg = <0x00 0x02900000 0x00 0x1000>,
 612                       <0x00 0x02907000 0x00 0x400>,
 613                       <0x00 0x0d000000 0x00 0x00800000>,
 614                       <0x00 0x10000000 0x00 0x08000000>;
 615                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 616                 interrupt-names = "link_state";
 617                 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
 618                 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
 619                 max-link-speed = <3>;
 620                 num-lanes = <2>;
 621                 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
 622                 clocks = <&k3_clks 239 1>;
 623                 clock-names = "fck";
 624                 max-functions = /bits/ 8 <6>;
 625                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 626                 dma-coherent;
 627         };
 628
 629         pcie1_rc: pcie@2910000 {
 630                 compatible = "ti,j721e-pcie-host";
 631                 reg = <0x00 0x02910000 0x00 0x1000>,
 632                       <0x00 0x02917000 0x00 0x400>,
 633                       <0x00 0x0d800000 0x00 0x00800000>,
 634                       <0x00 0x18000000 0x00 0x00001000>;
 635                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 636                 interrupt-names = "link_state";
 637                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 638                 device_type = "pci";
 639                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 640                 max-link-speed = <3>;
 641                 num-lanes = <2>;
 642                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 643                 clocks = <&k3_clks 240 1>;
 644                 clock-names = "fck";
 645                 #address-cells = <3>;
 646                 #size-cells = <2>;
 647                 bus-range = <0x0 0xf>;
 648                 vendor-id = <0x104c>;
 649                 device-id = <0xb00d>;
 650                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
 651                 dma-coherent;
 652                 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
 653                          <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
 654                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 655         };
 656
 657         pcie1_ep: pcie-ep@2910000 {
 658                 compatible = "ti,j721e-pcie-ep";
 659                 reg = <0x00 0x02910000 0x00 0x1000>,
 660                       <0x00 0x02917000 0x00 0x400>,
 661                       <0x00 0x0d800000 0x00 0x00800000>,
 662                       <0x00 0x18000000 0x00 0x08000000>;
 663                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 664                 interrupt-names = "link_state";
 665                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 666                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 667                 max-link-speed = <3>;
 668                 num-lanes = <2>;
 669                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 670                 clocks = <&k3_clks 240 1>;
 671                 clock-names = "fck";
 672                 max-functions = /bits/ 8 <6>;
 673                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 674                 dma-coherent;
 675         };
 676
 677         pcie2_rc: pcie@2920000 {
 678                 compatible = "ti,j721e-pcie-host";
 679                 reg = <0x00 0x02920000 0x00 0x1000>,
 680                       <0x00 0x02927000 0x00 0x400>,
 681                       <0x00 0x0e000000 0x00 0x00800000>,
 682                       <0x44 0x00000000 0x00 0x00001000>;
 683                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 684                 interrupt-names = "link_state";
 685                 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
 686                 device_type = "pci";
 687                 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
 688                 max-link-speed = <3>;
 689                 num-lanes = <2>;
 690                 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
 691                 clocks = <&k3_clks 241 1>;
 692                 clock-names = "fck";
 693                 #address-cells = <3>;
 694                 #size-cells = <2>;
 695                 bus-range = <0x0 0xf>;
 696                 vendor-id = <0x104c>;
 697                 device-id = <0xb00d>;
 698                 msi-map = <0x0 &gic_its 0x20000 0x10000>;
 699                 dma-coherent;
 700                 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
 701                          <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
 702                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 703         };
 704
 705         pcie2_ep: pcie-ep@2920000 {
 706                 compatible = "ti,j721e-pcie-ep";
 707                 reg = <0x00 0x02920000 0x00 0x1000>,
 708                       <0x00 0x02927000 0x00 0x400>,
 709                       <0x00 0x0e000000 0x00 0x00800000>,
 710                       <0x44 0x00000000 0x00 0x08000000>;
 711                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 712                 interrupt-names = "link_state";
 713                 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
 714                 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
 715                 max-link-speed = <3>;
 716                 num-lanes = <2>;
 717                 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
 718                 clocks = <&k3_clks 241 1>;
 719                 clock-names = "fck";
 720                 max-functions = /bits/ 8 <6>;
 721                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 722                 dma-coherent;
 723         };
 724
 725         pcie3_rc: pcie@2930000 {
 726                 compatible = "ti,j721e-pcie-host";
 727                 reg = <0x00 0x02930000 0x00 0x1000>,
 728                       <0x00 0x02937000 0x00 0x400>,
 729                       <0x00 0x0e800000 0x00 0x00800000>,
 730                       <0x44 0x10000000 0x00 0x00001000>;
 731                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 732                 interrupt-names = "link_state";
 733                 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
 734                 device_type = "pci";
 735                 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
 736                 max-link-speed = <3>;
 737                 num-lanes = <2>;
 738                 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
 739                 clocks = <&k3_clks 242 1>;
 740                 clock-names = "fck";
 741                 #address-cells = <3>;
 742                 #size-cells = <2>;
 743                 bus-range = <0x0 0xf>;
 744                 vendor-id = <0x104c>;
 745                 device-id = <0xb00d>;
 746                 msi-map = <0x0 &gic_its 0x30000 0x10000>;
 747                 dma-coherent;
 748                 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
 749                          <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
 750                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 751         };
 752
 753         pcie3_ep: pcie-ep@2930000 {
 754                 compatible = "ti,j721e-pcie-ep";
 755                 reg = <0x00 0x02930000 0x00 0x1000>,
 756                       <0x00 0x02937000 0x00 0x400>,
 757                       <0x00 0x0e800000 0x00 0x00800000>,
 758                       <0x44 0x10000000 0x00 0x08000000>;
 759                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 760                 interrupt-names = "link_state";
 761                 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
 762                 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
 763                 max-link-speed = <3>;
 764                 num-lanes = <2>;
 765                 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
 766                 clocks = <&k3_clks 242 1>;
 767                 clock-names = "fck";
 768                 max-functions = /bits/ 8 <6>;
 769                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 770                 dma-coherent;
 771                 #address-cells = <2>;
 772                 #size-cells = <2>;
 773         };
 774
 775         main_uart0: serial@2800000 {
 776                 compatible = "ti,j721e-uart", "ti,am654-uart";
 777                 reg = <0x00 0x02800000 0x00 0x100>;
 778                 reg-shift = <2>;
 779                 reg-io-width = <4>;
 780                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 781                 clock-frequency = <48000000>;
 782                 current-speed = <115200>;
 783                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 784                 clocks = <&k3_clks 146 0>;
 785                 clock-names = "fclk";
 786         };
 787
 788         main_uart1: serial@2810000 {
 789                 compatible = "ti,j721e-uart", "ti,am654-uart";
 790                 reg = <0x00 0x02810000 0x00 0x100>;
 791                 reg-shift = <2>;
 792                 reg-io-width = <4>;
 793                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 794                 clock-frequency = <48000000>;
 795                 current-speed = <115200>;
 796                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
 797                 clocks = <&k3_clks 278 0>;
 798                 clock-names = "fclk";
 799         };
 800
 801         main_uart2: serial@2820000 {
 802                 compatible = "ti,j721e-uart", "ti,am654-uart";
 803                 reg = <0x00 0x02820000 0x00 0x100>;
 804                 reg-shift = <2>;
 805                 reg-io-width = <4>;
 806                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 807                 clock-frequency = <48000000>;
 808                 current-speed = <115200>;
 809                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 810                 clocks = <&k3_clks 279 0>;
 811                 clock-names = "fclk";
 812         };
 813
 814         main_uart3: serial@2830000 {
 815                 compatible = "ti,j721e-uart", "ti,am654-uart";
 816                 reg = <0x00 0x02830000 0x00 0x100>;
 817                 reg-shift = <2>;
 818                 reg-io-width = <4>;
 819                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 820                 clock-frequency = <48000000>;
 821                 current-speed = <115200>;
 822                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 823                 clocks = <&k3_clks 280 0>;
 824                 clock-names = "fclk";
 825         };
 826
 827         main_uart4: serial@2840000 {
 828                 compatible = "ti,j721e-uart", "ti,am654-uart";
 829                 reg = <0x00 0x02840000 0x00 0x100>;
 830                 reg-shift = <2>;
 831                 reg-io-width = <4>;
 832                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 833                 clock-frequency = <48000000>;
 834                 current-speed = <115200>;
 835                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 836                 clocks = <&k3_clks 281 0>;
 837                 clock-names = "fclk";
 838         };
 839
 840         main_uart5: serial@2850000 {
 841                 compatible = "ti,j721e-uart", "ti,am654-uart";
 842                 reg = <0x00 0x02850000 0x00 0x100>;
 843                 reg-shift = <2>;
 844                 reg-io-width = <4>;
 845                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 846                 clock-frequency = <48000000>;
 847                 current-speed = <115200>;
 848                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 849                 clocks = <&k3_clks 282 0>;
 850                 clock-names = "fclk";
 851         };
 852
 853         main_uart6: serial@2860000 {
 854                 compatible = "ti,j721e-uart", "ti,am654-uart";
 855                 reg = <0x00 0x02860000 0x00 0x100>;
 856                 reg-shift = <2>;
 857                 reg-io-width = <4>;
 858                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 859                 clock-frequency = <48000000>;
 860                 current-speed = <115200>;
 861                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 862                 clocks = <&k3_clks 283 0>;
 863                 clock-names = "fclk";
 864         };
 865
 866         main_uart7: serial@2870000 {
 867                 compatible = "ti,j721e-uart", "ti,am654-uart";
 868                 reg = <0x00 0x02870000 0x00 0x100>;
 869                 reg-shift = <2>;
 870                 reg-io-width = <4>;
 871                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 872                 clock-frequency = <48000000>;
 873                 current-speed = <115200>;
 874                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 875                 clocks = <&k3_clks 284 0>;
 876                 clock-names = "fclk";
 877         };
 878
 879         main_uart8: serial@2880000 {
 880                 compatible = "ti,j721e-uart", "ti,am654-uart";
 881                 reg = <0x00 0x02880000 0x00 0x100>;
 882                 reg-shift = <2>;
 883                 reg-io-width = <4>;
 884                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 885                 clock-frequency = <48000000>;
 886                 current-speed = <115200>;
 887                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 888                 clocks = <&k3_clks 285 0>;
 889                 clock-names = "fclk";
 890         };
 891
 892         main_uart9: serial@2890000 {
 893                 compatible = "ti,j721e-uart", "ti,am654-uart";
 894                 reg = <0x00 0x02890000 0x00 0x100>;
 895                 reg-shift = <2>;
 896                 reg-io-width = <4>;
 897                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 898                 clock-frequency = <48000000>;
 899                 current-speed = <115200>;
 900                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 901                 clocks = <&k3_clks 286 0>;
 902                 clock-names = "fclk";
 903         };
 904
 905         main_gpio0: gpio@600000 {
 906                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 907                 reg = <0x0 0x00600000 0x0 0x100>;
 908                 gpio-controller;
 909                 #gpio-cells = <2>;
 910                 interrupt-parent = <&main_gpio_intr>;
 911                 interrupts = <256>, <257>, <258>, <259>,
 912                              <260>, <261>, <262>, <263>;
 913                 interrupt-controller;
 914                 #interrupt-cells = <2>;
 915                 ti,ngpio = <128>;
 916                 ti,davinci-gpio-unbanked = <0>;
 917                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 918                 clocks = <&k3_clks 105 0>;
 919                 clock-names = "gpio";
 920         };
 921
 922         main_gpio1: gpio@601000 {
 923                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 924                 reg = <0x0 0x00601000 0x0 0x100>;
 925                 gpio-controller;
 926                 #gpio-cells = <2>;
 927                 interrupt-parent = <&main_gpio_intr>;
 928                 interrupts = <288>, <289>, <290>;
 929                 interrupt-controller;
 930                 #interrupt-cells = <2>;
 931                 ti,ngpio = <36>;
 932                 ti,davinci-gpio-unbanked = <0>;
 933                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 934                 clocks = <&k3_clks 106 0>;
 935                 clock-names = "gpio";
 936         };
 937
 938         main_gpio2: gpio@610000 {
 939                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 940                 reg = <0x0 0x00610000 0x0 0x100>;
 941                 gpio-controller;
 942                 #gpio-cells = <2>;
 943                 interrupt-parent = <&main_gpio_intr>;
 944                 interrupts = <264>, <265>, <266>, <267>,
 945                              <268>, <269>, <270>, <271>;
 946                 interrupt-controller;
 947                 #interrupt-cells = <2>;
 948                 ti,ngpio = <128>;
 949                 ti,davinci-gpio-unbanked = <0>;
 950                 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 951                 clocks = <&k3_clks 107 0>;
 952                 clock-names = "gpio";
 953         };
 954
 955         main_gpio3: gpio@611000 {
 956                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 957                 reg = <0x0 0x00611000 0x0 0x100>;
 958                 gpio-controller;
 959                 #gpio-cells = <2>;
 960                 interrupt-parent = <&main_gpio_intr>;
 961                 interrupts = <292>, <293>, <294>;
 962                 interrupt-controller;
 963                 #interrupt-cells = <2>;
 964                 ti,ngpio = <36>;
 965                 ti,davinci-gpio-unbanked = <0>;
 966                 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
 967                 clocks = <&k3_clks 108 0>;
 968                 clock-names = "gpio";
 969         };
 970
 971         main_gpio4: gpio@620000 {
 972                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 973                 reg = <0x0 0x00620000 0x0 0x100>;
 974                 gpio-controller;
 975                 #gpio-cells = <2>;
 976                 interrupt-parent = <&main_gpio_intr>;
 977                 interrupts = <272>, <273>, <274>, <275>,
 978                              <276>, <277>, <278>, <279>;
 979                 interrupt-controller;
 980                 #interrupt-cells = <2>;
 981                 ti,ngpio = <128>;
 982                 ti,davinci-gpio-unbanked = <0>;
 983                 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
 984                 clocks = <&k3_clks 109 0>;
 985                 clock-names = "gpio";
 986         };
 987
 988         main_gpio5: gpio@621000 {
 989                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 990                 reg = <0x0 0x00621000 0x0 0x100>;
 991                 gpio-controller;
 992                 #gpio-cells = <2>;
 993                 interrupt-parent = <&main_gpio_intr>;
 994                 interrupts = <296>, <297>, <298>;
 995                 interrupt-controller;
 996                 #interrupt-cells = <2>;
 997                 ti,ngpio = <36>;
 998                 ti,davinci-gpio-unbanked = <0>;
 999                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1000                 clocks = <&k3_clks 110 0>;
1001                 clock-names = "gpio";
1002         };
1003
1004         main_gpio6: gpio@630000 {
1005                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1006                 reg = <0x0 0x00630000 0x0 0x100>;
1007                 gpio-controller;
1008                 #gpio-cells = <2>;
1009                 interrupt-parent = <&main_gpio_intr>;
1010                 interrupts = <280>, <281>, <282>, <283>,
1011                              <284>, <285>, <286>, <287>;
1012                 interrupt-controller;
1013                 #interrupt-cells = <2>;
1014                 ti,ngpio = <128>;
1015                 ti,davinci-gpio-unbanked = <0>;
1016                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1017                 clocks = <&k3_clks 111 0>;
1018                 clock-names = "gpio";
1019         };
1020
1021         main_gpio7: gpio@631000 {
1022                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1023                 reg = <0x0 0x00631000 0x0 0x100>;
1024                 gpio-controller;
1025                 #gpio-cells = <2>;
1026                 interrupt-parent = <&main_gpio_intr>;
1027                 interrupts = <300>, <301>, <302>;
1028                 interrupt-controller;
1029                 #interrupt-cells = <2>;
1030                 ti,ngpio = <36>;
1031                 ti,davinci-gpio-unbanked = <0>;
1032                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1033                 clocks = <&k3_clks 112 0>;
1034                 clock-names = "gpio";
1035         };
1036
1037         main_sdhci0: mmc@4f80000 {
1038                 compatible = "ti,j721e-sdhci-8bit";
1039                 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1040                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1041                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1042                 clock-names = "clk_ahb", "clk_xin";
1043                 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1044                 assigned-clocks = <&k3_clks 91 1>;
1045                 assigned-clock-parents = <&k3_clks 91 2>;
1046                 bus-width = <8>;
1047                 mmc-hs200-1_8v;
1048                 mmc-ddr-1_8v;
1049                 ti,otap-del-sel-legacy = <0xf>;
1050                 ti,otap-del-sel-mmc-hs = <0xf>;
1051                 ti,otap-del-sel-ddr52 = <0x5>;
1052                 ti,otap-del-sel-hs200 = <0x6>;
1053                 ti,otap-del-sel-hs400 = <0x0>;
1054                 ti,itap-del-sel-legacy = <0x10>;
1055                 ti,itap-del-sel-mmc-hs = <0xa>;
1056                 ti,itap-del-sel-ddr52 = <0x3>;
1057                 ti,trm-icp = <0x8>;
1058                 ti,strobe-sel = <0x77>;
1059                 dma-coherent;
1060         };
1061
1062         main_sdhci1: mmc@4fb0000 {
1063                 compatible = "ti,j721e-sdhci-4bit";
1064                 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1065                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1066                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1067                 clock-names = "clk_ahb", "clk_xin";
1068                 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1069                 assigned-clocks = <&k3_clks 92 0>;
1070                 assigned-clock-parents = <&k3_clks 92 1>;
1071                 ti,otap-del-sel-legacy = <0x0>;
1072                 ti,otap-del-sel-sd-hs = <0xf>;
1073                 ti,otap-del-sel-sdr12 = <0xf>;
1074                 ti,otap-del-sel-sdr25 = <0xf>;
1075                 ti,otap-del-sel-sdr50 = <0xc>;
1076                 ti,otap-del-sel-ddr50 = <0xc>;
1077                 ti,itap-del-sel-legacy = <0x0>;
1078                 ti,itap-del-sel-sd-hs = <0x0>;
1079                 ti,itap-del-sel-sdr12 = <0x0>;
1080                 ti,itap-del-sel-sdr25 = <0x0>;
1081                 ti,itap-del-sel-ddr50 = <0x2>;
1082                 ti,trm-icp = <0x8>;
1083                 ti,clkbuf-sel = <0x7>;
1084                 dma-coherent;
1085                 sdhci-caps-mask = <0x2 0x0>;
1086         };
1087
1088         main_sdhci2: mmc@4f98000 {
1089                 compatible = "ti,j721e-sdhci-4bit";
1090                 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1091                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1092                 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1093                 clock-names = "clk_ahb", "clk_xin";
1094                 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1095                 assigned-clocks = <&k3_clks 93 0>;
1096                 assigned-clock-parents = <&k3_clks 93 1>;
1097                 ti,otap-del-sel-legacy = <0x0>;
1098                 ti,otap-del-sel-sd-hs = <0xf>;
1099                 ti,otap-del-sel-sdr12 = <0xf>;
1100                 ti,otap-del-sel-sdr25 = <0xf>;
1101                 ti,otap-del-sel-sdr50 = <0xc>;
1102                 ti,otap-del-sel-ddr50 = <0xc>;
1103                 ti,itap-del-sel-legacy = <0x0>;
1104                 ti,itap-del-sel-sd-hs = <0x0>;
1105                 ti,itap-del-sel-sdr12 = <0x0>;
1106                 ti,itap-del-sel-sdr25 = <0x0>;
1107                 ti,itap-del-sel-ddr50 = <0x2>;
1108                 ti,trm-icp = <0x8>;
1109                 ti,clkbuf-sel = <0x7>;
1110                 dma-coherent;
1111                 sdhci-caps-mask = <0x2 0x0>;
1112         };
1113
1114         usbss0: cdns-usb@4104000 {
1115                 compatible = "ti,j721e-usb";
1116                 reg = <0x00 0x4104000 0x00 0x100>;
1117                 dma-coherent;
1118                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1119                 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1120                 clock-names = "ref", "lpm";
1121                 assigned-clocks = <&k3_clks 288 15>;    /* USB2_REFCLK */
1122                 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1123                 #address-cells = <2>;
1124                 #size-cells = <2>;
1125                 ranges;
1126
1127                 usb0: usb@6000000 {
1128                         compatible = "cdns,usb3";
1129                         reg = <0x00 0x6000000 0x00 0x10000>,
1130                               <0x00 0x6010000 0x00 0x10000>,
1131                               <0x00 0x6020000 0x00 0x10000>;
1132                         reg-names = "otg", "xhci", "dev";
1133                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
1134                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1135                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1136                         interrupt-names = "host",
1137                                           "peripheral",
1138                                           "otg";
1139                         maximum-speed = "super-speed";
1140                         dr_mode = "otg";
1141                 };
1142         };
1143
1144         usbss1: cdns-usb@4114000 {
1145                 compatible = "ti,j721e-usb";
1146                 reg = <0x00 0x4114000 0x00 0x100>;
1147                 dma-coherent;
1148                 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1149                 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1150                 clock-names = "ref", "lpm";
1151                 assigned-clocks = <&k3_clks 289 15>;    /* USB2_REFCLK */
1152                 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1153                 #address-cells = <2>;
1154                 #size-cells = <2>;
1155                 ranges;
1156
1157                 usb1: usb@6400000 {
1158                         compatible = "cdns,usb3";
1159                         reg = <0x00 0x6400000 0x00 0x10000>,
1160                               <0x00 0x6410000 0x00 0x10000>,
1161                               <0x00 0x6420000 0x00 0x10000>;
1162                         reg-names = "otg", "xhci", "dev";
1163                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1164                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1165                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1166                         interrupt-names = "host",
1167                                           "peripheral",
1168                                           "otg";
1169                         maximum-speed = "super-speed";
1170                         dr_mode = "otg";
1171                 };
1172         };
1173
1174         main_i2c0: i2c@2000000 {
1175                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1176                 reg = <0x0 0x2000000 0x0 0x100>;
1177                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1178                 #address-cells = <1>;
1179                 #size-cells = <0>;
1180                 clock-names = "fck";
1181                 clocks = <&k3_clks 187 0>;
1182                 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1183         };
1184
1185         main_i2c1: i2c@2010000 {
1186                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1187                 reg = <0x0 0x2010000 0x0 0x100>;
1188                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1189                 #address-cells = <1>;
1190                 #size-cells = <0>;
1191                 clock-names = "fck";
1192                 clocks = <&k3_clks 188 0>;
1193                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1194         };
1195
1196         main_i2c2: i2c@2020000 {
1197                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1198                 reg = <0x0 0x2020000 0x0 0x100>;
1199                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1200                 #address-cells = <1>;
1201                 #size-cells = <0>;
1202                 clock-names = "fck";
1203                 clocks = <&k3_clks 189 0>;
1204                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1205         };
1206
1207         main_i2c3: i2c@2030000 {
1208                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1209                 reg = <0x0 0x2030000 0x0 0x100>;
1210                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1211                 #address-cells = <1>;
1212                 #size-cells = <0>;
1213                 clock-names = "fck";
1214                 clocks = <&k3_clks 190 0>;
1215                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1216         };
1217
1218         main_i2c4: i2c@2040000 {
1219                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1220                 reg = <0x0 0x2040000 0x0 0x100>;
1221                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1222                 #address-cells = <1>;
1223                 #size-cells = <0>;
1224                 clock-names = "fck";
1225                 clocks = <&k3_clks 191 0>;
1226                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1227         };
1228
1229         main_i2c5: i2c@2050000 {
1230                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1231                 reg = <0x0 0x2050000 0x0 0x100>;
1232                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1233                 #address-cells = <1>;
1234                 #size-cells = <0>;
1235                 clock-names = "fck";
1236                 clocks = <&k3_clks 192 0>;
1237                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1238         };
1239
1240         main_i2c6: i2c@2060000 {
1241                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1242                 reg = <0x0 0x2060000 0x0 0x100>;
1243                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1244                 #address-cells = <1>;
1245                 #size-cells = <0>;
1246                 clock-names = "fck";
1247                 clocks = <&k3_clks 193 0>;
1248                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1249         };
1250
1251         ufs_wrapper: ufs-wrapper@4e80000 {
1252                 compatible = "ti,j721e-ufs";
1253                 reg = <0x0 0x4e80000 0x0 0x100>;
1254                 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1255                 clocks = <&k3_clks 277 1>;
1256                 assigned-clocks = <&k3_clks 277 1>;
1257                 assigned-clock-parents = <&k3_clks 277 4>;
1258                 ranges;
1259                 #address-cells = <2>;
1260                 #size-cells = <2>;
1261
1262                 ufs@4e84000 {
1263                         compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1264                         reg = <0x0 0x4e84000 0x0 0x10000>;
1265                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1266                         freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1267                         clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1268                         clock-names = "core_clk", "phy_clk", "ref_clk";
1269                         dma-coherent;
1270                 };
1271         };
1272
1273         dss: dss@4a00000 {
1274                 compatible = "ti,j721e-dss";
1275                 reg =
1276                         <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1277                         <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1278                         <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1279                         <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1280
1281                         <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1282                         <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1283                         <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1284                         <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1285
1286                         <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1287                         <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1288                         <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1289                         <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1290
1291                         <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1292                         <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1293                         <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1294                         <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1295                         <0x00 0x04af0000 0x00 0x10000>; /* wb */
1296
1297                 reg-names = "common_m", "common_s0",
1298                         "common_s1", "common_s2",
1299                         "vidl1", "vidl2","vid1","vid2",
1300                         "ovr1", "ovr2", "ovr3", "ovr4",
1301                         "vp1", "vp2", "vp3", "vp4",
1302                         "wb";
1303
1304                 clocks =        <&k3_clks 152 0>,
1305                                 <&k3_clks 152 1>,
1306                                 <&k3_clks 152 4>,
1307                                 <&k3_clks 152 9>,
1308                                 <&k3_clks 152 13>;
1309                 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1310
1311                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1312
1313                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1314                              <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1315                              <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1316                              <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1317                 interrupt-names = "common_m",
1318                                   "common_s0",
1319                                   "common_s1",
1320                                   "common_s2";
1321
1322                 dss_ports: ports {
1323                         #address-cells = <1>;
1324                         #size-cells = <0>;
1325                 };
1326         };
1327
1328         mcasp0: mcasp@2b00000 {
1329                 compatible = "ti,am33xx-mcasp-audio";
1330                 reg = <0x0 0x02b00000 0x0 0x2000>,
1331                         <0x0 0x02b08000 0x0 0x1000>;
1332                 reg-names = "mpu","dat";
1333                 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1334                                 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1335                 interrupt-names = "tx", "rx";
1336
1337                 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1338                 dma-names = "tx", "rx";
1339
1340                 clocks = <&k3_clks 174 1>;
1341                 clock-names = "fck";
1342                 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1343         };
1344
1345         mcasp1: mcasp@2b10000 {
1346                 compatible = "ti,am33xx-mcasp-audio";
1347                 reg = <0x0 0x02b10000 0x0 0x2000>,
1348                         <0x0 0x02b18000 0x0 0x1000>;
1349                 reg-names = "mpu","dat";
1350                 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1351                                 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1352                 interrupt-names = "tx", "rx";
1353
1354                 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1355                 dma-names = "tx", "rx";
1356
1357                 clocks = <&k3_clks 175 1>;
1358                 clock-names = "fck";
1359                 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1360         };
1361
1362         mcasp2: mcasp@2b20000 {
1363                 compatible = "ti,am33xx-mcasp-audio";
1364                 reg = <0x0 0x02b20000 0x0 0x2000>,
1365                         <0x0 0x02b28000 0x0 0x1000>;
1366                 reg-names = "mpu","dat";
1367                 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1368                                 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1369                 interrupt-names = "tx", "rx";
1370
1371                 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1372                 dma-names = "tx", "rx";
1373
1374                 clocks = <&k3_clks 176 1>;
1375                 clock-names = "fck";
1376                 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1377         };
1378
1379         mcasp3: mcasp@2b30000 {
1380                 compatible = "ti,am33xx-mcasp-audio";
1381                 reg = <0x0 0x02b30000 0x0 0x2000>,
1382                         <0x0 0x02b38000 0x0 0x1000>;
1383                 reg-names = "mpu","dat";
1384                 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1385                                 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1386                 interrupt-names = "tx", "rx";
1387
1388                 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1389                 dma-names = "tx", "rx";
1390
1391                 clocks = <&k3_clks 177 1>;
1392                 clock-names = "fck";
1393                 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1394         };
1395
1396         mcasp4: mcasp@2b40000 {
1397                 compatible = "ti,am33xx-mcasp-audio";
1398                 reg = <0x0 0x02b40000 0x0 0x2000>,
1399                         <0x0 0x02b48000 0x0 0x1000>;
1400                 reg-names = "mpu","dat";
1401                 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1402                                 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1403                 interrupt-names = "tx", "rx";
1404
1405                 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1406                 dma-names = "tx", "rx";
1407
1408                 clocks = <&k3_clks 178 1>;
1409                 clock-names = "fck";
1410                 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1411         };
1412
1413         mcasp5: mcasp@2b50000 {
1414                 compatible = "ti,am33xx-mcasp-audio";
1415                 reg = <0x0 0x02b50000 0x0 0x2000>,
1416                         <0x0 0x02b58000 0x0 0x1000>;
1417                 reg-names = "mpu","dat";
1418                 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1419                                 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1420                 interrupt-names = "tx", "rx";
1421
1422                 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1423                 dma-names = "tx", "rx";
1424
1425                 clocks = <&k3_clks 179 1>;
1426                 clock-names = "fck";
1427                 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1428         };
1429
1430         mcasp6: mcasp@2b60000 {
1431                 compatible = "ti,am33xx-mcasp-audio";
1432                 reg = <0x0 0x02b60000 0x0 0x2000>,
1433                         <0x0 0x02b68000 0x0 0x1000>;
1434                 reg-names = "mpu","dat";
1435                 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1436                                 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1437                 interrupt-names = "tx", "rx";
1438
1439                 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1440                 dma-names = "tx", "rx";
1441
1442                 clocks = <&k3_clks 180 1>;
1443                 clock-names = "fck";
1444                 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1445         };
1446
1447         mcasp7: mcasp@2b70000 {
1448                 compatible = "ti,am33xx-mcasp-audio";
1449                 reg = <0x0 0x02b70000 0x0 0x2000>,
1450                         <0x0 0x02b78000 0x0 0x1000>;
1451                 reg-names = "mpu","dat";
1452                 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1453                                 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1454                 interrupt-names = "tx", "rx";
1455
1456                 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1457                 dma-names = "tx", "rx";
1458
1459                 clocks = <&k3_clks 181 1>;
1460                 clock-names = "fck";
1461                 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1462         };
1463
1464         mcasp8: mcasp@2b80000 {
1465                 compatible = "ti,am33xx-mcasp-audio";
1466                 reg = <0x0 0x02b80000 0x0 0x2000>,
1467                         <0x0 0x02b88000 0x0 0x1000>;
1468                 reg-names = "mpu","dat";
1469                 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1470                                 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1471                 interrupt-names = "tx", "rx";
1472
1473                 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1474                 dma-names = "tx", "rx";
1475
1476                 clocks = <&k3_clks 182 1>;
1477                 clock-names = "fck";
1478                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1479         };
1480
1481         mcasp9: mcasp@2b90000 {
1482                 compatible = "ti,am33xx-mcasp-audio";
1483                 reg = <0x0 0x02b90000 0x0 0x2000>,
1484                         <0x0 0x02b98000 0x0 0x1000>;
1485                 reg-names = "mpu","dat";
1486                 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1487                                 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1488                 interrupt-names = "tx", "rx";
1489
1490                 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1491                 dma-names = "tx", "rx";
1492
1493                 clocks = <&k3_clks 183 1>;
1494                 clock-names = "fck";
1495                 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1496         };
1497
1498         mcasp10: mcasp@2ba0000 {
1499                 compatible = "ti,am33xx-mcasp-audio";
1500                 reg = <0x0 0x02ba0000 0x0 0x2000>,
1501                         <0x0 0x02ba8000 0x0 0x1000>;
1502                 reg-names = "mpu","dat";
1503                 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1504                                 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1505                 interrupt-names = "tx", "rx";
1506
1507                 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1508                 dma-names = "tx", "rx";
1509
1510                 clocks = <&k3_clks 184 1>;
1511                 clock-names = "fck";
1512                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1513         };
1514
1515         mcasp11: mcasp@2bb0000 {
1516                 compatible = "ti,am33xx-mcasp-audio";
1517                 reg = <0x0 0x02bb0000 0x0 0x2000>,
1518                         <0x0 0x02bb8000 0x0 0x1000>;
1519                 reg-names = "mpu","dat";
1520                 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
1521                                 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
1522                 interrupt-names = "tx", "rx";
1523
1524                 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1525                 dma-names = "tx", "rx";
1526
1527                 clocks = <&k3_clks 185 1>;
1528                 clock-names = "fck";
1529                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1530         };
1531
1532         watchdog0: watchdog@2200000 {
1533                 compatible = "ti,j7-rti-wdt";
1534                 reg = <0x0 0x2200000 0x0 0x100>;
1535                 clocks = <&k3_clks 252 1>;
1536                 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1537                 assigned-clocks = <&k3_clks 252 1>;
1538                 assigned-clock-parents = <&k3_clks 252 5>;
1539         };
1540
1541         watchdog1: watchdog@2210000 {
1542                 compatible = "ti,j7-rti-wdt";
1543                 reg = <0x0 0x2210000 0x0 0x100>;
1544                 clocks = <&k3_clks 253 1>;
1545                 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1546                 assigned-clocks = <&k3_clks 253 1>;
1547                 assigned-clock-parents = <&k3_clks 253 5>;
1548         };
1549
1550         main_r5fss0: r5fss@5c00000 {
1551                 compatible = "ti,j721e-r5fss";
1552                 ti,cluster-mode = <1>;
1553                 #address-cells = <1>;
1554                 #size-cells = <1>;
1555                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1556                          <0x5d00000 0x00 0x5d00000 0x20000>;
1557                 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1558
1559                 main_r5fss0_core0: r5f@5c00000 {
1560                         compatible = "ti,j721e-r5f";
1561                         reg = <0x5c00000 0x00008000>,
1562                               <0x5c10000 0x00008000>;
1563                         reg-names = "atcm", "btcm";
1564                         ti,sci = <&dmsc>;
1565                         ti,sci-dev-id = <245>;
1566                         ti,sci-proc-ids = <0x06 0xff>;
1567                         resets = <&k3_reset 245 1>;
1568                         firmware-name = "j7-main-r5f0_0-fw";
1569                         ti,atcm-enable = <1>;
1570                         ti,btcm-enable = <1>;
1571                         ti,loczrama = <1>;
1572                 };
1573
1574                 main_r5fss0_core1: r5f@5d00000 {
1575                         compatible = "ti,j721e-r5f";
1576                         reg = <0x5d00000 0x00008000>,
1577                               <0x5d10000 0x00008000>;
1578                         reg-names = "atcm", "btcm";
1579                         ti,sci = <&dmsc>;
1580                         ti,sci-dev-id = <246>;
1581                         ti,sci-proc-ids = <0x07 0xff>;
1582                         resets = <&k3_reset 246 1>;
1583                         firmware-name = "j7-main-r5f0_1-fw";
1584                         ti,atcm-enable = <1>;
1585                         ti,btcm-enable = <1>;
1586                         ti,loczrama = <1>;
1587                 };
1588         };
1589
1590         main_r5fss1: r5fss@5e00000 {
1591                 compatible = "ti,j721e-r5fss";
1592                 ti,cluster-mode = <1>;
1593                 #address-cells = <1>;
1594                 #size-cells = <1>;
1595                 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1596                          <0x5f00000 0x00 0x5f00000 0x20000>;
1597                 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1598
1599                 main_r5fss1_core0: r5f@5e00000 {
1600                         compatible = "ti,j721e-r5f";
1601                         reg = <0x5e00000 0x00008000>,
1602                               <0x5e10000 0x00008000>;
1603                         reg-names = "atcm", "btcm";
1604                         ti,sci = <&dmsc>;
1605                         ti,sci-dev-id = <247>;
1606                         ti,sci-proc-ids = <0x08 0xff>;
1607                         resets = <&k3_reset 247 1>;
1608                         firmware-name = "j7-main-r5f1_0-fw";
1609                         ti,atcm-enable = <1>;
1610                         ti,btcm-enable = <1>;
1611                         ti,loczrama = <1>;
1612                 };
1613
1614                 main_r5fss1_core1: r5f@5f00000 {
1615                         compatible = "ti,j721e-r5f";
1616                         reg = <0x5f00000 0x00008000>,
1617                               <0x5f10000 0x00008000>;
1618                         reg-names = "atcm", "btcm";
1619                         ti,sci = <&dmsc>;
1620                         ti,sci-dev-id = <248>;
1621                         ti,sci-proc-ids = <0x09 0xff>;
1622                         resets = <&k3_reset 248 1>;
1623                         firmware-name = "j7-main-r5f1_1-fw";
1624                         ti,atcm-enable = <1>;
1625                         ti,btcm-enable = <1>;
1626                         ti,loczrama = <1>;
1627                 };
1628         };
1629
1630         c66_0: dsp@4d80800000 {
1631                 compatible = "ti,j721e-c66-dsp";
1632                 reg = <0x4d 0x80800000 0x00 0x00048000>,
1633                       <0x4d 0x80e00000 0x00 0x00008000>,
1634                       <0x4d 0x80f00000 0x00 0x00008000>;
1635                 reg-names = "l2sram", "l1pram", "l1dram";
1636                 ti,sci = <&dmsc>;
1637                 ti,sci-dev-id = <142>;
1638                 ti,sci-proc-ids = <0x03 0xff>;
1639                 resets = <&k3_reset 142 1>;
1640                 firmware-name = "j7-c66_0-fw";
1641         };
1642
1643         c66_1: dsp@4d81800000 {
1644                 compatible = "ti,j721e-c66-dsp";
1645                 reg = <0x4d 0x81800000 0x00 0x00048000>,
1646                       <0x4d 0x81e00000 0x00 0x00008000>,
1647                       <0x4d 0x81f00000 0x00 0x00008000>;
1648                 reg-names = "l2sram", "l1pram", "l1dram";
1649                 ti,sci = <&dmsc>;
1650                 ti,sci-dev-id = <143>;
1651                 ti,sci-proc-ids = <0x04 0xff>;
1652                 resets = <&k3_reset 143 1>;
1653                 firmware-name = "j7-c66_1-fw";
1654         };
1655
1656         c71_0: dsp@64800000 {
1657                 compatible = "ti,j721e-c71-dsp";
1658                 reg = <0x00 0x64800000 0x00 0x00080000>,
1659                       <0x00 0x64e00000 0x00 0x0000c000>;
1660                 reg-names = "l2sram", "l1dram";
1661                 ti,sci = <&dmsc>;
1662                 ti,sci-dev-id = <15>;
1663                 ti,sci-proc-ids = <0x30 0xff>;
1664                 resets = <&k3_reset 15 1>;
1665                 firmware-name = "j7-c71_0-fw";
1666         };
1667
1668         icssg0: icssg@b000000 {
1669                 compatible = "ti,j721e-icssg";
1670                 reg = <0x00 0xb000000 0x00 0x80000>;
1671                 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
1672                 #address-cells = <1>;
1673                 #size-cells = <1>;
1674                 ranges = <0x0 0x00 0x0b000000 0x100000>;
1675
1676                 icssg0_mem: memories@0 {
1677                         reg = <0x0 0x2000>,
1678                               <0x2000 0x2000>,
1679                               <0x10000 0x10000>;
1680                         reg-names = "dram0", "dram1",
1681                                     "shrdram2";
1682                 };
1683
1684                 icssg0_cfg: cfg@26000 {
1685                         compatible = "ti,pruss-cfg", "syscon";
1686                         reg = <0x26000 0x200>;
1687                         #address-cells = <1>;
1688                         #size-cells = <1>;
1689                         ranges = <0x0 0x26000 0x2000>;
1690
1691                         clocks {
1692                                 #address-cells = <1>;
1693                                 #size-cells = <0>;
1694
1695                                 icssg0_coreclk_mux: coreclk-mux@3c {
1696                                         reg = <0x3c>;
1697                                         #clock-cells = <0>;
1698                                         clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
1699                                                  <&k3_clks 119 1>;  /* icssg0_iclk */
1700                                         assigned-clocks = <&icssg0_coreclk_mux>;
1701                                         assigned-clock-parents = <&k3_clks 119 1>;
1702                                 };
1703
1704                                 icssg0_iepclk_mux: iepclk-mux@30 {
1705                                         reg = <0x30>;
1706                                         #clock-cells = <0>;
1707                                         clocks = <&k3_clks 119 3>,      /* icssg0_iep_clk */
1708                                                  <&icssg0_coreclk_mux>; /* core_clk */
1709                                         assigned-clocks = <&icssg0_iepclk_mux>;
1710                                         assigned-clock-parents = <&icssg0_coreclk_mux>;
1711                                 };
1712                         };
1713                 };
1714
1715                 icssg0_mii_rt: mii-rt@32000 {
1716                         compatible = "ti,pruss-mii", "syscon";
1717                         reg = <0x32000 0x100>;
1718                 };
1719
1720                 icssg0_mii_g_rt: mii-g-rt@33000 {
1721                         compatible = "ti,pruss-mii-g", "syscon";
1722                         reg = <0x33000 0x1000>;
1723                 };
1724
1725                 icssg0_intc: interrupt-controller@20000 {
1726                         compatible = "ti,icssg-intc";
1727                         reg = <0x20000 0x2000>;
1728                         interrupt-controller;
1729                         #interrupt-cells = <3>;
1730                         interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1731                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1732                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1733                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1734                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1735                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1736                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1738                         interrupt-names = "host_intr0", "host_intr1",
1739                                           "host_intr2", "host_intr3",
1740                                           "host_intr4", "host_intr5",
1741                                           "host_intr6", "host_intr7";
1742                 };
1743
1744                 pru0_0: pru@34000 {
1745                         compatible = "ti,j721e-pru";
1746                         reg = <0x34000 0x3000>,
1747                               <0x22000 0x100>,
1748                               <0x22400 0x100>;
1749                         reg-names = "iram", "control", "debug";
1750                         firmware-name = "j7-pru0_0-fw";
1751                 };
1752
1753                 rtu0_0: rtu@4000 {
1754                         compatible = "ti,j721e-rtu";
1755                         reg = <0x4000 0x2000>,
1756                               <0x23000 0x100>,
1757                               <0x23400 0x100>;
1758                         reg-names = "iram", "control", "debug";
1759                         firmware-name = "j7-rtu0_0-fw";
1760                 };
1761
1762                 tx_pru0_0: txpru@a000 {
1763                         compatible = "ti,j721e-tx-pru";
1764                         reg = <0xa000 0x1800>,
1765                               <0x25000 0x100>,
1766                               <0x25400 0x100>;
1767                         reg-names = "iram", "control", "debug";
1768                         firmware-name = "j7-txpru0_0-fw";
1769                 };
1770
1771                 pru0_1: pru@38000 {
1772                         compatible = "ti,j721e-pru";
1773                         reg = <0x38000 0x3000>,
1774                               <0x24000 0x100>,
1775                               <0x24400 0x100>;
1776                         reg-names = "iram", "control", "debug";
1777                         firmware-name = "j7-pru0_1-fw";
1778                 };
1779
1780                 rtu0_1: rtu@6000 {
1781                         compatible = "ti,j721e-rtu";
1782                         reg = <0x6000 0x2000>,
1783                               <0x23800 0x100>,
1784                               <0x23c00 0x100>;
1785                         reg-names = "iram", "control", "debug";
1786                         firmware-name = "j7-rtu0_1-fw";
1787                 };
1788
1789                 tx_pru0_1: txpru@c000 {
1790                         compatible = "ti,j721e-tx-pru";
1791                         reg = <0xc000 0x1800>,
1792                               <0x25800 0x100>,
1793                               <0x25c00 0x100>;
1794                         reg-names = "iram", "control", "debug";
1795                         firmware-name = "j7-txpru0_1-fw";
1796                 };
1797         };
1798
1799         icssg1: icssg@b100000 {
1800                 compatible = "ti,j721e-icssg";
1801                 reg = <0x00 0xb100000 0x00 0x80000>;
1802                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
1803                 #address-cells = <1>;
1804                 #size-cells = <1>;
1805                 ranges = <0x0 0x00 0x0b100000 0x100000>;
1806
1807                 icssg1_mem: memories@b100000 {
1808                         reg = <0x0 0x2000>,
1809                               <0x2000 0x2000>,
1810                               <0x10000 0x10000>;
1811                         reg-names = "dram0", "dram1",
1812                                     "shrdram2";
1813                 };
1814
1815                 icssg1_cfg: cfg@26000 {
1816                         compatible = "ti,pruss-cfg", "syscon";
1817                         reg = <0x26000 0x200>;
1818                         #address-cells = <1>;
1819                         #size-cells = <1>;
1820                         ranges = <0x0 0x26000 0x2000>;
1821
1822                         clocks {
1823                                 #address-cells = <1>;
1824                                 #size-cells = <0>;
1825
1826                                 icssg1_coreclk_mux: coreclk-mux@3c {
1827                                         reg = <0x3c>;
1828                                         #clock-cells = <0>;
1829                                         clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
1830                                                  <&k3_clks 120 4>;  /* icssg1_iclk */
1831                                         assigned-clocks = <&icssg1_coreclk_mux>;
1832                                         assigned-clock-parents = <&k3_clks 120 4>;
1833                                 };
1834
1835                                 icssg1_iepclk_mux: iepclk-mux@30 {
1836                                         reg = <0x30>;
1837                                         #clock-cells = <0>;
1838                                         clocks = <&k3_clks 120 9>,      /* icssg1_iep_clk */
1839                                                  <&icssg1_coreclk_mux>; /* core_clk */
1840                                         assigned-clocks = <&icssg1_iepclk_mux>;
1841                                         assigned-clock-parents = <&icssg1_coreclk_mux>;
1842                                 };
1843                         };
1844                 };
1845
1846                 icssg1_mii_rt: mii-rt@32000 {
1847                         compatible = "ti,pruss-mii", "syscon";
1848                         reg = <0x32000 0x100>;
1849                 };
1850
1851                 icssg1_mii_g_rt: mii-g-rt@33000 {
1852                         compatible = "ti,pruss-mii-g", "syscon";
1853                         reg = <0x33000 0x1000>;
1854                 };
1855
1856                 icssg1_intc: interrupt-controller@20000 {
1857                         compatible = "ti,icssg-intc";
1858                         reg = <0x20000 0x2000>;
1859                         interrupt-controller;
1860                         #interrupt-cells = <3>;
1861                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1862                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1863                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1864                                      <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1865                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1866                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1867                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1868                                      <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1869                         interrupt-names = "host_intr0", "host_intr1",
1870                                           "host_intr2", "host_intr3",
1871                                           "host_intr4", "host_intr5",
1872                                           "host_intr6", "host_intr7";
1873                 };
1874
1875                 pru1_0: pru@34000 {
1876                         compatible = "ti,j721e-pru";
1877                         reg = <0x34000 0x4000>,
1878                               <0x22000 0x100>,
1879                               <0x22400 0x100>;
1880                         reg-names = "iram", "control", "debug";
1881                         firmware-name = "j7-pru1_0-fw";
1882                 };
1883
1884                 rtu1_0: rtu@4000 {
1885                         compatible = "ti,j721e-rtu";
1886                         reg = <0x4000 0x2000>,
1887                               <0x23000 0x100>,
1888                               <0x23400 0x100>;
1889                         reg-names = "iram", "control", "debug";
1890                         firmware-name = "j7-rtu1_0-fw";
1891                 };
1892
1893                 tx_pru1_0: txpru@a000 {
1894                         compatible = "ti,j721e-tx-pru";
1895                         reg = <0xa000 0x1800>,
1896                               <0x25000 0x100>,
1897                               <0x25400 0x100>;
1898                         reg-names = "iram", "control", "debug";
1899                         firmware-name = "j7-txpru1_0-fw";
1900                 };
1901
1902                 pru1_1: pru@38000 {
1903                         compatible = "ti,j721e-pru";
1904                         reg = <0x38000 0x4000>,
1905                               <0x24000 0x100>,
1906                               <0x24400 0x100>;
1907                         reg-names = "iram", "control", "debug";
1908                         firmware-name = "j7-pru1_1-fw";
1909                 };
1910
1911                 rtu1_1: rtu@6000 {
1912                         compatible = "ti,j721e-rtu";
1913                         reg = <0x6000 0x2000>,
1914                               <0x23800 0x100>,
1915                               <0x23c00 0x100>;
1916                         reg-names = "iram", "control", "debug";
1917                         firmware-name = "j7-rtu1_1-fw";
1918                 };
1919
1920                 tx_pru1_1: txpru@c000 {
1921                         compatible = "ti,j721e-tx-pru";
1922                         reg = <0xc000 0x1800>,
1923                               <0x25800 0x100>,
1924                               <0x25c00 0x100>;
1925                         reg-names = "iram", "control", "debug";
1926                         firmware-name = "j7-txpru1_1-fw";
1927                 };
1928         };
1929 };