arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu_wakeup {
   9         dmsc: dmsc@44083000 {
  10                 compatible = "ti,k2g-sci";
  11                 ti,host-id = <12>;
  12
  13                 mbox-names = "rx", "tx";
  14
  15                 mboxes= <&secure_proxy_main 11>,
  16                         <&secure_proxy_main 13>;
  17
  18                 reg-names = "debug_messages";
  19                 reg = <0x00 0x44083000 0x00 0x1000>;
  20
  21                 k3_pds: power-controller {
  22                         compatible = "ti,sci-pm-domain";
  23                         #power-domain-cells = <2>;
  24                 };
  25
  26                 k3_clks: clocks {
  27                         compatible = "ti,k2g-sci-clk";
  28                         #clock-cells = <2>;
  29                 };
  30
  31                 k3_reset: reset-controller {
  32                         compatible = "ti,sci-reset";
  33                         #reset-cells = <2>;
  34                 };
  35         };
  36
  37         mcu_conf: syscon@40f00000 {
  38                 compatible = "syscon", "simple-mfd";
  39                 reg = <0x00 0x40f00000 0x00 0x20000>;
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 ranges = <0x00 0x00 0x40f00000 0x20000>;
  43
  44                 phy_gmii_sel: phy@4040 {
  45                         compatible = "ti,am654-phy-gmii-sel";
  46                         reg = <0x4040 0x4>;
  47                         #phy-cells = <1>;
  48                 };
  49         };
  50
  51         chipid@43000014 {
  52                 compatible = "ti,am654-chipid";
  53                 reg = <0x00 0x43000014 0x00 0x4>;
  54         };
  55
  56         wkup_pmx0: pinctrl@4301c000 {
  57                 compatible = "pinctrl-single";
  58                 /* Proxy 0 addressing */
  59                 reg = <0x00 0x4301c000 0x00 0x178>;
  60                 #pinctrl-cells = <1>;
  61                 pinctrl-single,register-width = <32>;
  62                 pinctrl-single,function-mask = <0xffffffff>;
  63         };
  64
  65         mcu_ram: sram@41c00000 {
  66                 compatible = "mmio-sram";
  67                 reg = <0x00 0x41c00000 0x00 0x100000>;
  68                 ranges = <0x00 0x00 0x41c00000 0x100000>;
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71         };
  72
  73         wkup_uart0: serial@42300000 {
  74                 compatible = "ti,j721e-uart", "ti,am654-uart";
  75                 reg = <0x00 0x42300000 0x00 0x100>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <4>;
  78                 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
  79                 clock-frequency = <48000000>;
  80                 current-speed = <115200>;
  81                 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
  82                 clocks = <&k3_clks 287 2>;
  83                 clock-names = "fclk";
  84         };
  85
  86         mcu_uart0: serial@40a00000 {
  87                 compatible = "ti,j721e-uart", "ti,am654-uart";
  88                 reg = <0x00 0x40a00000 0x00 0x100>;
  89                 reg-shift = <2>;
  90                 reg-io-width = <4>;
  91                 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
  92                 clock-frequency = <96000000>;
  93                 current-speed = <115200>;
  94                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  95                 clocks = <&k3_clks 149 2>;
  96                 clock-names = "fclk";
  97         };
  98
  99         wkup_gpio_intr: interrupt-controller2 {
 100                 compatible = "ti,sci-intr";
 101                 ti,intr-trigger-type = <1>;
 102                 interrupt-controller;
 103                 interrupt-parent = <&gic500>;
 104                 #interrupt-cells = <1>;
 105                 ti,sci = <&dmsc>;
 106                 ti,sci-dev-id = <137>;
 107                 ti,interrupt-ranges = <16 960 16>;
 108         };
 109
 110         wkup_gpio0: gpio@42110000 {
 111                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 112                 reg = <0x00 0x42110000 0x00 0x100>;
 113                 gpio-controller;
 114                 #gpio-cells = <2>;
 115                 interrupt-parent = <&wkup_gpio_intr>;
 116                 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
 117                 interrupt-controller;
 118                 #interrupt-cells = <2>;
 119                 #address-cells = <0>;
 120                 ti,ngpio = <85>;
 121                 ti,davinci-gpio-unbanked = <0>;
 122                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 123                 clocks = <&k3_clks 113 0>;
 124                 clock-names = "gpio";
 125         };
 126
 127         wkup_gpio1: gpio@42100000 {
 128                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 129                 reg = <0x00 0x42100000 0x00 0x100>;
 130                 gpio-controller;
 131                 #gpio-cells = <2>;
 132                 interrupt-parent = <&wkup_gpio_intr>;
 133                 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
 134                 interrupt-controller;
 135                 #interrupt-cells = <2>;
 136                 #address-cells = <0>;
 137                 ti,ngpio = <85>;
 138                 ti,davinci-gpio-unbanked = <0>;
 139                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 140                 clocks = <&k3_clks 114 0>;
 141                 clock-names = "gpio";
 142         };
 143
 144         mcu_navss: bus@28380000 {
 145                 compatible = "simple-mfd";
 146                 #address-cells = <2>;
 147                 #size-cells = <2>;
 148                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
 149                 dma-coherent;
 150                 dma-ranges;
 151                 ti,sci-dev-id = <232>;
 152
 153                 mcu_ringacc: ringacc@2b800000 {
 154                         compatible = "ti,am654-navss-ringacc";
 155                         reg =   <0x00 0x2b800000 0x00 0x400000>,
 156                                 <0x00 0x2b000000 0x00 0x400000>,
 157                                 <0x00 0x28590000 0x00 0x100>,
 158                                 <0x00 0x2a500000 0x00 0x40000>;
 159                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 160                         ti,num-rings = <286>;
 161                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 162                         ti,sci = <&dmsc>;
 163                         ti,sci-dev-id = <235>;
 164                         msi-parent = <&main_udmass_inta>;
 165                 };
 166
 167                 mcu_udmap: dma-controller@285c0000 {
 168                         compatible = "ti,j721e-navss-mcu-udmap";
 169                         reg =   <0x00 0x285c0000 0x00 0x100>,
 170                                 <0x00 0x2a800000 0x00 0x40000>,
 171                                 <0x00 0x2aa00000 0x00 0x40000>;
 172                         reg-names = "gcfg", "rchanrt", "tchanrt";
 173                         msi-parent = <&main_udmass_inta>;
 174                         #dma-cells = <1>;
 175
 176                         ti,sci = <&dmsc>;
 177                         ti,sci-dev-id = <236>;
 178                         ti,ringacc = <&mcu_ringacc>;
 179
 180                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 181                                                 <0x0f>; /* TX_HCHAN */
 182                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 183                                                 <0x0b>; /* RX_HCHAN */
 184                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 185                 };
 186         };
 187
 188         mcu_cpsw: ethernet@46000000 {
 189                 compatible = "ti,j721e-cpsw-nuss";
 190                 #address-cells = <2>;
 191                 #size-cells = <2>;
 192                 reg = <0x00 0x46000000 0x00 0x200000>;
 193                 reg-names = "cpsw_nuss";
 194                 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
 195                 dma-coherent;
 196                 clocks = <&k3_clks 18 21>;
 197                 clock-names = "fck";
 198                 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
 199
 200                 dmas = <&mcu_udmap 0xf000>,
 201                        <&mcu_udmap 0xf001>,
 202                        <&mcu_udmap 0xf002>,
 203                        <&mcu_udmap 0xf003>,
 204                        <&mcu_udmap 0xf004>,
 205                        <&mcu_udmap 0xf005>,
 206                        <&mcu_udmap 0xf006>,
 207                        <&mcu_udmap 0xf007>,
 208                        <&mcu_udmap 0x7000>;
 209                 dma-names = "tx0", "tx1", "tx2", "tx3",
 210                             "tx4", "tx5", "tx6", "tx7",
 211                             "rx";
 212
 213                 ethernet-ports {
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216
 217                         cpsw_port1: port@1 {
 218                                 reg = <1>;
 219                                 ti,mac-only;
 220                                 label = "port1";
 221                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 222                                 phys = <&phy_gmii_sel 1>;
 223                         };
 224                 };
 225
 226                 davinci_mdio: mdio@f00 {
 227                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 228                         reg = <0x00 0xf00 0x00 0x100>;
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         clocks = <&k3_clks 18 21>;
 232                         clock-names = "fck";
 233                         bus_freq = <1000000>;
 234                 };
 235
 236                 cpts@3d000 {
 237                         compatible = "ti,am65-cpts";
 238                         reg = <0x00 0x3d000 0x00 0x400>;
 239                         clocks = <&k3_clks 18 2>;
 240                         clock-names = "cpts";
 241                         interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 242                         interrupt-names = "cpts";
 243                         ti,cpts-ext-ts-inputs = <4>;
 244                         ti,cpts-periodic-outputs = <2>;
 245                 };
 246         };
 247
 248         mcu_i2c0: i2c@40b00000 {
 249                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 250                 reg = <0x00 0x40b00000 0x00 0x100>;
 251                 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254                 clock-names = "fck";
 255                 clocks = <&k3_clks 194 1>;
 256                 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
 257         };
 258
 259         mcu_i2c1: i2c@40b10000 {
 260                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 261                 reg = <0x00 0x40b10000 0x00 0x100>;
 262                 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 clock-names = "fck";
 266                 clocks = <&k3_clks 195 1>;
 267                 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
 268         };
 269
 270         wkup_i2c0: i2c@42120000 {
 271                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 272                 reg = <0x00 0x42120000 0x00 0x100>;
 273                 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 clock-names = "fck";
 277                 clocks = <&k3_clks 197 1>;
 278                 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
 279         };
 280
 281         fss: syscon@47000000 {
 282                 compatible = "syscon", "simple-mfd";
 283                 reg = <0x00 0x47000000 0x00 0x100>;
 284                 #address-cells = <2>;
 285                 #size-cells = <2>;
 286                 ranges;
 287
 288                 hbmc_mux: hbmc-mux {
 289                         compatible = "mmio-mux";
 290                         #mux-control-cells = <1>;
 291                         mux-reg-masks = <0x4 0x2>; /* HBMC select */
 292                 };
 293
 294                 hbmc: hyperbus@47034000 {
 295                         compatible = "ti,am654-hbmc";
 296                         reg = <0x00 0x47034000 0x00 0x100>,
 297                                 <0x05 0x00000000 0x01 0x0000000>;
 298                         power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 299                         clocks = <&k3_clks 102 0>;
 300                         assigned-clocks = <&k3_clks 102 5>;
 301                         assigned-clock-rates = <333333333>;
 302                         #address-cells = <2>;
 303                         #size-cells = <1>;
 304                         mux-controls = <&hbmc_mux 0>;
 305                 };
 306
 307                 ospi0: spi@47040000 {
 308                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 309                         reg = <0x0 0x47040000 0x0 0x100>,
 310                               <0x5 0x00000000 0x1 0x0000000>;
 311                         interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
 312                         cdns,fifo-depth = <256>;
 313                         cdns,fifo-width = <4>;
 314                         cdns,trigger-address = <0x0>;
 315                         clocks = <&k3_clks 103 0>;
 316                         assigned-clocks = <&k3_clks 103 0>;
 317                         assigned-clock-parents = <&k3_clks 103 2>;
 318                         assigned-clock-rates = <166666666>;
 319                         power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                 };
 323         };
 324
 325         tscadc0: tscadc@40200000 {
 326                 compatible = "ti,am3359-tscadc";
 327                 reg = <0x00 0x40200000 0x00 0x1000>;
 328                 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
 329                 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
 330                 clocks = <&k3_clks 0 1>;
 331                 assigned-clocks = <&k3_clks 0 3>;
 332                 assigned-clock-rates = <60000000>;
 333                 clock-names = "adc_tsc_fck";
 334                 dmas = <&main_udmap 0x7400>,
 335                         <&main_udmap 0x7401>;
 336                 dma-names = "fifo0", "fifo1";
 337
 338                 adc {
 339                         #io-channel-cells = <1>;
 340                         compatible = "ti,am3359-adc";
 341                 };
 342         };
 343
 344         mcu_r5fss0: r5fss@41000000 {
 345                 compatible = "ti,j7200-r5fss";
 346                 ti,cluster-mode = <1>;
 347                 #address-cells = <1>;
 348                 #size-cells = <1>;
 349                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 350                          <0x41400000 0x00 0x41400000 0x20000>;
 351                 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
 352
 353                 mcu_r5fss0_core0: r5f@41000000 {
 354                         compatible = "ti,j7200-r5f";
 355                         reg = <0x41000000 0x00010000>,
 356                               <0x41010000 0x00010000>;
 357                         reg-names = "atcm", "btcm";
 358                         ti,sci = <&dmsc>;
 359                         ti,sci-dev-id = <250>;
 360                         ti,sci-proc-ids = <0x01 0xff>;
 361                         resets = <&k3_reset 250 1>;
 362                         firmware-name = "j7200-mcu-r5f0_0-fw";
 363                         ti,atcm-enable = <1>;
 364                         ti,btcm-enable = <1>;
 365                         ti,loczrama = <1>;
 366                 };
 367
 368                 mcu_r5fss0_core1: r5f@41400000 {
 369                         compatible = "ti,j7200-r5f";
 370                         reg = <0x41400000 0x00008000>,
 371                               <0x41410000 0x00008000>;
 372                         reg-names = "atcm", "btcm";
 373                         ti,sci = <&dmsc>;
 374                         ti,sci-dev-id = <251>;
 375                         ti,sci-proc-ids = <0x02 0xff>;
 376                         resets = <&k3_reset 251 1>;
 377                         firmware-name = "j7200-mcu-r5f0_1-fw";
 378                         ti,atcm-enable = <1>;
 379                         ti,btcm-enable = <1>;
 380                         ti,loczrama = <1>;
 381                 };
 382         };
 383 };