arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family MCU Domain peripherals
   4  *
   5  * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu {
   9         mcu_conf: scm-conf@40f00000 {
  10                 compatible = "syscon", "simple-mfd";
  11                 reg = <0x0 0x40f00000 0x0 0x20000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x0 0x40f00000 0x20000>;
  15
  16                 phy_gmii_sel: phy@4040 {
  17                         compatible = "ti,am654-phy-gmii-sel";
  18                         reg = <0x4040 0x4>;
  19                         #phy-cells = <1>;
  20                 };
  21         };
  22
  23         mcu_uart0: serial@40a00000 {
  24                 compatible = "ti,am654-uart";
  25                         reg = <0x00 0x40a00000 0x00 0x100>;
  26                         reg-shift = <2>;
  27                         reg-io-width = <4>;
  28                         interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
  29                         clock-frequency = <96000000>;
  30                         current-speed = <115200>;
  31                         power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  32         };
  33
  34         mcu_ram: sram@41c00000 {
  35                 compatible = "mmio-sram";
  36                 reg = <0x00 0x41c00000 0x00 0x80000>;
  37                 ranges = <0x0 0x00 0x41c00000 0x80000>;
  38                 #address-cells = <1>;
  39                 #size-cells = <1>;
  40         };
  41
  42         mcu_i2c0: i2c@40b00000 {
  43                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
  44                 reg = <0x0 0x40b00000 0x0 0x100>;
  45                 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 clock-names = "fck";
  49                 clocks = <&k3_clks 114 1>;
  50                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
  51         };
  52
  53         mcu_spi0: spi@40300000 {
  54                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  55                 reg = <0x0 0x40300000 0x0 0x400>;
  56                 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
  57                 clocks = <&k3_clks 142 1>;
  58                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61         };
  62
  63         mcu_spi1: spi@40310000 {
  64                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  65                 reg = <0x0 0x40310000 0x0 0x400>;
  66                 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
  67                 clocks = <&k3_clks 143 1>;
  68                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71         };
  72
  73         mcu_spi2: spi@40320000 {
  74                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  75                 reg = <0x0 0x40320000 0x0 0x400>;
  76                 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&k3_clks 144 1>;
  78                 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81         };
  82
  83         tscadc0: tscadc@40200000 {
  84                 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
  85                 reg = <0x0 0x40200000 0x0 0x1000>;
  86                 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
  87                 clocks = <&k3_clks 0 2>;
  88                 assigned-clocks = <&k3_clks 0 2>;
  89                 assigned-clock-rates = <60000000>;
  90                 clock-names = "adc_tsc_fck";
  91                 dmas = <&mcu_udmap 0x7100>,
  92                         <&mcu_udmap 0x7101 >;
  93                 dma-names = "fifo0", "fifo1";
  94
  95                 adc {
  96                         #io-channel-cells = <1>;
  97                         compatible = "ti,am654-adc", "ti,am3359-adc";
  98                 };
  99         };
 100
 101         tscadc1: tscadc@40210000 {
 102                 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
 103                 reg = <0x0 0x40210000 0x0 0x1000>;
 104                 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
 105                 clocks = <&k3_clks 1 2>;
 106                 assigned-clocks = <&k3_clks 1 2>;
 107                 assigned-clock-rates = <60000000>;
 108                 clock-names = "adc_tsc_fck";
 109                 dmas = <&mcu_udmap 0x7102>,
 110                         <&mcu_udmap 0x7103>;
 111                 dma-names = "fifo0", "fifo1";
 112
 113                 adc {
 114                         #io-channel-cells = <1>;
 115                         compatible = "ti,am654-adc", "ti,am3359-adc";
 116                 };
 117         };
 118
 119         mcu-navss {
 120                 compatible = "simple-mfd";
 121                 #address-cells = <2>;
 122                 #size-cells = <2>;
 123                 ranges;
 124                 dma-coherent;
 125                 dma-ranges;
 126
 127                 ti,sci-dev-id = <119>;
 128
 129                 mcu_ringacc: ringacc@2b800000 {
 130                         compatible = "ti,am654-navss-ringacc";
 131                         reg =   <0x0 0x2b800000 0x0 0x400000>,
 132                                 <0x0 0x2b000000 0x0 0x400000>,
 133                                 <0x0 0x28590000 0x0 0x100>,
 134                                 <0x0 0x2a500000 0x0 0x40000>;
 135                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 136                         ti,num-rings = <286>;
 137                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 138                         ti,sci = <&dmsc>;
 139                         ti,sci-dev-id = <195>;
 140                         msi-parent = <&inta_main_udmass>;
 141                 };
 142
 143                 mcu_udmap: dma-controller@285c0000 {
 144                         compatible = "ti,am654-navss-mcu-udmap";
 145                         reg =   <0x0 0x285c0000 0x0 0x100>,
 146                                 <0x0 0x2a800000 0x0 0x40000>,
 147                                 <0x0 0x2aa00000 0x0 0x40000>;
 148                         reg-names = "gcfg", "rchanrt", "tchanrt";
 149                         msi-parent = <&inta_main_udmass>;
 150                         #dma-cells = <1>;
 151
 152                         ti,sci = <&dmsc>;
 153                         ti,sci-dev-id = <194>;
 154                         ti,ringacc = <&mcu_ringacc>;
 155
 156                         ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
 157                                                 <0xd>; /* TX_CHAN */
 158                         ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
 159                                                 <0xa>; /* RX_CHAN */
 160                         ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
 161                 };
 162         };
 163
 164         fss: fss@47000000 {
 165                 compatible = "simple-bus";
 166                 #address-cells = <2>;
 167                 #size-cells = <2>;
 168                 ranges;
 169
 170                 ospi0: spi@47040000 {
 171                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 172                         reg = <0x0 0x47040000 0x0 0x100>,
 173                                 <0x5 0x00000000 0x1 0x0000000>;
 174                         interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
 175                         cdns,fifo-depth = <256>;
 176                         cdns,fifo-width = <4>;
 177                         cdns,trigger-address = <0x0>;
 178                         clocks = <&k3_clks 248 0>;
 179                         assigned-clocks = <&k3_clks 248 0>;
 180                         assigned-clock-parents = <&k3_clks 248 2>;
 181                         assigned-clock-rates = <166666666>;
 182                         power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                 };
 186
 187                 ospi1: spi@47050000 {
 188                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 189                         reg = <0x0 0x47050000 0x0 0x100>,
 190                                 <0x7 0x00000000 0x1 0x00000000>;
 191                         interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
 192                         cdns,fifo-depth = <256>;
 193                         cdns,fifo-width = <4>;
 194                         cdns,trigger-address = <0x0>;
 195                         clocks = <&k3_clks 249 6>;
 196                         power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                 };
 200         };
 201
 202         mcu_cpsw: ethernet@46000000 {
 203                 compatible = "ti,am654-cpsw-nuss";
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 reg = <0x0 0x46000000 0x0 0x200000>;
 207                 reg-names = "cpsw_nuss";
 208                 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
 209                 dma-coherent;
 210                 clocks = <&k3_clks 5 10>;
 211                 clock-names = "fck";
 212                 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
 213
 214                 dmas = <&mcu_udmap 0xf000>,
 215                        <&mcu_udmap 0xf001>,
 216                        <&mcu_udmap 0xf002>,
 217                        <&mcu_udmap 0xf003>,
 218                        <&mcu_udmap 0xf004>,
 219                        <&mcu_udmap 0xf005>,
 220                        <&mcu_udmap 0xf006>,
 221                        <&mcu_udmap 0xf007>,
 222                        <&mcu_udmap 0x7000>;
 223                 dma-names = "tx0", "tx1", "tx2", "tx3",
 224                             "tx4", "tx5", "tx6", "tx7",
 225                             "rx";
 226
 227                 ethernet-ports {
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230
 231                         cpsw_port1: port@1 {
 232                                 reg = <1>;
 233                                 ti,mac-only;
 234                                 label = "port1";
 235                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 236                                 phys = <&phy_gmii_sel 1>;
 237                         };
 238                 };
 239
 240                 davinci_mdio: mdio@f00 {
 241                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 242                         reg = <0x0 0xf00 0x0 0x100>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         clocks = <&k3_clks 5 10>;
 246                         clock-names = "fck";
 247                         bus_freq = <1000000>;
 248                 };
 249
 250                 cpts@3d000 {
 251                         compatible = "ti,am65-cpts";
 252                         reg = <0x0 0x3d000 0x0 0x400>;
 253                         clocks = <&mcu_cpsw_cpts_mux>;
 254                         clock-names = "cpts";
 255                         interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
 256                         interrupt-names = "cpts";
 257                         ti,cpts-ext-ts-inputs = <4>;
 258                         ti,cpts-periodic-outputs = <2>;
 259
 260                         mcu_cpsw_cpts_mux: refclk-mux {
 261                                 #clock-cells = <0>;
 262                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
 263                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
 264                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
 265                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
 266                                 assigned-clocks = <&mcu_cpsw_cpts_mux>;
 267                                 assigned-clock-parents = <&k3_clks 118 5>;
 268                         };
 269                 };
 270         };
 271
 272         mcu_r5fss0: r5fss@41000000 {
 273                 compatible = "ti,am654-r5fss";
 274                 ti,cluster-mode = <1>;
 275                 #address-cells = <1>;
 276                 #size-cells = <1>;
 277                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 278                          <0x41400000 0x00 0x41400000 0x20000>;
 279                 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
 280
 281                 mcu_r5fss0_core0: r5f@41000000 {
 282                         compatible = "ti,am654-r5f";
 283                         reg = <0x41000000 0x00008000>,
 284                               <0x41010000 0x00008000>;
 285                         reg-names = "atcm", "btcm";
 286                         ti,sci = <&dmsc>;
 287                         ti,sci-dev-id = <159>;
 288                         ti,sci-proc-ids = <0x01 0xff>;
 289                         resets = <&k3_reset 159 1>;
 290                         firmware-name = "am65x-mcu-r5f0_0-fw";
 291                         ti,atcm-enable = <1>;
 292                         ti,btcm-enable = <1>;
 293                         ti,loczrama = <1>;
 294                 };
 295
 296                 mcu_r5fss0_core1: r5f@41400000 {
 297                         compatible = "ti,am654-r5f";
 298                         reg = <0x41400000 0x00008000>,
 299                               <0x41410000 0x00008000>;
 300                         reg-names = "atcm", "btcm";
 301                         ti,sci = <&dmsc>;
 302                         ti,sci-dev-id = <245>;
 303                         ti,sci-proc-ids = <0x02 0xff>;
 304                         resets = <&k3_reset 245 1>;
 305                         firmware-name = "am65x-mcu-r5f0_1-fw";
 306                         ti,atcm-enable = <1>;
 307                         ti,btcm-enable = <1>;
 308                         ti,loczrama = <1>;
 309                 };
 310         };
 311
 312         mcu_rti1: watchdog@40610000 {
 313                 compatible = "ti,j7-rti-wdt";
 314                 reg = <0x0 0x40610000 0x0 0x100>;
 315                 clocks = <&k3_clks 135 0>;
 316                 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
 317                 assigned-clocks = <&k3_clks 135 0>;
 318                 assigned-clock-parents = <&k3_clks 135 4>;
 319         };
 320 };