arch/arm64/boot/dts/ti/k3-am65-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy-am654-serdes.h>
   8
   9 &cbass_main {
  10         msmc_ram: sram@70000000 {
  11                 compatible = "mmio-sram";
  12                 reg = <0x0 0x70000000 0x0 0x200000>;
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges = <0x0 0x0 0x70000000 0x200000>;
  16
  17                 atf-sram@0 {
  18                         reg = <0x0 0x20000>;
  19                 };
  20
  21                 sysfw-sram@f0000 {
  22                         reg = <0xf0000 0x10000>;
  23                 };
  24
  25                 l3cache-sram@100000 {
  26                         reg = <0x100000 0x100000>;
  27                 };
  28         };
  29
  30         gic500: interrupt-controller@1800000 {
  31                 compatible = "arm,gic-v3";
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  38                       <0x00 0x01880000 0x00 0x90000>;   /* GICR */
  39                 /*
  40                  * vcpumntirq:
  41                  * virtual CPU interface maintenance interrupt
  42                  */
  43                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  44
  45                 gic_its: msi-controller@1820000 {
  46                         compatible = "arm,gic-v3-its";
  47                         reg = <0x00 0x01820000 0x00 0x10000>;
  48                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  49                         msi-controller;
  50                         #msi-cells = <1>;
  51                 };
  52         };
  53
  54         serdes0: serdes@900000 {
  55                 compatible = "ti,phy-am654-serdes";
  56                 reg = <0x0 0x900000 0x0 0x2000>;
  57                 reg-names = "serdes";
  58                 #phy-cells = <2>;
  59                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
  60                 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
  61                 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
  62                 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
  63                 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
  64                 ti,serdes-clk = <&serdes0_clk>;
  65                 #clock-cells = <1>;
  66                 mux-controls = <&serdes_mux 0>;
  67         };
  68
  69         serdes1: serdes@910000 {
  70                 compatible = "ti,phy-am654-serdes";
  71                 reg = <0x0 0x910000 0x0 0x2000>;
  72                 reg-names = "serdes";
  73                 #phy-cells = <2>;
  74                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
  75                 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
  76                 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
  77                 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
  78                 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
  79                 ti,serdes-clk = <&serdes1_clk>;
  80                 #clock-cells = <1>;
  81                 mux-controls = <&serdes_mux 1>;
  82         };
  83
  84         main_uart0: serial@2800000 {
  85                 compatible = "ti,am654-uart";
  86                 reg = <0x00 0x02800000 0x00 0x100>;
  87                 reg-shift = <2>;
  88                 reg-io-width = <4>;
  89                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  90                 clock-frequency = <48000000>;
  91                 current-speed = <115200>;
  92                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  93         };
  94
  95         main_uart1: serial@2810000 {
  96                 compatible = "ti,am654-uart";
  97                 reg = <0x00 0x02810000 0x00 0x100>;
  98                 reg-shift = <2>;
  99                 reg-io-width = <4>;
 100                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 101                 clock-frequency = <48000000>;
 102                 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
 103         };
 104
 105         main_uart2: serial@2820000 {
 106                 compatible = "ti,am654-uart";
 107                 reg = <0x00 0x02820000 0x00 0x100>;
 108                 reg-shift = <2>;
 109                 reg-io-width = <4>;
 110                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 111                 clock-frequency = <48000000>;
 112                 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 113         };
 114
 115         crypto: crypto@4e00000 {
 116                 compatible = "ti,am654-sa2ul";
 117                 reg = <0x0 0x4e00000 0x0 0x1200>;
 118                 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
 119                 #address-cells = <2>;
 120                 #size-cells = <2>;
 121                 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
 122                 status = "okay";
 123
 124                 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
 125                                 <&main_udmap 0x4001>;
 126                 dma-names = "tx", "rx1", "rx2";
 127                 dma-coherent;
 128
 129                 rng: rng@4e10000 {
 130                         compatible = "inside-secure,safexcel-eip76";
 131                         reg = <0x0 0x4e10000 0x0 0x7d>;
 132                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 133                         clocks = <&k3_clks 136 1>;
 134                 };
 135         };
 136
 137         main_pmx0: pinmux@11c000 {
 138                 compatible = "pinctrl-single";
 139                 reg = <0x0 0x11c000 0x0 0x2e4>;
 140                 #pinctrl-cells = <1>;
 141                 pinctrl-single,register-width = <32>;
 142                 pinctrl-single,function-mask = <0xffffffff>;
 143         };
 144
 145         main_pmx1: pinmux@11c2e8 {
 146                 compatible = "pinctrl-single";
 147                 reg = <0x0 0x11c2e8 0x0 0x24>;
 148                 #pinctrl-cells = <1>;
 149                 pinctrl-single,register-width = <32>;
 150                 pinctrl-single,function-mask = <0xffffffff>;
 151         };
 152
 153         main_i2c0: i2c@2000000 {
 154                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 155                 reg = <0x0 0x2000000 0x0 0x100>;
 156                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 clock-names = "fck";
 160                 clocks = <&k3_clks 110 1>;
 161                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 162         };
 163
 164         main_i2c1: i2c@2010000 {
 165                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 166                 reg = <0x0 0x2010000 0x0 0x100>;
 167                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 clock-names = "fck";
 171                 clocks = <&k3_clks 111 1>;
 172                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 173         };
 174
 175         main_i2c2: i2c@2020000 {
 176                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 177                 reg = <0x0 0x2020000 0x0 0x100>;
 178                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181                 clock-names = "fck";
 182                 clocks = <&k3_clks 112 1>;
 183                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 184         };
 185
 186         main_i2c3: i2c@2030000 {
 187                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 188                 reg = <0x0 0x2030000 0x0 0x100>;
 189                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 clock-names = "fck";
 193                 clocks = <&k3_clks 113 1>;
 194                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 195         };
 196
 197         ecap0: pwm@3100000 {
 198                 compatible = "ti,am654-ecap", "ti,am3352-ecap";
 199                 #pwm-cells = <3>;
 200                 reg = <0x0 0x03100000 0x0 0x60>;
 201                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 202                 clocks = <&k3_clks 39 0>;
 203                 clock-names = "fck";
 204         };
 205
 206         main_spi0: spi@2100000 {
 207                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 208                 reg = <0x0 0x2100000 0x0 0x400>;
 209                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 210                 clocks = <&k3_clks 137 1>;
 211                 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
 215                 dma-names = "tx0", "rx0";
 216         };
 217
 218         main_spi1: spi@2110000 {
 219                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 220                 reg = <0x0 0x2110000 0x0 0x400>;
 221                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&k3_clks 138 1>;
 223                 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226                 assigned-clocks = <&k3_clks 137 1>;
 227                 assigned-clock-rates = <48000000>;
 228         };
 229
 230         main_spi2: spi@2120000 {
 231                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 232                 reg = <0x0 0x2120000 0x0 0x400>;
 233                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&k3_clks 139 1>;
 235                 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238         };
 239
 240         main_spi3: spi@2130000 {
 241                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 242                 reg = <0x0 0x2130000 0x0 0x400>;
 243                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 244                 clocks = <&k3_clks 140 1>;
 245                 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
 246                 #address-cells = <1>;
 247                 #size-cells = <0>;
 248         };
 249
 250         main_spi4: spi@2140000 {
 251                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 252                 reg = <0x0 0x2140000 0x0 0x400>;
 253                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&k3_clks 141 1>;
 255                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258         };
 259
 260         sdhci0: sdhci@4f80000 {
 261                 compatible = "ti,am654-sdhci-5.1";
 262                 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
 263                 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
 264                 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
 265                 clock-names = "clk_ahb", "clk_xin";
 266                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 267                 mmc-ddr-1_8v;
 268                 mmc-hs200-1_8v;
 269                 ti,otap-del-sel-legacy = <0x0>;
 270                 ti,otap-del-sel-mmc-hs = <0x0>;
 271                 ti,otap-del-sel-sd-hs = <0x0>;
 272                 ti,otap-del-sel-sdr12 = <0x0>;
 273                 ti,otap-del-sel-sdr25 = <0x0>;
 274                 ti,otap-del-sel-sdr50 = <0x8>;
 275                 ti,otap-del-sel-sdr104 = <0x7>;
 276                 ti,otap-del-sel-ddr50 = <0x5>;
 277                 ti,otap-del-sel-ddr52 = <0x5>;
 278                 ti,otap-del-sel-hs200 = <0x5>;
 279                 ti,otap-del-sel-hs400 = <0x0>;
 280                 ti,trm-icp = <0x8>;
 281                 dma-coherent;
 282         };
 283
 284         sdhci1: sdhci@4fa0000 {
 285                 compatible = "ti,am654-sdhci-5.1";
 286                 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
 287                 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
 288                 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
 289                 clock-names = "clk_ahb", "clk_xin";
 290                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 291                 ti,otap-del-sel-legacy = <0x0>;
 292                 ti,otap-del-sel-mmc-hs = <0x0>;
 293                 ti,otap-del-sel-sd-hs = <0x0>;
 294                 ti,otap-del-sel-sdr12 = <0x0>;
 295                 ti,otap-del-sel-sdr25 = <0x0>;
 296                 ti,otap-del-sel-sdr50 = <0x8>;
 297                 ti,otap-del-sel-sdr104 = <0x7>;
 298                 ti,otap-del-sel-ddr50 = <0x4>;
 299                 ti,otap-del-sel-ddr52 = <0x4>;
 300                 ti,otap-del-sel-hs200 = <0x7>;
 301                 ti,clkbuf-sel = <0x7>;
 302                 ti,otap-del-sel = <0x2>;
 303                 ti,trm-icp = <0x8>;
 304                 dma-coherent;
 305                 no-1-8-v;
 306         };
 307
 308         scm_conf: scm_conf@100000 {
 309                 compatible = "syscon", "simple-mfd";
 310                 reg = <0 0x00100000 0 0x1c000>;
 311                 #address-cells = <1>;
 312                 #size-cells = <1>;
 313                 ranges = <0x0 0x0 0x00100000 0x1c000>;
 314
 315                 pcie0_mode: pcie-mode@4060 {
 316                         compatible = "syscon";
 317                         reg = <0x00004060 0x4>;
 318                 };
 319
 320                 pcie1_mode: pcie-mode@4070 {
 321                         compatible = "syscon";
 322                         reg = <0x00004070 0x4>;
 323                 };
 324
 325                 pcie_devid: pcie-devid@210 {
 326                         compatible = "syscon";
 327                         reg = <0x00000210 0x4>;
 328                 };
 329
 330                 serdes0_clk: serdes_clk@4080 {
 331                         compatible = "syscon";
 332                         reg = <0x00004080 0x4>;
 333                 };
 334
 335                 serdes1_clk: serdes_clk@4090 {
 336                         compatible = "syscon";
 337                         reg = <0x00004090 0x4>;
 338                 };
 339
 340                 serdes_mux: mux-controller {
 341                         compatible = "mmio-mux";
 342                         #mux-control-cells = <1>;
 343                         mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
 344                                         <0x4090 0x3>; /* SERDES1 lane select */
 345                 };
 346
 347                 dss_oldi_io_ctrl: dss_oldi_io_ctrl@41e0 {
 348                         compatible = "syscon";
 349                         reg = <0x0000041e0 0x14>;
 350                 };
 351
 352                 ehrpwm_tbclk: syscon@4140 {
 353                         compatible = "ti,am654-ehrpwm-tbclk", "syscon";
 354                         reg = <0x4140 0x18>;
 355                         #clock-cells = <1>;
 356                 };
 357         };
 358
 359         dwc3_0: dwc3@4000000 {
 360                 compatible = "ti,am654-dwc3";
 361                 reg = <0x0 0x4000000 0x0 0x4000>;
 362                 #address-cells = <1>;
 363                 #size-cells = <1>;
 364                 ranges = <0x0 0x0 0x4000000 0x20000>;
 365                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 366                 dma-coherent;
 367                 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
 368                 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 369                 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 370                 assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 371                                          <&k3_clks 151 9>;      /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
 372
 373                 usb0: usb@10000 {
 374                         compatible = "snps,dwc3";
 375                         reg = <0x10000 0x10000>;
 376                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 377                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 378                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 379                         interrupt-names = "peripheral",
 380                                           "host",
 381                                           "otg";
 382                         maximum-speed = "high-speed";
 383                         dr_mode = "otg";
 384                         phys = <&usb0_phy>;
 385                         phy-names = "usb2-phy";
 386                         snps,dis_u3_susphy_quirk;
 387                 };
 388         };
 389
 390         usb0_phy: phy@4100000 {
 391                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 392                 reg = <0x0 0x4100000 0x0 0x54>;
 393                 syscon-phy-power = <&scm_conf 0x4000>;
 394                 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
 395                 clock-names = "wkupclk", "refclk";
 396                 #phy-cells = <0>;
 397         };
 398
 399         dwc3_1: dwc3@4020000 {
 400                 compatible = "ti,am654-dwc3";
 401                 reg = <0x0 0x4020000 0x0 0x4000>;
 402                 #address-cells = <1>;
 403                 #size-cells = <1>;
 404                 ranges = <0x0 0x0 0x4020000 0x20000>;
 405                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 406                 dma-coherent;
 407                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 408                 clocks = <&k3_clks 152 2>;
 409                 assigned-clocks = <&k3_clks 152 2>;
 410                 assigned-clock-parents = <&k3_clks 152 4>;      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 411
 412                 usb1: usb@10000 {
 413                         compatible = "snps,dwc3";
 414                         reg = <0x10000 0x10000>;
 415                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 416                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 417                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 418                         interrupt-names = "peripheral",
 419                                           "host",
 420                                           "otg";
 421                         maximum-speed = "high-speed";
 422                         dr_mode = "otg";
 423                         phys = <&usb1_phy>;
 424                         phy-names = "usb2-phy";
 425                 };
 426         };
 427
 428         usb1_phy: phy@4110000 {
 429                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 430                 reg = <0x0 0x4110000 0x0 0x54>;
 431                 syscon-phy-power = <&scm_conf 0x4020>;
 432                 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
 433                 clock-names = "wkupclk", "refclk";
 434                 #phy-cells = <0>;
 435         };
 436
 437         intr_main_gpio: interrupt-controller0 {
 438                 compatible = "ti,sci-intr";
 439                 ti,intr-trigger-type = <1>;
 440                 interrupt-controller;
 441                 interrupt-parent = <&gic500>;
 442                 #interrupt-cells = <1>;
 443                 ti,sci = <&dmsc>;
 444                 ti,sci-dev-id = <100>;
 445                 ti,interrupt-ranges = <0 392 32>;
 446         };
 447
 448         main_navss {
 449                 compatible = "simple-mfd";
 450                 #address-cells = <2>;
 451                 #size-cells = <2>;
 452                 ranges;
 453                 dma-coherent;
 454                 dma-ranges;
 455
 456                 ti,sci-dev-id = <118>;
 457
 458                 intr_main_navss: interrupt-controller1 {
 459                         compatible = "ti,sci-intr";
 460                         ti,intr-trigger-type = <4>;
 461                         interrupt-controller;
 462                         interrupt-parent = <&gic500>;
 463                         #interrupt-cells = <1>;
 464                         ti,sci = <&dmsc>;
 465                         ti,sci-dev-id = <182>;
 466                         ti,interrupt-ranges = <0 64 64>,
 467                                               <64 448 64>;
 468                 };
 469
 470                 inta_main_udmass: interrupt-controller@33d00000 {
 471                         compatible = "ti,sci-inta";
 472                         reg = <0x0 0x33d00000 0x0 0x100000>;
 473                         interrupt-controller;
 474                         interrupt-parent = <&intr_main_navss>;
 475                         msi-controller;
 476                         ti,sci = <&dmsc>;
 477                         ti,sci-dev-id = <179>;
 478                         ti,interrupt-ranges = <0 0 256>;
 479                 };
 480
 481                 secure_proxy_main: mailbox@32c00000 {
 482                         compatible = "ti,am654-secure-proxy";
 483                         #mbox-cells = <1>;
 484                         reg-names = "target_data", "rt", "scfg";
 485                         reg = <0x00 0x32c00000 0x00 0x100000>,
 486                               <0x00 0x32400000 0x00 0x100000>,
 487                               <0x00 0x32800000 0x00 0x100000>;
 488                         interrupt-names = "rx_011";
 489                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 490                 };
 491
 492                 hwspinlock: spinlock@30e00000 {
 493                         compatible = "ti,am654-hwspinlock";
 494                         reg = <0x00 0x30e00000 0x00 0x1000>;
 495                         #hwlock-cells = <1>;
 496                 };
 497
 498                 mailbox0_cluster0: mailbox@31f80000 {
 499                         compatible = "ti,am654-mailbox";
 500                         reg = <0x00 0x31f80000 0x00 0x200>;
 501                         #mbox-cells = <1>;
 502                         ti,mbox-num-users = <4>;
 503                         ti,mbox-num-fifos = <16>;
 504                         interrupt-parent = <&intr_main_navss>;
 505                 };
 506
 507                 mailbox0_cluster1: mailbox@31f81000 {
 508                         compatible = "ti,am654-mailbox";
 509                         reg = <0x00 0x31f81000 0x00 0x200>;
 510                         #mbox-cells = <1>;
 511                         ti,mbox-num-users = <4>;
 512                         ti,mbox-num-fifos = <16>;
 513                         interrupt-parent = <&intr_main_navss>;
 514                 };
 515
 516                 mailbox0_cluster2: mailbox@31f82000 {
 517                         compatible = "ti,am654-mailbox";
 518                         reg = <0x00 0x31f82000 0x00 0x200>;
 519                         #mbox-cells = <1>;
 520                         ti,mbox-num-users = <4>;
 521                         ti,mbox-num-fifos = <16>;
 522                         interrupt-parent = <&intr_main_navss>;
 523                 };
 524
 525                 mailbox0_cluster3: mailbox@31f83000 {
 526                         compatible = "ti,am654-mailbox";
 527                         reg = <0x00 0x31f83000 0x00 0x200>;
 528                         #mbox-cells = <1>;
 529                         ti,mbox-num-users = <4>;
 530                         ti,mbox-num-fifos = <16>;
 531                         interrupt-parent = <&intr_main_navss>;
 532                 };
 533
 534                 mailbox0_cluster4: mailbox@31f84000 {
 535                         compatible = "ti,am654-mailbox";
 536                         reg = <0x00 0x31f84000 0x00 0x200>;
 537                         #mbox-cells = <1>;
 538                         ti,mbox-num-users = <4>;
 539                         ti,mbox-num-fifos = <16>;
 540                         interrupt-parent = <&intr_main_navss>;
 541                 };
 542
 543                 mailbox0_cluster5: mailbox@31f85000 {
 544                         compatible = "ti,am654-mailbox";
 545                         reg = <0x00 0x31f85000 0x00 0x200>;
 546                         #mbox-cells = <1>;
 547                         ti,mbox-num-users = <4>;
 548                         ti,mbox-num-fifos = <16>;
 549                         interrupt-parent = <&intr_main_navss>;
 550                 };
 551
 552                 mailbox0_cluster6: mailbox@31f86000 {
 553                         compatible = "ti,am654-mailbox";
 554                         reg = <0x00 0x31f86000 0x00 0x200>;
 555                         #mbox-cells = <1>;
 556                         ti,mbox-num-users = <4>;
 557                         ti,mbox-num-fifos = <16>;
 558                         interrupt-parent = <&intr_main_navss>;
 559                 };
 560
 561                 mailbox0_cluster7: mailbox@31f87000 {
 562                         compatible = "ti,am654-mailbox";
 563                         reg = <0x00 0x31f87000 0x00 0x200>;
 564                         #mbox-cells = <1>;
 565                         ti,mbox-num-users = <4>;
 566                         ti,mbox-num-fifos = <16>;
 567                         interrupt-parent = <&intr_main_navss>;
 568                 };
 569
 570                 mailbox0_cluster8: mailbox@31f88000 {
 571                         compatible = "ti,am654-mailbox";
 572                         reg = <0x00 0x31f88000 0x00 0x200>;
 573                         #mbox-cells = <1>;
 574                         ti,mbox-num-users = <4>;
 575                         ti,mbox-num-fifos = <16>;
 576                         interrupt-parent = <&intr_main_navss>;
 577                 };
 578
 579                 mailbox0_cluster9: mailbox@31f89000 {
 580                         compatible = "ti,am654-mailbox";
 581                         reg = <0x00 0x31f89000 0x00 0x200>;
 582                         #mbox-cells = <1>;
 583                         ti,mbox-num-users = <4>;
 584                         ti,mbox-num-fifos = <16>;
 585                         interrupt-parent = <&intr_main_navss>;
 586                 };
 587
 588                 mailbox0_cluster10: mailbox@31f8a000 {
 589                         compatible = "ti,am654-mailbox";
 590                         reg = <0x00 0x31f8a000 0x00 0x200>;
 591                         #mbox-cells = <1>;
 592                         ti,mbox-num-users = <4>;
 593                         ti,mbox-num-fifos = <16>;
 594                         interrupt-parent = <&intr_main_navss>;
 595                 };
 596
 597                 mailbox0_cluster11: mailbox@31f8b000 {
 598                         compatible = "ti,am654-mailbox";
 599                         reg = <0x00 0x31f8b000 0x00 0x200>;
 600                         #mbox-cells = <1>;
 601                         ti,mbox-num-users = <4>;
 602                         ti,mbox-num-fifos = <16>;
 603                         interrupt-parent = <&intr_main_navss>;
 604                 };
 605
 606                 ringacc: ringacc@3c000000 {
 607                         compatible = "ti,am654-navss-ringacc";
 608                         reg =   <0x0 0x3c000000 0x0 0x400000>,
 609                                 <0x0 0x38000000 0x0 0x400000>,
 610                                 <0x0 0x31120000 0x0 0x100>,
 611                                 <0x0 0x33000000 0x0 0x40000>;
 612                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 613                         ti,num-rings = <818>;
 614                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 615                         ti,dma-ring-reset-quirk;
 616                         ti,sci = <&dmsc>;
 617                         ti,sci-dev-id = <187>;
 618                         msi-parent = <&inta_main_udmass>;
 619                 };
 620
 621                 main_udmap: dma-controller@31150000 {
 622                         compatible = "ti,am654-navss-main-udmap";
 623                         reg =   <0x0 0x31150000 0x0 0x100>,
 624                                 <0x0 0x34000000 0x0 0x100000>,
 625                                 <0x0 0x35000000 0x0 0x100000>;
 626                         reg-names = "gcfg", "rchanrt", "tchanrt";
 627                         msi-parent = <&inta_main_udmass>;
 628                         #dma-cells = <1>;
 629
 630                         ti,sci = <&dmsc>;
 631                         ti,sci-dev-id = <188>;
 632                         ti,ringacc = <&ringacc>;
 633
 634                         ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
 635                                                 <0xd>; /* TX_CHAN */
 636                         ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
 637                                                 <0xa>; /* RX_CHAN */
 638                         ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
 639                 };
 640
 641                 cpts@310d0000 {
 642                         compatible = "ti,am65-cpts";
 643                         reg = <0x0 0x310d0000 0x0 0x400>;
 644                         reg-names = "cpts";
 645                         clocks = <&main_cpts_mux>;
 646                         clock-names = "cpts";
 647                         interrupts-extended = <&intr_main_navss 391>;
 648                         interrupt-names = "cpts";
 649                         ti,cpts-periodic-outputs = <6>;
 650                         ti,cpts-ext-ts-inputs = <8>;
 651
 652                         main_cpts_mux: refclk-mux {
 653                                 #clock-cells = <0>;
 654                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
 655                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
 656                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
 657                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
 658                                 assigned-clocks = <&main_cpts_mux>;
 659                                 assigned-clock-parents = <&k3_clks 118 5>;
 660                         };
 661                 };
 662         };
 663
 664         main_gpio0:  main_gpio0@600000 {
 665                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 666                 reg = <0x0 0x600000 0x0 0x100>;
 667                 gpio-controller;
 668                 #gpio-cells = <2>;
 669                 interrupt-parent = <&intr_main_gpio>;
 670                 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
 671                 interrupt-controller;
 672                 #interrupt-cells = <2>;
 673                 ti,ngpio = <96>;
 674                 ti,davinci-gpio-unbanked = <0>;
 675                 clocks = <&k3_clks 57 0>;
 676                 clock-names = "gpio";
 677         };
 678
 679         main_gpio1:  main_gpio1@601000 {
 680                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 681                 reg = <0x0 0x601000 0x0 0x100>;
 682                 gpio-controller;
 683                 #gpio-cells = <2>;
 684                 interrupt-parent = <&intr_main_gpio>;
 685                 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
 686                 interrupt-controller;
 687                 #interrupt-cells = <2>;
 688                 ti,ngpio = <90>;
 689                 ti,davinci-gpio-unbanked = <0>;
 690                 clocks = <&k3_clks 58 0>;
 691                 clock-names = "gpio";
 692         };
 693
 694         pcie0_rc: pcie@5500000 {
 695                 compatible = "ti,am654-pcie-rc";
 696                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
 697                 reg-names = "app", "dbics", "config", "atu";
 698                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 699                 #address-cells = <3>;
 700                 #size-cells = <2>;
 701                 ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
 702                           0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
 703                 ti,syscon-pcie-id = <&pcie_devid>;
 704                 ti,syscon-pcie-mode = <&pcie0_mode>;
 705                 bus-range = <0x0 0xff>;
 706                 num-viewport = <16>;
 707                 max-link-speed = <2>;
 708                 dma-coherent;
 709                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 710                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 711         };
 712
 713         pcie0_ep: pcie-ep@5500000 {
 714                 compatible = "ti,am654-pcie-ep";
 715                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
 716                 reg-names = "app", "dbics", "addr_space", "atu";
 717                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 718                 ti,syscon-pcie-mode = <&pcie0_mode>;
 719                 num-ib-windows = <16>;
 720                 num-ob-windows = <16>;
 721                 max-link-speed = <2>;
 722                 dma-coherent;
 723                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 724         };
 725
 726         pcie1_rc: pcie@5600000 {
 727                 compatible = "ti,am654-pcie-rc";
 728                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
 729                 reg-names = "app", "dbics", "config", "atu";
 730                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 731                 #address-cells = <3>;
 732                 #size-cells = <2>;
 733                 ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
 734                           0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
 735                 ti,syscon-pcie-id = <&pcie_devid>;
 736                 ti,syscon-pcie-mode = <&pcie1_mode>;
 737                 bus-range = <0x0 0xff>;
 738                 num-viewport = <16>;
 739                 max-link-speed = <2>;
 740                 dma-coherent;
 741                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 742                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
 743         };
 744
 745         pcie1_ep: pcie-ep@5600000 {
 746                 compatible = "ti,am654-pcie-ep";
 747                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
 748                 reg-names = "app", "dbics", "addr_space", "atu";
 749                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 750                 ti,syscon-pcie-mode = <&pcie1_mode>;
 751                 num-ib-windows = <16>;
 752                 num-ob-windows = <16>;
 753                 max-link-speed = <2>;
 754                 dma-coherent;
 755                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 756         };
 757
 758         mcasp0: mcasp@2b00000 {
 759                 compatible = "ti,am33xx-mcasp-audio";
 760                 reg = <0x0 0x02b00000 0x0 0x2000>,
 761                         <0x0 0x02b08000 0x0 0x1000>;
 762                 reg-names = "mpu","dat";
 763                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 764                                 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 765                 interrupt-names = "tx", "rx";
 766
 767                 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
 768                 dma-names = "tx", "rx";
 769
 770                 clocks = <&k3_clks 104 0>;
 771                 clock-names = "fck";
 772                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 773
 774                 status = "disabled";
 775         };
 776
 777         mcasp1: mcasp@2b10000 {
 778                 compatible = "ti,am33xx-mcasp-audio";
 779                 reg = <0x0 0x02b10000 0x0 0x2000>,
 780                         <0x0 0x02b18000 0x0 0x1000>;
 781                 reg-names = "mpu","dat";
 782                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 783                                 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 784                 interrupt-names = "tx", "rx";
 785
 786                 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
 787                 dma-names = "tx", "rx";
 788
 789                 clocks = <&k3_clks 105 0>;
 790                 clock-names = "fck";
 791                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 792
 793                 status = "disabled";
 794         };
 795
 796         mcasp2: mcasp@2b20000 {
 797                 compatible = "ti,am33xx-mcasp-audio";
 798                 reg = <0x0 0x02b20000 0x0 0x2000>,
 799                         <0x0 0x02b28000 0x0 0x1000>;
 800                 reg-names = "mpu","dat";
 801                 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 802                                 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 803                 interrupt-names = "tx", "rx";
 804
 805                 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
 806                 dma-names = "tx", "rx";
 807
 808                 clocks = <&k3_clks 106 0>;
 809                 clock-names = "fck";
 810                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 811
 812                 status = "disabled";
 813         };
 814
 815         cal: cal@6f03000 {
 816                 compatible = "ti,am654-cal";
 817                 reg = <0x0 0x06f03000 0x0 0x400>,
 818                       <0x0 0x06f03800 0x0 0x40>;
 819                 reg-names = "cal_top",
 820                             "cal_rx_core0";
 821                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 822                 ti,camerrx-control = <&scm_conf 0x40c0>;
 823                 clock-names = "fck";
 824                 clocks = <&k3_clks 2 0>;
 825                 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
 826
 827                 ports {
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830
 831                         csi2_0: port@0 {
 832                                 reg = <0>;
 833                         };
 834                 };
 835         };
 836
 837         dss: dss@04a00000 {
 838                 compatible = "ti,am65x-dss";
 839                 reg =   <0x0 0x04a00000 0x0 0x1000>, /* common */
 840                         <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
 841                         <0x0 0x04a06000 0x0 0x1000>, /* vid */
 842                         <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
 843                         <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
 844                         <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
 845                         <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
 846                 reg-names = "common", "vidl1", "vid",
 847                         "ovr1", "ovr2", "vp1", "vp2";
 848
 849                 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
 850
 851                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 852
 853                 clocks =        <&k3_clks 67 1>,
 854                                 <&k3_clks 216 1>,
 855                                 <&k3_clks 67 2>;
 856                 clock-names = "fck", "vp1", "vp2";
 857
 858                 /*
 859                  * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
 860                  * DIV1. See "Figure 12-3365. DSS Integration"
 861                  * in AM65x TRM for details.
 862                  */
 863                 assigned-clocks = <&k3_clks 67 2>;
 864                 assigned-clock-parents = <&k3_clks 67 5>;
 865
 866                 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
 867
 868                 status = "disabled";
 869
 870                 dss_ports: ports {
 871                         #address-cells = <1>;
 872                         #size-cells = <0>;
 873                 };
 874         };
 875
 876         ehrpwm0: pwm@3000000 {
 877                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 878                 #pwm-cells = <3>;
 879                 reg = <0x0 0x3000000 0x0 0x100>;
 880                 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
 881                 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
 882                 clock-names = "tbclk", "fck";
 883         };
 884
 885         ehrpwm1: pwm@3010000 {
 886                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 887                 #pwm-cells = <3>;
 888                 reg = <0x0 0x3010000 0x0 0x100>;
 889                 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
 890                 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
 891                 clock-names = "tbclk", "fck";
 892         };
 893
 894         ehrpwm2: pwm@3020000 {
 895                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 896                 #pwm-cells = <3>;
 897                 reg = <0x0 0x3020000 0x0 0x100>;
 898                 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
 899                 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
 900                 clock-names = "tbclk", "fck";
 901         };
 902
 903         ehrpwm3: pwm@3030000 {
 904                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 905                 #pwm-cells = <3>;
 906                 reg = <0x0 0x3030000 0x0 0x100>;
 907                 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
 908                 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
 909                 clock-names = "tbclk", "fck";
 910         };
 911
 912         ehrpwm4: pwm@3040000 {
 913                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 914                 #pwm-cells = <3>;
 915                 reg = <0x0 0x3040000 0x0 0x100>;
 916                 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
 917                 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
 918                 clock-names = "tbclk", "fck";
 919         };
 920
 921         ehrpwm5: pwm@3050000 {
 922                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 923                 #pwm-cells = <3>;
 924                 reg = <0x0 0x3050000 0x0 0x100>;
 925                 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
 926                 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
 927                 clock-names = "tbclk", "fck";
 928         };
 929 };