arch/arm64/boot/dts/rockchip/rk3568.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include "rk356x.dtsi"
   7
   8 / {
   9         compatible = "rockchip,rk3568";
  10
  11         pipe_phy_grf0: syscon@fdc70000 {
  12                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
  13                 reg = <0x0 0xfdc70000 0x0 0x1000>;
  14         };
  15
  16         qos_pcie3x1: qos@fe190080 {
  17                 compatible = "rockchip,rk3568-qos", "syscon";
  18                 reg = <0x0 0xfe190080 0x0 0x20>;
  19         };
  20
  21         qos_pcie3x2: qos@fe190100 {
  22                 compatible = "rockchip,rk3568-qos", "syscon";
  23                 reg = <0x0 0xfe190100 0x0 0x20>;
  24         };
  25
  26         qos_sata0: qos@fe190200 {
  27                 compatible = "rockchip,rk3568-qos", "syscon";
  28                 reg = <0x0 0xfe190200 0x0 0x20>;
  29         };
  30
  31         gmac0: ethernet@fe2a0000 {
  32                 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
  33                 reg = <0x0 0xfe2a0000 0x0 0x10000>;
  34                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
  35                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  36                 interrupt-names = "macirq", "eth_wake_irq";
  37                 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
  38                          <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
  39                          <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
  40                          <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
  41                          <&cru PCLK_XPCS>;
  42                 clock-names = "stmmaceth", "mac_clk_rx",
  43                               "mac_clk_tx", "clk_mac_refout",
  44                               "aclk_mac", "pclk_mac",
  45                               "clk_mac_speed", "ptp_ref",
  46                               "pclk_xpcs";
  47                 resets = <&cru SRST_A_GMAC0>;
  48                 reset-names = "stmmaceth";
  49                 rockchip,grf = <&grf>;
  50                 snps,axi-config = <&gmac0_stmmac_axi_setup>;
  51                 snps,mixed-burst;
  52                 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
  53                 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
  54                 snps,tso;
  55                 status = "disabled";
  56
  57                 mdio0: mdio {
  58                         compatible = "snps,dwmac-mdio";
  59                         #address-cells = <0x1>;
  60                         #size-cells = <0x0>;
  61                 };
  62
  63                 gmac0_stmmac_axi_setup: stmmac-axi-config {
  64                         snps,blen = <0 0 0 0 16 8 4>;
  65                         snps,rd_osr_lmt = <8>;
  66                         snps,wr_osr_lmt = <4>;
  67                 };
  68
  69                 gmac0_mtl_rx_setup: rx-queues-config {
  70                         snps,rx-queues-to-use = <1>;
  71                         queue0 {};
  72                 };
  73
  74                 gmac0_mtl_tx_setup: tx-queues-config {
  75                         snps,tx-queues-to-use = <1>;
  76                         queue0 {};
  77                 };
  78         };
  79
  80         combphy0: phy@fe820000 {
  81                 compatible = "rockchip,rk3568-naneng-combphy";
  82                 reg = <0x0 0xfe820000 0x0 0x100>;
  83                 clocks = <&pmucru CLK_PCIEPHY0_REF>,
  84                          <&cru PCLK_PIPEPHY0>,
  85                          <&cru PCLK_PIPE>;
  86                 clock-names = "ref", "apb", "pipe";
  87                 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
  88                 assigned-clock-rates = <100000000>;
  89                 resets = <&cru SRST_PIPEPHY0>;
  90                 rockchip,pipe-grf = <&pipegrf>;
  91                 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
  92                 #phy-cells = <1>;
  93                 status = "disabled";
  94         };
  95 };
  96
  97 &cpu0_opp_table {
  98         opp-1992000000 {
  99                 opp-hz = /bits/ 64 <1992000000>;
 100                 opp-microvolt = <1150000 1150000 1150000>;
 101         };
 102 };
 103
 104 &power {
 105         power-domain@RK3568_PD_PIPE {
 106                 reg = <RK3568_PD_PIPE>;
 107                 clocks = <&cru PCLK_PIPE>;
 108                 pm_qos = <&qos_pcie2x1>,
 109                          <&qos_pcie3x1>,
 110                          <&qos_pcie3x2>,
 111                          <&qos_sata0>,
 112                          <&qos_sata1>,
 113                          <&qos_sata2>,
 114                          <&qos_usb3_0>,
 115                          <&qos_usb3_1>;
 116                 #power-domain-cells = <0>;
 117         };
 118 };