arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2020, Compass Electronics Group, LLC
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/clk/versaclock.h>
   8
   9 / {
  10         memory@48000000 {
  11                 device_type = "memory";
  12                 /* first 128MB is reserved for secure area. */
  13                 reg = <0x0 0x48000000 0x0 0x78000000>;
  14         };
  15
  16         osc_32k: osc_32k {
  17                 compatible = "fixed-clock";
  18                 #clock-cells = <0>;
  19                 clock-frequency = <32768>;
  20                 clock-output-names = "osc_32k";
  21         };
  22
  23         reg_1p8v: regulator0 {
  24                 compatible = "regulator-fixed";
  25                 regulator-name = "fixed-1.8V";
  26                 regulator-min-microvolt = <1800000>;
  27                 regulator-max-microvolt = <1800000>;
  28                 regulator-boot-on;
  29                 regulator-always-on;
  30         };
  31
  32         reg_3p3v: regulator1 {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "fixed-3.3V";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37                 regulator-boot-on;
  38                 regulator-always-on;
  39         };
  40
  41         wlan_pwrseq: wlan_pwrseq {
  42                 compatible = "mmc-pwrseq-simple";
  43                 reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
  44                 clocks = <&osc_32k>;
  45                 clock-names = "ext_clock";
  46                 post-power-on-delay-ms = <80>;
  47         };
  48 };
  49
  50 &avb {
  51         pinctrl-0 = <&avb_pins>;
  52         pinctrl-names = "default";
  53         phy-handle = <&phy0>;
  54         rx-internal-delay-ps = <1800>;
  55         tx-internal-delay-ps = <2000>;
  56         clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
  57         clock-names = "fck", "refclk";
  58         status = "okay";
  59
  60         phy0: ethernet-phy@0 {
  61                 reg = <0>;
  62                 interrupt-parent = <&gpio2>;
  63                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  64                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  65         };
  66 };
  67
  68 &extal_clk {
  69         clock-frequency = <16666666>;
  70 };
  71
  72 &extalr_clk {
  73         clock-frequency = <32768>;
  74 };
  75
  76 &gpio6 {
  77         usb_hub_reset {
  78                 gpio-hog;
  79                 gpios = <10 GPIO_ACTIVE_HIGH>;
  80                 output-high;
  81                 line-name = "usb-hub-reset";
  82         };
  83 };
  84
  85 &hscif0 {
  86         pinctrl-0 = <&hscif0_pins>;
  87         pinctrl-names = "default";
  88         uart-has-rtscts;
  89         status = "okay";
  90
  91         bluetooth {
  92                 compatible = "brcm,bcm43438-bt";
  93                 shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
  94                 host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  95                 device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
  96                 clocks = <&osc_32k>;
  97                 clock-names = "extclk";
  98                 max-speed = <4000000>;
  99         };
 100 };
 101
 102 &hscif2 {
 103         status = "okay";
 104         pinctrl-0 = <&hscif2_pins>;
 105         pinctrl-names = "default";
 106 };
 107
 108 &i2c4 {
 109         status = "okay";
 110         clock-frequency = <100000>;
 111
 112         pca9654: gpio@20 {
 113                 compatible = "onnn,pca9654";
 114                 reg = <0x20>;
 115                 gpio-controller;
 116                 #gpio-cells = <2>;
 117                 gpio-line-names =
 118                         "i2c4_20_0",
 119                         "wl_reg_on",
 120                         "bt_reg_on",
 121                         "i2c4_20_3",
 122                         "i2c4_20_4",
 123                         "bt_dev_wake",
 124                         "i2c4_20_6",
 125                         "i2c4_20_7";
 126         };
 127
 128         pca9654_lte: gpio@21 {
 129                 compatible = "onnn,pca9654";
 130                 reg = <0x21>;
 131                 interrupt-parent = <&gpio5>;
 132                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 133                 interrupt-controller;
 134                 #interrupt-cells = <2>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137                 gpio-line-names =
 138                         "i2c4_21_0",
 139                         "zoe_pwr_on",
 140                         "zoe_extint",
 141                         "zoe_reset_n",
 142                         "sara_reset",
 143                         "i2c4_21_5",
 144                         "sara_pwr_off",
 145                         "sara_networking_status";
 146         };
 147
 148         eeprom@50 {
 149                 compatible = "microchip,24c64", "atmel,24c64";
 150                 pagesize = <32>;
 151                 read-only;      /* Manufacturing EEPROM programmed at factory */
 152                 reg = <0x50>;
 153         };
 154
 155         rtc@51 {
 156                 compatible = "nxp,pcf85263";
 157                 reg = <0x51>;
 158         };
 159
 160         versaclock5: versaclock_som@6a {
 161                 compatible = "idt,5p49v6965";
 162                 reg = <0x6a>;
 163                 #clock-cells = <1>;
 164                 clocks = <&x304_clk>;
 165                 clock-names = "xin";
 166                 /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
 167                 assigned-clocks = <&versaclock5 1>,
 168                                    <&versaclock5 2>,
 169                                    <&versaclock5 3>,
 170                                    <&versaclock5 4>;
 171
 172                 assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
 173
 174                 OUT1 {
 175                         idt,mode = <VC5_CMOS>;
 176                         idt,voltage-microvolt = <1800000>;
 177                         idt,slew-percent = <100>;
 178                 };
 179
 180                 OUT2 {
 181                         idt,mode = <VC5_CMOS>;
 182                         idt,voltage-microvolt = <1800000>;
 183                         idt,slew-percent = <100>;
 184                 };
 185
 186                 OUT3 {
 187                         idt,mode = <VC5_CMOS>;
 188                         idt,voltage-microvolt = <1800000>;
 189                         idt,slew-percent = <100>;
 190                 };
 191
 192                 OUT4 {
 193                         idt,mode = <VC5_CMOS>;
 194                         idt,voltage-microvolt = <3300000>;
 195                         idt,slew-percent = <100>;
 196                 };
 197         };
 198 };
 199
 200 &pfc {
 201         pinctrl-0 = <&scif_clk_pins>;
 202         pinctrl-names = "default";
 203
 204         avb_pins: avb {
 205                 mux {
 206                         groups = "avb_link", "avb_mdio", "avb_mii";
 207                         function = "avb";
 208                 };
 209
 210                 pins_mdio {
 211                         groups = "avb_mdio";
 212                         drive-strength = <24>;
 213                 };
 214
 215                 pins_mii_tx {
 216                         pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 217                                "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 218                         drive-strength = <12>;
 219                 };
 220         };
 221
 222         scif2_pins: scif2 {
 223                 groups = "scif2_data_a";
 224                 function = "scif2";
 225         };
 226
 227         hscif0_pins: hscif0 {
 228                 groups = "hscif0_data", "hscif0_ctrl";
 229                 function = "hscif0";
 230         };
 231
 232         hscif1_pins: hscif1 {
 233                 groups = "hscif1_data_a", "hscif1_ctrl_a";
 234                 function = "hscif1";
 235         };
 236
 237         hscif2_pins: hscif2 {
 238                 groups = "hscif2_data_a";
 239                 function = "hscif2";
 240         };
 241
 242         scif0_pins: scif0 {
 243                 groups = "scif0_data";
 244                 function = "scif0";
 245         };
 246
 247         scif5_pins: scif5 {
 248                 groups = "scif5_data_a";
 249                 function = "scif5";
 250         };
 251
 252         scif_clk_pins: scif_clk {
 253                 groups = "scif_clk_a";
 254                 function = "scif_clk";
 255         };
 256
 257         i2c0_pins: i2c0 {
 258                 groups = "i2c0";
 259                 function = "i2c0";
 260         };
 261
 262         sdhi2_pins: sd2 {
 263                 groups = "sdhi2_data4", "sdhi2_ctrl";
 264                 function = "sdhi2";
 265                 power-source = <1800>;
 266         };
 267
 268         sdhi3_pins: sd3 {
 269                 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
 270                 function = "sdhi3";
 271                 power-source = <1800>;
 272         };
 273 };
 274
 275 &scif_clk {
 276         clock-frequency = <14745600>;
 277 };
 278
 279 &scif2 {
 280         pinctrl-0 = <&scif2_pins>;
 281         pinctrl-names = "default";
 282         status = "okay";
 283 };
 284
 285 &sdhi2 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&sdhi2_pins>;
 288         bus-width = <4>;
 289         vmmc-supply = <&reg_3p3v>;
 290         vqmmc-supply = <&reg_1p8v>;
 291         non-removable;
 292         cap-power-off-card;
 293         pm-ignore-notify;
 294         keep-power-in-suspend;
 295         mmc-pwrseq = <&wlan_pwrseq>;
 296         status = "okay";
 297         #address-cells = <1>;
 298         #size-cells = <0>;
 299
 300         brcmf: bcrmf@1 {
 301                 reg = <1>;
 302                 compatible = "brcm,bcm4329-fmac";
 303                 interrupt-parent = <&gpio1>;
 304                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 305                 interrupt-names = "host-wake";
 306         };
 307 };
 308
 309 &sdhi3 {
 310         pinctrl-0 = <&sdhi3_pins>;
 311         pinctrl-1 = <&sdhi3_pins>;
 312         pinctrl-names = "default", "state_uhs";
 313         vmmc-supply = <&reg_3p3v>;
 314         vqmmc-supply = <&reg_1p8v>;
 315         bus-width = <8>;
 316         mmc-hs200-1_8v;
 317         no-sd;
 318         no-sdio;
 319         non-removable;
 320         fixed-emmc-driver-type = <1>;
 321         status = "okay";
 322 };
 323
 324 &usb2_clksel {
 325         clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
 326                   <&versaclock5 3>, <&usb3s0_clk>;
 327         status = "okay";
 328 };
 329
 330 &usb3s0_clk {
 331         clock-frequency = <100000000>;
 332 };