1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, Linaro Limited
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/interconnect/qcom,sm8350.h>
10 #include <dt-bindings/mailbox/qcom-ipcc.h>
11 #include <dt-bindings/power/qcom-aoss-qmp.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
14 #include <dt-bindings/thermal/thermal.h>
15 #include <dt-bindings/interconnect/qcom,sm8350.h>
18 interrupt-parent = <&intc>;
27 compatible = "fixed-clock";
29 clock-frequency = <38400000>;
30 clock-output-names = "xo_board";
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 clock-frequency = <32000>;
46 compatible = "qcom,kryo685";
48 enable-method = "psci";
49 next-level-cache = <&L2_0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
54 next-level-cache = <&L3_0>;
63 compatible = "qcom,kryo685";
65 enable-method = "psci";
66 next-level-cache = <&L2_100>;
67 qcom,freq-domain = <&cpufreq_hw 0>;
71 next-level-cache = <&L3_0>;
77 compatible = "qcom,kryo685";
79 enable-method = "psci";
80 next-level-cache = <&L2_200>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L3_0>;
91 compatible = "qcom,kryo685";
93 enable-method = "psci";
94 next-level-cache = <&L2_300>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
99 next-level-cache = <&L3_0>;
105 compatible = "qcom,kryo685";
107 enable-method = "psci";
108 next-level-cache = <&L2_400>;
109 qcom,freq-domain = <&cpufreq_hw 1>;
110 #cooling-cells = <2>;
112 compatible = "cache";
113 next-level-cache = <&L3_0>;
119 compatible = "qcom,kryo685";
121 enable-method = "psci";
122 next-level-cache = <&L2_500>;
123 qcom,freq-domain = <&cpufreq_hw 1>;
124 #cooling-cells = <2>;
126 compatible = "cache";
127 next-level-cache = <&L3_0>;
134 compatible = "qcom,kryo685";
136 enable-method = "psci";
137 next-level-cache = <&L2_600>;
138 qcom,freq-domain = <&cpufreq_hw 1>;
139 #cooling-cells = <2>;
141 compatible = "cache";
142 next-level-cache = <&L3_0>;
148 compatible = "qcom,kryo685";
150 enable-method = "psci";
151 next-level-cache = <&L2_700>;
152 qcom,freq-domain = <&cpufreq_hw 2>;
153 #cooling-cells = <2>;
155 compatible = "cache";
156 next-level-cache = <&L3_0>;
163 compatible = "qcom,scm-sm8350", "qcom,scm";
169 device_type = "memory";
170 /* We expect the bootloader to fill in the size */
171 reg = <0x0 0x80000000 0x0 0x0>;
175 compatible = "arm,armv8-pmuv3";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
180 compatible = "arm,psci-1.0";
184 reserved_memory: reserved-memory {
185 #address-cells = <2>;
189 hyp_mem: memory@80000000 {
190 reg = <0x0 0x80000000 0x0 0x600000>;
194 xbl_aop_mem: memory@80700000 {
196 reg = <0x0 0x80700000 0x0 0x160000>;
199 cmd_db: memory@80860000 {
200 compatible = "qcom,cmd-db";
201 reg = <0x0 0x80860000 0x0 0x20000>;
205 reserved_xbl_uefi_log: memory@80880000 {
206 reg = <0x0 0x80880000 0x0 0x14000>;
210 smem_mem: memory@80900000 {
211 reg = <0x0 0x80900000 0x0 0x200000>;
215 cpucp_fw_mem: memory@80b00000 {
216 reg = <0x0 0x80b00000 0x0 0x100000>;
220 cdsp_secure_heap: memory@80c00000 {
221 reg = <0x0 0x80c00000 0x0 0x4600000>;
225 pil_camera_mem: mmeory@85200000 {
226 reg = <0x0 0x85200000 0x0 0x500000>;
230 pil_video_mem: memory@85700000 {
231 reg = <0x0 0x85700000 0x0 0x500000>;
235 pil_cvp_mem: memory@85c00000 {
236 reg = <0x0 0x85c00000 0x0 0x500000>;
240 pil_adsp_mem: memory@86100000 {
241 reg = <0x0 0x86100000 0x0 0x2100000>;
245 pil_slpi_mem: memory@88200000 {
246 reg = <0x0 0x88200000 0x0 0x1500000>;
250 pil_cdsp_mem: memory@89700000 {
251 reg = <0x0 0x89700000 0x0 0x1e00000>;
255 pil_ipa_fw_mem: memory@8b500000 {
256 reg = <0x0 0x8b500000 0x0 0x10000>;
260 pil_ipa_gsi_mem: memory@8b510000 {
261 reg = <0x0 0x8b510000 0x0 0xa000>;
265 pil_gpu_mem: memory@8b51a000 {
266 reg = <0x0 0x8b51a000 0x0 0x2000>;
270 pil_spss_mem: memory@8b600000 {
271 reg = <0x0 0x8b600000 0x0 0x100000>;
275 pil_modem_mem: memory@8b800000 {
276 reg = <0x0 0x8b800000 0x0 0x10000000>;
280 rmtfs_mem: memory@9b800000 {
281 compatible = "qcom,rmtfs-mem";
282 reg = <0x0 0x9b800000 0x0 0x280000>;
285 qcom,client-id = <1>;
289 hyp_reserved_mem: memory@d0000000 {
290 reg = <0x0 0xd0000000 0x0 0x800000>;
294 pil_trustedvm_mem: memory@d0800000 {
295 reg = <0x0 0xd0800000 0x0 0x76f7000>;
299 qrtr_shbuf: memory@d7ef7000 {
300 reg = <0x0 0xd7ef7000 0x0 0x9000>;
304 chan0_shbuf: memory@d7f00000 {
305 reg = <0x0 0xd7f00000 0x0 0x80000>;
309 chan1_shbuf: memory@d7f80000 {
310 reg = <0x0 0xd7f80000 0x0 0x80000>;
314 removed_mem: memory@d8800000 {
315 reg = <0x0 0xd8800000 0x0 0x6800000>;
321 compatible = "qcom,smem";
322 memory-region = <&smem_mem>;
323 hwlocks = <&tcsr_mutex 3>;
327 compatible = "qcom,smp2p";
328 qcom,smem = <443>, <429>;
329 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
330 IPCC_MPROC_SIGNAL_SMP2P
331 IRQ_TYPE_EDGE_RISING>;
332 mboxes = <&ipcc IPCC_CLIENT_LPASS
333 IPCC_MPROC_SIGNAL_SMP2P>;
335 qcom,local-pid = <0>;
336 qcom,remote-pid = <2>;
338 smp2p_adsp_out: master-kernel {
339 qcom,entry-name = "master-kernel";
340 #qcom,smem-state-cells = <1>;
343 smp2p_adsp_in: slave-kernel {
344 qcom,entry-name = "slave-kernel";
345 interrupt-controller;
346 #interrupt-cells = <2>;
351 compatible = "qcom,smp2p";
352 qcom,smem = <94>, <432>;
353 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
354 IPCC_MPROC_SIGNAL_SMP2P
355 IRQ_TYPE_EDGE_RISING>;
356 mboxes = <&ipcc IPCC_CLIENT_CDSP
357 IPCC_MPROC_SIGNAL_SMP2P>;
359 qcom,local-pid = <0>;
360 qcom,remote-pid = <5>;
362 smp2p_cdsp_out: master-kernel {
363 qcom,entry-name = "master-kernel";
364 #qcom,smem-state-cells = <1>;
367 smp2p_cdsp_in: slave-kernel {
368 qcom,entry-name = "slave-kernel";
369 interrupt-controller;
370 #interrupt-cells = <2>;
375 compatible = "qcom,smp2p";
376 qcom,smem = <435>, <428>;
377 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
378 IPCC_MPROC_SIGNAL_SMP2P
379 IRQ_TYPE_EDGE_RISING>;
380 mboxes = <&ipcc IPCC_CLIENT_MPSS
381 IPCC_MPROC_SIGNAL_SMP2P>;
383 qcom,local-pid = <0>;
384 qcom,remote-pid = <1>;
386 smp2p_modem_out: master-kernel {
387 qcom,entry-name = "master-kernel";
388 #qcom,smem-state-cells = <1>;
391 smp2p_modem_in: slave-kernel {
392 qcom,entry-name = "slave-kernel";
393 interrupt-controller;
394 #interrupt-cells = <2>;
397 ipa_smp2p_out: ipa-ap-to-modem {
398 qcom,entry-name = "ipa";
399 #qcom,smem-state-cells = <1>;
402 ipa_smp2p_in: ipa-modem-to-ap {
403 qcom,entry-name = "ipa";
404 interrupt-controller;
405 #interrupt-cells = <2>;
410 compatible = "qcom,smp2p";
411 qcom,smem = <481>, <430>;
412 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
413 IPCC_MPROC_SIGNAL_SMP2P
414 IRQ_TYPE_EDGE_RISING>;
415 mboxes = <&ipcc IPCC_CLIENT_SLPI
416 IPCC_MPROC_SIGNAL_SMP2P>;
418 qcom,local-pid = <0>;
419 qcom,remote-pid = <3>;
421 smp2p_slpi_out: master-kernel {
422 qcom,entry-name = "master-kernel";
423 #qcom,smem-state-cells = <1>;
426 smp2p_slpi_in: slave-kernel {
427 qcom,entry-name = "slave-kernel";
428 interrupt-controller;
429 #interrupt-cells = <2>;
434 #address-cells = <2>;
436 ranges = <0 0 0 0 0x10 0>;
437 dma-ranges = <0 0 0 0 0x10 0>;
438 compatible = "simple-bus";
440 gcc: clock-controller@100000 {
441 compatible = "qcom,gcc-sm8350";
442 reg = <0x0 0x00100000 0x0 0x1f0000>;
445 #power-domain-cells = <1>;
446 clock-names = "bi_tcxo", "sleep_clk";
447 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
450 ipcc: mailbox@408000 {
451 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
452 reg = <0 0x00408000 0 0x1000>;
453 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-controller;
455 #interrupt-cells = <3>;
459 qupv3_id_0: geniqup@9c0000 {
460 compatible = "qcom,geni-se-qup";
461 reg = <0x0 0x009c0000 0x0 0x6000>;
462 clock-names = "m-ahb", "s-ahb";
463 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
464 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
465 #address-cells = <2>;
470 uart2: serial@98c000 {
471 compatible = "qcom,geni-debug-uart";
472 reg = <0 0x0098c000 0 0x4000>;
474 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&qup_uart3_default_state>;
477 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
484 qupv3_id_1: geniqup@ac0000 {
485 compatible = "qcom,geni-se-qup";
486 reg = <0x0 0x00ac0000 0x0 0x6000>;
487 clock-names = "m-ahb", "s-ahb";
488 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
489 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
490 #address-cells = <2>;
496 compatible = "qcom,geni-i2c";
497 reg = <0 0x00a94000 0 0x4000>;
499 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&qup_i2c13_default_state>;
502 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
509 apps_smmu: iommu@15000000 {
510 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
511 reg = <0 0x15000000 0 0x100000>;
513 #global-interrupts = <2>;
514 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
614 config_noc: interconnect@1500000 {
615 compatible = "qcom,sm8350-config-noc";
616 reg = <0 0x01500000 0 0xa580>;
617 #interconnect-cells = <1>;
618 qcom,bcm-voters = <&apps_bcm_voter>;
621 mc_virt: interconnect@1580000 {
622 compatible = "qcom,sm8350-mc-virt";
623 reg = <0 0x01580000 0 0x1000>;
624 #interconnect-cells = <1>;
625 qcom,bcm-voters = <&apps_bcm_voter>;
628 system_noc: interconnect@1680000 {
629 compatible = "qcom,sm8350-system-noc";
630 reg = <0 0x01680000 0 0x1c200>;
631 #interconnect-cells = <1>;
632 qcom,bcm-voters = <&apps_bcm_voter>;
635 aggre1_noc: interconnect@16e0000 {
636 compatible = "qcom,sm8350-aggre1-noc";
637 reg = <0 0x016e0000 0 0x1f180>;
638 #interconnect-cells = <1>;
639 qcom,bcm-voters = <&apps_bcm_voter>;
642 aggre2_noc: interconnect@1700000 {
643 compatible = "qcom,sm8350-aggre2-noc";
644 reg = <0 0x01700000 0 0x33000>;
645 #interconnect-cells = <1>;
646 qcom,bcm-voters = <&apps_bcm_voter>;
649 mmss_noc: interconnect@1740000 {
650 compatible = "qcom,sm8350-mmss-noc";
651 reg = <0 0x01740000 0 0x1f080>;
652 #interconnect-cells = <1>;
653 qcom,bcm-voters = <&apps_bcm_voter>;
656 lpass_ag_noc: interconnect@3c40000 {
657 compatible = "qcom,sm8350-lpass-ag-noc";
658 reg = <0 0x03c40000 0 0xf080>;
659 #interconnect-cells = <1>;
660 qcom,bcm-voters = <&apps_bcm_voter>;
663 compute_noc: interconnect@a0c0000{
664 compatible = "qcom,sm8350-compute-noc";
665 reg = <0 0x0a0c0000 0 0xa180>;
666 #interconnect-cells = <1>;
667 qcom,bcm-voters = <&apps_bcm_voter>;
671 compatible = "qcom,sm8350-ipa";
673 iommus = <&apps_smmu 0x5c0 0x0>,
674 <&apps_smmu 0x5c2 0x0>;
675 reg = <0 0x1e40000 0 0x8000>,
676 <0 0x1e50000 0 0x4b20>,
677 <0 0x1e04000 0 0x23000>;
678 reg-names = "ipa-reg",
682 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
683 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
684 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
685 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
686 interrupt-names = "ipa",
691 clocks = <&rpmhcc RPMH_IPA_CLK>;
692 clock-names = "core";
694 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
695 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
696 interconnect-names = "memory",
699 qcom,smem-states = <&ipa_smp2p_out 0>,
701 qcom,smem-state-names = "ipa-clock-enabled-valid",
707 tcsr_mutex: hwlock@1f40000 {
708 compatible = "qcom,tcsr-mutex";
709 reg = <0x0 0x01f40000 0x0 0x40000>;
713 mpss: remoteproc@4080000 {
714 compatible = "qcom,sm8350-mpss-pas";
715 reg = <0x0 0x04080000 0x0 0x4040>;
717 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
718 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
719 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
720 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
721 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
722 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
723 interrupt-names = "wdog", "fatal", "ready", "handover",
724 "stop-ack", "shutdown-ack";
726 clocks = <&rpmhcc RPMH_CXO_CLK>;
729 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
732 power-domain-names = "load_state", "cx", "mss";
734 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
736 memory-region = <&pil_modem_mem>;
738 qcom,smem-states = <&smp2p_modem_out 0>;
739 qcom,smem-state-names = "stop";
744 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
745 IPCC_MPROC_SIGNAL_GLINK_QMP
746 IRQ_TYPE_EDGE_RISING>;
747 mboxes = <&ipcc IPCC_CLIENT_MPSS
748 IPCC_MPROC_SIGNAL_GLINK_QMP>;
749 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
751 qcom,remote-pid = <1>;
755 pdc: interrupt-controller@b220000 {
756 compatible = "qcom,sm8350-pdc", "qcom,pdc";
757 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
758 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
759 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
760 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
762 #interrupt-cells = <2>;
763 interrupt-parent = <&intc>;
764 interrupt-controller;
767 tsens0: thermal-sensor@c263000 {
768 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
769 reg = <0 0x0c263000 0 0x1ff>, /* TM */
770 <0 0x0c222000 0 0x8>; /* SROT */
771 #qcom,sensors = <15>;
772 interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
773 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
774 interrupt-names = "uplow", "critical";
775 #thermal-sensor-cells = <1>;
778 tsens1: thermal-sensor@c265000 {
779 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
780 reg = <0 0x0c265000 0 0x1ff>, /* TM */
781 <0 0x0c223000 0 0x8>; /* SROT */
782 #qcom,sensors = <14>;
783 interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
784 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
785 interrupt-names = "uplow", "critical";
786 #thermal-sensor-cells = <1>;
789 aoss_qmp: power-controller@c300000 {
790 compatible = "qcom,sm8350-aoss-qmp";
791 reg = <0 0x0c300000 0 0x100000>;
792 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
793 IRQ_TYPE_EDGE_RISING>;
794 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
797 #power-domain-cells = <1>;
800 spmi_bus: spmi@c440000 {
801 compatible = "qcom,spmi-pmic-arb";
802 reg = <0x0 0xc440000 0x0 0x1100>,
803 <0x0 0xc600000 0x0 0x2000000>,
804 <0x0 0xe600000 0x0 0x100000>,
805 <0x0 0xe700000 0x0 0xa0000>,
806 <0x0 0xc40a000 0x0 0x26000>;
807 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
808 interrupt-names = "periph_irq";
809 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
812 #address-cells = <2>;
814 interrupt-controller;
815 #interrupt-cells = <4>;
818 tlmm: pinctrl@f100000 {
819 compatible = "qcom,sm8350-tlmm";
820 reg = <0 0x0f100000 0 0x300000>;
821 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-controller;
825 #interrupt-cells = <2>;
826 gpio-ranges = <&tlmm 0 0 204>;
827 wakeup-parent = <&pdc>;
829 qup_uart3_default_state: qup-uart3-default-state {
840 qup_i2c13_default_state: qup-i2c13-default-state {
842 pins = "gpio0", "gpio1";
847 pins = "gpio0", "gpio1";
848 drive-strength = <2>;
855 compatible = "qcom,prng-ee";
856 reg = <0 0x010d3000 0 0x1000>;
857 clocks = <&rpmhcc RPMH_HWKM_CLK>;
858 clock-names = "core";
861 intc: interrupt-controller@17a00000 {
862 compatible = "arm,gic-v3";
863 #interrupt-cells = <3>;
864 interrupt-controller;
865 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
866 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
867 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
871 compatible = "arm,armv7-timer-mem";
872 #address-cells = <2>;
875 reg = <0x0 0x17c20000 0x0 0x1000>;
876 clock-frequency = <19200000>;
880 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
882 reg = <0x0 0x17c21000 0x0 0x1000>,
883 <0x0 0x17c22000 0x0 0x1000>;
888 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
889 reg = <0x0 0x17c23000 0x0 0x1000>;
895 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
896 reg = <0x0 0x17c25000 0x0 0x1000>;
902 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
903 reg = <0x0 0x17c27000 0x0 0x1000>;
909 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
910 reg = <0x0 0x17c29000 0x0 0x1000>;
916 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
917 reg = <0x0 0x17c2b000 0x0 0x1000>;
923 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
924 reg = <0x0 0x17c2d000 0x0 0x1000>;
929 apps_rsc: rsc@18200000 {
931 compatible = "qcom,rpmh-rsc";
932 reg = <0x0 0x18200000 0x0 0x10000>,
933 <0x0 0x18210000 0x0 0x10000>,
934 <0x0 0x18220000 0x0 0x10000>;
935 reg-names = "drv-0", "drv-1", "drv-2";
936 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
939 qcom,tcs-offset = <0xd00>;
941 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
942 <WAKE_TCS 3>, <CONTROL_TCS 1>;
944 rpmhcc: clock-controller {
945 compatible = "qcom,sm8350-rpmh-clk";
948 clocks = <&xo_board>;
951 rpmhpd: power-controller {
952 compatible = "qcom,sm8350-rpmhpd";
953 #power-domain-cells = <1>;
954 operating-points-v2 = <&rpmhpd_opp_table>;
956 rpmhpd_opp_table: opp-table {
957 compatible = "operating-points-v2";
959 rpmhpd_opp_ret: opp1 {
960 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
963 rpmhpd_opp_min_svs: opp2 {
964 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
967 rpmhpd_opp_low_svs: opp3 {
968 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
971 rpmhpd_opp_svs: opp4 {
972 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
975 rpmhpd_opp_svs_l1: opp5 {
976 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
979 rpmhpd_opp_nom: opp6 {
980 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
983 rpmhpd_opp_nom_l1: opp7 {
984 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
987 rpmhpd_opp_nom_l2: opp8 {
988 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
991 rpmhpd_opp_turbo: opp9 {
992 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
995 rpmhpd_opp_turbo_l1: opp10 {
996 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1001 apps_bcm_voter: bcm_voter {
1002 compatible = "qcom,bcm-voter";
1006 cpufreq_hw: cpufreq@18591000 {
1007 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
1008 reg = <0 0x18591000 0 0x1000>,
1009 <0 0x18592000 0 0x1000>,
1010 <0 0x18593000 0 0x1000>;
1011 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
1013 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1014 clock-names = "xo", "alternate";
1016 #freq-domain-cells = <1>;
1019 ufs_mem_hc: ufshc@1d84000 {
1020 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1022 reg = <0 0x01d84000 0 0x3000>;
1023 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1024 phys = <&ufs_mem_phy_lanes>;
1025 phy-names = "ufsphy";
1026 lanes-per-direction = <2>;
1028 resets = <&gcc GCC_UFS_PHY_BCR>;
1029 reset-names = "rst";
1031 power-domains = <&gcc UFS_PHY_GDSC>;
1033 iommus = <&apps_smmu 0xe0 0x0>;
1042 "tx_lane0_sync_clk",
1043 "rx_lane0_sync_clk",
1044 "rx_lane1_sync_clk";
1046 <&rpmhcc RPMH_CXO_CLK>,
1047 <&gcc GCC_UFS_PHY_AXI_CLK>,
1048 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1049 <&gcc GCC_UFS_PHY_AHB_CLK>,
1050 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1051 <&rpmhcc RPMH_CXO_CLK>,
1052 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1053 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1054 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1056 <75000000 300000000>,
1057 <75000000 300000000>,
1060 <75000000 300000000>,
1063 <75000000 300000000>,
1064 <75000000 300000000>;
1065 status = "disabled";
1068 ufs_mem_phy: phy@1d87000 {
1069 compatible = "qcom,sm8350-qmp-ufs-phy";
1070 reg = <0 0x01d87000 0 0xe10>;
1071 #address-cells = <2>;
1075 clock-names = "ref",
1077 clocks = <&rpmhcc RPMH_CXO_CLK>,
1078 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1080 resets = <&ufs_mem_hc 0>;
1081 reset-names = "ufsphy";
1082 status = "disabled";
1084 ufs_mem_phy_lanes: lanes@1d87400 {
1085 reg = <0 0x01d87400 0 0x108>,
1086 <0 0x01d87600 0 0x1e0>,
1087 <0 0x01d87c00 0 0x1dc>,
1088 <0 0x01d87800 0 0x108>,
1089 <0 0x01d87a00 0 0x1e0>;
1095 slpi: remoteproc@5c00000 {
1096 compatible = "qcom,sm8350-slpi-pas";
1097 reg = <0 0x05c00000 0 0x4000>;
1099 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1100 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1101 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1102 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1103 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1104 interrupt-names = "wdog", "fatal", "ready",
1105 "handover", "stop-ack";
1107 clocks = <&rpmhcc RPMH_CXO_CLK>;
1110 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1113 power-domain-names = "load_state", "lcx", "lmx";
1115 memory-region = <&pil_slpi_mem>;
1117 qcom,smem-states = <&smp2p_slpi_out 0>;
1118 qcom,smem-state-names = "stop";
1120 status = "disabled";
1123 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1124 IPCC_MPROC_SIGNAL_GLINK_QMP
1125 IRQ_TYPE_EDGE_RISING>;
1126 mboxes = <&ipcc IPCC_CLIENT_SLPI
1127 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1130 qcom,remote-pid = <3>;
1135 cdsp: remoteproc@98900000 {
1136 compatible = "qcom,sm8350-cdsp-pas";
1137 reg = <0 0x098900000 0 0x1400000>;
1139 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1140 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1141 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1142 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1143 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1144 interrupt-names = "wdog", "fatal", "ready",
1145 "handover", "stop-ack";
1147 clocks = <&rpmhcc RPMH_CXO_CLK>;
1150 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1153 power-domain-names = "load_state", "cx", "mxc";
1155 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
1157 memory-region = <&pil_cdsp_mem>;
1159 qcom,smem-states = <&smp2p_cdsp_out 0>;
1160 qcom,smem-state-names = "stop";
1162 status = "disabled";
1165 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1166 IPCC_MPROC_SIGNAL_GLINK_QMP
1167 IRQ_TYPE_EDGE_RISING>;
1168 mboxes = <&ipcc IPCC_CLIENT_CDSP
1169 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1172 qcom,remote-pid = <5>;
1176 usb_1_hsphy: phy@88e3000 {
1177 compatible = "qcom,sm8350-usb-hs-phy",
1178 "qcom,usb-snps-hs-7nm-phy";
1179 reg = <0 0x088e3000 0 0x400>;
1180 status = "disabled";
1183 clocks = <&rpmhcc RPMH_CXO_CLK>;
1184 clock-names = "ref";
1186 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1189 usb_2_hsphy: phy@88e4000 {
1190 compatible = "qcom,sm8250-usb-hs-phy",
1191 "qcom,usb-snps-hs-7nm-phy";
1192 reg = <0 0x088e4000 0 0x400>;
1193 status = "disabled";
1196 clocks = <&rpmhcc RPMH_CXO_CLK>;
1197 clock-names = "ref";
1199 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1202 usb_1_qmpphy: phy-wrapper@88e9000 {
1203 compatible = "qcom,sm8350-qmp-usb3-phy";
1204 reg = <0 0x088e9000 0 0x200>,
1205 <0 0x088e8000 0 0x20>;
1206 reg-names = "reg-base", "dp_com";
1207 status = "disabled";
1209 #address-cells = <2>;
1213 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1214 <&rpmhcc RPMH_CXO_CLK>,
1215 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1216 clock-names = "aux", "ref_clk_src", "com_aux";
1218 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1219 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1220 reset-names = "phy", "common";
1222 usb_1_ssphy: phy@88e9200 {
1223 reg = <0 0x088e9200 0 0x200>,
1224 <0 0x088e9400 0 0x200>,
1225 <0 0x088e9c00 0 0x400>,
1226 <0 0x088e9600 0 0x200>,
1227 <0 0x088e9800 0 0x200>,
1228 <0 0x088e9a00 0 0x100>;
1231 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1232 clock-names = "pipe0";
1233 clock-output-names = "usb3_phy_pipe_clk_src";
1237 usb_2_qmpphy: phy-wrapper@88eb000 {
1238 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
1239 reg = <0 0x088eb000 0 0x200>;
1240 status = "disabled";
1242 #address-cells = <2>;
1246 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1247 <&rpmhcc RPMH_CXO_CLK>,
1248 <&gcc GCC_USB3_SEC_CLKREF_EN>,
1249 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1250 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1252 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1253 <&gcc GCC_USB3_PHY_SEC_BCR>;
1254 reset-names = "phy", "common";
1256 usb_2_ssphy: phy@88ebe00 {
1257 reg = <0 0x088ebe00 0 0x200>,
1258 <0 0x088ec000 0 0x200>,
1259 <0 0x088eb200 0 0x1100>;
1262 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1263 clock-names = "pipe0";
1264 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1268 dc_noc: interconnect@90c0000 {
1269 compatible = "qcom,sm8350-dc-noc";
1270 reg = <0 0x090c0000 0 0x4200>;
1271 #interconnect-cells = <1>;
1272 qcom,bcm-voters = <&apps_bcm_voter>;
1275 gem_noc: interconnect@9100000 {
1276 compatible = "qcom,sm8350-gem-noc";
1277 reg = <0 0x09100000 0 0xb4000>;
1278 #interconnect-cells = <1>;
1279 qcom,bcm-voters = <&apps_bcm_voter>;
1282 usb_1: usb@a6f8800 {
1283 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1284 reg = <0 0x0a6f8800 0 0x400>;
1285 status = "disabled";
1286 #address-cells = <2>;
1290 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1291 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1292 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1293 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1294 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1295 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1298 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1299 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1300 assigned-clock-rates = <19200000>, <200000000>;
1302 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1303 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1304 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1305 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1306 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1307 "dm_hs_phy_irq", "ss_phy_irq";
1309 power-domains = <&gcc USB30_PRIM_GDSC>;
1311 resets = <&gcc GCC_USB30_PRIM_BCR>;
1313 usb_1_dwc3: usb@a600000 {
1314 compatible = "snps,dwc3";
1315 reg = <0 0x0a600000 0 0xcd00>;
1316 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1317 iommus = <&apps_smmu 0x0 0x0>;
1318 snps,dis_u2_susphy_quirk;
1319 snps,dis_enblslpm_quirk;
1320 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1321 phy-names = "usb2-phy", "usb3-phy";
1325 usb_2: usb@a8f8800 {
1326 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1327 reg = <0 0x0a8f8800 0 0x400>;
1328 status = "disabled";
1329 #address-cells = <2>;
1333 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1334 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1335 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1336 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1337 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1338 <&gcc GCC_USB3_SEC_CLKREF_EN>;
1339 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1342 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1343 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1344 assigned-clock-rates = <19200000>, <200000000>;
1346 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1347 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1348 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1349 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1350 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1351 "dm_hs_phy_irq", "ss_phy_irq";
1353 power-domains = <&gcc USB30_SEC_GDSC>;
1355 resets = <&gcc GCC_USB30_SEC_BCR>;
1357 usb_2_dwc3: usb@a800000 {
1358 compatible = "snps,dwc3";
1359 reg = <0 0x0a800000 0 0xcd00>;
1360 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1361 iommus = <&apps_smmu 0x20 0x0>;
1362 snps,dis_u2_susphy_quirk;
1363 snps,dis_enblslpm_quirk;
1364 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1365 phy-names = "usb2-phy", "usb3-phy";
1369 adsp: remoteproc@17300000 {
1370 compatible = "qcom,sm8350-adsp-pas";
1371 reg = <0 0x17300000 0 0x100>;
1373 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1374 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1375 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1376 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1377 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1378 interrupt-names = "wdog", "fatal", "ready",
1379 "handover", "stop-ack";
1381 clocks = <&rpmhcc RPMH_CXO_CLK>;
1384 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1387 power-domain-names = "load_state", "lcx", "lmx";
1389 memory-region = <&pil_adsp_mem>;
1391 qcom,smem-states = <&smp2p_adsp_out 0>;
1392 qcom,smem-state-names = "stop";
1394 status = "disabled";
1397 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1398 IPCC_MPROC_SIGNAL_GLINK_QMP
1399 IRQ_TYPE_EDGE_RISING>;
1400 mboxes = <&ipcc IPCC_CLIENT_LPASS
1401 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1404 qcom,remote-pid = <2>;
1409 thermal_zones: thermal-zones {
1411 polling-delay-passive = <250>;
1412 polling-delay = <1000>;
1414 thermal-sensors = <&tsens0 1>;
1417 cpu0_alert0: trip-point0 {
1418 temperature = <90000>;
1419 hysteresis = <2000>;
1423 cpu0_alert1: trip-point1 {
1424 temperature = <95000>;
1425 hysteresis = <2000>;
1429 cpu0_crit: cpu_crit {
1430 temperature = <110000>;
1431 hysteresis = <1000>;
1438 trip = <&cpu0_alert0>;
1439 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1440 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1441 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1442 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1445 trip = <&cpu0_alert1>;
1446 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1447 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1448 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1449 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1455 polling-delay-passive = <250>;
1456 polling-delay = <1000>;
1458 thermal-sensors = <&tsens0 2>;
1461 cpu1_alert0: trip-point0 {
1462 temperature = <90000>;
1463 hysteresis = <2000>;
1467 cpu1_alert1: trip-point1 {
1468 temperature = <95000>;
1469 hysteresis = <2000>;
1473 cpu1_crit: cpu_crit {
1474 temperature = <110000>;
1475 hysteresis = <1000>;
1482 trip = <&cpu1_alert0>;
1483 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1484 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1485 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1486 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1489 trip = <&cpu1_alert1>;
1490 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1491 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1492 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1493 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1499 polling-delay-passive = <250>;
1500 polling-delay = <1000>;
1502 thermal-sensors = <&tsens0 3>;
1505 cpu2_alert0: trip-point0 {
1506 temperature = <90000>;
1507 hysteresis = <2000>;
1511 cpu2_alert1: trip-point1 {
1512 temperature = <95000>;
1513 hysteresis = <2000>;
1517 cpu2_crit: cpu_crit {
1518 temperature = <110000>;
1519 hysteresis = <1000>;
1526 trip = <&cpu2_alert0>;
1527 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1528 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1529 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1530 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1533 trip = <&cpu2_alert1>;
1534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1535 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1536 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1537 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1543 polling-delay-passive = <250>;
1544 polling-delay = <1000>;
1546 thermal-sensors = <&tsens0 4>;
1549 cpu3_alert0: trip-point0 {
1550 temperature = <90000>;
1551 hysteresis = <2000>;
1555 cpu3_alert1: trip-point1 {
1556 temperature = <95000>;
1557 hysteresis = <2000>;
1561 cpu3_crit: cpu_crit {
1562 temperature = <110000>;
1563 hysteresis = <1000>;
1570 trip = <&cpu3_alert0>;
1571 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1572 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1573 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1574 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1577 trip = <&cpu3_alert1>;
1578 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1579 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1580 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1581 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1587 polling-delay-passive = <250>;
1588 polling-delay = <1000>;
1590 thermal-sensors = <&tsens0 7>;
1593 cpu4_top_alert0: trip-point0 {
1594 temperature = <90000>;
1595 hysteresis = <2000>;
1599 cpu4_top_alert1: trip-point1 {
1600 temperature = <95000>;
1601 hysteresis = <2000>;
1605 cpu4_top_crit: cpu_crit {
1606 temperature = <110000>;
1607 hysteresis = <1000>;
1614 trip = <&cpu4_top_alert0>;
1615 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1616 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1617 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1618 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1621 trip = <&cpu4_top_alert1>;
1622 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1623 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1624 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1625 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1631 polling-delay-passive = <250>;
1632 polling-delay = <1000>;
1634 thermal-sensors = <&tsens0 8>;
1637 cpu5_top_alert0: trip-point0 {
1638 temperature = <90000>;
1639 hysteresis = <2000>;
1643 cpu5_top_alert1: trip-point1 {
1644 temperature = <95000>;
1645 hysteresis = <2000>;
1649 cpu5_top_crit: cpu_crit {
1650 temperature = <110000>;
1651 hysteresis = <1000>;
1658 trip = <&cpu5_top_alert0>;
1659 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1660 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1661 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1662 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1665 trip = <&cpu5_top_alert1>;
1666 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1667 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1668 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1669 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1675 polling-delay-passive = <250>;
1676 polling-delay = <1000>;
1678 thermal-sensors = <&tsens0 9>;
1681 cpu6_top_alert0: trip-point0 {
1682 temperature = <90000>;
1683 hysteresis = <2000>;
1687 cpu6_top_alert1: trip-point1 {
1688 temperature = <95000>;
1689 hysteresis = <2000>;
1693 cpu6_top_crit: cpu_crit {
1694 temperature = <110000>;
1695 hysteresis = <1000>;
1702 trip = <&cpu6_top_alert0>;
1703 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1704 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1705 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1706 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1709 trip = <&cpu6_top_alert1>;
1710 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1711 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1712 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1713 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1719 polling-delay-passive = <250>;
1720 polling-delay = <1000>;
1722 thermal-sensors = <&tsens0 10>;
1725 cpu7_top_alert0: trip-point0 {
1726 temperature = <90000>;
1727 hysteresis = <2000>;
1731 cpu7_top_alert1: trip-point1 {
1732 temperature = <95000>;
1733 hysteresis = <2000>;
1737 cpu7_top_crit: cpu_crit {
1738 temperature = <110000>;
1739 hysteresis = <1000>;
1746 trip = <&cpu7_top_alert0>;
1747 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1748 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1749 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1750 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1753 trip = <&cpu7_top_alert1>;
1754 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1755 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1756 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1757 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1762 cpu4-bottom-thermal {
1763 polling-delay-passive = <250>;
1764 polling-delay = <1000>;
1766 thermal-sensors = <&tsens0 11>;
1769 cpu4_bottom_alert0: trip-point0 {
1770 temperature = <90000>;
1771 hysteresis = <2000>;
1775 cpu4_bottom_alert1: trip-point1 {
1776 temperature = <95000>;
1777 hysteresis = <2000>;
1781 cpu4_bottom_crit: cpu_crit {
1782 temperature = <110000>;
1783 hysteresis = <1000>;
1790 trip = <&cpu4_bottom_alert0>;
1791 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1792 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1793 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1794 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1797 trip = <&cpu4_bottom_alert1>;
1798 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1799 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1800 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1801 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1806 cpu5-bottom-thermal {
1807 polling-delay-passive = <250>;
1808 polling-delay = <1000>;
1810 thermal-sensors = <&tsens0 12>;
1813 cpu5_bottom_alert0: trip-point0 {
1814 temperature = <90000>;
1815 hysteresis = <2000>;
1819 cpu5_bottom_alert1: trip-point1 {
1820 temperature = <95000>;
1821 hysteresis = <2000>;
1825 cpu5_bottom_crit: cpu_crit {
1826 temperature = <110000>;
1827 hysteresis = <1000>;
1834 trip = <&cpu5_bottom_alert0>;
1835 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1836 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1837 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1838 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1841 trip = <&cpu5_bottom_alert1>;
1842 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1843 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1844 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1845 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1850 cpu6-bottom-thermal {
1851 polling-delay-passive = <250>;
1852 polling-delay = <1000>;
1854 thermal-sensors = <&tsens0 13>;
1857 cpu6_bottom_alert0: trip-point0 {
1858 temperature = <90000>;
1859 hysteresis = <2000>;
1863 cpu6_bottom_alert1: trip-point1 {
1864 temperature = <95000>;
1865 hysteresis = <2000>;
1869 cpu6_bottom_crit: cpu_crit {
1870 temperature = <110000>;
1871 hysteresis = <1000>;
1878 trip = <&cpu6_bottom_alert0>;
1879 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1880 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1881 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1882 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1885 trip = <&cpu6_bottom_alert1>;
1886 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1887 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1888 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1889 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1894 cpu7-bottom-thermal {
1895 polling-delay-passive = <250>;
1896 polling-delay = <1000>;
1898 thermal-sensors = <&tsens0 14>;
1901 cpu7_bottom_alert0: trip-point0 {
1902 temperature = <90000>;
1903 hysteresis = <2000>;
1907 cpu7_bottom_alert1: trip-point1 {
1908 temperature = <95000>;
1909 hysteresis = <2000>;
1913 cpu7_bottom_crit: cpu_crit {
1914 temperature = <110000>;
1915 hysteresis = <1000>;
1922 trip = <&cpu7_bottom_alert0>;
1923 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1924 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1925 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1926 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1929 trip = <&cpu7_bottom_alert1>;
1930 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1931 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1932 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1933 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1939 polling-delay-passive = <250>;
1940 polling-delay = <1000>;
1942 thermal-sensors = <&tsens0 0>;
1945 aoss0_alert0: trip-point0 {
1946 temperature = <90000>;
1947 hysteresis = <2000>;
1954 polling-delay-passive = <250>;
1955 polling-delay = <1000>;
1957 thermal-sensors = <&tsens0 5>;
1960 cluster0_alert0: trip-point0 {
1961 temperature = <90000>;
1962 hysteresis = <2000>;
1965 cluster0_crit: cluster0_crit {
1966 temperature = <110000>;
1967 hysteresis = <2000>;
1974 polling-delay-passive = <250>;
1975 polling-delay = <1000>;
1977 thermal-sensors = <&tsens0 6>;
1980 cluster1_alert0: trip-point0 {
1981 temperature = <90000>;
1982 hysteresis = <2000>;
1985 cluster1_crit: cluster1_crit {
1986 temperature = <110000>;
1987 hysteresis = <2000>;
1994 polling-delay-passive = <250>;
1995 polling-delay = <1000>;
1997 thermal-sensors = <&tsens1 0>;
2000 aoss1_alert0: trip-point0 {
2001 temperature = <90000>;
2002 hysteresis = <2000>;
2009 polling-delay-passive = <250>;
2010 polling-delay = <1000>;
2012 thermal-sensors = <&tsens1 1>;
2015 gpu1_alert0: trip-point0 {
2016 temperature = <90000>;
2017 hysteresis = <1000>;
2023 gpu-thermal-bottom {
2024 polling-delay-passive = <250>;
2025 polling-delay = <1000>;
2027 thermal-sensors = <&tsens1 2>;
2030 gpu2_alert0: trip-point0 {
2031 temperature = <90000>;
2032 hysteresis = <1000>;
2039 polling-delay-passive = <250>;
2040 polling-delay = <1000>;
2042 thermal-sensors = <&tsens1 3>;
2045 nspss1_alert0: trip-point0 {
2046 temperature = <90000>;
2047 hysteresis = <1000>;
2054 polling-delay-passive = <250>;
2055 polling-delay = <1000>;
2057 thermal-sensors = <&tsens1 4>;
2060 nspss2_alert0: trip-point0 {
2061 temperature = <90000>;
2062 hysteresis = <1000>;
2069 polling-delay-passive = <250>;
2070 polling-delay = <1000>;
2072 thermal-sensors = <&tsens1 5>;
2075 nspss3_alert0: trip-point0 {
2076 temperature = <90000>;
2077 hysteresis = <1000>;
2084 polling-delay-passive = <250>;
2085 polling-delay = <1000>;
2087 thermal-sensors = <&tsens1 6>;
2090 video_alert0: trip-point0 {
2091 temperature = <90000>;
2092 hysteresis = <2000>;
2099 polling-delay-passive = <250>;
2100 polling-delay = <1000>;
2102 thermal-sensors = <&tsens1 7>;
2105 mem_alert0: trip-point0 {
2106 temperature = <90000>;
2107 hysteresis = <2000>;
2113 modem1-thermal-top {
2114 polling-delay-passive = <250>;
2115 polling-delay = <1000>;
2117 thermal-sensors = <&tsens1 8>;
2120 modem1_alert0: trip-point0 {
2121 temperature = <90000>;
2122 hysteresis = <2000>;
2128 modem2-thermal-top {
2129 polling-delay-passive = <250>;
2130 polling-delay = <1000>;
2132 thermal-sensors = <&tsens1 9>;
2135 modem2_alert0: trip-point0 {
2136 temperature = <90000>;
2137 hysteresis = <2000>;
2143 modem3-thermal-top {
2144 polling-delay-passive = <250>;
2145 polling-delay = <1000>;
2147 thermal-sensors = <&tsens1 10>;
2150 modem3_alert0: trip-point0 {
2151 temperature = <90000>;
2152 hysteresis = <2000>;
2158 modem4-thermal-top {
2159 polling-delay-passive = <250>;
2160 polling-delay = <1000>;
2162 thermal-sensors = <&tsens1 11>;
2165 modem4_alert0: trip-point0 {
2166 temperature = <90000>;
2167 hysteresis = <2000>;
2173 camera-thermal-top {
2174 polling-delay-passive = <250>;
2175 polling-delay = <1000>;
2177 thermal-sensors = <&tsens1 12>;
2180 camera1_alert0: trip-point0 {
2181 temperature = <90000>;
2182 hysteresis = <2000>;
2188 camera-thermal-bottom {
2189 polling-delay-passive = <250>;
2190 polling-delay = <1000>;
2192 thermal-sensors = <&tsens1 13>;
2195 camera2_alert0: trip-point0 {
2196 temperature = <90000>;
2197 hysteresis = <2000>;
2205 compatible = "arm,armv8-timer";
2206 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2207 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2208 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2209 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;