arch/arm64/boot/dts/qcom/sm8350.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/interconnect/qcom,sm8350.h>
  10 #include <dt-bindings/mailbox/qcom-ipcc.h>
  11 #include <dt-bindings/power/qcom-aoss-qmp.h>
  12 #include <dt-bindings/power/qcom-rpmpd.h>
  13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15 #include <dt-bindings/interconnect/qcom,sm8350.h>
  16
  17 / {
  18         interrupt-parent = <&intc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         clocks {
  26                 xo_board: xo-board {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <38400000>;
  30                         clock-output-names = "xo_board";
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         clock-frequency = <32000>;
  36                         #clock-cells = <0>;
  37                 };
  38         };
  39
  40         cpus {
  41                 #address-cells = <2>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "qcom,kryo685";
  47                         reg = <0x0 0x0>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&L2_0>;
  50                         qcom,freq-domain = <&cpufreq_hw 0>;
  51                         #cooling-cells = <2>;
  52                         L2_0: l2-cache {
  53                               compatible = "cache";
  54                               next-level-cache = <&L3_0>;
  55                                 L3_0: l3-cache {
  56                                       compatible = "cache";
  57                                 };
  58                         };
  59                 };
  60
  61                 CPU1: cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "qcom,kryo685";
  64                         reg = <0x0 0x100>;
  65                         enable-method = "psci";
  66                         next-level-cache = <&L2_100>;
  67                         qcom,freq-domain = <&cpufreq_hw 0>;
  68                         #cooling-cells = <2>;
  69                         L2_100: l2-cache {
  70                               compatible = "cache";
  71                               next-level-cache = <&L3_0>;
  72                         };
  73                 };
  74
  75                 CPU2: cpu@200 {
  76                         device_type = "cpu";
  77                         compatible = "qcom,kryo685";
  78                         reg = <0x0 0x200>;
  79                         enable-method = "psci";
  80                         next-level-cache = <&L2_200>;
  81                         qcom,freq-domain = <&cpufreq_hw 0>;
  82                         #cooling-cells = <2>;
  83                         L2_200: l2-cache {
  84                               compatible = "cache";
  85                               next-level-cache = <&L3_0>;
  86                         };
  87                 };
  88
  89                 CPU3: cpu@300 {
  90                         device_type = "cpu";
  91                         compatible = "qcom,kryo685";
  92                         reg = <0x0 0x300>;
  93                         enable-method = "psci";
  94                         next-level-cache = <&L2_300>;
  95                         qcom,freq-domain = <&cpufreq_hw 0>;
  96                         #cooling-cells = <2>;
  97                         L2_300: l2-cache {
  98                               compatible = "cache";
  99                               next-level-cache = <&L3_0>;
 100                         };
 101                 };
 102
 103                 CPU4: cpu@400 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo685";
 106                         reg = <0x0 0x400>;
 107                         enable-method = "psci";
 108                         next-level-cache = <&L2_400>;
 109                         qcom,freq-domain = <&cpufreq_hw 1>;
 110                         #cooling-cells = <2>;
 111                         L2_400: l2-cache {
 112                               compatible = "cache";
 113                               next-level-cache = <&L3_0>;
 114                         };
 115                 };
 116
 117                 CPU5: cpu@500 {
 118                         device_type = "cpu";
 119                         compatible = "qcom,kryo685";
 120                         reg = <0x0 0x500>;
 121                         enable-method = "psci";
 122                         next-level-cache = <&L2_500>;
 123                         qcom,freq-domain = <&cpufreq_hw 1>;
 124                         #cooling-cells = <2>;
 125                         L2_500: l2-cache {
 126                               compatible = "cache";
 127                               next-level-cache = <&L3_0>;
 128                         };
 129
 130                 };
 131
 132                 CPU6: cpu@600 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo685";
 135                         reg = <0x0 0x600>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&L2_600>;
 138                         qcom,freq-domain = <&cpufreq_hw 1>;
 139                         #cooling-cells = <2>;
 140                         L2_600: l2-cache {
 141                               compatible = "cache";
 142                               next-level-cache = <&L3_0>;
 143                         };
 144                 };
 145
 146                 CPU7: cpu@700 {
 147                         device_type = "cpu";
 148                         compatible = "qcom,kryo685";
 149                         reg = <0x0 0x700>;
 150                         enable-method = "psci";
 151                         next-level-cache = <&L2_700>;
 152                         qcom,freq-domain = <&cpufreq_hw 2>;
 153                         #cooling-cells = <2>;
 154                         L2_700: l2-cache {
 155                               compatible = "cache";
 156                               next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159         };
 160
 161         firmware {
 162                 scm: scm {
 163                         compatible = "qcom,scm-sm8350", "qcom,scm";
 164                         #reset-cells = <1>;
 165                 };
 166         };
 167
 168         memory@80000000 {
 169                 device_type = "memory";
 170                 /* We expect the bootloader to fill in the size */
 171                 reg = <0x0 0x80000000 0x0 0x0>;
 172         };
 173
 174         pmu {
 175                 compatible = "arm,armv8-pmuv3";
 176                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 177         };
 178
 179         psci {
 180                 compatible = "arm,psci-1.0";
 181                 method = "smc";
 182         };
 183
 184         reserved_memory: reserved-memory {
 185                 #address-cells = <2>;
 186                 #size-cells = <2>;
 187                 ranges;
 188
 189                 hyp_mem: memory@80000000 {
 190                         reg = <0x0 0x80000000 0x0 0x600000>;
 191                         no-map;
 192                 };
 193
 194                 xbl_aop_mem: memory@80700000 {
 195                         no-map;
 196                         reg = <0x0 0x80700000 0x0 0x160000>;
 197                 };
 198
 199                 cmd_db: memory@80860000 {
 200                         compatible = "qcom,cmd-db";
 201                         reg = <0x0 0x80860000 0x0 0x20000>;
 202                         no-map;
 203                 };
 204
 205                 reserved_xbl_uefi_log: memory@80880000 {
 206                         reg = <0x0 0x80880000 0x0 0x14000>;
 207                         no-map;
 208                 };
 209
 210                 smem_mem: memory@80900000 {
 211                         reg = <0x0 0x80900000 0x0 0x200000>;
 212                         no-map;
 213                 };
 214
 215                 cpucp_fw_mem: memory@80b00000 {
 216                         reg = <0x0 0x80b00000 0x0 0x100000>;
 217                         no-map;
 218                 };
 219
 220                 cdsp_secure_heap: memory@80c00000 {
 221                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 222                         no-map;
 223                 };
 224
 225                 pil_camera_mem: mmeory@85200000 {
 226                         reg = <0x0 0x85200000 0x0 0x500000>;
 227                         no-map;
 228                 };
 229
 230                 pil_video_mem: memory@85700000 {
 231                         reg = <0x0 0x85700000 0x0 0x500000>;
 232                         no-map;
 233                 };
 234
 235                 pil_cvp_mem: memory@85c00000 {
 236                         reg = <0x0 0x85c00000 0x0 0x500000>;
 237                         no-map;
 238                 };
 239
 240                 pil_adsp_mem: memory@86100000 {
 241                         reg = <0x0 0x86100000 0x0 0x2100000>;
 242                         no-map;
 243                 };
 244
 245                 pil_slpi_mem: memory@88200000 {
 246                         reg = <0x0 0x88200000 0x0 0x1500000>;
 247                         no-map;
 248                 };
 249
 250                 pil_cdsp_mem: memory@89700000 {
 251                         reg = <0x0 0x89700000 0x0 0x1e00000>;
 252                         no-map;
 253                 };
 254
 255                 pil_ipa_fw_mem: memory@8b500000 {
 256                         reg = <0x0 0x8b500000 0x0 0x10000>;
 257                         no-map;
 258                 };
 259
 260                 pil_ipa_gsi_mem: memory@8b510000 {
 261                         reg = <0x0 0x8b510000 0x0 0xa000>;
 262                         no-map;
 263                 };
 264
 265                 pil_gpu_mem: memory@8b51a000 {
 266                         reg = <0x0 0x8b51a000 0x0 0x2000>;
 267                         no-map;
 268                 };
 269
 270                 pil_spss_mem: memory@8b600000 {
 271                         reg = <0x0 0x8b600000 0x0 0x100000>;
 272                         no-map;
 273                 };
 274
 275                 pil_modem_mem: memory@8b800000 {
 276                         reg = <0x0 0x8b800000 0x0 0x10000000>;
 277                         no-map;
 278                 };
 279
 280                 rmtfs_mem: memory@9b800000 {
 281                         compatible = "qcom,rmtfs-mem";
 282                         reg = <0x0 0x9b800000 0x0 0x280000>;
 283                         no-map;
 284
 285                         qcom,client-id = <1>;
 286                         qcom,vmid = <15>;
 287                 };
 288
 289                 hyp_reserved_mem: memory@d0000000 {
 290                         reg = <0x0 0xd0000000 0x0 0x800000>;
 291                         no-map;
 292                 };
 293
 294                 pil_trustedvm_mem: memory@d0800000 {
 295                         reg = <0x0 0xd0800000 0x0 0x76f7000>;
 296                         no-map;
 297                 };
 298
 299                 qrtr_shbuf: memory@d7ef7000 {
 300                         reg = <0x0 0xd7ef7000 0x0 0x9000>;
 301                         no-map;
 302                 };
 303
 304                 chan0_shbuf: memory@d7f00000 {
 305                         reg = <0x0 0xd7f00000 0x0 0x80000>;
 306                         no-map;
 307                 };
 308
 309                 chan1_shbuf: memory@d7f80000 {
 310                         reg = <0x0 0xd7f80000 0x0 0x80000>;
 311                         no-map;
 312                 };
 313
 314                 removed_mem: memory@d8800000 {
 315                         reg = <0x0 0xd8800000 0x0 0x6800000>;
 316                         no-map;
 317                 };
 318         };
 319
 320         smem: qcom,smem {
 321                 compatible = "qcom,smem";
 322                 memory-region = <&smem_mem>;
 323                 hwlocks = <&tcsr_mutex 3>;
 324         };
 325
 326         smp2p-adsp {
 327                 compatible = "qcom,smp2p";
 328                 qcom,smem = <443>, <429>;
 329                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 330                                              IPCC_MPROC_SIGNAL_SMP2P
 331                                              IRQ_TYPE_EDGE_RISING>;
 332                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 333                                 IPCC_MPROC_SIGNAL_SMP2P>;
 334
 335                 qcom,local-pid = <0>;
 336                 qcom,remote-pid = <2>;
 337
 338                 smp2p_adsp_out: master-kernel {
 339                         qcom,entry-name = "master-kernel";
 340                         #qcom,smem-state-cells = <1>;
 341                 };
 342
 343                 smp2p_adsp_in: slave-kernel {
 344                         qcom,entry-name = "slave-kernel";
 345                         interrupt-controller;
 346                         #interrupt-cells = <2>;
 347                 };
 348         };
 349
 350         smp2p-cdsp {
 351                 compatible = "qcom,smp2p";
 352                 qcom,smem = <94>, <432>;
 353                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 354                                              IPCC_MPROC_SIGNAL_SMP2P
 355                                              IRQ_TYPE_EDGE_RISING>;
 356                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 357                                 IPCC_MPROC_SIGNAL_SMP2P>;
 358
 359                 qcom,local-pid = <0>;
 360                 qcom,remote-pid = <5>;
 361
 362                 smp2p_cdsp_out: master-kernel {
 363                         qcom,entry-name = "master-kernel";
 364                         #qcom,smem-state-cells = <1>;
 365                 };
 366
 367                 smp2p_cdsp_in: slave-kernel {
 368                         qcom,entry-name = "slave-kernel";
 369                         interrupt-controller;
 370                         #interrupt-cells = <2>;
 371                 };
 372         };
 373
 374         smp2p-modem {
 375                 compatible = "qcom,smp2p";
 376                 qcom,smem = <435>, <428>;
 377                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 378                                              IPCC_MPROC_SIGNAL_SMP2P
 379                                              IRQ_TYPE_EDGE_RISING>;
 380                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 381                                 IPCC_MPROC_SIGNAL_SMP2P>;
 382
 383                 qcom,local-pid = <0>;
 384                 qcom,remote-pid = <1>;
 385
 386                 smp2p_modem_out: master-kernel {
 387                         qcom,entry-name = "master-kernel";
 388                         #qcom,smem-state-cells = <1>;
 389                 };
 390
 391                 smp2p_modem_in: slave-kernel {
 392                         qcom,entry-name = "slave-kernel";
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                 };
 396
 397                 ipa_smp2p_out: ipa-ap-to-modem {
 398                         qcom,entry-name = "ipa";
 399                         #qcom,smem-state-cells = <1>;
 400                 };
 401
 402                 ipa_smp2p_in: ipa-modem-to-ap {
 403                         qcom,entry-name = "ipa";
 404                         interrupt-controller;
 405                         #interrupt-cells = <2>;
 406                 };
 407         };
 408
 409         smp2p-slpi {
 410                 compatible = "qcom,smp2p";
 411                 qcom,smem = <481>, <430>;
 412                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 413                                              IPCC_MPROC_SIGNAL_SMP2P
 414                                              IRQ_TYPE_EDGE_RISING>;
 415                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 416                                 IPCC_MPROC_SIGNAL_SMP2P>;
 417
 418                 qcom,local-pid = <0>;
 419                 qcom,remote-pid = <3>;
 420
 421                 smp2p_slpi_out: master-kernel {
 422                         qcom,entry-name = "master-kernel";
 423                         #qcom,smem-state-cells = <1>;
 424                 };
 425
 426                 smp2p_slpi_in: slave-kernel {
 427                         qcom,entry-name = "slave-kernel";
 428                         interrupt-controller;
 429                         #interrupt-cells = <2>;
 430                 };
 431         };
 432
 433         soc: soc@0 {
 434                 #address-cells = <2>;
 435                 #size-cells = <2>;
 436                 ranges = <0 0 0 0 0x10 0>;
 437                 dma-ranges = <0 0 0 0 0x10 0>;
 438                 compatible = "simple-bus";
 439
 440                 gcc: clock-controller@100000 {
 441                         compatible = "qcom,gcc-sm8350";
 442                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 443                         #clock-cells = <1>;
 444                         #reset-cells = <1>;
 445                         #power-domain-cells = <1>;
 446                         clock-names = "bi_tcxo", "sleep_clk";
 447                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
 448                 };
 449
 450                 ipcc: mailbox@408000 {
 451                         compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
 452                         reg = <0 0x00408000 0 0x1000>;
 453                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 454                         interrupt-controller;
 455                         #interrupt-cells = <3>;
 456                         #mbox-cells = <2>;
 457                 };
 458
 459                 qupv3_id_1: geniqup@9c0000 {
 460                         compatible = "qcom,geni-se-qup";
 461                         reg = <0x0 0x009c0000 0x0 0x6000>;
 462                         clock-names = "m-ahb", "s-ahb";
 463                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 464                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 465                         #address-cells = <2>;
 466                         #size-cells = <2>;
 467                         ranges;
 468                         status = "disabled";
 469
 470                         uart2: serial@98c000 {
 471                                 compatible = "qcom,geni-debug-uart";
 472                                 reg = <0 0x0098c000 0 0x4000>;
 473                                 clock-names = "se";
 474                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 475                                 pinctrl-names = "default";
 476                                 pinctrl-0 = <&qup_uart3_default_state>;
 477                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 478                                 #address-cells = <1>;
 479                                 #size-cells = <0>;
 480                                 status = "disabled";
 481                         };
 482                 };
 483
 484                 apps_smmu: iommu@15000000 {
 485                         compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
 486                         reg = <0 0x15000000 0 0x100000>;
 487                         #iommu-cells = <2>;
 488                         #global-interrupts = <2>;
 489                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 490                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 491                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 492                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 493                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 494                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 495                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 496                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 497                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 498                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 499                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 500                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 501                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 502                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 503                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 504                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 505                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 506                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 507                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 508                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 509                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 510                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 511                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 512                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 513                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 514                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 515                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 516                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 517                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 518                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 519                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 520                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 521                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 522                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 523                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 524                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 525                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 526                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 527                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 528                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 529                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 530                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 531                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
 532                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
 533                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
 534                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
 535                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
 536                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 537                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
 538                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 539                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 540                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 541                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 542                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 543                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 544                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 545                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 546                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 547                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 548                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 549                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 550                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 551                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 552                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 553                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 554                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 555                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 556                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 557                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 558                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 559                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 560                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 561                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 562                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 563                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 564                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 565                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 566                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 567                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
 568                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 569                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
 570                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
 571                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
 572                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 573                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 574                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 575                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 576                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 577                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 578                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
 579                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
 580                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
 581                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
 582                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
 583                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
 584                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
 585                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
 586                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
 587                 };
 588
 589                 config_noc: interconnect@1500000 {
 590                         compatible = "qcom,sm8350-config-noc";
 591                         reg = <0 0x01500000 0 0xa580>;
 592                         #interconnect-cells = <1>;
 593                         qcom,bcm-voters = <&apps_bcm_voter>;
 594                 };
 595
 596                 mc_virt: interconnect@1580000 {
 597                         compatible = "qcom,sm8350-mc-virt";
 598                         reg = <0 0x01580000 0 0x1000>;
 599                         #interconnect-cells = <1>;
 600                         qcom,bcm-voters = <&apps_bcm_voter>;
 601                 };
 602
 603                 system_noc: interconnect@1680000 {
 604                         compatible = "qcom,sm8350-system-noc";
 605                         reg = <0 0x01680000 0 0x1c200>;
 606                         #interconnect-cells = <1>;
 607                         qcom,bcm-voters = <&apps_bcm_voter>;
 608                 };
 609
 610                 aggre1_noc: interconnect@16e0000 {
 611                         compatible = "qcom,sm8350-aggre1-noc";
 612                         reg = <0 0x016e0000 0 0x1f180>;
 613                         #interconnect-cells = <1>;
 614                         qcom,bcm-voters = <&apps_bcm_voter>;
 615                 };
 616
 617                 aggre2_noc: interconnect@1700000 {
 618                         compatible = "qcom,sm8350-aggre2-noc";
 619                         reg = <0 0x01700000 0 0x33000>;
 620                         #interconnect-cells = <1>;
 621                         qcom,bcm-voters = <&apps_bcm_voter>;
 622                 };
 623
 624                 mmss_noc: interconnect@1740000 {
 625                         compatible = "qcom,sm8350-mmss-noc";
 626                         reg = <0 0x01740000 0 0x1f080>;
 627                         #interconnect-cells = <1>;
 628                         qcom,bcm-voters = <&apps_bcm_voter>;
 629                 };
 630
 631                 lpass_ag_noc: interconnect@3c40000 {
 632                         compatible = "qcom,sm8350-lpass-ag-noc";
 633                         reg = <0 0x03c40000 0 0xf080>;
 634                         #interconnect-cells = <1>;
 635                         qcom,bcm-voters = <&apps_bcm_voter>;
 636                 };
 637
 638                 compute_noc: interconnect@a0c0000{
 639                         compatible = "qcom,sm8350-compute-noc";
 640                         reg = <0 0x0a0c0000 0 0xa180>;
 641                         #interconnect-cells = <1>;
 642                         qcom,bcm-voters = <&apps_bcm_voter>;
 643                 };
 644
 645                 ipa: ipa@1e40000 {
 646                         compatible = "qcom,sm8350-ipa";
 647
 648                         iommus = <&apps_smmu 0x5c0 0x0>,
 649                                  <&apps_smmu 0x5c2 0x0>;
 650                         reg = <0 0x1e40000 0 0x8000>,
 651                               <0 0x1e50000 0 0x4b20>,
 652                               <0 0x1e04000 0 0x23000>;
 653                         reg-names = "ipa-reg",
 654                                     "ipa-shared",
 655                                     "gsi";
 656
 657                         interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
 658                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
 659                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 660                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
 661                         interrupt-names = "ipa",
 662                                           "gsi",
 663                                           "ipa-clock-query",
 664                                           "ipa-setup-ready";
 665
 666                         clocks = <&rpmhcc RPMH_IPA_CLK>;
 667                         clock-names = "core";
 668
 669                         interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
 670                                         <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
 671                                         <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
 672                         interconnect-names = "ipa_to_llcc",
 673                                              "llcc_to_ebi1",
 674                                              "appss_to_ipa";
 675
 676                         qcom,smem-states = <&ipa_smp2p_out 0>,
 677                                            <&ipa_smp2p_out 1>;
 678                         qcom,smem-state-names = "ipa-clock-enabled-valid",
 679                                                 "ipa-clock-enabled";
 680
 681                         status = "disabled";
 682                 };
 683
 684                 tcsr_mutex: hwlock@1f40000 {
 685                         compatible = "qcom,tcsr-mutex";
 686                         reg = <0x0 0x01f40000 0x0 0x40000>;
 687                         #hwlock-cells = <1>;
 688                 };
 689
 690                 mpss: remoteproc@4080000 {
 691                         compatible = "qcom,sm8350-mpss-pas";
 692                         reg = <0x0 0x04080000 0x0 0x4040>;
 693
 694                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
 695                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
 696                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
 697                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
 698                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
 699                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
 700                         interrupt-names = "wdog", "fatal", "ready", "handover",
 701                                           "stop-ack", "shutdown-ack";
 702
 703                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 704                         clock-names = "xo";
 705
 706                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
 707                                         <&rpmhpd 0>,
 708                                         <&rpmhpd 12>;
 709                         power-domain-names = "load_state", "cx", "mss";
 710
 711                         interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
 712
 713                         memory-region = <&pil_modem_mem>;
 714
 715                         qcom,smem-states = <&smp2p_modem_out 0>;
 716                         qcom,smem-state-names = "stop";
 717
 718                         status = "disabled";
 719
 720                         glink-edge {
 721                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 722                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
 723                                                              IRQ_TYPE_EDGE_RISING>;
 724                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 725                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
 726                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
 727                                 label = "modem";
 728                                 qcom,remote-pid = <1>;
 729                         };
 730                 };
 731
 732                 pdc: interrupt-controller@b220000 {
 733                         compatible = "qcom,sm8350-pdc", "qcom,pdc";
 734                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
 735                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
 736                                           <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
 737                                           <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
 738                                           <156 716 12>;
 739                         #interrupt-cells = <2>;
 740                         interrupt-parent = <&intc>;
 741                         interrupt-controller;
 742                 };
 743
 744                 tsens0: thermal-sensor@c263000 {
 745                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
 746                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
 747                               <0 0x0c222000 0 0x8>; /* SROT */
 748                         #qcom,sensors = <15>;
 749                         interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
 751                         interrupt-names = "uplow", "critical";
 752                         #thermal-sensor-cells = <1>;
 753                 };
 754
 755                 tsens1: thermal-sensor@c265000 {
 756                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
 757                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
 758                               <0 0x0c223000 0 0x8>; /* SROT */
 759                         #qcom,sensors = <14>;
 760                         interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
 762                         interrupt-names = "uplow", "critical";
 763                         #thermal-sensor-cells = <1>;
 764                 };
 765
 766                 aoss_qmp: power-controller@c300000 {
 767                         compatible = "qcom,sm8350-aoss-qmp";
 768                         reg = <0 0x0c300000 0 0x100000>;
 769                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
 770                                                      IRQ_TYPE_EDGE_RISING>;
 771                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
 772
 773                         #clock-cells = <0>;
 774                         #power-domain-cells = <1>;
 775                 };
 776
 777                 spmi_bus: spmi@c440000 {
 778                         compatible = "qcom,spmi-pmic-arb";
 779                         reg = <0x0 0xc440000 0x0 0x1100>,
 780                               <0x0 0xc600000 0x0 0x2000000>,
 781                               <0x0 0xe600000 0x0 0x100000>,
 782                               <0x0 0xe700000 0x0 0xa0000>,
 783                               <0x0 0xc40a000 0x0 0x26000>;
 784                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 785                         interrupt-names = "periph_irq";
 786                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
 787                         qcom,ee = <0>;
 788                         qcom,channel = <0>;
 789                         #address-cells = <2>;
 790                         #size-cells = <0>;
 791                         interrupt-controller;
 792                         #interrupt-cells = <4>;
 793                 };
 794
 795                 tlmm: pinctrl@f100000 {
 796                         compatible = "qcom,sm8350-tlmm";
 797                         reg = <0 0x0f100000 0 0x300000>;
 798                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 799                         gpio-controller;
 800                         #gpio-cells = <2>;
 801                         interrupt-controller;
 802                         #interrupt-cells = <2>;
 803                         gpio-ranges = <&tlmm 0 0 204>;
 804
 805                         qup_uart3_default_state: qup-uart3-default-state {
 806                                 rx {
 807                                         pins = "gpio18";
 808                                         function = "qup3";
 809                                 };
 810                                 tx {
 811                                         pins = "gpio19";
 812                                         function = "qup3";
 813                                 };
 814                         };
 815                 };
 816
 817                 rng: rng@10d3000 {
 818                         compatible = "qcom,prng-ee";
 819                         reg = <0 0x010d3000 0 0x1000>;
 820                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
 821                         clock-names = "core";
 822                 };
 823
 824                 intc: interrupt-controller@17a00000 {
 825                         compatible = "arm,gic-v3";
 826                         #interrupt-cells = <3>;
 827                         interrupt-controller;
 828                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
 829                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
 830                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 831                 };
 832
 833                 timer@17c20000 {
 834                         compatible = "arm,armv7-timer-mem";
 835                         #address-cells = <2>;
 836                         #size-cells = <2>;
 837                         ranges;
 838                         reg = <0x0 0x17c20000 0x0 0x1000>;
 839                         clock-frequency = <19200000>;
 840
 841                         frame@17c21000 {
 842                                 frame-number = <0>;
 843                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 844                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 845                                 reg = <0x0 0x17c21000 0x0 0x1000>,
 846                                       <0x0 0x17c22000 0x0 0x1000>;
 847                         };
 848
 849                         frame@17c23000 {
 850                                 frame-number = <1>;
 851                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 852                                 reg = <0x0 0x17c23000 0x0 0x1000>;
 853                                 status = "disabled";
 854                         };
 855
 856                         frame@17c25000 {
 857                                 frame-number = <2>;
 858                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 859                                 reg = <0x0 0x17c25000 0x0 0x1000>;
 860                                 status = "disabled";
 861                         };
 862
 863                         frame@17c27000 {
 864                                 frame-number = <3>;
 865                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 866                                 reg = <0x0 0x17c27000 0x0 0x1000>;
 867                                 status = "disabled";
 868                         };
 869
 870                         frame@17c29000 {
 871                                 frame-number = <4>;
 872                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 873                                 reg = <0x0 0x17c29000 0x0 0x1000>;
 874                                 status = "disabled";
 875                         };
 876
 877                         frame@17c2b000 {
 878                                 frame-number = <5>;
 879                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 880                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
 881                                 status = "disabled";
 882                         };
 883
 884                         frame@17c2d000 {
 885                                 frame-number = <6>;
 886                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 887                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
 888                                 status = "disabled";
 889                         };
 890                 };
 891
 892                 apps_rsc: rsc@18200000 {
 893                         label = "apps_rsc";
 894                         compatible = "qcom,rpmh-rsc";
 895                         reg = <0x0 0x18200000 0x0 0x10000>,
 896                                 <0x0 0x18210000 0x0 0x10000>,
 897                                 <0x0 0x18220000 0x0 0x10000>;
 898                         reg-names = "drv-0", "drv-1", "drv-2";
 899                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 900                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 901                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 902                         qcom,tcs-offset = <0xd00>;
 903                         qcom,drv-id = <2>;
 904                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
 905                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
 906
 907                         rpmhcc: clock-controller {
 908                                 compatible = "qcom,sm8350-rpmh-clk";
 909                                 #clock-cells = <1>;
 910                                 clock-names = "xo";
 911                                 clocks = <&xo_board>;
 912                         };
 913
 914                         rpmhpd: power-controller {
 915                                 compatible = "qcom,sm8350-rpmhpd";
 916                                 #power-domain-cells = <1>;
 917                                 operating-points-v2 = <&rpmhpd_opp_table>;
 918
 919                                 rpmhpd_opp_table: opp-table {
 920                                         compatible = "operating-points-v2";
 921
 922                                         rpmhpd_opp_ret: opp1 {
 923                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
 924                                         };
 925
 926                                         rpmhpd_opp_min_svs: opp2 {
 927                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 928                                         };
 929
 930                                         rpmhpd_opp_low_svs: opp3 {
 931                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 932                                         };
 933
 934                                         rpmhpd_opp_svs: opp4 {
 935                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 936                                         };
 937
 938                                         rpmhpd_opp_svs_l1: opp5 {
 939                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 940                                         };
 941
 942                                         rpmhpd_opp_nom: opp6 {
 943                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 944                                         };
 945
 946                                         rpmhpd_opp_nom_l1: opp7 {
 947                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 948                                         };
 949
 950                                         rpmhpd_opp_nom_l2: opp8 {
 951                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
 952                                         };
 953
 954                                         rpmhpd_opp_turbo: opp9 {
 955                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 956                                         };
 957
 958                                         rpmhpd_opp_turbo_l1: opp10 {
 959                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 960                                         };
 961                                 };
 962                         };
 963
 964                         apps_bcm_voter: bcm_voter {
 965                                 compatible = "qcom,bcm-voter";
 966                         };
 967                 };
 968
 969                 cpufreq_hw: cpufreq@18591000 {
 970                         compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
 971                         reg = <0 0x18591000 0 0x1000>,
 972                               <0 0x18592000 0 0x1000>,
 973                               <0 0x18593000 0 0x1000>;
 974                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
 975
 976                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
 977                         clock-names = "xo", "alternate";
 978
 979                         #freq-domain-cells = <1>;
 980                 };
 981
 982                 ufs_mem_hc: ufshc@1d84000 {
 983                         compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
 984                                      "jedec,ufs-2.0";
 985                         reg = <0 0x01d84000 0 0x3000>;
 986                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 987                         phys = <&ufs_mem_phy_lanes>;
 988                         phy-names = "ufsphy";
 989                         lanes-per-direction = <2>;
 990                         #reset-cells = <1>;
 991                         resets = <&gcc GCC_UFS_PHY_BCR>;
 992                         reset-names = "rst";
 993
 994                         power-domains = <&gcc UFS_PHY_GDSC>;
 995
 996                         iommus = <&apps_smmu 0xe0 0x0>;
 997
 998                         clock-names =
 999                                 "ref_clk",
1000                                 "core_clk",
1001                                 "bus_aggr_clk",
1002                                 "iface_clk",
1003                                 "core_clk_unipro",
1004                                 "ref_clk",
1005                                 "tx_lane0_sync_clk",
1006                                 "rx_lane0_sync_clk",
1007                                 "rx_lane1_sync_clk";
1008                         clocks =
1009                                 <&rpmhcc RPMH_CXO_CLK>,
1010                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1011                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1012                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1013                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1014                                 <&rpmhcc RPMH_CXO_CLK>,
1015                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1016                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1017                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1018                         freq-table-hz =
1019                                 <75000000 300000000>,
1020                                 <75000000 300000000>,
1021                                 <0 0>,
1022                                 <0 0>,
1023                                 <75000000 300000000>,
1024                                 <0 0>,
1025                                 <0 0>,
1026                                 <75000000 300000000>,
1027                                 <75000000 300000000>;
1028                         status = "disabled";
1029                 };
1030
1031                 ufs_mem_phy: phy@1d87000 {
1032                         compatible = "qcom,sm8350-qmp-ufs-phy";
1033                         reg = <0 0x01d87000 0 0xe10>;
1034                         #address-cells = <2>;
1035                         #size-cells = <2>;
1036                         #clock-cells = <1>;
1037                         ranges;
1038                         clock-names = "ref",
1039                                       "ref_aux";
1040                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1041                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1042
1043                         resets = <&ufs_mem_hc 0>;
1044                         reset-names = "ufsphy";
1045                         status = "disabled";
1046
1047                         ufs_mem_phy_lanes: lanes@1d87400 {
1048                                 reg = <0 0x01d87400 0 0x108>,
1049                                       <0 0x01d87600 0 0x1e0>,
1050                                       <0 0x01d87c00 0 0x1dc>,
1051                                       <0 0x01d87800 0 0x108>,
1052                                       <0 0x01d87a00 0 0x1e0>;
1053                                 #phy-cells = <0>;
1054                                 #clock-cells = <0>;
1055                         };
1056                 };
1057
1058                 slpi: remoteproc@5c00000 {
1059                         compatible = "qcom,sm8350-slpi-pas";
1060                         reg = <0 0x05c00000 0 0x4000>;
1061
1062                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1063                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1064                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1065                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1066                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1067                         interrupt-names = "wdog", "fatal", "ready",
1068                                           "handover", "stop-ack";
1069
1070                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1071                         clock-names = "xo";
1072
1073                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1074                                         <&rpmhpd 4>,
1075                                         <&rpmhpd 5>;
1076                         power-domain-names = "load_state", "lcx", "lmx";
1077
1078                         memory-region = <&pil_slpi_mem>;
1079
1080                         qcom,smem-states = <&smp2p_slpi_out 0>;
1081                         qcom,smem-state-names = "stop";
1082
1083                         status = "disabled";
1084
1085                         glink-edge {
1086                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1087                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1088                                                              IRQ_TYPE_EDGE_RISING>;
1089                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1090                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1091
1092                                 label = "slpi";
1093                                 qcom,remote-pid = <3>;
1094
1095                         };
1096                 };
1097
1098                 cdsp: remoteproc@98900000 {
1099                         compatible = "qcom,sm8350-cdsp-pas";
1100                         reg = <0 0x098900000 0 0x1400000>;
1101
1102                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1103                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1104                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1105                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1106                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1107                         interrupt-names = "wdog", "fatal", "ready",
1108                                           "handover", "stop-ack";
1109
1110                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1111                         clock-names = "xo";
1112
1113                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1114                                         <&rpmhpd 0>,
1115                                         <&rpmhpd 10>;
1116                         power-domain-names = "load_state", "cx", "mxc";
1117
1118                         interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
1119
1120                         memory-region = <&pil_cdsp_mem>;
1121
1122                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1123                         qcom,smem-state-names = "stop";
1124
1125                         status = "disabled";
1126
1127                         glink-edge {
1128                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1129                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1130                                                              IRQ_TYPE_EDGE_RISING>;
1131                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1132                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1133
1134                                 label = "cdsp";
1135                                 qcom,remote-pid = <5>;
1136                         };
1137                 };
1138
1139                 usb_1_hsphy: phy@88e3000 {
1140                         compatible = "qcom,sm8350-usb-hs-phy",
1141                                      "qcom,usb-snps-hs-7nm-phy";
1142                         reg = <0 0x088e3000 0 0x400>;
1143                         status = "disabled";
1144                         #phy-cells = <0>;
1145
1146                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1147                         clock-names = "ref";
1148
1149                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1150                 };
1151
1152                 usb_2_hsphy: phy@88e4000 {
1153                         compatible = "qcom,sm8250-usb-hs-phy",
1154                                      "qcom,usb-snps-hs-7nm-phy";
1155                         reg = <0 0x088e4000 0 0x400>;
1156                         status = "disabled";
1157                         #phy-cells = <0>;
1158
1159                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1160                         clock-names = "ref";
1161
1162                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1163                 };
1164
1165                 usb_1_qmpphy: phy-wrapper@88e9000 {
1166                         compatible = "qcom,sm8350-qmp-usb3-phy";
1167                         reg = <0 0x088e9000 0 0x200>,
1168                               <0 0x088e8000 0 0x20>;
1169                         reg-names = "reg-base", "dp_com";
1170                         status = "disabled";
1171                         #clock-cells = <1>;
1172                         #address-cells = <2>;
1173                         #size-cells = <2>;
1174                         ranges;
1175
1176                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1177                                  <&rpmhcc RPMH_CXO_CLK>,
1178                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1179                         clock-names = "aux", "ref_clk_src", "com_aux";
1180
1181                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1182                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
1183                         reset-names = "phy", "common";
1184
1185                         usb_1_ssphy: phy@88e9200 {
1186                                 reg = <0 0x088e9200 0 0x200>,
1187                                       <0 0x088e9400 0 0x200>,
1188                                       <0 0x088e9c00 0 0x400>,
1189                                       <0 0x088e9600 0 0x200>,
1190                                       <0 0x088e9800 0 0x200>,
1191                                       <0 0x088e9a00 0 0x100>;
1192                                 #phy-cells = <0>;
1193                                 #clock-cells = <1>;
1194                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1195                                 clock-names = "pipe0";
1196                                 clock-output-names = "usb3_phy_pipe_clk_src";
1197                         };
1198                 };
1199
1200                 usb_2_qmpphy: phy-wrapper@88eb000 {
1201                         compatible = "qcom,sm8350-qmp-usb3-uni-phy";
1202                         reg = <0 0x088eb000 0 0x200>;
1203                         status = "disabled";
1204                         #clock-cells = <1>;
1205                         #address-cells = <2>;
1206                         #size-cells = <2>;
1207                         ranges;
1208
1209                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1210                                  <&rpmhcc RPMH_CXO_CLK>,
1211                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
1212                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1213                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1214
1215                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1216                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
1217                         reset-names = "phy", "common";
1218
1219                         usb_2_ssphy: phy@88ebe00 {
1220                                 reg = <0 0x088ebe00 0 0x200>,
1221                                       <0 0x088ec000 0 0x200>,
1222                                       <0 0x088eb200 0 0x1100>;
1223                                 #phy-cells = <0>;
1224                                 #clock-cells = <1>;
1225                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1226                                 clock-names = "pipe0";
1227                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1228                         };
1229                 };
1230
1231                 dc_noc: interconnect@90c0000 {
1232                         compatible = "qcom,sm8350-dc-noc";
1233                         reg = <0 0x090c0000 0 0x4200>;
1234                         #interconnect-cells = <1>;
1235                         qcom,bcm-voters = <&apps_bcm_voter>;
1236                 };
1237
1238                 gem_noc: interconnect@9100000 {
1239                         compatible = "qcom,sm8350-gem-noc";
1240                         reg = <0 0x09100000 0 0xb4000>;
1241                         #interconnect-cells = <1>;
1242                         qcom,bcm-voters = <&apps_bcm_voter>;
1243                 };
1244
1245                 usb_1: usb@a6f8800 {
1246                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1247                         reg = <0 0x0a6f8800 0 0x400>;
1248                         status = "disabled";
1249                         #address-cells = <2>;
1250                         #size-cells = <2>;
1251                         ranges;
1252
1253                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1254                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1255                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1256                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1257                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1258                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1259                                       "sleep";
1260
1261                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1262                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1263                         assigned-clock-rates = <19200000>, <200000000>;
1264
1265                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1266                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1267                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1268                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1269                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1270                                           "dm_hs_phy_irq", "ss_phy_irq";
1271
1272                         power-domains = <&gcc USB30_PRIM_GDSC>;
1273
1274                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1275
1276                         usb_1_dwc3: dwc3@a600000 {
1277                                 compatible = "snps,dwc3";
1278                                 reg = <0 0x0a600000 0 0xcd00>;
1279                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1280                                 iommus = <&apps_smmu 0x0 0x0>;
1281                                 snps,dis_u2_susphy_quirk;
1282                                 snps,dis_enblslpm_quirk;
1283                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1284                                 phy-names = "usb2-phy", "usb3-phy";
1285                         };
1286                 };
1287
1288                 usb_2: usb@a8f8800 {
1289                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1290                         reg = <0 0x0a8f8800 0 0x400>;
1291                         status = "disabled";
1292                         #address-cells = <2>;
1293                         #size-cells = <2>;
1294                         ranges;
1295
1296                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1297                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1298                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1299                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1300                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1301                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1302                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1303                                       "sleep", "xo";
1304
1305                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1306                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1307                         assigned-clock-rates = <19200000>, <200000000>;
1308
1309                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1310                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1311                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1312                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1313                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1314                                           "dm_hs_phy_irq", "ss_phy_irq";
1315
1316                         power-domains = <&gcc USB30_SEC_GDSC>;
1317
1318                         resets = <&gcc GCC_USB30_SEC_BCR>;
1319
1320                         usb_2_dwc3: dwc3@a800000 {
1321                                 compatible = "snps,dwc3";
1322                                 reg = <0 0x0a800000 0 0xcd00>;
1323                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1324                                 iommus = <&apps_smmu 0x20 0x0>;
1325                                 snps,dis_u2_susphy_quirk;
1326                                 snps,dis_enblslpm_quirk;
1327                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1328                                 phy-names = "usb2-phy", "usb3-phy";
1329                         };
1330                 };
1331
1332                 adsp: remoteproc@17300000 {
1333                         compatible = "qcom,sm8350-adsp-pas";
1334                         reg = <0 0x17300000 0 0x100>;
1335
1336                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1337                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1338                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1339                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1340                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1341                         interrupt-names = "wdog", "fatal", "ready",
1342                                           "handover", "stop-ack";
1343
1344                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1345                         clock-names = "xo";
1346
1347                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1348                                         <&rpmhpd 4>,
1349                                         <&rpmhpd 5>;
1350                         power-domain-names = "load_state", "lcx", "lmx";
1351
1352                         memory-region = <&pil_adsp_mem>;
1353
1354                         qcom,smem-states = <&smp2p_adsp_out 0>;
1355                         qcom,smem-state-names = "stop";
1356
1357                         status = "disabled";
1358
1359                         glink-edge {
1360                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1361                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1362                                                              IRQ_TYPE_EDGE_RISING>;
1363                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
1364                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1365
1366                                 label = "lpass";
1367                                 qcom,remote-pid = <2>;
1368                         };
1369                 };
1370         };
1371
1372         thermal_zones: thermal-zones {
1373                 cpu0-thermal {
1374                         polling-delay-passive = <250>;
1375                         polling-delay = <1000>;
1376
1377                         thermal-sensors = <&tsens0 1>;
1378
1379                         trips {
1380                                 cpu0_alert0: trip-point0 {
1381                                         temperature = <90000>;
1382                                         hysteresis = <2000>;
1383                                         type = "passive";
1384                                 };
1385
1386                                 cpu0_alert1: trip-point1 {
1387                                         temperature = <95000>;
1388                                         hysteresis = <2000>;
1389                                         type = "passive";
1390                                 };
1391
1392                                 cpu0_crit: cpu_crit {
1393                                         temperature = <110000>;
1394                                         hysteresis = <1000>;
1395                                         type = "critical";
1396                                 };
1397                         };
1398
1399                         cooling-maps {
1400                                 map0 {
1401                                         trip = <&cpu0_alert0>;
1402                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1403                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1404                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1405                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1406                                 };
1407                                 map1 {
1408                                         trip = <&cpu0_alert1>;
1409                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1410                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1411                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1412                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1413                                 };
1414                         };
1415                 };
1416
1417                 cpu1-thermal {
1418                         polling-delay-passive = <250>;
1419                         polling-delay = <1000>;
1420
1421                         thermal-sensors = <&tsens0 2>;
1422
1423                         trips {
1424                                 cpu1_alert0: trip-point0 {
1425                                         temperature = <90000>;
1426                                         hysteresis = <2000>;
1427                                         type = "passive";
1428                                 };
1429
1430                                 cpu1_alert1: trip-point1 {
1431                                         temperature = <95000>;
1432                                         hysteresis = <2000>;
1433                                         type = "passive";
1434                                 };
1435
1436                                 cpu1_crit: cpu_crit {
1437                                         temperature = <110000>;
1438                                         hysteresis = <1000>;
1439                                         type = "critical";
1440                                 };
1441                         };
1442
1443                         cooling-maps {
1444                                 map0 {
1445                                         trip = <&cpu1_alert0>;
1446                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1447                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1448                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1449                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1450                                 };
1451                                 map1 {
1452                                         trip = <&cpu1_alert1>;
1453                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1454                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1455                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1456                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1457                                 };
1458                         };
1459                 };
1460
1461                 cpu2-thermal {
1462                         polling-delay-passive = <250>;
1463                         polling-delay = <1000>;
1464
1465                         thermal-sensors = <&tsens0 3>;
1466
1467                         trips {
1468                                 cpu2_alert0: trip-point0 {
1469                                         temperature = <90000>;
1470                                         hysteresis = <2000>;
1471                                         type = "passive";
1472                                 };
1473
1474                                 cpu2_alert1: trip-point1 {
1475                                         temperature = <95000>;
1476                                         hysteresis = <2000>;
1477                                         type = "passive";
1478                                 };
1479
1480                                 cpu2_crit: cpu_crit {
1481                                         temperature = <110000>;
1482                                         hysteresis = <1000>;
1483                                         type = "critical";
1484                                 };
1485                         };
1486
1487                         cooling-maps {
1488                                 map0 {
1489                                         trip = <&cpu2_alert0>;
1490                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1491                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1492                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1493                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1494                                 };
1495                                 map1 {
1496                                         trip = <&cpu2_alert1>;
1497                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1498                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1499                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1500                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1501                                 };
1502                         };
1503                 };
1504
1505                 cpu3-thermal {
1506                         polling-delay-passive = <250>;
1507                         polling-delay = <1000>;
1508
1509                         thermal-sensors = <&tsens0 4>;
1510
1511                         trips {
1512                                 cpu3_alert0: trip-point0 {
1513                                         temperature = <90000>;
1514                                         hysteresis = <2000>;
1515                                         type = "passive";
1516                                 };
1517
1518                                 cpu3_alert1: trip-point1 {
1519                                         temperature = <95000>;
1520                                         hysteresis = <2000>;
1521                                         type = "passive";
1522                                 };
1523
1524                                 cpu3_crit: cpu_crit {
1525                                         temperature = <110000>;
1526                                         hysteresis = <1000>;
1527                                         type = "critical";
1528                                 };
1529                         };
1530
1531                         cooling-maps {
1532                                 map0 {
1533                                         trip = <&cpu3_alert0>;
1534                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1535                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1536                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1537                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1538                                 };
1539                                 map1 {
1540                                         trip = <&cpu3_alert1>;
1541                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1542                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1543                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1544                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1545                                 };
1546                         };
1547                 };
1548
1549                 cpu4-top-thermal {
1550                         polling-delay-passive = <250>;
1551                         polling-delay = <1000>;
1552
1553                         thermal-sensors = <&tsens0 7>;
1554
1555                         trips {
1556                                 cpu4_top_alert0: trip-point0 {
1557                                         temperature = <90000>;
1558                                         hysteresis = <2000>;
1559                                         type = "passive";
1560                                 };
1561
1562                                 cpu4_top_alert1: trip-point1 {
1563                                         temperature = <95000>;
1564                                         hysteresis = <2000>;
1565                                         type = "passive";
1566                                 };
1567
1568                                 cpu4_top_crit: cpu_crit {
1569                                         temperature = <110000>;
1570                                         hysteresis = <1000>;
1571                                         type = "critical";
1572                                 };
1573                         };
1574
1575                         cooling-maps {
1576                                 map0 {
1577                                         trip = <&cpu4_top_alert0>;
1578                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1579                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1580                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1581                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1582                                 };
1583                                 map1 {
1584                                         trip = <&cpu4_top_alert1>;
1585                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1586                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1587                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1588                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1589                                 };
1590                         };
1591                 };
1592
1593                 cpu5-top-thermal {
1594                         polling-delay-passive = <250>;
1595                         polling-delay = <1000>;
1596
1597                         thermal-sensors = <&tsens0 8>;
1598
1599                         trips {
1600                                 cpu5_top_alert0: trip-point0 {
1601                                         temperature = <90000>;
1602                                         hysteresis = <2000>;
1603                                         type = "passive";
1604                                 };
1605
1606                                 cpu5_top_alert1: trip-point1 {
1607                                         temperature = <95000>;
1608                                         hysteresis = <2000>;
1609                                         type = "passive";
1610                                 };
1611
1612                                 cpu5_top_crit: cpu_crit {
1613                                         temperature = <110000>;
1614                                         hysteresis = <1000>;
1615                                         type = "critical";
1616                                 };
1617                         };
1618
1619                         cooling-maps {
1620                                 map0 {
1621                                         trip = <&cpu5_top_alert0>;
1622                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1623                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1624                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1625                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1626                                 };
1627                                 map1 {
1628                                         trip = <&cpu5_top_alert1>;
1629                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1630                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1631                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1632                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1633                                 };
1634                         };
1635                 };
1636
1637                 cpu6-top-thermal {
1638                         polling-delay-passive = <250>;
1639                         polling-delay = <1000>;
1640
1641                         thermal-sensors = <&tsens0 9>;
1642
1643                         trips {
1644                                 cpu6_top_alert0: trip-point0 {
1645                                         temperature = <90000>;
1646                                         hysteresis = <2000>;
1647                                         type = "passive";
1648                                 };
1649
1650                                 cpu6_top_alert1: trip-point1 {
1651                                         temperature = <95000>;
1652                                         hysteresis = <2000>;
1653                                         type = "passive";
1654                                 };
1655
1656                                 cpu6_top_crit: cpu_crit {
1657                                         temperature = <110000>;
1658                                         hysteresis = <1000>;
1659                                         type = "critical";
1660                                 };
1661                         };
1662
1663                         cooling-maps {
1664                                 map0 {
1665                                         trip = <&cpu6_top_alert0>;
1666                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1667                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1668                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1669                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1670                                 };
1671                                 map1 {
1672                                         trip = <&cpu6_top_alert1>;
1673                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1674                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1675                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1676                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1677                                 };
1678                         };
1679                 };
1680
1681                 cpu7-top-thermal {
1682                         polling-delay-passive = <250>;
1683                         polling-delay = <1000>;
1684
1685                         thermal-sensors = <&tsens0 10>;
1686
1687                         trips {
1688                                 cpu7_top_alert0: trip-point0 {
1689                                         temperature = <90000>;
1690                                         hysteresis = <2000>;
1691                                         type = "passive";
1692                                 };
1693
1694                                 cpu7_top_alert1: trip-point1 {
1695                                         temperature = <95000>;
1696                                         hysteresis = <2000>;
1697                                         type = "passive";
1698                                 };
1699
1700                                 cpu7_top_crit: cpu_crit {
1701                                         temperature = <110000>;
1702                                         hysteresis = <1000>;
1703                                         type = "critical";
1704                                 };
1705                         };
1706
1707                         cooling-maps {
1708                                 map0 {
1709                                         trip = <&cpu7_top_alert0>;
1710                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1711                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1712                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1713                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1714                                 };
1715                                 map1 {
1716                                         trip = <&cpu7_top_alert1>;
1717                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1718                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1719                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1720                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1721                                 };
1722                         };
1723                 };
1724
1725                 cpu4-bottom-thermal {
1726                         polling-delay-passive = <250>;
1727                         polling-delay = <1000>;
1728
1729                         thermal-sensors = <&tsens0 11>;
1730
1731                         trips {
1732                                 cpu4_bottom_alert0: trip-point0 {
1733                                         temperature = <90000>;
1734                                         hysteresis = <2000>;
1735                                         type = "passive";
1736                                 };
1737
1738                                 cpu4_bottom_alert1: trip-point1 {
1739                                         temperature = <95000>;
1740                                         hysteresis = <2000>;
1741                                         type = "passive";
1742                                 };
1743
1744                                 cpu4_bottom_crit: cpu_crit {
1745                                         temperature = <110000>;
1746                                         hysteresis = <1000>;
1747                                         type = "critical";
1748                                 };
1749                         };
1750
1751                         cooling-maps {
1752                                 map0 {
1753                                         trip = <&cpu4_bottom_alert0>;
1754                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1755                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1756                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1757                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1758                                 };
1759                                 map1 {
1760                                         trip = <&cpu4_bottom_alert1>;
1761                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1762                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1763                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1764                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1765                                 };
1766                         };
1767                 };
1768
1769                 cpu5-bottom-thermal {
1770                         polling-delay-passive = <250>;
1771                         polling-delay = <1000>;
1772
1773                         thermal-sensors = <&tsens0 12>;
1774
1775                         trips {
1776                                 cpu5_bottom_alert0: trip-point0 {
1777                                         temperature = <90000>;
1778                                         hysteresis = <2000>;
1779                                         type = "passive";
1780                                 };
1781
1782                                 cpu5_bottom_alert1: trip-point1 {
1783                                         temperature = <95000>;
1784                                         hysteresis = <2000>;
1785                                         type = "passive";
1786                                 };
1787
1788                                 cpu5_bottom_crit: cpu_crit {
1789                                         temperature = <110000>;
1790                                         hysteresis = <1000>;
1791                                         type = "critical";
1792                                 };
1793                         };
1794
1795                         cooling-maps {
1796                                 map0 {
1797                                         trip = <&cpu5_bottom_alert0>;
1798                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1799                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1800                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1801                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1802                                 };
1803                                 map1 {
1804                                         trip = <&cpu5_bottom_alert1>;
1805                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1806                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1807                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1808                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1809                                 };
1810                         };
1811                 };
1812
1813                 cpu6-bottom-thermal {
1814                         polling-delay-passive = <250>;
1815                         polling-delay = <1000>;
1816
1817                         thermal-sensors = <&tsens0 13>;
1818
1819                         trips {
1820                                 cpu6_bottom_alert0: trip-point0 {
1821                                         temperature = <90000>;
1822                                         hysteresis = <2000>;
1823                                         type = "passive";
1824                                 };
1825
1826                                 cpu6_bottom_alert1: trip-point1 {
1827                                         temperature = <95000>;
1828                                         hysteresis = <2000>;
1829                                         type = "passive";
1830                                 };
1831
1832                                 cpu6_bottom_crit: cpu_crit {
1833                                         temperature = <110000>;
1834                                         hysteresis = <1000>;
1835                                         type = "critical";
1836                                 };
1837                         };
1838
1839                         cooling-maps {
1840                                 map0 {
1841                                         trip = <&cpu6_bottom_alert0>;
1842                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1843                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1844                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1845                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1846                                 };
1847                                 map1 {
1848                                         trip = <&cpu6_bottom_alert1>;
1849                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1850                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1851                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1852                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1853                                 };
1854                         };
1855                 };
1856
1857                 cpu7-bottom-thermal {
1858                         polling-delay-passive = <250>;
1859                         polling-delay = <1000>;
1860
1861                         thermal-sensors = <&tsens0 14>;
1862
1863                         trips {
1864                                 cpu7_bottom_alert0: trip-point0 {
1865                                         temperature = <90000>;
1866                                         hysteresis = <2000>;
1867                                         type = "passive";
1868                                 };
1869
1870                                 cpu7_bottom_alert1: trip-point1 {
1871                                         temperature = <95000>;
1872                                         hysteresis = <2000>;
1873                                         type = "passive";
1874                                 };
1875
1876                                 cpu7_bottom_crit: cpu_crit {
1877                                         temperature = <110000>;
1878                                         hysteresis = <1000>;
1879                                         type = "critical";
1880                                 };
1881                         };
1882
1883                         cooling-maps {
1884                                 map0 {
1885                                         trip = <&cpu7_bottom_alert0>;
1886                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1887                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1888                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1889                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1890                                 };
1891                                 map1 {
1892                                         trip = <&cpu7_bottom_alert1>;
1893                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1894                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1895                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1896                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1897                                 };
1898                         };
1899                 };
1900
1901                 aoss0-thermal {
1902                         polling-delay-passive = <250>;
1903                         polling-delay = <1000>;
1904
1905                         thermal-sensors = <&tsens0 0>;
1906
1907                         trips {
1908                                 aoss0_alert0: trip-point0 {
1909                                         temperature = <90000>;
1910                                         hysteresis = <2000>;
1911                                         type = "hot";
1912                                 };
1913                         };
1914                 };
1915
1916                 cluster0-thermal {
1917                         polling-delay-passive = <250>;
1918                         polling-delay = <1000>;
1919
1920                         thermal-sensors = <&tsens0 5>;
1921
1922                         trips {
1923                                 cluster0_alert0: trip-point0 {
1924                                         temperature = <90000>;
1925                                         hysteresis = <2000>;
1926                                         type = "hot";
1927                                 };
1928                                 cluster0_crit: cluster0_crit {
1929                                         temperature = <110000>;
1930                                         hysteresis = <2000>;
1931                                         type = "critical";
1932                                 };
1933                         };
1934                 };
1935
1936                 cluster1-thermal {
1937                         polling-delay-passive = <250>;
1938                         polling-delay = <1000>;
1939
1940                         thermal-sensors = <&tsens0 6>;
1941
1942                         trips {
1943                                 cluster1_alert0: trip-point0 {
1944                                         temperature = <90000>;
1945                                         hysteresis = <2000>;
1946                                         type = "hot";
1947                                 };
1948                                 cluster1_crit: cluster1_crit {
1949                                         temperature = <110000>;
1950                                         hysteresis = <2000>;
1951                                         type = "critical";
1952                                 };
1953                         };
1954                 };
1955
1956                 aoss1-thermal {
1957                         polling-delay-passive = <250>;
1958                         polling-delay = <1000>;
1959
1960                         thermal-sensors = <&tsens1 0>;
1961
1962                         trips {
1963                                 aoss1_alert0: trip-point0 {
1964                                         temperature = <90000>;
1965                                         hysteresis = <2000>;
1966                                         type = "hot";
1967                                 };
1968                         };
1969                 };
1970
1971                 gpu-thermal-top {
1972                         polling-delay-passive = <250>;
1973                         polling-delay = <1000>;
1974
1975                         thermal-sensors = <&tsens1 1>;
1976
1977                         trips {
1978                                 gpu1_alert0: trip-point0 {
1979                                         temperature = <90000>;
1980                                         hysteresis = <1000>;
1981                                         type = "hot";
1982                                 };
1983                         };
1984                 };
1985
1986                 gpu-thermal-bottom {
1987                         polling-delay-passive = <250>;
1988                         polling-delay = <1000>;
1989
1990                         thermal-sensors = <&tsens1 2>;
1991
1992                         trips {
1993                                 gpu2_alert0: trip-point0 {
1994                                         temperature = <90000>;
1995                                         hysteresis = <1000>;
1996                                         type = "hot";
1997                                 };
1998                         };
1999                 };
2000
2001                 nspss1-thermal {
2002                         polling-delay-passive = <250>;
2003                         polling-delay = <1000>;
2004
2005                         thermal-sensors = <&tsens1 3>;
2006
2007                         trips {
2008                                 nspss1_alert0: trip-point0 {
2009                                         temperature = <90000>;
2010                                         hysteresis = <1000>;
2011                                         type = "hot";
2012                                 };
2013                         };
2014                 };
2015
2016                 nspss2-thermal {
2017                         polling-delay-passive = <250>;
2018                         polling-delay = <1000>;
2019
2020                         thermal-sensors = <&tsens1 4>;
2021
2022                         trips {
2023                                 nspss2_alert0: trip-point0 {
2024                                         temperature = <90000>;
2025                                         hysteresis = <1000>;
2026                                         type = "hot";
2027                                 };
2028                         };
2029                 };
2030
2031                 nspss3-thermal {
2032                         polling-delay-passive = <250>;
2033                         polling-delay = <1000>;
2034
2035                         thermal-sensors = <&tsens1 5>;
2036
2037                         trips {
2038                                 nspss3_alert0: trip-point0 {
2039                                         temperature = <90000>;
2040                                         hysteresis = <1000>;
2041                                         type = "hot";
2042                                 };
2043                         };
2044                 };
2045
2046                 video-thermal {
2047                         polling-delay-passive = <250>;
2048                         polling-delay = <1000>;
2049
2050                         thermal-sensors = <&tsens1 6>;
2051
2052                         trips {
2053                                 video_alert0: trip-point0 {
2054                                         temperature = <90000>;
2055                                         hysteresis = <2000>;
2056                                         type = "hot";
2057                                 };
2058                         };
2059                 };
2060
2061                 mem-thermal {
2062                         polling-delay-passive = <250>;
2063                         polling-delay = <1000>;
2064
2065                         thermal-sensors = <&tsens1 7>;
2066
2067                         trips {
2068                                 mem_alert0: trip-point0 {
2069                                         temperature = <90000>;
2070                                         hysteresis = <2000>;
2071                                         type = "hot";
2072                                 };
2073                         };
2074                 };
2075
2076                 modem1-thermal-top {
2077                         polling-delay-passive = <250>;
2078                         polling-delay = <1000>;
2079
2080                         thermal-sensors = <&tsens1 8>;
2081
2082                         trips {
2083                                 modem1_alert0: trip-point0 {
2084                                         temperature = <90000>;
2085                                         hysteresis = <2000>;
2086                                         type = "hot";
2087                                 };
2088                         };
2089                 };
2090
2091                 modem2-thermal-top {
2092                         polling-delay-passive = <250>;
2093                         polling-delay = <1000>;
2094
2095                         thermal-sensors = <&tsens1 9>;
2096
2097                         trips {
2098                                 modem2_alert0: trip-point0 {
2099                                         temperature = <90000>;
2100                                         hysteresis = <2000>;
2101                                         type = "hot";
2102                                 };
2103                         };
2104                 };
2105
2106                 modem3-thermal-top {
2107                         polling-delay-passive = <250>;
2108                         polling-delay = <1000>;
2109
2110                         thermal-sensors = <&tsens1 10>;
2111
2112                         trips {
2113                                 modem3_alert0: trip-point0 {
2114                                         temperature = <90000>;
2115                                         hysteresis = <2000>;
2116                                         type = "hot";
2117                                 };
2118                         };
2119                 };
2120
2121                 modem4-thermal-top {
2122                         polling-delay-passive = <250>;
2123                         polling-delay = <1000>;
2124
2125                         thermal-sensors = <&tsens1 11>;
2126
2127                         trips {
2128                                 modem4_alert0: trip-point0 {
2129                                         temperature = <90000>;
2130                                         hysteresis = <2000>;
2131                                         type = "hot";
2132                                 };
2133                         };
2134                 };
2135
2136                 camera-thermal-top {
2137                         polling-delay-passive = <250>;
2138                         polling-delay = <1000>;
2139
2140                         thermal-sensors = <&tsens1 12>;
2141
2142                         trips {
2143                                 camera1_alert0: trip-point0 {
2144                                         temperature = <90000>;
2145                                         hysteresis = <2000>;
2146                                         type = "hot";
2147                                 };
2148                         };
2149                 };
2150
2151                 camera-thermal-bottom {
2152                         polling-delay-passive = <250>;
2153                         polling-delay = <1000>;
2154
2155                         thermal-sensors = <&tsens1 13>;
2156
2157                         trips {
2158                                 camera2_alert0: trip-point0 {
2159                                         temperature = <90000>;
2160                                         hysteresis = <2000>;
2161                                         type = "hot";
2162                                 };
2163                         };
2164                 };
2165         };
2166
2167         timer {
2168                 compatible = "arm,armv8-timer";
2169                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2170                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2171                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2172                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2173         };
2174 };