arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/dma/qcom-gpi.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  14 #include <dt-bindings/interconnect/qcom,sm8250.h>
  15 #include <dt-bindings/mailbox/qcom-ipcc.h>
  16 #include <dt-bindings/power/qcom-aoss-qmp.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/soc/qcom,apr.h>
  19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  20 #include <dt-bindings/sound/qcom,q6afe.h>
  21 #include <dt-bindings/thermal/thermal.h>
  22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  23
  24 / {
  25         interrupt-parent = <&intc>;
  26
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         aliases {
  31                 i2c0 = &i2c0;
  32                 i2c1 = &i2c1;
  33                 i2c2 = &i2c2;
  34                 i2c3 = &i2c3;
  35                 i2c4 = &i2c4;
  36                 i2c5 = &i2c5;
  37                 i2c6 = &i2c6;
  38                 i2c7 = &i2c7;
  39                 i2c8 = &i2c8;
  40                 i2c9 = &i2c9;
  41                 i2c10 = &i2c10;
  42                 i2c11 = &i2c11;
  43                 i2c12 = &i2c12;
  44                 i2c13 = &i2c13;
  45                 i2c14 = &i2c14;
  46                 i2c15 = &i2c15;
  47                 i2c16 = &i2c16;
  48                 i2c17 = &i2c17;
  49                 i2c18 = &i2c18;
  50                 i2c19 = &i2c19;
  51                 spi0 = &spi0;
  52                 spi1 = &spi1;
  53                 spi2 = &spi2;
  54                 spi3 = &spi3;
  55                 spi4 = &spi4;
  56                 spi5 = &spi5;
  57                 spi6 = &spi6;
  58                 spi7 = &spi7;
  59                 spi8 = &spi8;
  60                 spi9 = &spi9;
  61                 spi10 = &spi10;
  62                 spi11 = &spi11;
  63                 spi12 = &spi12;
  64                 spi13 = &spi13;
  65                 spi14 = &spi14;
  66                 spi15 = &spi15;
  67                 spi16 = &spi16;
  68                 spi17 = &spi17;
  69                 spi18 = &spi18;
  70                 spi19 = &spi19;
  71         };
  72
  73         chosen { };
  74
  75         clocks {
  76                 xo_board: xo-board {
  77                         compatible = "fixed-clock";
  78                         #clock-cells = <0>;
  79                         clock-frequency = <38400000>;
  80                         clock-output-names = "xo_board";
  81                 };
  82
  83                 sleep_clk: sleep-clk {
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                         #clock-cells = <0>;
  87                 };
  88         };
  89
  90         cpus {
  91                 #address-cells = <2>;
  92                 #size-cells = <0>;
  93
  94                 CPU0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "qcom,kryo485";
  97                         reg = <0x0 0x0>;
  98                         enable-method = "psci";
  99                         capacity-dmips-mhz = <448>;
 100                         dynamic-power-coefficient = <205>;
 101                         next-level-cache = <&L2_0>;
 102                         qcom,freq-domain = <&cpufreq_hw 0>;
 103                         #cooling-cells = <2>;
 104                         L2_0: l2-cache {
 105                                 compatible = "cache";
 106                                 next-level-cache = <&L3_0>;
 107                                 L3_0: l3-cache {
 108                                         compatible = "cache";
 109                                 };
 110                         };
 111                 };
 112
 113                 CPU1: cpu@100 {
 114                         device_type = "cpu";
 115                         compatible = "qcom,kryo485";
 116                         reg = <0x0 0x100>;
 117                         enable-method = "psci";
 118                         capacity-dmips-mhz = <448>;
 119                         dynamic-power-coefficient = <205>;
 120                         next-level-cache = <&L2_100>;
 121                         qcom,freq-domain = <&cpufreq_hw 0>;
 122                         #cooling-cells = <2>;
 123                         L2_100: l2-cache {
 124                                 compatible = "cache";
 125                                 next-level-cache = <&L3_0>;
 126                         };
 127                 };
 128
 129                 CPU2: cpu@200 {
 130                         device_type = "cpu";
 131                         compatible = "qcom,kryo485";
 132                         reg = <0x0 0x200>;
 133                         enable-method = "psci";
 134                         capacity-dmips-mhz = <448>;
 135                         dynamic-power-coefficient = <205>;
 136                         next-level-cache = <&L2_200>;
 137                         qcom,freq-domain = <&cpufreq_hw 0>;
 138                         #cooling-cells = <2>;
 139                         L2_200: l2-cache {
 140                                 compatible = "cache";
 141                                 next-level-cache = <&L3_0>;
 142                         };
 143                 };
 144
 145                 CPU3: cpu@300 {
 146                         device_type = "cpu";
 147                         compatible = "qcom,kryo485";
 148                         reg = <0x0 0x300>;
 149                         enable-method = "psci";
 150                         capacity-dmips-mhz = <448>;
 151                         dynamic-power-coefficient = <205>;
 152                         next-level-cache = <&L2_300>;
 153                         qcom,freq-domain = <&cpufreq_hw 0>;
 154                         #cooling-cells = <2>;
 155                         L2_300: l2-cache {
 156                                 compatible = "cache";
 157                                 next-level-cache = <&L3_0>;
 158                         };
 159                 };
 160
 161                 CPU4: cpu@400 {
 162                         device_type = "cpu";
 163                         compatible = "qcom,kryo485";
 164                         reg = <0x0 0x400>;
 165                         enable-method = "psci";
 166                         capacity-dmips-mhz = <1024>;
 167                         dynamic-power-coefficient = <379>;
 168                         next-level-cache = <&L2_400>;
 169                         qcom,freq-domain = <&cpufreq_hw 1>;
 170                         #cooling-cells = <2>;
 171                         L2_400: l2-cache {
 172                                 compatible = "cache";
 173                                 next-level-cache = <&L3_0>;
 174                         };
 175                 };
 176
 177                 CPU5: cpu@500 {
 178                         device_type = "cpu";
 179                         compatible = "qcom,kryo485";
 180                         reg = <0x0 0x500>;
 181                         enable-method = "psci";
 182                         capacity-dmips-mhz = <1024>;
 183                         dynamic-power-coefficient = <379>;
 184                         next-level-cache = <&L2_500>;
 185                         qcom,freq-domain = <&cpufreq_hw 1>;
 186                         #cooling-cells = <2>;
 187                         L2_500: l2-cache {
 188                                 compatible = "cache";
 189                                 next-level-cache = <&L3_0>;
 190                         };
 191
 192                 };
 193
 194                 CPU6: cpu@600 {
 195                         device_type = "cpu";
 196                         compatible = "qcom,kryo485";
 197                         reg = <0x0 0x600>;
 198                         enable-method = "psci";
 199                         capacity-dmips-mhz = <1024>;
 200                         dynamic-power-coefficient = <379>;
 201                         next-level-cache = <&L2_600>;
 202                         qcom,freq-domain = <&cpufreq_hw 1>;
 203                         #cooling-cells = <2>;
 204                         L2_600: l2-cache {
 205                                 compatible = "cache";
 206                                 next-level-cache = <&L3_0>;
 207                         };
 208                 };
 209
 210                 CPU7: cpu@700 {
 211                         device_type = "cpu";
 212                         compatible = "qcom,kryo485";
 213                         reg = <0x0 0x700>;
 214                         enable-method = "psci";
 215                         capacity-dmips-mhz = <1024>;
 216                         dynamic-power-coefficient = <444>;
 217                         next-level-cache = <&L2_700>;
 218                         qcom,freq-domain = <&cpufreq_hw 2>;
 219                         #cooling-cells = <2>;
 220                         L2_700: l2-cache {
 221                                 compatible = "cache";
 222                                 next-level-cache = <&L3_0>;
 223                         };
 224                 };
 225
 226                 cpu-map {
 227                         cluster0 {
 228                                 core0 {
 229                                         cpu = <&CPU0>;
 230                                 };
 231
 232                                 core1 {
 233                                         cpu = <&CPU1>;
 234                                 };
 235
 236                                 core2 {
 237                                         cpu = <&CPU2>;
 238                                 };
 239
 240                                 core3 {
 241                                         cpu = <&CPU3>;
 242                                 };
 243
 244                                 core4 {
 245                                         cpu = <&CPU4>;
 246                                 };
 247
 248                                 core5 {
 249                                         cpu = <&CPU5>;
 250                                 };
 251
 252                                 core6 {
 253                                         cpu = <&CPU6>;
 254                                 };
 255
 256                                 core7 {
 257                                         cpu = <&CPU7>;
 258                                 };
 259                         };
 260                 };
 261         };
 262
 263         firmware {
 264                 scm: scm {
 265                         compatible = "qcom,scm";
 266                         #reset-cells = <1>;
 267                 };
 268         };
 269
 270         memory@80000000 {
 271                 device_type = "memory";
 272                 /* We expect the bootloader to fill in the size */
 273                 reg = <0x0 0x80000000 0x0 0x0>;
 274         };
 275
 276         mmcx_reg: mmcx-reg {
 277                 compatible = "regulator-fixed-domain";
 278                 power-domains = <&rpmhpd SM8250_MMCX>;
 279                 required-opps = <&rpmhpd_opp_low_svs>;
 280                 regulator-name = "MMCX";
 281         };
 282
 283         pmu {
 284                 compatible = "arm,armv8-pmuv3";
 285                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 286         };
 287
 288         psci {
 289                 compatible = "arm,psci-1.0";
 290                 method = "smc";
 291         };
 292
 293         reserved-memory {
 294                 #address-cells = <2>;
 295                 #size-cells = <2>;
 296                 ranges;
 297
 298                 hyp_mem: memory@80000000 {
 299                         reg = <0x0 0x80000000 0x0 0x600000>;
 300                         no-map;
 301                 };
 302
 303                 xbl_aop_mem: memory@80700000 {
 304                         reg = <0x0 0x80700000 0x0 0x160000>;
 305                         no-map;
 306                 };
 307
 308                 cmd_db: memory@80860000 {
 309                         compatible = "qcom,cmd-db";
 310                         reg = <0x0 0x80860000 0x0 0x20000>;
 311                         no-map;
 312                 };
 313
 314                 smem_mem: memory@80900000 {
 315                         reg = <0x0 0x80900000 0x0 0x200000>;
 316                         no-map;
 317                 };
 318
 319                 removed_mem: memory@80b00000 {
 320                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 321                         no-map;
 322                 };
 323
 324                 camera_mem: memory@86200000 {
 325                         reg = <0x0 0x86200000 0x0 0x500000>;
 326                         no-map;
 327                 };
 328
 329                 wlan_mem: memory@86700000 {
 330                         reg = <0x0 0x86700000 0x0 0x100000>;
 331                         no-map;
 332                 };
 333
 334                 ipa_fw_mem: memory@86800000 {
 335                         reg = <0x0 0x86800000 0x0 0x10000>;
 336                         no-map;
 337                 };
 338
 339                 ipa_gsi_mem: memory@86810000 {
 340                         reg = <0x0 0x86810000 0x0 0xa000>;
 341                         no-map;
 342                 };
 343
 344                 gpu_mem: memory@8681a000 {
 345                         reg = <0x0 0x8681a000 0x0 0x2000>;
 346                         no-map;
 347                 };
 348
 349                 npu_mem: memory@86900000 {
 350                         reg = <0x0 0x86900000 0x0 0x500000>;
 351                         no-map;
 352                 };
 353
 354                 video_mem: memory@86e00000 {
 355                         reg = <0x0 0x86e00000 0x0 0x500000>;
 356                         no-map;
 357                 };
 358
 359                 cvp_mem: memory@87300000 {
 360                         reg = <0x0 0x87300000 0x0 0x500000>;
 361                         no-map;
 362                 };
 363
 364                 cdsp_mem: memory@87800000 {
 365                         reg = <0x0 0x87800000 0x0 0x1400000>;
 366                         no-map;
 367                 };
 368
 369                 slpi_mem: memory@88c00000 {
 370                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 371                         no-map;
 372                 };
 373
 374                 adsp_mem: memory@8a100000 {
 375                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 376                         no-map;
 377                 };
 378
 379                 spss_mem: memory@8be00000 {
 380                         reg = <0x0 0x8be00000 0x0 0x100000>;
 381                         no-map;
 382                 };
 383
 384                 cdsp_secure_heap: memory@8bf00000 {
 385                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 386                         no-map;
 387                 };
 388         };
 389
 390         smem {
 391                 compatible = "qcom,smem";
 392                 memory-region = <&smem_mem>;
 393                 hwlocks = <&tcsr_mutex 3>;
 394         };
 395
 396         smp2p-adsp {
 397                 compatible = "qcom,smp2p";
 398                 qcom,smem = <443>, <429>;
 399                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 400                                              IPCC_MPROC_SIGNAL_SMP2P
 401                                              IRQ_TYPE_EDGE_RISING>;
 402                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 403                                 IPCC_MPROC_SIGNAL_SMP2P>;
 404
 405                 qcom,local-pid = <0>;
 406                 qcom,remote-pid = <2>;
 407
 408                 smp2p_adsp_out: master-kernel {
 409                         qcom,entry-name = "master-kernel";
 410                         #qcom,smem-state-cells = <1>;
 411                 };
 412
 413                 smp2p_adsp_in: slave-kernel {
 414                         qcom,entry-name = "slave-kernel";
 415                         interrupt-controller;
 416                         #interrupt-cells = <2>;
 417                 };
 418         };
 419
 420         smp2p-cdsp {
 421                 compatible = "qcom,smp2p";
 422                 qcom,smem = <94>, <432>;
 423                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 424                                              IPCC_MPROC_SIGNAL_SMP2P
 425                                              IRQ_TYPE_EDGE_RISING>;
 426                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 427                                 IPCC_MPROC_SIGNAL_SMP2P>;
 428
 429                 qcom,local-pid = <0>;
 430                 qcom,remote-pid = <5>;
 431
 432                 smp2p_cdsp_out: master-kernel {
 433                         qcom,entry-name = "master-kernel";
 434                         #qcom,smem-state-cells = <1>;
 435                 };
 436
 437                 smp2p_cdsp_in: slave-kernel {
 438                         qcom,entry-name = "slave-kernel";
 439                         interrupt-controller;
 440                         #interrupt-cells = <2>;
 441                 };
 442         };
 443
 444         smp2p-slpi {
 445                 compatible = "qcom,smp2p";
 446                 qcom,smem = <481>, <430>;
 447                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 448                                              IPCC_MPROC_SIGNAL_SMP2P
 449                                              IRQ_TYPE_EDGE_RISING>;
 450                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 451                                 IPCC_MPROC_SIGNAL_SMP2P>;
 452
 453                 qcom,local-pid = <0>;
 454                 qcom,remote-pid = <3>;
 455
 456                 smp2p_slpi_out: master-kernel {
 457                         qcom,entry-name = "master-kernel";
 458                         #qcom,smem-state-cells = <1>;
 459                 };
 460
 461                 smp2p_slpi_in: slave-kernel {
 462                         qcom,entry-name = "slave-kernel";
 463                         interrupt-controller;
 464                         #interrupt-cells = <2>;
 465                 };
 466         };
 467
 468         soc: soc@0 {
 469                 #address-cells = <2>;
 470                 #size-cells = <2>;
 471                 ranges = <0 0 0 0 0x10 0>;
 472                 dma-ranges = <0 0 0 0 0x10 0>;
 473                 compatible = "simple-bus";
 474
 475                 gcc: clock-controller@100000 {
 476                         compatible = "qcom,gcc-sm8250";
 477                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 478                         #clock-cells = <1>;
 479                         #reset-cells = <1>;
 480                         #power-domain-cells = <1>;
 481                         clock-names = "bi_tcxo",
 482                                       "bi_tcxo_ao",
 483                                       "sleep_clk";
 484                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 485                                  <&rpmhcc RPMH_CXO_CLK_A>,
 486                                  <&sleep_clk>;
 487                 };
 488
 489                 ipcc: mailbox@408000 {
 490                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 491                         reg = <0 0x00408000 0 0x1000>;
 492                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 493                         interrupt-controller;
 494                         #interrupt-cells = <3>;
 495                         #mbox-cells = <2>;
 496                 };
 497
 498                 rng: rng@793000 {
 499                         compatible = "qcom,prng-ee";
 500                         reg = <0 0x00793000 0 0x1000>;
 501                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 502                         clock-names = "core";
 503                 };
 504
 505                 qup_opp_table: qup-opp-table {
 506                         compatible = "operating-points-v2";
 507
 508                         opp-50000000 {
 509                                 opp-hz = /bits/ 64 <50000000>;
 510                                 required-opps = <&rpmhpd_opp_min_svs>;
 511                         };
 512
 513                         opp-75000000 {
 514                                 opp-hz = /bits/ 64 <75000000>;
 515                                 required-opps = <&rpmhpd_opp_low_svs>;
 516                         };
 517
 518                         opp-120000000 {
 519                                 opp-hz = /bits/ 64 <120000000>;
 520                                 required-opps = <&rpmhpd_opp_svs>;
 521                         };
 522                 };
 523
 524                 gpi_dma2: dma-controller@800000 {
 525                         compatible = "qcom,sm8250-gpi-dma";
 526                         reg = <0 0x00800000 0 0x70000>;
 527                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 528                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 529                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 530                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 531                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 532                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
 537                         dma-channels = <10>;
 538                         dma-channel-mask = <0x3f>;
 539                         iommus = <&apps_smmu 0x76 0x0>;
 540                         #dma-cells = <3>;
 541                         status = "disabled";
 542                 };
 543
 544                 qupv3_id_2: geniqup@8c0000 {
 545                         compatible = "qcom,geni-se-qup";
 546                         reg = <0x0 0x008c0000 0x0 0x6000>;
 547                         clock-names = "m-ahb", "s-ahb";
 548                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 549                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 550                         #address-cells = <2>;
 551                         #size-cells = <2>;
 552                         iommus = <&apps_smmu 0x63 0x0>;
 553                         ranges;
 554                         status = "disabled";
 555
 556                         i2c14: i2c@880000 {
 557                                 compatible = "qcom,geni-i2c";
 558                                 reg = <0 0x00880000 0 0x4000>;
 559                                 clock-names = "se";
 560                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 561                                 pinctrl-names = "default";
 562                                 pinctrl-0 = <&qup_i2c14_default>;
 563                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 564                                 #address-cells = <1>;
 565                                 #size-cells = <0>;
 566                                 status = "disabled";
 567                         };
 568
 569                         spi14: spi@880000 {
 570                                 compatible = "qcom,geni-spi";
 571                                 reg = <0 0x00880000 0 0x4000>;
 572                                 clock-names = "se";
 573                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 574                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 575                                 #address-cells = <1>;
 576                                 #size-cells = <0>;
 577                                 power-domains = <&rpmhpd SM8250_CX>;
 578                                 operating-points-v2 = <&qup_opp_table>;
 579                                 status = "disabled";
 580                         };
 581
 582                         i2c15: i2c@884000 {
 583                                 compatible = "qcom,geni-i2c";
 584                                 reg = <0 0x00884000 0 0x4000>;
 585                                 clock-names = "se";
 586                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 587                                 pinctrl-names = "default";
 588                                 pinctrl-0 = <&qup_i2c15_default>;
 589                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 590                                 #address-cells = <1>;
 591                                 #size-cells = <0>;
 592                                 status = "disabled";
 593                         };
 594
 595                         spi15: spi@884000 {
 596                                 compatible = "qcom,geni-spi";
 597                                 reg = <0 0x00884000 0 0x4000>;
 598                                 clock-names = "se";
 599                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 600                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 601                                 #address-cells = <1>;
 602                                 #size-cells = <0>;
 603                                 power-domains = <&rpmhpd SM8250_CX>;
 604                                 operating-points-v2 = <&qup_opp_table>;
 605                                 status = "disabled";
 606                         };
 607
 608                         i2c16: i2c@888000 {
 609                                 compatible = "qcom,geni-i2c";
 610                                 reg = <0 0x00888000 0 0x4000>;
 611                                 clock-names = "se";
 612                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 613                                 pinctrl-names = "default";
 614                                 pinctrl-0 = <&qup_i2c16_default>;
 615                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 616                                 #address-cells = <1>;
 617                                 #size-cells = <0>;
 618                                 status = "disabled";
 619                         };
 620
 621                         spi16: spi@888000 {
 622                                 compatible = "qcom,geni-spi";
 623                                 reg = <0 0x00888000 0 0x4000>;
 624                                 clock-names = "se";
 625                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 626                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 627                                 #address-cells = <1>;
 628                                 #size-cells = <0>;
 629                                 power-domains = <&rpmhpd SM8250_CX>;
 630                                 operating-points-v2 = <&qup_opp_table>;
 631                                 status = "disabled";
 632                         };
 633
 634                         i2c17: i2c@88c000 {
 635                                 compatible = "qcom,geni-i2c";
 636                                 reg = <0 0x0088c000 0 0x4000>;
 637                                 clock-names = "se";
 638                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 639                                 pinctrl-names = "default";
 640                                 pinctrl-0 = <&qup_i2c17_default>;
 641                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 642                                 #address-cells = <1>;
 643                                 #size-cells = <0>;
 644                                 status = "disabled";
 645                         };
 646
 647                         spi17: spi@88c000 {
 648                                 compatible = "qcom,geni-spi";
 649                                 reg = <0 0x0088c000 0 0x4000>;
 650                                 clock-names = "se";
 651                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 652                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655                                 power-domains = <&rpmhpd SM8250_CX>;
 656                                 operating-points-v2 = <&qup_opp_table>;
 657                                 status = "disabled";
 658                         };
 659
 660                         uart17: serial@88c000 {
 661                                 compatible = "qcom,geni-uart";
 662                                 reg = <0 0x0088c000 0 0x4000>;
 663                                 clock-names = "se";
 664                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 665                                 pinctrl-names = "default";
 666                                 pinctrl-0 = <&qup_uart17_default>;
 667                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 668                                 power-domains = <&rpmhpd SM8250_CX>;
 669                                 operating-points-v2 = <&qup_opp_table>;
 670                                 status = "disabled";
 671                         };
 672
 673                         i2c18: i2c@890000 {
 674                                 compatible = "qcom,geni-i2c";
 675                                 reg = <0 0x00890000 0 0x4000>;
 676                                 clock-names = "se";
 677                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 678                                 pinctrl-names = "default";
 679                                 pinctrl-0 = <&qup_i2c18_default>;
 680                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 681                                 #address-cells = <1>;
 682                                 #size-cells = <0>;
 683                                 status = "disabled";
 684                         };
 685
 686                         spi18: spi@890000 {
 687                                 compatible = "qcom,geni-spi";
 688                                 reg = <0 0x00890000 0 0x4000>;
 689                                 clock-names = "se";
 690                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 691                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 692                                 #address-cells = <1>;
 693                                 #size-cells = <0>;
 694                                 power-domains = <&rpmhpd SM8250_CX>;
 695                                 operating-points-v2 = <&qup_opp_table>;
 696                                 status = "disabled";
 697                         };
 698
 699                         uart18: serial@890000 {
 700                                 compatible = "qcom,geni-uart";
 701                                 reg = <0 0x00890000 0 0x4000>;
 702                                 clock-names = "se";
 703                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 704                                 pinctrl-names = "default";
 705                                 pinctrl-0 = <&qup_uart18_default>;
 706                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 707                                 power-domains = <&rpmhpd SM8250_CX>;
 708                                 operating-points-v2 = <&qup_opp_table>;
 709                                 status = "disabled";
 710                         };
 711
 712                         i2c19: i2c@894000 {
 713                                 compatible = "qcom,geni-i2c";
 714                                 reg = <0 0x00894000 0 0x4000>;
 715                                 clock-names = "se";
 716                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 717                                 pinctrl-names = "default";
 718                                 pinctrl-0 = <&qup_i2c19_default>;
 719                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 720                                 #address-cells = <1>;
 721                                 #size-cells = <0>;
 722                                 status = "disabled";
 723                         };
 724
 725                         spi19: spi@894000 {
 726                                 compatible = "qcom,geni-spi";
 727                                 reg = <0 0x00894000 0 0x4000>;
 728                                 clock-names = "se";
 729                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 730                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 731                                 #address-cells = <1>;
 732                                 #size-cells = <0>;
 733                                 power-domains = <&rpmhpd SM8250_CX>;
 734                                 operating-points-v2 = <&qup_opp_table>;
 735                                 status = "disabled";
 736                         };
 737                 };
 738
 739                 gpi_dma0: dma-controller@900000 {
 740                         compatible = "qcom,sm8250-gpi-dma";
 741                         reg = <0 0x00900000 0 0x70000>;
 742                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 755                         dma-channels = <15>;
 756                         dma-channel-mask = <0x7ff>;
 757                         iommus = <&apps_smmu 0x5b6 0x0>;
 758                         #dma-cells = <3>;
 759                         status = "disabled";
 760                 };
 761
 762                 qupv3_id_0: geniqup@9c0000 {
 763                         compatible = "qcom,geni-se-qup";
 764                         reg = <0x0 0x009c0000 0x0 0x6000>;
 765                         clock-names = "m-ahb", "s-ahb";
 766                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 767                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 768                         #address-cells = <2>;
 769                         #size-cells = <2>;
 770                         iommus = <&apps_smmu 0x5a3 0x0>;
 771                         ranges;
 772                         status = "disabled";
 773
 774                         i2c0: i2c@980000 {
 775                                 compatible = "qcom,geni-i2c";
 776                                 reg = <0 0x00980000 0 0x4000>;
 777                                 clock-names = "se";
 778                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 779                                 pinctrl-names = "default";
 780                                 pinctrl-0 = <&qup_i2c0_default>;
 781                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 782                                 #address-cells = <1>;
 783                                 #size-cells = <0>;
 784                                 status = "disabled";
 785                         };
 786
 787                         spi0: spi@980000 {
 788                                 compatible = "qcom,geni-spi";
 789                                 reg = <0 0x00980000 0 0x4000>;
 790                                 clock-names = "se";
 791                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 792                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795                                 power-domains = <&rpmhpd SM8250_CX>;
 796                                 operating-points-v2 = <&qup_opp_table>;
 797                                 status = "disabled";
 798                         };
 799
 800                         i2c1: i2c@984000 {
 801                                 compatible = "qcom,geni-i2c";
 802                                 reg = <0 0x00984000 0 0x4000>;
 803                                 clock-names = "se";
 804                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 805                                 pinctrl-names = "default";
 806                                 pinctrl-0 = <&qup_i2c1_default>;
 807                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 808                                 #address-cells = <1>;
 809                                 #size-cells = <0>;
 810                                 status = "disabled";
 811                         };
 812
 813                         spi1: spi@984000 {
 814                                 compatible = "qcom,geni-spi";
 815                                 reg = <0 0x00984000 0 0x4000>;
 816                                 clock-names = "se";
 817                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 818                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 819                                 #address-cells = <1>;
 820                                 #size-cells = <0>;
 821                                 power-domains = <&rpmhpd SM8250_CX>;
 822                                 operating-points-v2 = <&qup_opp_table>;
 823                                 status = "disabled";
 824                         };
 825
 826                         i2c2: i2c@988000 {
 827                                 compatible = "qcom,geni-i2c";
 828                                 reg = <0 0x00988000 0 0x4000>;
 829                                 clock-names = "se";
 830                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 831                                 pinctrl-names = "default";
 832                                 pinctrl-0 = <&qup_i2c2_default>;
 833                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 834                                 #address-cells = <1>;
 835                                 #size-cells = <0>;
 836                                 status = "disabled";
 837                         };
 838
 839                         spi2: spi@988000 {
 840                                 compatible = "qcom,geni-spi";
 841                                 reg = <0 0x00988000 0 0x4000>;
 842                                 clock-names = "se";
 843                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 844                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 845                                 #address-cells = <1>;
 846                                 #size-cells = <0>;
 847                                 power-domains = <&rpmhpd SM8250_CX>;
 848                                 operating-points-v2 = <&qup_opp_table>;
 849                                 status = "disabled";
 850                         };
 851
 852                         uart2: serial@988000 {
 853                                 compatible = "qcom,geni-debug-uart";
 854                                 reg = <0 0x00988000 0 0x4000>;
 855                                 clock-names = "se";
 856                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 857                                 pinctrl-names = "default";
 858                                 pinctrl-0 = <&qup_uart2_default>;
 859                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 860                                 power-domains = <&rpmhpd SM8250_CX>;
 861                                 operating-points-v2 = <&qup_opp_table>;
 862                                 status = "disabled";
 863                         };
 864
 865                         i2c3: i2c@98c000 {
 866                                 compatible = "qcom,geni-i2c";
 867                                 reg = <0 0x0098c000 0 0x4000>;
 868                                 clock-names = "se";
 869                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 870                                 pinctrl-names = "default";
 871                                 pinctrl-0 = <&qup_i2c3_default>;
 872                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 873                                 #address-cells = <1>;
 874                                 #size-cells = <0>;
 875                                 status = "disabled";
 876                         };
 877
 878                         spi3: spi@98c000 {
 879                                 compatible = "qcom,geni-spi";
 880                                 reg = <0 0x0098c000 0 0x4000>;
 881                                 clock-names = "se";
 882                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 883                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886                                 power-domains = <&rpmhpd SM8250_CX>;
 887                                 operating-points-v2 = <&qup_opp_table>;
 888                                 status = "disabled";
 889                         };
 890
 891                         i2c4: i2c@990000 {
 892                                 compatible = "qcom,geni-i2c";
 893                                 reg = <0 0x00990000 0 0x4000>;
 894                                 clock-names = "se";
 895                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 896                                 pinctrl-names = "default";
 897                                 pinctrl-0 = <&qup_i2c4_default>;
 898                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 899                                 #address-cells = <1>;
 900                                 #size-cells = <0>;
 901                                 status = "disabled";
 902                         };
 903
 904                         spi4: spi@990000 {
 905                                 compatible = "qcom,geni-spi";
 906                                 reg = <0 0x00990000 0 0x4000>;
 907                                 clock-names = "se";
 908                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 909                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 910                                 #address-cells = <1>;
 911                                 #size-cells = <0>;
 912                                 power-domains = <&rpmhpd SM8250_CX>;
 913                                 operating-points-v2 = <&qup_opp_table>;
 914                                 status = "disabled";
 915                         };
 916
 917                         i2c5: i2c@994000 {
 918                                 compatible = "qcom,geni-i2c";
 919                                 reg = <0 0x00994000 0 0x4000>;
 920                                 clock-names = "se";
 921                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 922                                 pinctrl-names = "default";
 923                                 pinctrl-0 = <&qup_i2c5_default>;
 924                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 status = "disabled";
 928                         };
 929
 930                         spi5: spi@994000 {
 931                                 compatible = "qcom,geni-spi";
 932                                 reg = <0 0x00994000 0 0x4000>;
 933                                 clock-names = "se";
 934                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 935                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 936                                 #address-cells = <1>;
 937                                 #size-cells = <0>;
 938                                 power-domains = <&rpmhpd SM8250_CX>;
 939                                 operating-points-v2 = <&qup_opp_table>;
 940                                 status = "disabled";
 941                         };
 942
 943                         i2c6: i2c@998000 {
 944                                 compatible = "qcom,geni-i2c";
 945                                 reg = <0 0x00998000 0 0x4000>;
 946                                 clock-names = "se";
 947                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 948                                 pinctrl-names = "default";
 949                                 pinctrl-0 = <&qup_i2c6_default>;
 950                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953                                 status = "disabled";
 954                         };
 955
 956                         spi6: spi@998000 {
 957                                 compatible = "qcom,geni-spi";
 958                                 reg = <0 0x00998000 0 0x4000>;
 959                                 clock-names = "se";
 960                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 961                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 962                                 #address-cells = <1>;
 963                                 #size-cells = <0>;
 964                                 power-domains = <&rpmhpd SM8250_CX>;
 965                                 operating-points-v2 = <&qup_opp_table>;
 966                                 status = "disabled";
 967                         };
 968
 969                         uart6: serial@998000 {
 970                                 compatible = "qcom,geni-uart";
 971                                 reg = <0 0x00998000 0 0x4000>;
 972                                 clock-names = "se";
 973                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 974                                 pinctrl-names = "default";
 975                                 pinctrl-0 = <&qup_uart6_default>;
 976                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 977                                 power-domains = <&rpmhpd SM8250_CX>;
 978                                 operating-points-v2 = <&qup_opp_table>;
 979                                 status = "disabled";
 980                         };
 981
 982                         i2c7: i2c@99c000 {
 983                                 compatible = "qcom,geni-i2c";
 984                                 reg = <0 0x0099c000 0 0x4000>;
 985                                 clock-names = "se";
 986                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 987                                 pinctrl-names = "default";
 988                                 pinctrl-0 = <&qup_i2c7_default>;
 989                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 990                                 #address-cells = <1>;
 991                                 #size-cells = <0>;
 992                                 status = "disabled";
 993                         };
 994
 995                         spi7: spi@99c000 {
 996                                 compatible = "qcom,geni-spi";
 997                                 reg = <0 0x0099c000 0 0x4000>;
 998                                 clock-names = "se";
 999                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1000                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1001                                 #address-cells = <1>;
1002                                 #size-cells = <0>;
1003                                 power-domains = <&rpmhpd SM8250_CX>;
1004                                 operating-points-v2 = <&qup_opp_table>;
1005                                 status = "disabled";
1006                         };
1007                 };
1008
1009                 gpi_dma1: dma-controller@a00000 {
1010                         compatible = "qcom,sm8250-gpi-dma";
1011                         reg = <0 0x00a00000 0 0x70000>;
1012                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1013                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1014                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1015                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1016                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1017                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1018                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1019                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1020                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1021                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1022                         dma-channels = <10>;
1023                         dma-channel-mask = <0x3f>;
1024                         iommus = <&apps_smmu 0x56 0x0>;
1025                         #dma-cells = <3>;
1026                         status = "disabled";
1027                 };
1028
1029                 qupv3_id_1: geniqup@ac0000 {
1030                         compatible = "qcom,geni-se-qup";
1031                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1032                         clock-names = "m-ahb", "s-ahb";
1033                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1034                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1035                         #address-cells = <2>;
1036                         #size-cells = <2>;
1037                         iommus = <&apps_smmu 0x43 0x0>;
1038                         ranges;
1039                         status = "disabled";
1040
1041                         i2c8: i2c@a80000 {
1042                                 compatible = "qcom,geni-i2c";
1043                                 reg = <0 0x00a80000 0 0x4000>;
1044                                 clock-names = "se";
1045                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1046                                 pinctrl-names = "default";
1047                                 pinctrl-0 = <&qup_i2c8_default>;
1048                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1049                                 #address-cells = <1>;
1050                                 #size-cells = <0>;
1051                                 status = "disabled";
1052                         };
1053
1054                         spi8: spi@a80000 {
1055                                 compatible = "qcom,geni-spi";
1056                                 reg = <0 0x00a80000 0 0x4000>;
1057                                 clock-names = "se";
1058                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1059                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1060                                 #address-cells = <1>;
1061                                 #size-cells = <0>;
1062                                 power-domains = <&rpmhpd SM8250_CX>;
1063                                 operating-points-v2 = <&qup_opp_table>;
1064                                 status = "disabled";
1065                         };
1066
1067                         i2c9: i2c@a84000 {
1068                                 compatible = "qcom,geni-i2c";
1069                                 reg = <0 0x00a84000 0 0x4000>;
1070                                 clock-names = "se";
1071                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1072                                 pinctrl-names = "default";
1073                                 pinctrl-0 = <&qup_i2c9_default>;
1074                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1075                                 #address-cells = <1>;
1076                                 #size-cells = <0>;
1077                                 status = "disabled";
1078                         };
1079
1080                         spi9: spi@a84000 {
1081                                 compatible = "qcom,geni-spi";
1082                                 reg = <0 0x00a84000 0 0x4000>;
1083                                 clock-names = "se";
1084                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1085                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1086                                 #address-cells = <1>;
1087                                 #size-cells = <0>;
1088                                 power-domains = <&rpmhpd SM8250_CX>;
1089                                 operating-points-v2 = <&qup_opp_table>;
1090                                 status = "disabled";
1091                         };
1092
1093                         i2c10: i2c@a88000 {
1094                                 compatible = "qcom,geni-i2c";
1095                                 reg = <0 0x00a88000 0 0x4000>;
1096                                 clock-names = "se";
1097                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1098                                 pinctrl-names = "default";
1099                                 pinctrl-0 = <&qup_i2c10_default>;
1100                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1101                                 #address-cells = <1>;
1102                                 #size-cells = <0>;
1103                                 status = "disabled";
1104                         };
1105
1106                         spi10: spi@a88000 {
1107                                 compatible = "qcom,geni-spi";
1108                                 reg = <0 0x00a88000 0 0x4000>;
1109                                 clock-names = "se";
1110                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1111                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1112                                 #address-cells = <1>;
1113                                 #size-cells = <0>;
1114                                 power-domains = <&rpmhpd SM8250_CX>;
1115                                 operating-points-v2 = <&qup_opp_table>;
1116                                 status = "disabled";
1117                         };
1118
1119                         i2c11: i2c@a8c000 {
1120                                 compatible = "qcom,geni-i2c";
1121                                 reg = <0 0x00a8c000 0 0x4000>;
1122                                 clock-names = "se";
1123                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1124                                 pinctrl-names = "default";
1125                                 pinctrl-0 = <&qup_i2c11_default>;
1126                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1127                                 #address-cells = <1>;
1128                                 #size-cells = <0>;
1129                                 status = "disabled";
1130                         };
1131
1132                         spi11: spi@a8c000 {
1133                                 compatible = "qcom,geni-spi";
1134                                 reg = <0 0x00a8c000 0 0x4000>;
1135                                 clock-names = "se";
1136                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1137                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 power-domains = <&rpmhpd SM8250_CX>;
1141                                 operating-points-v2 = <&qup_opp_table>;
1142                                 status = "disabled";
1143                         };
1144
1145                         i2c12: i2c@a90000 {
1146                                 compatible = "qcom,geni-i2c";
1147                                 reg = <0 0x00a90000 0 0x4000>;
1148                                 clock-names = "se";
1149                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1150                                 pinctrl-names = "default";
1151                                 pinctrl-0 = <&qup_i2c12_default>;
1152                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1153                                 #address-cells = <1>;
1154                                 #size-cells = <0>;
1155                                 status = "disabled";
1156                         };
1157
1158                         spi12: spi@a90000 {
1159                                 compatible = "qcom,geni-spi";
1160                                 reg = <0 0x00a90000 0 0x4000>;
1161                                 clock-names = "se";
1162                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1163                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1164                                 #address-cells = <1>;
1165                                 #size-cells = <0>;
1166                                 power-domains = <&rpmhpd SM8250_CX>;
1167                                 operating-points-v2 = <&qup_opp_table>;
1168                                 status = "disabled";
1169                         };
1170
1171                         uart12: serial@a90000 {
1172                                 compatible = "qcom,geni-debug-uart";
1173                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1174                                 clock-names = "se";
1175                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1176                                 pinctrl-names = "default";
1177                                 pinctrl-0 = <&qup_uart12_default>;
1178                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1179                                 power-domains = <&rpmhpd SM8250_CX>;
1180                                 operating-points-v2 = <&qup_opp_table>;
1181                                 status = "disabled";
1182                         };
1183
1184                         i2c13: i2c@a94000 {
1185                                 compatible = "qcom,geni-i2c";
1186                                 reg = <0 0x00a94000 0 0x4000>;
1187                                 clock-names = "se";
1188                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1189                                 pinctrl-names = "default";
1190                                 pinctrl-0 = <&qup_i2c13_default>;
1191                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1192                                 #address-cells = <1>;
1193                                 #size-cells = <0>;
1194                                 status = "disabled";
1195                         };
1196
1197                         spi13: spi@a94000 {
1198                                 compatible = "qcom,geni-spi";
1199                                 reg = <0 0x00a94000 0 0x4000>;
1200                                 clock-names = "se";
1201                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1202                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1203                                 #address-cells = <1>;
1204                                 #size-cells = <0>;
1205                                 power-domains = <&rpmhpd SM8250_CX>;
1206                                 operating-points-v2 = <&qup_opp_table>;
1207                                 status = "disabled";
1208                         };
1209                 };
1210
1211                 config_noc: interconnect@1500000 {
1212                         compatible = "qcom,sm8250-config-noc";
1213                         reg = <0 0x01500000 0 0xa580>;
1214                         #interconnect-cells = <1>;
1215                         qcom,bcm-voters = <&apps_bcm_voter>;
1216                 };
1217
1218                 system_noc: interconnect@1620000 {
1219                         compatible = "qcom,sm8250-system-noc";
1220                         reg = <0 0x01620000 0 0x1c200>;
1221                         #interconnect-cells = <1>;
1222                         qcom,bcm-voters = <&apps_bcm_voter>;
1223                 };
1224
1225                 mc_virt: interconnect@163d000 {
1226                         compatible = "qcom,sm8250-mc-virt";
1227                         reg = <0 0x0163d000 0 0x1000>;
1228                         #interconnect-cells = <1>;
1229                         qcom,bcm-voters = <&apps_bcm_voter>;
1230                 };
1231
1232                 aggre1_noc: interconnect@16e0000 {
1233                         compatible = "qcom,sm8250-aggre1-noc";
1234                         reg = <0 0x016e0000 0 0x1f180>;
1235                         #interconnect-cells = <1>;
1236                         qcom,bcm-voters = <&apps_bcm_voter>;
1237                 };
1238
1239                 aggre2_noc: interconnect@1700000 {
1240                         compatible = "qcom,sm8250-aggre2-noc";
1241                         reg = <0 0x01700000 0 0x33000>;
1242                         #interconnect-cells = <1>;
1243                         qcom,bcm-voters = <&apps_bcm_voter>;
1244                 };
1245
1246                 compute_noc: interconnect@1733000 {
1247                         compatible = "qcom,sm8250-compute-noc";
1248                         reg = <0 0x01733000 0 0xa180>;
1249                         #interconnect-cells = <1>;
1250                         qcom,bcm-voters = <&apps_bcm_voter>;
1251                 };
1252
1253                 mmss_noc: interconnect@1740000 {
1254                         compatible = "qcom,sm8250-mmss-noc";
1255                         reg = <0 0x01740000 0 0x1f080>;
1256                         #interconnect-cells = <1>;
1257                         qcom,bcm-voters = <&apps_bcm_voter>;
1258                 };
1259
1260                 pcie0: pci@1c00000 {
1261                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1262                         reg = <0 0x01c00000 0 0x3000>,
1263                               <0 0x60000000 0 0xf1d>,
1264                               <0 0x60000f20 0 0xa8>,
1265                               <0 0x60001000 0 0x1000>,
1266                               <0 0x60100000 0 0x100000>;
1267                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1268                         device_type = "pci";
1269                         linux,pci-domain = <0>;
1270                         bus-range = <0x00 0xff>;
1271                         num-lanes = <1>;
1272
1273                         #address-cells = <3>;
1274                         #size-cells = <2>;
1275
1276                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1277                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1278
1279                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1280                         interrupt-names = "msi";
1281                         #interrupt-cells = <1>;
1282                         interrupt-map-mask = <0 0 0 0x7>;
1283                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1284                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1285                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1286                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1287
1288                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1289                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1290                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1291                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1292                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1293                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1294                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1295                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1296                         clock-names = "pipe",
1297                                       "aux",
1298                                       "cfg",
1299                                       "bus_master",
1300                                       "bus_slave",
1301                                       "slave_q2a",
1302                                       "tbu",
1303                                       "ddrss_sf_tbu";
1304
1305                         iommus = <&apps_smmu 0x1c00 0x7f>;
1306                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1307                                     <0x100 &apps_smmu 0x1c01 0x1>;
1308
1309                         resets = <&gcc GCC_PCIE_0_BCR>;
1310                         reset-names = "pci";
1311
1312                         power-domains = <&gcc PCIE_0_GDSC>;
1313
1314                         phys = <&pcie0_lane>;
1315                         phy-names = "pciephy";
1316
1317                         perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
1318                         enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1319
1320                         pinctrl-names = "default";
1321                         pinctrl-0 = <&pcie0_default_state>;
1322
1323                         status = "disabled";
1324                 };
1325
1326                 pcie0_phy: phy@1c06000 {
1327                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1328                         reg = <0 0x01c06000 0 0x1c0>;
1329                         #address-cells = <2>;
1330                         #size-cells = <2>;
1331                         ranges;
1332                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1333                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1334                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1335                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1336                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1337
1338                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1339                         reset-names = "phy";
1340
1341                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1342                         assigned-clock-rates = <100000000>;
1343
1344                         status = "disabled";
1345
1346                         pcie0_lane: lanes@1c06200 {
1347                                 reg = <0 0x1c06200 0 0x170>, /* tx */
1348                                       <0 0x1c06400 0 0x200>, /* rx */
1349                                       <0 0x1c06800 0 0x1f0>, /* pcs */
1350                                       <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1351                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1352                                 clock-names = "pipe0";
1353
1354                                 #phy-cells = <0>;
1355                                 clock-output-names = "pcie_0_pipe_clk";
1356                         };
1357                 };
1358
1359                 pcie1: pci@1c08000 {
1360                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1361                         reg = <0 0x01c08000 0 0x3000>,
1362                               <0 0x40000000 0 0xf1d>,
1363                               <0 0x40000f20 0 0xa8>,
1364                               <0 0x40001000 0 0x1000>,
1365                               <0 0x40100000 0 0x100000>;
1366                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1367                         device_type = "pci";
1368                         linux,pci-domain = <1>;
1369                         bus-range = <0x00 0xff>;
1370                         num-lanes = <2>;
1371
1372                         #address-cells = <3>;
1373                         #size-cells = <2>;
1374
1375                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1376                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1377
1378                         interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
1379                         interrupt-names = "msi";
1380                         #interrupt-cells = <1>;
1381                         interrupt-map-mask = <0 0 0 0x7>;
1382                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1383                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1384                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1385                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1386
1387                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1388                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1389                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1390                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1391                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1392                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1393                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1394                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1395                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1396                         clock-names = "pipe",
1397                                       "aux",
1398                                       "cfg",
1399                                       "bus_master",
1400                                       "bus_slave",
1401                                       "slave_q2a",
1402                                       "ref",
1403                                       "tbu",
1404                                       "ddrss_sf_tbu";
1405
1406                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1407                         assigned-clock-rates = <19200000>;
1408
1409                         iommus = <&apps_smmu 0x1c80 0x7f>;
1410                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1411                                     <0x100 &apps_smmu 0x1c81 0x1>;
1412
1413                         resets = <&gcc GCC_PCIE_1_BCR>;
1414                         reset-names = "pci";
1415
1416                         power-domains = <&gcc PCIE_1_GDSC>;
1417
1418                         phys = <&pcie1_lane>;
1419                         phy-names = "pciephy";
1420
1421                         perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
1422                         enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1423
1424                         pinctrl-names = "default";
1425                         pinctrl-0 = <&pcie1_default_state>;
1426
1427                         status = "disabled";
1428                 };
1429
1430                 pcie1_phy: phy@1c0e000 {
1431                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1432                         reg = <0 0x01c0e000 0 0x1c0>;
1433                         #address-cells = <2>;
1434                         #size-cells = <2>;
1435                         ranges;
1436                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1437                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1438                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1439                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1440                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1441
1442                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1443                         reset-names = "phy";
1444
1445                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1446                         assigned-clock-rates = <100000000>;
1447
1448                         status = "disabled";
1449
1450                         pcie1_lane: lanes@1c0e200 {
1451                                 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1452                                       <0 0x1c0e400 0 0x200>, /* rx0 */
1453                                       <0 0x1c0ea00 0 0x1f0>, /* pcs */
1454                                       <0 0x1c0e600 0 0x170>, /* tx1 */
1455                                       <0 0x1c0e800 0 0x200>, /* rx1 */
1456                                       <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1457                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1458                                 clock-names = "pipe0";
1459
1460                                 #phy-cells = <0>;
1461                                 clock-output-names = "pcie_1_pipe_clk";
1462                         };
1463                 };
1464
1465                 pcie2: pci@1c10000 {
1466                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1467                         reg = <0 0x01c10000 0 0x3000>,
1468                               <0 0x64000000 0 0xf1d>,
1469                               <0 0x64000f20 0 0xa8>,
1470                               <0 0x64001000 0 0x1000>,
1471                               <0 0x64100000 0 0x100000>;
1472                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1473                         device_type = "pci";
1474                         linux,pci-domain = <2>;
1475                         bus-range = <0x00 0xff>;
1476                         num-lanes = <2>;
1477
1478                         #address-cells = <3>;
1479                         #size-cells = <2>;
1480
1481                         ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
1482                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
1483
1484                         interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
1485                         interrupt-names = "msi";
1486                         #interrupt-cells = <1>;
1487                         interrupt-map-mask = <0 0 0 0x7>;
1488                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1489                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1490                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1491                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1492
1493                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1494                                  <&gcc GCC_PCIE_2_AUX_CLK>,
1495                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1496                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1497                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
1498                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
1499                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1500                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1501                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1502                         clock-names = "pipe",
1503                                       "aux",
1504                                       "cfg",
1505                                       "bus_master",
1506                                       "bus_slave",
1507                                       "slave_q2a",
1508                                       "ref",
1509                                       "tbu",
1510                                       "ddrss_sf_tbu";
1511
1512                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1513                         assigned-clock-rates = <19200000>;
1514
1515                         iommus = <&apps_smmu 0x1d00 0x7f>;
1516                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
1517                                     <0x100 &apps_smmu 0x1d01 0x1>;
1518
1519                         resets = <&gcc GCC_PCIE_2_BCR>;
1520                         reset-names = "pci";
1521
1522                         power-domains = <&gcc PCIE_2_GDSC>;
1523
1524                         phys = <&pcie2_lane>;
1525                         phy-names = "pciephy";
1526
1527                         perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
1528                         enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
1529
1530                         pinctrl-names = "default";
1531                         pinctrl-0 = <&pcie2_default_state>;
1532
1533                         status = "disabled";
1534                 };
1535
1536                 pcie2_phy: phy@1c16000 {
1537                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
1538                         reg = <0 0x1c16000 0 0x1c0>;
1539                         #address-cells = <2>;
1540                         #size-cells = <2>;
1541                         ranges;
1542                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1543                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1544                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1545                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1546                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1547
1548                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1549                         reset-names = "phy";
1550
1551                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1552                         assigned-clock-rates = <100000000>;
1553
1554                         status = "disabled";
1555
1556                         pcie2_lane: lanes@1c16200 {
1557                                 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1558                                       <0 0x1c16400 0 0x200>, /* rx0 */
1559                                       <0 0x1c16a00 0 0x1f0>, /* pcs */
1560                                       <0 0x1c16600 0 0x170>, /* tx1 */
1561                                       <0 0x1c16800 0 0x200>, /* rx1 */
1562                                       <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1563                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1564                                 clock-names = "pipe0";
1565
1566                                 #phy-cells = <0>;
1567                                 clock-output-names = "pcie_2_pipe_clk";
1568                         };
1569                 };
1570
1571                 ufs_mem_hc: ufshc@1d84000 {
1572                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1573                                      "jedec,ufs-2.0";
1574                         reg = <0 0x01d84000 0 0x3000>;
1575                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1576                         phys = <&ufs_mem_phy_lanes>;
1577                         phy-names = "ufsphy";
1578                         lanes-per-direction = <2>;
1579                         #reset-cells = <1>;
1580                         resets = <&gcc GCC_UFS_PHY_BCR>;
1581                         reset-names = "rst";
1582
1583                         power-domains = <&gcc UFS_PHY_GDSC>;
1584
1585                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1586
1587                         clock-names =
1588                                 "core_clk",
1589                                 "bus_aggr_clk",
1590                                 "iface_clk",
1591                                 "core_clk_unipro",
1592                                 "ref_clk",
1593                                 "tx_lane0_sync_clk",
1594                                 "rx_lane0_sync_clk",
1595                                 "rx_lane1_sync_clk";
1596                         clocks =
1597                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1598                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1599                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1600                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1601                                 <&rpmhcc RPMH_CXO_CLK>,
1602                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1603                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1604                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1605                         freq-table-hz =
1606                                 <37500000 300000000>,
1607                                 <0 0>,
1608                                 <0 0>,
1609                                 <37500000 300000000>,
1610                                 <0 0>,
1611                                 <0 0>,
1612                                 <0 0>,
1613                                 <0 0>;
1614
1615                         status = "disabled";
1616                 };
1617
1618                 ufs_mem_phy: phy@1d87000 {
1619                         compatible = "qcom,sm8250-qmp-ufs-phy";
1620                         reg = <0 0x01d87000 0 0x1c0>;
1621                         #address-cells = <2>;
1622                         #size-cells = <2>;
1623                         ranges;
1624                         clock-names = "ref",
1625                                       "ref_aux";
1626                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1627                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1628
1629                         resets = <&ufs_mem_hc 0>;
1630                         reset-names = "ufsphy";
1631                         status = "disabled";
1632
1633                         ufs_mem_phy_lanes: lanes@1d87400 {
1634                                 reg = <0 0x01d87400 0 0x108>,
1635                                       <0 0x01d87600 0 0x1e0>,
1636                                       <0 0x01d87c00 0 0x1dc>,
1637                                       <0 0x01d87800 0 0x108>,
1638                                       <0 0x01d87a00 0 0x1e0>;
1639                                 #phy-cells = <0>;
1640                         };
1641                 };
1642
1643                 ipa_virt: interconnect@1e00000 {
1644                         compatible = "qcom,sm8250-ipa-virt";
1645                         reg = <0 0x01e00000 0 0x1000>;
1646                         #interconnect-cells = <1>;
1647                         qcom,bcm-voters = <&apps_bcm_voter>;
1648                 };
1649
1650                 tcsr_mutex: hwlock@1f40000 {
1651                         compatible = "qcom,tcsr-mutex";
1652                         reg = <0x0 0x01f40000 0x0 0x40000>;
1653                         #hwlock-cells = <1>;
1654                 };
1655
1656                 wsamacro: codec@3240000 {
1657                         compatible = "qcom,sm8250-lpass-wsa-macro";
1658                         reg = <0 0x03240000 0 0x1000>;
1659                         clocks = <&audiocc 1>,
1660                                  <&audiocc 0>,
1661                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1662                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1663                                  <&aoncc 0>,
1664                                  <&vamacro>;
1665
1666                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
1667
1668                         #clock-cells = <0>;
1669                         clock-frequency = <9600000>;
1670                         clock-output-names = "mclk";
1671                         #sound-dai-cells = <1>;
1672
1673                         pinctrl-names = "default";
1674                         pinctrl-0 = <&wsa_swr_active>;
1675                 };
1676
1677                 swr0: soundwire-controller@3250000 {
1678                         reg = <0 0x03250000 0 0x2000>;
1679                         compatible = "qcom,soundwire-v1.5.1";
1680                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1681                         clocks = <&wsamacro>;
1682                         clock-names = "iface";
1683
1684                         qcom,din-ports = <2>;
1685                         qcom,dout-ports = <6>;
1686
1687                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1688                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1689                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1690                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
1691
1692                         #sound-dai-cells = <1>;
1693                         #address-cells = <2>;
1694                         #size-cells = <0>;
1695                 };
1696
1697                 audiocc: clock-controller@3300000 {
1698                         compatible = "qcom,sm8250-lpass-audiocc";
1699                         reg = <0 0x03300000 0 0x30000>;
1700                         #clock-cells = <1>;
1701                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1702                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1703                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1704                         clock-names = "core", "audio", "bus";
1705                 };
1706
1707                 vamacro: codec@3370000 {
1708                         compatible = "qcom,sm8250-lpass-va-macro";
1709                         reg = <0 0x03370000 0 0x1000>;
1710                         clocks = <&aoncc 0>,
1711                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1712                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1713
1714                         clock-names = "mclk", "macro", "dcodec";
1715
1716                         #clock-cells = <0>;
1717                         clock-frequency = <9600000>;
1718                         clock-output-names = "fsgen";
1719                         #sound-dai-cells = <1>;
1720                 };
1721
1722                 aoncc: clock-controller@3380000 {
1723                         compatible = "qcom,sm8250-lpass-aoncc";
1724                         reg = <0 0x03380000 0 0x40000>;
1725                         #clock-cells = <1>;
1726                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1727                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1728                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1729                         clock-names = "core", "audio", "bus";
1730                 };
1731
1732                 lpass_tlmm: pinctrl@33c0000{
1733                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
1734                         reg = <0 0x033c0000 0x0 0x20000>,
1735                               <0 0x03550000 0x0 0x10000>;
1736                         gpio-controller;
1737                         #gpio-cells = <2>;
1738                         gpio-ranges = <&lpass_tlmm 0 0 14>;
1739
1740                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1741                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1742                         clock-names = "core", "audio";
1743
1744                         wsa_swr_active: wsa-swr-active-pins {
1745                                 clk {
1746                                         pins = "gpio10";
1747                                         function = "wsa_swr_clk";
1748                                         drive-strength = <2>;
1749                                         slew-rate = <1>;
1750                                         bias-disable;
1751                                 };
1752
1753                                 data {
1754                                         pins = "gpio11";
1755                                         function = "wsa_swr_data";
1756                                         drive-strength = <2>;
1757                                         slew-rate = <1>;
1758                                         bias-bus-hold;
1759
1760                                 };
1761                         };
1762
1763                         wsa_swr_sleep: wsa-swr-sleep-pins {
1764                                 clk {
1765                                         pins = "gpio10";
1766                                         function = "wsa_swr_clk";
1767                                         drive-strength = <2>;
1768                                         input-enable;
1769                                         bias-pull-down;
1770                                 };
1771
1772                                 data {
1773                                         pins = "gpio11";
1774                                         function = "wsa_swr_data";
1775                                         drive-strength = <2>;
1776                                         input-enable;
1777                                         bias-pull-down;
1778
1779                                 };
1780                         };
1781
1782                         dmic01_active: dmic01-active-pins {
1783                                 clk {
1784                                         pins = "gpio6";
1785                                         function = "dmic1_clk";
1786                                         drive-strength = <8>;
1787                                         output-high;
1788                                 };
1789                                 data {
1790                                         pins = "gpio7";
1791                                         function = "dmic1_data";
1792                                         drive-strength = <8>;
1793                                         input-enable;
1794                                 };
1795                         };
1796
1797                         dmic01_sleep: dmic01-sleep-pins {
1798                                 clk {
1799                                         pins = "gpio6";
1800                                         function = "dmic1_clk";
1801                                         drive-strength = <2>;
1802                                         bias-disable;
1803                                         output-low;
1804                                 };
1805
1806                                 data {
1807                                         pins = "gpio7";
1808                                         function = "dmic1_data";
1809                                         drive-strength = <2>;
1810                                         pull-down;
1811                                         input-enable;
1812                                 };
1813                         };
1814                 };
1815
1816                 gpu: gpu@3d00000 {
1817                         compatible = "qcom,adreno-650.2",
1818                                      "qcom,adreno";
1819                         #stream-id-cells = <16>;
1820
1821                         reg = <0 0x03d00000 0 0x40000>;
1822                         reg-names = "kgsl_3d0_reg_memory";
1823
1824                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1825
1826                         iommus = <&adreno_smmu 0 0x401>;
1827
1828                         operating-points-v2 = <&gpu_opp_table>;
1829
1830                         qcom,gmu = <&gmu>;
1831
1832                         status = "disabled";
1833
1834                         zap-shader {
1835                                 memory-region = <&gpu_mem>;
1836                         };
1837
1838                         /* note: downstream checks gpu binning for 670 Mhz */
1839                         gpu_opp_table: opp-table {
1840                                 compatible = "operating-points-v2";
1841
1842                                 opp-670000000 {
1843                                         opp-hz = /bits/ 64 <670000000>;
1844                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1845                                 };
1846
1847                                 opp-587000000 {
1848                                         opp-hz = /bits/ 64 <587000000>;
1849                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1850                                 };
1851
1852                                 opp-525000000 {
1853                                         opp-hz = /bits/ 64 <525000000>;
1854                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1855                                 };
1856
1857                                 opp-490000000 {
1858                                         opp-hz = /bits/ 64 <490000000>;
1859                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1860                                 };
1861
1862                                 opp-441600000 {
1863                                         opp-hz = /bits/ 64 <441600000>;
1864                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1865                                 };
1866
1867                                 opp-400000000 {
1868                                         opp-hz = /bits/ 64 <400000000>;
1869                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1870                                 };
1871
1872                                 opp-305000000 {
1873                                         opp-hz = /bits/ 64 <305000000>;
1874                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1875                                 };
1876                         };
1877                 };
1878
1879                 gmu: gmu@3d6a000 {
1880                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1881
1882                         reg = <0 0x03d6a000 0 0x30000>,
1883                               <0 0x3de0000 0 0x10000>,
1884                               <0 0xb290000 0 0x10000>,
1885                               <0 0xb490000 0 0x10000>;
1886                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1887
1888                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1889                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1890                         interrupt-names = "hfi", "gmu";
1891
1892                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1893                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1894                                  <&gpucc GPU_CC_CXO_CLK>,
1895                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1896                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1897                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1898
1899                         power-domains = <&gpucc GPU_CX_GDSC>,
1900                                         <&gpucc GPU_GX_GDSC>;
1901                         power-domain-names = "cx", "gx";
1902
1903                         iommus = <&adreno_smmu 5 0x400>;
1904
1905                         operating-points-v2 = <&gmu_opp_table>;
1906
1907                         status = "disabled";
1908
1909                         gmu_opp_table: opp-table {
1910                                 compatible = "operating-points-v2";
1911
1912                                 opp-200000000 {
1913                                         opp-hz = /bits/ 64 <200000000>;
1914                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1915                                 };
1916                         };
1917                 };
1918
1919                 gpucc: clock-controller@3d90000 {
1920                         compatible = "qcom,sm8250-gpucc";
1921                         reg = <0 0x03d90000 0 0x9000>;
1922                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1923                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1924                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1925                         clock-names = "bi_tcxo",
1926                                       "gcc_gpu_gpll0_clk_src",
1927                                       "gcc_gpu_gpll0_div_clk_src";
1928                         #clock-cells = <1>;
1929                         #reset-cells = <1>;
1930                         #power-domain-cells = <1>;
1931                 };
1932
1933                 adreno_smmu: iommu@3da0000 {
1934                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1935                         reg = <0 0x03da0000 0 0x10000>;
1936                         #iommu-cells = <2>;
1937                         #global-interrupts = <2>;
1938                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1939                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1940                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1941                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1942                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1943                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1944                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1945                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1946                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1947                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1948                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1949                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1950                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1951                         clock-names = "ahb", "bus", "iface";
1952
1953                         power-domains = <&gpucc GPU_CX_GDSC>;
1954                 };
1955
1956                 slpi: remoteproc@5c00000 {
1957                         compatible = "qcom,sm8250-slpi-pas";
1958                         reg = <0 0x05c00000 0 0x4000>;
1959
1960                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1961                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1962                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1963                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1964                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1965                         interrupt-names = "wdog", "fatal", "ready",
1966                                           "handover", "stop-ack";
1967
1968                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1969                         clock-names = "xo";
1970
1971                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1972                                         <&rpmhpd SM8250_LCX>,
1973                                         <&rpmhpd SM8250_LMX>;
1974                         power-domain-names = "load_state", "lcx", "lmx";
1975
1976                         memory-region = <&slpi_mem>;
1977
1978                         qcom,smem-states = <&smp2p_slpi_out 0>;
1979                         qcom,smem-state-names = "stop";
1980
1981                         status = "disabled";
1982
1983                         glink-edge {
1984                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1985                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1986                                                              IRQ_TYPE_EDGE_RISING>;
1987                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1988                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1989
1990                                 label = "slpi";
1991                                 qcom,remote-pid = <3>;
1992
1993                                 fastrpc {
1994                                         compatible = "qcom,fastrpc";
1995                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1996                                         label = "sdsp";
1997                                         #address-cells = <1>;
1998                                         #size-cells = <0>;
1999
2000                                         compute-cb@1 {
2001                                                 compatible = "qcom,fastrpc-compute-cb";
2002                                                 reg = <1>;
2003                                                 iommus = <&apps_smmu 0x0541 0x0>;
2004                                         };
2005
2006                                         compute-cb@2 {
2007                                                 compatible = "qcom,fastrpc-compute-cb";
2008                                                 reg = <2>;
2009                                                 iommus = <&apps_smmu 0x0542 0x0>;
2010                                         };
2011
2012                                         compute-cb@3 {
2013                                                 compatible = "qcom,fastrpc-compute-cb";
2014                                                 reg = <3>;
2015                                                 iommus = <&apps_smmu 0x0543 0x0>;
2016                                                 /* note: shared-cb = <4> in downstream */
2017                                         };
2018                                 };
2019                         };
2020                 };
2021
2022                 cdsp: remoteproc@8300000 {
2023                         compatible = "qcom,sm8250-cdsp-pas";
2024                         reg = <0 0x08300000 0 0x10000>;
2025
2026                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2027                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2028                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2029                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2030                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2031                         interrupt-names = "wdog", "fatal", "ready",
2032                                           "handover", "stop-ack";
2033
2034                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2035                         clock-names = "xo";
2036
2037                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2038                                         <&rpmhpd SM8250_CX>;
2039                         power-domain-names = "load_state", "cx";
2040
2041                         memory-region = <&cdsp_mem>;
2042
2043                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2044                         qcom,smem-state-names = "stop";
2045
2046                         status = "disabled";
2047
2048                         glink-edge {
2049                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2050                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2051                                                              IRQ_TYPE_EDGE_RISING>;
2052                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2053                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2054
2055                                 label = "cdsp";
2056                                 qcom,remote-pid = <5>;
2057
2058                                 fastrpc {
2059                                         compatible = "qcom,fastrpc";
2060                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2061                                         label = "cdsp";
2062                                         #address-cells = <1>;
2063                                         #size-cells = <0>;
2064
2065                                         compute-cb@1 {
2066                                                 compatible = "qcom,fastrpc-compute-cb";
2067                                                 reg = <1>;
2068                                                 iommus = <&apps_smmu 0x1001 0x0460>;
2069                                         };
2070
2071                                         compute-cb@2 {
2072                                                 compatible = "qcom,fastrpc-compute-cb";
2073                                                 reg = <2>;
2074                                                 iommus = <&apps_smmu 0x1002 0x0460>;
2075                                         };
2076
2077                                         compute-cb@3 {
2078                                                 compatible = "qcom,fastrpc-compute-cb";
2079                                                 reg = <3>;
2080                                                 iommus = <&apps_smmu 0x1003 0x0460>;
2081                                         };
2082
2083                                         compute-cb@4 {
2084                                                 compatible = "qcom,fastrpc-compute-cb";
2085                                                 reg = <4>;
2086                                                 iommus = <&apps_smmu 0x1004 0x0460>;
2087                                         };
2088
2089                                         compute-cb@5 {
2090                                                 compatible = "qcom,fastrpc-compute-cb";
2091                                                 reg = <5>;
2092                                                 iommus = <&apps_smmu 0x1005 0x0460>;
2093                                         };
2094
2095                                         compute-cb@6 {
2096                                                 compatible = "qcom,fastrpc-compute-cb";
2097                                                 reg = <6>;
2098                                                 iommus = <&apps_smmu 0x1006 0x0460>;
2099                                         };
2100
2101                                         compute-cb@7 {
2102                                                 compatible = "qcom,fastrpc-compute-cb";
2103                                                 reg = <7>;
2104                                                 iommus = <&apps_smmu 0x1007 0x0460>;
2105                                         };
2106
2107                                         compute-cb@8 {
2108                                                 compatible = "qcom,fastrpc-compute-cb";
2109                                                 reg = <8>;
2110                                                 iommus = <&apps_smmu 0x1008 0x0460>;
2111                                         };
2112
2113                                         /* note: secure cb9 in downstream */
2114                                 };
2115                         };
2116                 };
2117
2118                 sound: sound {
2119                 };
2120
2121                 usb_1_hsphy: phy@88e3000 {
2122                         compatible = "qcom,sm8250-usb-hs-phy",
2123                                      "qcom,usb-snps-hs-7nm-phy";
2124                         reg = <0 0x088e3000 0 0x400>;
2125                         status = "disabled";
2126                         #phy-cells = <0>;
2127
2128                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2129                         clock-names = "ref";
2130
2131                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2132                 };
2133
2134                 usb_2_hsphy: phy@88e4000 {
2135                         compatible = "qcom,sm8250-usb-hs-phy",
2136                                      "qcom,usb-snps-hs-7nm-phy";
2137                         reg = <0 0x088e4000 0 0x400>;
2138                         status = "disabled";
2139                         #phy-cells = <0>;
2140
2141                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2142                         clock-names = "ref";
2143
2144                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2145                 };
2146
2147                 usb_1_qmpphy: phy@88e9000 {
2148                         compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2149                         reg = <0 0x088e9000 0 0x200>,
2150                               <0 0x088e8000 0 0x40>,
2151                               <0 0x088ea000 0 0x200>;
2152                         status = "disabled";
2153                         #address-cells = <2>;
2154                         #size-cells = <2>;
2155                         ranges;
2156
2157                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2158                                  <&rpmhcc RPMH_CXO_CLK>,
2159                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2160                         clock-names = "aux", "ref_clk_src", "com_aux";
2161
2162                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2163                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2164                         reset-names = "phy", "common";
2165
2166                         usb_1_ssphy: usb3-phy@88e9200 {
2167                                 reg = <0 0x088e9200 0 0x200>,
2168                                       <0 0x088e9400 0 0x200>,
2169                                       <0 0x088e9c00 0 0x400>,
2170                                       <0 0x088e9600 0 0x200>,
2171                                       <0 0x088e9800 0 0x200>,
2172                                       <0 0x088e9a00 0 0x100>;
2173                                 #clock-cells = <0>;
2174                                 #phy-cells = <0>;
2175                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2176                                 clock-names = "pipe0";
2177                                 clock-output-names = "usb3_phy_pipe_clk_src";
2178                         };
2179
2180                         dp_phy: dp-phy@88ea200 {
2181                                 reg = <0 0x088ea200 0 0x200>,
2182                                       <0 0x088ea400 0 0x200>,
2183                                       <0 0x088eac00 0 0x400>,
2184                                       <0 0x088ea600 0 0x200>,
2185                                       <0 0x088ea800 0 0x200>,
2186                                       <0 0x088eaa00 0 0x100>;
2187                                 #phy-cells = <0>;
2188                                 #clock-cells = <1>;
2189                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2190                                 clock-names = "pipe0";
2191                                 clock-output-names = "usb3_phy_pipe_clk_src";
2192                         };
2193                 };
2194
2195                 usb_2_qmpphy: phy@88eb000 {
2196                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2197                         reg = <0 0x088eb000 0 0x200>;
2198                         status = "disabled";
2199                         #address-cells = <2>;
2200                         #size-cells = <2>;
2201                         ranges;
2202
2203                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2204                                  <&rpmhcc RPMH_CXO_CLK>,
2205                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2206                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2207                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2208
2209                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2210                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2211                         reset-names = "phy", "common";
2212
2213                         usb_2_ssphy: lane@88eb200 {
2214                                 reg = <0 0x088eb200 0 0x200>,
2215                                       <0 0x088eb400 0 0x200>,
2216                                       <0 0x088eb800 0 0x800>;
2217                                 #clock-cells = <0>;
2218                                 #phy-cells = <0>;
2219                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2220                                 clock-names = "pipe0";
2221                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2222                         };
2223                 };
2224
2225                 sdhc_2: sdhci@8804000 {
2226                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2227                         reg = <0 0x08804000 0 0x1000>;
2228
2229                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2230                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2231                         interrupt-names = "hc_irq", "pwr_irq";
2232
2233                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234                                  <&gcc GCC_SDCC2_APPS_CLK>,
2235                                  <&rpmhcc RPMH_CXO_CLK>;
2236                         clock-names = "iface", "core", "xo";
2237                         iommus = <&apps_smmu 0x4a0 0x0>;
2238                         qcom,dll-config = <0x0007642c>;
2239                         qcom,ddr-config = <0x80040868>;
2240                         power-domains = <&rpmhpd SM8250_CX>;
2241                         operating-points-v2 = <&sdhc2_opp_table>;
2242
2243                         status = "disabled";
2244
2245                         sdhc2_opp_table: sdhc2-opp-table {
2246                                 compatible = "operating-points-v2";
2247
2248                                 opp-19200000 {
2249                                         opp-hz = /bits/ 64 <19200000>;
2250                                         required-opps = <&rpmhpd_opp_min_svs>;
2251                                 };
2252
2253                                 opp-50000000 {
2254                                         opp-hz = /bits/ 64 <50000000>;
2255                                         required-opps = <&rpmhpd_opp_low_svs>;
2256                                 };
2257
2258                                 opp-100000000 {
2259                                         opp-hz = /bits/ 64 <100000000>;
2260                                         required-opps = <&rpmhpd_opp_svs>;
2261                                 };
2262
2263                                 opp-202000000 {
2264                                         opp-hz = /bits/ 64 <202000000>;
2265                                         required-opps = <&rpmhpd_opp_svs_l1>;
2266                                 };
2267                         };
2268                 };
2269
2270                 dc_noc: interconnect@90c0000 {
2271                         compatible = "qcom,sm8250-dc-noc";
2272                         reg = <0 0x090c0000 0 0x4200>;
2273                         #interconnect-cells = <1>;
2274                         qcom,bcm-voters = <&apps_bcm_voter>;
2275                 };
2276
2277                 gem_noc: interconnect@9100000 {
2278                         compatible = "qcom,sm8250-gem-noc";
2279                         reg = <0 0x09100000 0 0xb4000>;
2280                         #interconnect-cells = <1>;
2281                         qcom,bcm-voters = <&apps_bcm_voter>;
2282                 };
2283
2284                 npu_noc: interconnect@9990000 {
2285                         compatible = "qcom,sm8250-npu-noc";
2286                         reg = <0 0x09990000 0 0x1600>;
2287                         #interconnect-cells = <1>;
2288                         qcom,bcm-voters = <&apps_bcm_voter>;
2289                 };
2290
2291                 usb_1: usb@a6f8800 {
2292                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2293                         reg = <0 0x0a6f8800 0 0x400>;
2294                         status = "disabled";
2295                         #address-cells = <2>;
2296                         #size-cells = <2>;
2297                         ranges;
2298                         dma-ranges;
2299
2300                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2301                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2302                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2303                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2304                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2305                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2306                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2307                                       "sleep", "xo";
2308
2309                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2310                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2311                         assigned-clock-rates = <19200000>, <200000000>;
2312
2313                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2314                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2315                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2316                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2317                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2318                                           "dm_hs_phy_irq", "ss_phy_irq";
2319
2320                         power-domains = <&gcc USB30_PRIM_GDSC>;
2321
2322                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2323
2324                         usb_1_dwc3: dwc3@a600000 {
2325                                 compatible = "snps,dwc3";
2326                                 reg = <0 0x0a600000 0 0xcd00>;
2327                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2328                                 iommus = <&apps_smmu 0x0 0x0>;
2329                                 snps,dis_u2_susphy_quirk;
2330                                 snps,dis_enblslpm_quirk;
2331                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2332                                 phy-names = "usb2-phy", "usb3-phy";
2333                         };
2334                 };
2335
2336                 system-cache-controller@9200000 {
2337                         compatible = "qcom,sm8250-llcc";
2338                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2339                         reg-names = "llcc_base", "llcc_broadcast_base";
2340                 };
2341
2342                 usb_2: usb@a8f8800 {
2343                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2344                         reg = <0 0x0a8f8800 0 0x400>;
2345                         status = "disabled";
2346                         #address-cells = <2>;
2347                         #size-cells = <2>;
2348                         ranges;
2349                         dma-ranges;
2350
2351                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2352                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2353                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2354                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2355                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2356                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2357                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2358                                       "sleep", "xo";
2359
2360                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2361                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2362                         assigned-clock-rates = <19200000>, <200000000>;
2363
2364                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2365                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2366                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2367                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2368                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2369                                           "dm_hs_phy_irq", "ss_phy_irq";
2370
2371                         power-domains = <&gcc USB30_SEC_GDSC>;
2372
2373                         resets = <&gcc GCC_USB30_SEC_BCR>;
2374
2375                         usb_2_dwc3: dwc3@a800000 {
2376                                 compatible = "snps,dwc3";
2377                                 reg = <0 0x0a800000 0 0xcd00>;
2378                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2379                                 iommus = <&apps_smmu 0x20 0>;
2380                                 snps,dis_u2_susphy_quirk;
2381                                 snps,dis_enblslpm_quirk;
2382                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2383                                 phy-names = "usb2-phy", "usb3-phy";
2384                         };
2385                 };
2386
2387                 venus: video-codec@aa00000 {
2388                         compatible = "qcom,sm8250-venus";
2389                         reg = <0 0x0aa00000 0 0x100000>;
2390                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2391                         power-domains = <&videocc MVS0C_GDSC>,
2392                                         <&videocc MVS0_GDSC>,
2393                                         <&rpmhpd SM8250_MX>;
2394                         power-domain-names = "venus", "vcodec0", "mx";
2395                         operating-points-v2 = <&venus_opp_table>;
2396
2397                         clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
2398                                  <&videocc VIDEO_CC_MVS0C_CLK>,
2399                                  <&videocc VIDEO_CC_MVS0_CLK>;
2400                         clock-names = "iface", "core", "vcodec0_core";
2401
2402                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
2403                                         <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
2404                         interconnect-names = "cpu-cfg", "video-mem";
2405
2406                         iommus = <&apps_smmu 0x2100 0x0400>;
2407                         memory-region = <&video_mem>;
2408
2409                         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
2410                                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
2411                         reset-names = "bus", "core";
2412
2413                         status = "disabled";
2414
2415                         video-decoder {
2416                                 compatible = "venus-decoder";
2417                         };
2418
2419                         video-encoder {
2420                                 compatible = "venus-encoder";
2421                         };
2422
2423                         venus_opp_table: venus-opp-table {
2424                                 compatible = "operating-points-v2";
2425
2426                                 opp-720000000 {
2427                                         opp-hz = /bits/ 64 <720000000>;
2428                                         required-opps = <&rpmhpd_opp_low_svs>;
2429                                 };
2430
2431                                 opp-1014000000 {
2432                                         opp-hz = /bits/ 64 <1014000000>;
2433                                         required-opps = <&rpmhpd_opp_svs>;
2434                                 };
2435
2436                                 opp-1098000000 {
2437                                         opp-hz = /bits/ 64 <1098000000>;
2438                                         required-opps = <&rpmhpd_opp_svs_l1>;
2439                                 };
2440
2441                                 opp-1332000000 {
2442                                         opp-hz = /bits/ 64 <1332000000>;
2443                                         required-opps = <&rpmhpd_opp_nom>;
2444                                 };
2445                         };
2446                 };
2447
2448                 videocc: clock-controller@abf0000 {
2449                         compatible = "qcom,sm8250-videocc";
2450                         reg = <0 0x0abf0000 0 0x10000>;
2451                         clocks = <&gcc GCC_VIDEO_AHB_CLK>,
2452                                  <&rpmhcc RPMH_CXO_CLK>,
2453                                  <&rpmhcc RPMH_CXO_CLK_A>;
2454                         mmcx-supply = <&mmcx_reg>;
2455                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
2456                         #clock-cells = <1>;
2457                         #reset-cells = <1>;
2458                         #power-domain-cells = <1>;
2459                 };
2460
2461                 mdss: mdss@ae00000 {
2462                         compatible = "qcom,sm8250-mdss";
2463                         reg = <0 0x0ae00000 0 0x1000>;
2464                         reg-names = "mdss";
2465
2466                         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
2467                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
2468                         interconnect-names = "mdp0-mem", "mdp1-mem";
2469
2470                         power-domains = <&dispcc MDSS_GDSC>;
2471
2472                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2473                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2474                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2475                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2476                         clock-names = "iface", "bus", "nrt_bus", "core";
2477
2478                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2479                         assigned-clock-rates = <460000000>;
2480
2481                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2482                         interrupt-controller;
2483                         #interrupt-cells = <1>;
2484
2485                         iommus = <&apps_smmu 0x820 0x402>;
2486
2487                         status = "disabled";
2488
2489                         #address-cells = <2>;
2490                         #size-cells = <2>;
2491                         ranges;
2492
2493                         mdss_mdp: mdp@ae01000 {
2494                                 compatible = "qcom,sm8250-dpu";
2495                                 reg = <0 0x0ae01000 0 0x8f000>,
2496                                       <0 0x0aeb0000 0 0x2008>;
2497                                 reg-names = "mdp", "vbif";
2498
2499                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2500                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2501                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2502                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2503                                 clock-names = "iface", "bus", "core", "vsync";
2504
2505                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2506                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2507                                 assigned-clock-rates = <460000000>,
2508                                                        <19200000>;
2509
2510                                 operating-points-v2 = <&mdp_opp_table>;
2511                                 power-domains = <&rpmhpd SM8250_MMCX>;
2512
2513                                 interrupt-parent = <&mdss>;
2514                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2515
2516                                 ports {
2517                                         #address-cells = <1>;
2518                                         #size-cells = <0>;
2519
2520                                         port@0 {
2521                                                 reg = <0>;
2522                                                 dpu_intf1_out: endpoint {
2523                                                         remote-endpoint = <&dsi0_in>;
2524                                                 };
2525                                         };
2526
2527                                         port@1 {
2528                                                 reg = <1>;
2529                                                 dpu_intf2_out: endpoint {
2530                                                         remote-endpoint = <&dsi1_in>;
2531                                                 };
2532                                         };
2533                                 };
2534
2535                                 mdp_opp_table: mdp-opp-table {
2536                                         compatible = "operating-points-v2";
2537
2538                                         opp-200000000 {
2539                                                 opp-hz = /bits/ 64 <200000000>;
2540                                                 required-opps = <&rpmhpd_opp_low_svs>;
2541                                         };
2542
2543                                         opp-300000000 {
2544                                                 opp-hz = /bits/ 64 <300000000>;
2545                                                 required-opps = <&rpmhpd_opp_svs>;
2546                                         };
2547
2548                                         opp-345000000 {
2549                                                 opp-hz = /bits/ 64 <345000000>;
2550                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2551                                         };
2552
2553                                         opp-460000000 {
2554                                                 opp-hz = /bits/ 64 <460000000>;
2555                                                 required-opps = <&rpmhpd_opp_nom>;
2556                                         };
2557                                 };
2558                         };
2559
2560                         dsi0: dsi@ae94000 {
2561                                 compatible = "qcom,mdss-dsi-ctrl";
2562                                 reg = <0 0x0ae94000 0 0x400>;
2563                                 reg-names = "dsi_ctrl";
2564
2565                                 interrupt-parent = <&mdss>;
2566                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2567
2568                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2569                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2570                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2571                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2572                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2573                                         <&gcc GCC_DISP_HF_AXI_CLK>;
2574                                 clock-names = "byte",
2575                                               "byte_intf",
2576                                               "pixel",
2577                                               "core",
2578                                               "iface",
2579                                               "bus";
2580
2581                                 operating-points-v2 = <&dsi_opp_table>;
2582                                 power-domains = <&rpmhpd SM8250_MMCX>;
2583
2584                                 phys = <&dsi0_phy>;
2585                                 phy-names = "dsi";
2586
2587                                 status = "disabled";
2588
2589                                 #address-cells = <1>;
2590                                 #size-cells = <0>;
2591
2592                                 ports {
2593                                         #address-cells = <1>;
2594                                         #size-cells = <0>;
2595
2596                                         port@0 {
2597                                                 reg = <0>;
2598                                                 dsi0_in: endpoint {
2599                                                         remote-endpoint = <&dpu_intf1_out>;
2600                                                 };
2601                                         };
2602
2603                                         port@1 {
2604                                                 reg = <1>;
2605                                                 dsi0_out: endpoint {
2606                                                 };
2607                                         };
2608                                 };
2609                         };
2610
2611                         dsi0_phy: dsi-phy@ae94400 {
2612                                 compatible = "qcom,dsi-phy-7nm";
2613                                 reg = <0 0x0ae94400 0 0x200>,
2614                                       <0 0x0ae94600 0 0x280>,
2615                                       <0 0x0ae94900 0 0x260>;
2616                                 reg-names = "dsi_phy",
2617                                             "dsi_phy_lane",
2618                                             "dsi_pll";
2619
2620                                 #clock-cells = <1>;
2621                                 #phy-cells = <0>;
2622
2623                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2624                                          <&rpmhcc RPMH_CXO_CLK>;
2625                                 clock-names = "iface", "ref";
2626
2627                                 status = "disabled";
2628                         };
2629
2630                         dsi1: dsi@ae96000 {
2631                                 compatible = "qcom,mdss-dsi-ctrl";
2632                                 reg = <0 0x0ae96000 0 0x400>;
2633                                 reg-names = "dsi_ctrl";
2634
2635                                 interrupt-parent = <&mdss>;
2636                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2637
2638                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2639                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2640                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2641                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2642                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2643                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2644                                 clock-names = "byte",
2645                                               "byte_intf",
2646                                               "pixel",
2647                                               "core",
2648                                               "iface",
2649                                               "bus";
2650
2651                                 operating-points-v2 = <&dsi_opp_table>;
2652                                 power-domains = <&rpmhpd SM8250_MMCX>;
2653
2654                                 phys = <&dsi1_phy>;
2655                                 phy-names = "dsi";
2656
2657                                 status = "disabled";
2658
2659                                 #address-cells = <1>;
2660                                 #size-cells = <0>;
2661
2662                                 ports {
2663                                         #address-cells = <1>;
2664                                         #size-cells = <0>;
2665
2666                                         port@0 {
2667                                                 reg = <0>;
2668                                                 dsi1_in: endpoint {
2669                                                         remote-endpoint = <&dpu_intf2_out>;
2670                                                 };
2671                                         };
2672
2673                                         port@1 {
2674                                                 reg = <1>;
2675                                                 dsi1_out: endpoint {
2676                                                 };
2677                                         };
2678                                 };
2679                         };
2680
2681                         dsi1_phy: dsi-phy@ae96400 {
2682                                 compatible = "qcom,dsi-phy-7nm";
2683                                 reg = <0 0x0ae96400 0 0x200>,
2684                                       <0 0x0ae96600 0 0x280>,
2685                                       <0 0x0ae96900 0 0x260>;
2686                                 reg-names = "dsi_phy",
2687                                             "dsi_phy_lane",
2688                                             "dsi_pll";
2689
2690                                 #clock-cells = <1>;
2691                                 #phy-cells = <0>;
2692
2693                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2694                                          <&rpmhcc RPMH_CXO_CLK>;
2695                                 clock-names = "iface", "ref";
2696
2697                                 status = "disabled";
2698
2699                                 dsi_opp_table: dsi-opp-table {
2700                                         compatible = "operating-points-v2";
2701
2702                                         opp-187500000 {
2703                                                 opp-hz = /bits/ 64 <187500000>;
2704                                                 required-opps = <&rpmhpd_opp_low_svs>;
2705                                         };
2706
2707                                         opp-300000000 {
2708                                                 opp-hz = /bits/ 64 <300000000>;
2709                                                 required-opps = <&rpmhpd_opp_svs>;
2710                                         };
2711
2712                                         opp-358000000 {
2713                                                 opp-hz = /bits/ 64 <358000000>;
2714                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2715                                         };
2716                                 };
2717                         };
2718                 };
2719
2720                 dispcc: clock-controller@af00000 {
2721                         compatible = "qcom,sm8250-dispcc";
2722                         reg = <0 0x0af00000 0 0x10000>;
2723                         mmcx-supply = <&mmcx_reg>;
2724                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2725                                  <&dsi0_phy 0>,
2726                                  <&dsi0_phy 1>,
2727                                  <&dsi1_phy 0>,
2728                                  <&dsi1_phy 1>,
2729                                  <&dp_phy 0>,
2730                                  <&dp_phy 1>;
2731                         clock-names = "bi_tcxo",
2732                                       "dsi0_phy_pll_out_byteclk",
2733                                       "dsi0_phy_pll_out_dsiclk",
2734                                       "dsi1_phy_pll_out_byteclk",
2735                                       "dsi1_phy_pll_out_dsiclk",
2736                                       "dp_phy_pll_link_clk",
2737                                       "dp_phy_pll_vco_div_clk";
2738                         #clock-cells = <1>;
2739                         #reset-cells = <1>;
2740                         #power-domain-cells = <1>;
2741                 };
2742
2743                 pdc: interrupt-controller@b220000 {
2744                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
2745                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2746                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2747                                           <125 63 1>, <126 716 12>;
2748                         #interrupt-cells = <2>;
2749                         interrupt-parent = <&intc>;
2750                         interrupt-controller;
2751                 };
2752
2753                 tsens0: thermal-sensor@c263000 {
2754                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2755                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2756                               <0 0x0c222000 0 0x1ff>; /* SROT */
2757                         #qcom,sensors = <16>;
2758                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2759                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2760                         interrupt-names = "uplow", "critical";
2761                         #thermal-sensor-cells = <1>;
2762                 };
2763
2764                 tsens1: thermal-sensor@c265000 {
2765                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2766                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2767                               <0 0x0c223000 0 0x1ff>; /* SROT */
2768                         #qcom,sensors = <9>;
2769                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2770                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2771                         interrupt-names = "uplow", "critical";
2772                         #thermal-sensor-cells = <1>;
2773                 };
2774
2775                 aoss_qmp: power-controller@c300000 {
2776                         compatible = "qcom,sm8250-aoss-qmp";
2777                         reg = <0 0x0c300000 0 0x100000>;
2778                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2779                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
2780                                                      IRQ_TYPE_EDGE_RISING>;
2781                         mboxes = <&ipcc IPCC_CLIENT_AOP
2782                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
2783
2784                         #clock-cells = <0>;
2785                         #power-domain-cells = <1>;
2786                 };
2787
2788                 spmi_bus: spmi@c440000 {
2789                         compatible = "qcom,spmi-pmic-arb";
2790                         reg = <0x0 0x0c440000 0x0 0x0001100>,
2791                               <0x0 0x0c600000 0x0 0x2000000>,
2792                               <0x0 0x0e600000 0x0 0x0100000>,
2793                               <0x0 0x0e700000 0x0 0x00a0000>,
2794                               <0x0 0x0c40a000 0x0 0x0026000>;
2795                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2796                         interrupt-names = "periph_irq";
2797                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2798                         qcom,ee = <0>;
2799                         qcom,channel = <0>;
2800                         #address-cells = <2>;
2801                         #size-cells = <0>;
2802                         interrupt-controller;
2803                         #interrupt-cells = <4>;
2804                 };
2805
2806                 tlmm: pinctrl@f100000 {
2807                         compatible = "qcom,sm8250-pinctrl";
2808                         reg = <0 0x0f100000 0 0x300000>,
2809                               <0 0x0f500000 0 0x300000>,
2810                               <0 0x0f900000 0 0x300000>;
2811                         reg-names = "west", "south", "north";
2812                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2813                         gpio-controller;
2814                         #gpio-cells = <2>;
2815                         interrupt-controller;
2816                         #interrupt-cells = <2>;
2817                         gpio-ranges = <&tlmm 0 0 181>;
2818                         wakeup-parent = <&pdc>;
2819
2820                         pri_mi2s_active: pri-mi2s-active {
2821                                 sclk {
2822                                         pins = "gpio138";
2823                                         function = "mi2s0_sck";
2824                                         drive-strength = <8>;
2825                                         bias-disable;
2826                                 };
2827
2828                                 ws {
2829                                         pins = "gpio141";
2830                                         function = "mi2s0_ws";
2831                                         drive-strength = <8>;
2832                                         output-high;
2833                                 };
2834
2835                                 data0 {
2836                                         pins = "gpio139";
2837                                         function = "mi2s0_data0";
2838                                         drive-strength = <8>;
2839                                         bias-disable;
2840                                         output-high;
2841                                 };
2842
2843                                 data1 {
2844                                         pins = "gpio140";
2845                                         function = "mi2s0_data1";
2846                                         drive-strength = <8>;
2847                                         output-high;
2848                                 };
2849                         };
2850
2851                         qup_i2c0_default: qup-i2c0-default {
2852                                 mux {
2853                                         pins = "gpio28", "gpio29";
2854                                         function = "qup0";
2855                                 };
2856
2857                                 config {
2858                                         pins = "gpio28", "gpio29";
2859                                         drive-strength = <2>;
2860                                         bias-disable;
2861                                 };
2862                         };
2863
2864                         qup_i2c1_default: qup-i2c1-default {
2865                                 pinmux {
2866                                         pins = "gpio4", "gpio5";
2867                                         function = "qup1";
2868                                 };
2869
2870                                 config {
2871                                         pins = "gpio4", "gpio5";
2872                                         drive-strength = <2>;
2873                                         bias-disable;
2874                                 };
2875                         };
2876
2877                         qup_i2c2_default: qup-i2c2-default {
2878                                 mux {
2879                                         pins = "gpio115", "gpio116";
2880                                         function = "qup2";
2881                                 };
2882
2883                                 config {
2884                                         pins = "gpio115", "gpio116";
2885                                         drive-strength = <2>;
2886                                         bias-disable;
2887                                 };
2888                         };
2889
2890                         qup_i2c3_default: qup-i2c3-default {
2891                                 mux {
2892                                         pins = "gpio119", "gpio120";
2893                                         function = "qup3";
2894                                 };
2895
2896                                 config {
2897                                         pins = "gpio119", "gpio120";
2898                                         drive-strength = <2>;
2899                                         bias-disable;
2900                                 };
2901                         };
2902
2903                         qup_i2c4_default: qup-i2c4-default {
2904                                 mux {
2905                                         pins = "gpio8", "gpio9";
2906                                         function = "qup4";
2907                                 };
2908
2909                                 config {
2910                                         pins = "gpio8", "gpio9";
2911                                         drive-strength = <2>;
2912                                         bias-disable;
2913                                 };
2914                         };
2915
2916                         qup_i2c5_default: qup-i2c5-default {
2917                                 mux {
2918                                         pins = "gpio12", "gpio13";
2919                                         function = "qup5";
2920                                 };
2921
2922                                 config {
2923                                         pins = "gpio12", "gpio13";
2924                                         drive-strength = <2>;
2925                                         bias-disable;
2926                                 };
2927                         };
2928
2929                         qup_i2c6_default: qup-i2c6-default {
2930                                 mux {
2931                                         pins = "gpio16", "gpio17";
2932                                         function = "qup6";
2933                                 };
2934
2935                                 config {
2936                                         pins = "gpio16", "gpio17";
2937                                         drive-strength = <2>;
2938                                         bias-disable;
2939                                 };
2940                         };
2941
2942                         qup_i2c7_default: qup-i2c7-default {
2943                                 mux {
2944                                         pins = "gpio20", "gpio21";
2945                                         function = "qup7";
2946                                 };
2947
2948                                 config {
2949                                         pins = "gpio20", "gpio21";
2950                                         drive-strength = <2>;
2951                                         bias-disable;
2952                                 };
2953                         };
2954
2955                         qup_i2c8_default: qup-i2c8-default {
2956                                 mux {
2957                                         pins = "gpio24", "gpio25";
2958                                         function = "qup8";
2959                                 };
2960
2961                                 config {
2962                                         pins = "gpio24", "gpio25";
2963                                         drive-strength = <2>;
2964                                         bias-disable;
2965                                 };
2966                         };
2967
2968                         qup_i2c9_default: qup-i2c9-default {
2969                                 mux {
2970                                         pins = "gpio125", "gpio126";
2971                                         function = "qup9";
2972                                 };
2973
2974                                 config {
2975                                         pins = "gpio125", "gpio126";
2976                                         drive-strength = <2>;
2977                                         bias-disable;
2978                                 };
2979                         };
2980
2981                         qup_i2c10_default: qup-i2c10-default {
2982                                 mux {
2983                                         pins = "gpio129", "gpio130";
2984                                         function = "qup10";
2985                                 };
2986
2987                                 config {
2988                                         pins = "gpio129", "gpio130";
2989                                         drive-strength = <2>;
2990                                         bias-disable;
2991                                 };
2992                         };
2993
2994                         qup_i2c11_default: qup-i2c11-default {
2995                                 mux {
2996                                         pins = "gpio60", "gpio61";
2997                                         function = "qup11";
2998                                 };
2999
3000                                 config {
3001                                         pins = "gpio60", "gpio61";
3002                                         drive-strength = <2>;
3003                                         bias-disable;
3004                                 };
3005                         };
3006
3007                         qup_i2c12_default: qup-i2c12-default {
3008                                 mux {
3009                                         pins = "gpio32", "gpio33";
3010                                         function = "qup12";
3011                                 };
3012
3013                                 config {
3014                                         pins = "gpio32", "gpio33";
3015                                         drive-strength = <2>;
3016                                         bias-disable;
3017                                 };
3018                         };
3019
3020                         qup_i2c13_default: qup-i2c13-default {
3021                                 mux {
3022                                         pins = "gpio36", "gpio37";
3023                                         function = "qup13";
3024                                 };
3025
3026                                 config {
3027                                         pins = "gpio36", "gpio37";
3028                                         drive-strength = <2>;
3029                                         bias-disable;
3030                                 };
3031                         };
3032
3033                         qup_i2c14_default: qup-i2c14-default {
3034                                 mux {
3035                                         pins = "gpio40", "gpio41";
3036                                         function = "qup14";
3037                                 };
3038
3039                                 config {
3040                                         pins = "gpio40", "gpio41";
3041                                         drive-strength = <2>;
3042                                         bias-disable;
3043                                 };
3044                         };
3045
3046                         qup_i2c15_default: qup-i2c15-default {
3047                                 mux {
3048                                         pins = "gpio44", "gpio45";
3049                                         function = "qup15";
3050                                 };
3051
3052                                 config {
3053                                         pins = "gpio44", "gpio45";
3054                                         drive-strength = <2>;
3055                                         bias-disable;
3056                                 };
3057                         };
3058
3059                         qup_i2c16_default: qup-i2c16-default {
3060                                 mux {
3061                                         pins = "gpio48", "gpio49";
3062                                         function = "qup16";
3063                                 };
3064
3065                                 config {
3066                                         pins = "gpio48", "gpio49";
3067                                         drive-strength = <2>;
3068                                         bias-disable;
3069                                 };
3070                         };
3071
3072                         qup_i2c17_default: qup-i2c17-default {
3073                                 mux {
3074                                         pins = "gpio52", "gpio53";
3075                                         function = "qup17";
3076                                 };
3077
3078                                 config {
3079                                         pins = "gpio52", "gpio53";
3080                                         drive-strength = <2>;
3081                                         bias-disable;
3082                                 };
3083                         };
3084
3085                         qup_i2c18_default: qup-i2c18-default {
3086                                 mux {
3087                                         pins = "gpio56", "gpio57";
3088                                         function = "qup18";
3089                                 };
3090
3091                                 config {
3092                                         pins = "gpio56", "gpio57";
3093                                         drive-strength = <2>;
3094                                         bias-disable;
3095                                 };
3096                         };
3097
3098                         qup_i2c19_default: qup-i2c19-default {
3099                                 mux {
3100                                         pins = "gpio0", "gpio1";
3101                                         function = "qup19";
3102                                 };
3103
3104                                 config {
3105                                         pins = "gpio0", "gpio1";
3106                                         drive-strength = <2>;
3107                                         bias-disable;
3108                                 };
3109                         };
3110
3111                         qup_spi0_cs: qup-spi0-cs {
3112                                 pins = "gpio31";
3113                                 function = "qup0";
3114                         };
3115
3116                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
3117                                 pins = "gpio31";
3118                                 function = "gpio";
3119                         };
3120
3121                         qup_spi0_data_clk: qup-spi0-data-clk {
3122                                 pins = "gpio28", "gpio29",
3123                                        "gpio30";
3124                                 function = "qup0";
3125                         };
3126
3127                         qup_spi1_cs: qup-spi1-cs {
3128                                 pins = "gpio7";
3129                                 function = "qup1";
3130                         };
3131
3132                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
3133                                 pins = "gpio7";
3134                                 function = "gpio";
3135                         };
3136
3137                         qup_spi1_data_clk: qup-spi1-data-clk {
3138                                 pins = "gpio4", "gpio5",
3139                                        "gpio6";
3140                                 function = "qup1";
3141                         };
3142
3143                         qup_spi2_cs: qup-spi2-cs {
3144                                 pins = "gpio118";
3145                                 function = "qup2";
3146                         };
3147
3148                         qup_spi2_cs_gpio: qup-spi2-cs-gpio {
3149                                 pins = "gpio118";
3150                                 function = "gpio";
3151                         };
3152
3153                         qup_spi2_data_clk: qup-spi2-data-clk {
3154                                 pins = "gpio115", "gpio116",
3155                                        "gpio117";
3156                                 function = "qup2";
3157                         };
3158
3159                         qup_spi3_cs: qup-spi3-cs {
3160                                 pins = "gpio122";
3161                                 function = "qup3";
3162                         };
3163
3164                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
3165                                 pins = "gpio122";
3166                                 function = "gpio";
3167                         };
3168
3169                         qup_spi3_data_clk: qup-spi3-data-clk {
3170                                 pins = "gpio119", "gpio120",
3171                                        "gpio121";
3172                                 function = "qup3";
3173                         };
3174
3175                         qup_spi4_cs: qup-spi4-cs {
3176                                 pins = "gpio11";
3177                                 function = "qup4";
3178                         };
3179
3180                         qup_spi4_cs_gpio: qup-spi4-cs-gpio {
3181                                 pins = "gpio11";
3182                                 function = "gpio";
3183                         };
3184
3185                         qup_spi4_data_clk: qup-spi4-data-clk {
3186                                 pins = "gpio8", "gpio9",
3187                                        "gpio10";
3188                                 function = "qup4";
3189                         };
3190
3191                         qup_spi5_cs: qup-spi5-cs {
3192                                 pins = "gpio15";
3193                                 function = "qup5";
3194                         };
3195
3196                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
3197                                 pins = "gpio15";
3198                                 function = "gpio";
3199                         };
3200
3201                         qup_spi5_data_clk: qup-spi5-data-clk {
3202                                 pins = "gpio12", "gpio13",
3203                                        "gpio14";
3204                                 function = "qup5";
3205                         };
3206
3207                         qup_spi6_cs: qup-spi6-cs {
3208                                 pins = "gpio19";
3209                                 function = "qup6";
3210                         };
3211
3212                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
3213                                 pins = "gpio19";
3214                                 function = "gpio";
3215                         };
3216
3217                         qup_spi6_data_clk: qup-spi6-data-clk {
3218                                 pins = "gpio16", "gpio17",
3219                                        "gpio18";
3220                                 function = "qup6";
3221                         };
3222
3223                         qup_spi7_cs: qup-spi7-cs {
3224                                 pins = "gpio23";
3225                                 function = "qup7";
3226                         };
3227
3228                         qup_spi7_cs_gpio: qup-spi7-cs-gpio {
3229                                 pins = "gpio23";
3230                                 function = "gpio";
3231                         };
3232
3233                         qup_spi7_data_clk: qup-spi7-data-clk {
3234                                 pins = "gpio20", "gpio21",
3235                                        "gpio22";
3236                                 function = "qup7";
3237                         };
3238
3239                         qup_spi8_cs: qup-spi8-cs {
3240                                 pins = "gpio27";
3241                                 function = "qup8";
3242                         };
3243
3244                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
3245                                 pins = "gpio27";
3246                                 function = "gpio";
3247                         };
3248
3249                         qup_spi8_data_clk: qup-spi8-data-clk {
3250                                 pins = "gpio24", "gpio25",
3251                                        "gpio26";
3252                                 function = "qup8";
3253                         };
3254
3255                         qup_spi9_cs: qup-spi9-cs {
3256                                 pins = "gpio128";
3257                                 function = "qup9";
3258                         };
3259
3260                         qup_spi9_cs_gpio: qup-spi9-cs-gpio {
3261                                 pins = "gpio128";
3262                                 function = "gpio";
3263                         };
3264
3265                         qup_spi9_data_clk: qup-spi9-data-clk {
3266                                 pins = "gpio125", "gpio126",
3267                                        "gpio127";
3268                                 function = "qup9";
3269                         };
3270
3271                         qup_spi10_cs: qup-spi10-cs {
3272                                 pins = "gpio132";
3273                                 function = "qup10";
3274                         };
3275
3276                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
3277                                 pins = "gpio132";
3278                                 function = "gpio";
3279                         };
3280
3281                         qup_spi10_data_clk: qup-spi10-data-clk {
3282                                 pins = "gpio129", "gpio130",
3283                                        "gpio131";
3284                                 function = "qup10";
3285                         };
3286
3287                         qup_spi11_cs: qup-spi11-cs {
3288                                 pins = "gpio63";
3289                                 function = "qup11";
3290                         };
3291
3292                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
3293                                 pins = "gpio63";
3294                                 function = "gpio";
3295                         };
3296
3297                         qup_spi11_data_clk: qup-spi11-data-clk {
3298                                 pins = "gpio60", "gpio61",
3299                                        "gpio62";
3300                                 function = "qup11";
3301                         };
3302
3303                         qup_spi12_cs: qup-spi12-cs {
3304                                 pins = "gpio35";
3305                                 function = "qup12";
3306                         };
3307
3308                         qup_spi12_cs_gpio: qup-spi12-cs-gpio {
3309                                 pins = "gpio35";
3310                                 function = "gpio";
3311                         };
3312
3313                         qup_spi12_data_clk: qup-spi12-data-clk {
3314                                 pins = "gpio32", "gpio33",
3315                                        "gpio34";
3316                                 function = "qup12";
3317                         };
3318
3319                         qup_spi13_cs: qup-spi13-cs {
3320                                 pins = "gpio39";
3321                                 function = "qup13";
3322                         };
3323
3324                         qup_spi13_cs_gpio: qup-spi13-cs-gpio {
3325                                 pins = "gpio39";
3326                                 function = "gpio";
3327                         };
3328
3329                         qup_spi13_data_clk: qup-spi13-data-clk {
3330                                 pins = "gpio36", "gpio37",
3331                                        "gpio38";
3332                                 function = "qup13";
3333                         };
3334
3335                         qup_spi14_cs: qup-spi14-cs {
3336                                 pins = "gpio43";
3337                                 function = "qup14";
3338                         };
3339
3340                         qup_spi14_cs_gpio: qup-spi14-cs-gpio {
3341                                 pins = "gpio43";
3342                                 function = "gpio";
3343                         };
3344
3345                         qup_spi14_data_clk: qup-spi14-data-clk {
3346                                 pins = "gpio40", "gpio41",
3347                                        "gpio42";
3348                                 function = "qup14";
3349                         };
3350
3351                         qup_spi15_cs: qup-spi15-cs {
3352                                 pins = "gpio47";
3353                                 function = "qup15";
3354                         };
3355
3356                         qup_spi15_cs_gpio: qup-spi15-cs-gpio {
3357                                 pins = "gpio47";
3358                                 function = "gpio";
3359                         };
3360
3361                         qup_spi15_data_clk: qup-spi15-data-clk {
3362                                 pins = "gpio44", "gpio45",
3363                                        "gpio46";
3364                                 function = "qup15";
3365                         };
3366
3367                         qup_spi16_cs: qup-spi16-cs {
3368                                 pins = "gpio51";
3369                                 function = "qup16";
3370                         };
3371
3372                         qup_spi16_cs_gpio: qup-spi16-cs-gpio {
3373                                 pins = "gpio51";
3374                                 function = "gpio";
3375                         };
3376
3377                         qup_spi16_data_clk: qup-spi16-data-clk {
3378                                 pins = "gpio48", "gpio49",
3379                                        "gpio50";
3380                                 function = "qup16";
3381                         };
3382
3383                         qup_spi17_cs: qup-spi17-cs {
3384                                 pins = "gpio55";
3385                                 function = "qup17";
3386                         };
3387
3388                         qup_spi17_cs_gpio: qup-spi17-cs-gpio {
3389                                 pins = "gpio55";
3390                                 function = "gpio";
3391                         };
3392
3393                         qup_spi17_data_clk: qup-spi17-data-clk {
3394                                 pins = "gpio52", "gpio53",
3395                                        "gpio54";
3396                                 function = "qup17";
3397                         };
3398
3399                         qup_spi18_cs: qup-spi18-cs {
3400                                 pins = "gpio59";
3401                                 function = "qup18";
3402                         };
3403
3404                         qup_spi18_cs_gpio: qup-spi18-cs-gpio {
3405                                 pins = "gpio59";
3406                                 function = "gpio";
3407                         };
3408
3409                         qup_spi18_data_clk: qup-spi18-data-clk {
3410                                 pins = "gpio56", "gpio57",
3411                                        "gpio58";
3412                                 function = "qup18";
3413                         };
3414
3415                         qup_spi19_cs: qup-spi19-cs {
3416                                 pins = "gpio3";
3417                                 function = "qup19";
3418                         };
3419
3420                         qup_spi19_cs_gpio: qup-spi19-cs-gpio {
3421                                 pins = "gpio3";
3422                                 function = "gpio";
3423                         };
3424
3425                         qup_spi19_data_clk: qup-spi19-data-clk {
3426                                 pins = "gpio0", "gpio1",
3427                                        "gpio2";
3428                                 function = "qup19";
3429                         };
3430
3431                         qup_uart2_default: qup-uart2-default {
3432                                 mux {
3433                                         pins = "gpio117", "gpio118";
3434                                         function = "qup2";
3435                                 };
3436                         };
3437
3438                         qup_uart6_default: qup-uart6-default {
3439                                 mux {
3440                                         pins = "gpio16", "gpio17",
3441                                                 "gpio18", "gpio19";
3442                                         function = "qup6";
3443                                 };
3444                         };
3445
3446                         qup_uart12_default: qup-uart12-default {
3447                                 mux {
3448                                         pins = "gpio34", "gpio35";
3449                                         function = "qup12";
3450                                 };
3451                         };
3452
3453                         qup_uart17_default: qup-uart17-default {
3454                                 mux {
3455                                         pins = "gpio52", "gpio53",
3456                                                 "gpio54", "gpio55";
3457                                         function = "qup17";
3458                                 };
3459                         };
3460
3461                         qup_uart18_default: qup-uart18-default {
3462                                 mux {
3463                                         pins = "gpio58", "gpio59";
3464                                         function = "qup18";
3465                                 };
3466                         };
3467
3468                         tert_mi2s_active: tert-mi2s-active {
3469                                 sck {
3470                                         pins = "gpio133";
3471                                         function = "mi2s2_sck";
3472                                         drive-strength = <8>;
3473                                         bias-disable;
3474                                 };
3475
3476                                 data0 {
3477                                         pins = "gpio134";
3478                                         function = "mi2s2_data0";
3479                                         drive-strength = <8>;
3480                                         bias-disable;
3481                                         output-high;
3482                                 };
3483
3484                                 ws {
3485                                         pins = "gpio135";
3486                                         function = "mi2s2_ws";
3487                                         drive-strength = <8>;
3488                                         output-high;
3489                                 };
3490                         };
3491
3492                         sdc2_sleep_state: sdc2-sleep {
3493                                 clk {
3494                                         pins = "sdc2_clk";
3495                                         drive-strength = <2>;
3496                                         bias-disable;
3497                                 };
3498
3499                                 cmd {
3500                                         pins = "sdc2_cmd";
3501                                         drive-strength = <2>;
3502                                         bias-pull-up;
3503                                 };
3504
3505                                 data {
3506                                         pins = "sdc2_data";
3507                                         drive-strength = <2>;
3508                                         bias-pull-up;
3509                                 };
3510                         };
3511
3512                         pcie0_default_state: pcie0-default {
3513                                 perst {
3514                                         pins = "gpio79";
3515                                         function = "gpio";
3516                                         drive-strength = <2>;
3517                                         bias-pull-down;
3518                                 };
3519
3520                                 clkreq {
3521                                         pins = "gpio80";
3522                                         function = "pci_e0";
3523                                         drive-strength = <2>;
3524                                         bias-pull-up;
3525                                 };
3526
3527                                 wake {
3528                                         pins = "gpio81";
3529                                         function = "gpio";
3530                                         drive-strength = <2>;
3531                                         bias-pull-up;
3532                                 };
3533                         };
3534
3535                         pcie1_default_state: pcie1-default {
3536                                 perst {
3537                                         pins = "gpio82";
3538                                         function = "gpio";
3539                                         drive-strength = <2>;
3540                                         bias-pull-down;
3541                                 };
3542
3543                                 clkreq {
3544                                         pins = "gpio83";
3545                                         function = "pci_e1";
3546                                         drive-strength = <2>;
3547                                         bias-pull-up;
3548                                 };
3549
3550                                 wake {
3551                                         pins = "gpio84";
3552                                         function = "gpio";
3553                                         drive-strength = <2>;
3554                                         bias-pull-up;
3555                                 };
3556                         };
3557
3558                         pcie2_default_state: pcie2-default {
3559                                 perst {
3560                                         pins = "gpio85";
3561                                         function = "gpio";
3562                                         drive-strength = <2>;
3563                                         bias-pull-down;
3564                                 };
3565
3566                                 clkreq {
3567                                         pins = "gpio86";
3568                                         function = "pci_e2";
3569                                         drive-strength = <2>;
3570                                         bias-pull-up;
3571                                 };
3572
3573                                 wake {
3574                                         pins = "gpio87";
3575                                         function = "gpio";
3576                                         drive-strength = <2>;
3577                                         bias-pull-up;
3578                                 };
3579                         };
3580                 };
3581
3582                 apps_smmu: iommu@15000000 {
3583                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3584                         reg = <0 0x15000000 0 0x100000>;
3585                         #iommu-cells = <2>;
3586                         #global-interrupts = <2>;
3587                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3588                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3589                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3590                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3591                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3592                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3593                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3594                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3595                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3596                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3597                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3598                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3599                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3600                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3601                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3602                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3603                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3604                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3605                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3606                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3607                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3608                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3609                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3610                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3611                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3612                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3613                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3614                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3615                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3616                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3617                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3618                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3619                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3620                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3621                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3622                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3623                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3624                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3625                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3626                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3627                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3628                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3629                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3630                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3631                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3632                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3633                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3634                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3635                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3636                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3637                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3638                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3639                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3640                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3641                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3642                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3643                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3644                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3645                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3646                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3647                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3648                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3649                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3650                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3651                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3652                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3653                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3654                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3655                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3656                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3657                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3658                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3659                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3660                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3661                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3662                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3663                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3664                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3665                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3666                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3667                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3668                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3669                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3670                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3671                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3672                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3673                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3674                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3675                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3676                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3677                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3678                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3679                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3680                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3681                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3682                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3683                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3684                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3685                 };
3686
3687                 adsp: remoteproc@17300000 {
3688                         compatible = "qcom,sm8250-adsp-pas";
3689                         reg = <0 0x17300000 0 0x100>;
3690
3691                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3692                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3693                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3694                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3695                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3696                         interrupt-names = "wdog", "fatal", "ready",
3697                                           "handover", "stop-ack";
3698
3699                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3700                         clock-names = "xo";
3701
3702                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3703                                         <&rpmhpd SM8250_LCX>,
3704                                         <&rpmhpd SM8250_LMX>;
3705                         power-domain-names = "load_state", "lcx", "lmx";
3706
3707                         memory-region = <&adsp_mem>;
3708
3709                         qcom,smem-states = <&smp2p_adsp_out 0>;
3710                         qcom,smem-state-names = "stop";
3711
3712                         status = "disabled";
3713
3714                         glink-edge {
3715                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3716                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3717                                                              IRQ_TYPE_EDGE_RISING>;
3718                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
3719                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3720
3721                                 label = "lpass";
3722                                 qcom,remote-pid = <2>;
3723
3724                                 apr {
3725                                         compatible = "qcom,apr-v2";
3726                                         qcom,glink-channels = "apr_audio_svc";
3727                                         qcom,apr-domain = <APR_DOMAIN_ADSP>;
3728                                         #address-cells = <1>;
3729                                         #size-cells = <0>;
3730
3731                                         apr-service@3 {
3732                                                 reg = <APR_SVC_ADSP_CORE>;
3733                                                 compatible = "qcom,q6core";
3734                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3735                                         };
3736
3737                                         q6afe: apr-service@4 {
3738                                                 compatible = "qcom,q6afe";
3739                                                 reg = <APR_SVC_AFE>;
3740                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3741                                                 q6afedai: dais {
3742                                                         compatible = "qcom,q6afe-dais";
3743                                                         #address-cells = <1>;
3744                                                         #size-cells = <0>;
3745                                                         #sound-dai-cells = <1>;
3746                                                 };
3747
3748                                                 q6afecc: cc {
3749                                                         compatible = "qcom,q6afe-clocks";
3750                                                         #clock-cells = <2>;
3751                                                 };
3752                                         };
3753
3754                                         q6asm: apr-service@7 {
3755                                                 compatible = "qcom,q6asm";
3756                                                 reg = <APR_SVC_ASM>;
3757                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3758                                                 q6asmdai: dais {
3759                                                         compatible = "qcom,q6asm-dais";
3760                                                         #address-cells = <1>;
3761                                                         #size-cells = <0>;
3762                                                         #sound-dai-cells = <1>;
3763                                                         iommus = <&apps_smmu 0x1801 0x0>;
3764                                                 };
3765                                         };
3766
3767                                         q6adm: apr-service@8 {
3768                                                 compatible = "qcom,q6adm";
3769                                                 reg = <APR_SVC_ADM>;
3770                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3771                                                 q6routing: routing {
3772                                                         compatible = "qcom,q6adm-routing";
3773                                                         #sound-dai-cells = <0>;
3774                                                 };
3775                                         };
3776                                 };
3777
3778                                 fastrpc {
3779                                         compatible = "qcom,fastrpc";
3780                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3781                                         label = "adsp";
3782                                         #address-cells = <1>;
3783                                         #size-cells = <0>;
3784
3785                                         compute-cb@3 {
3786                                                 compatible = "qcom,fastrpc-compute-cb";
3787                                                 reg = <3>;
3788                                                 iommus = <&apps_smmu 0x1803 0x0>;
3789                                         };
3790
3791                                         compute-cb@4 {
3792                                                 compatible = "qcom,fastrpc-compute-cb";
3793                                                 reg = <4>;
3794                                                 iommus = <&apps_smmu 0x1804 0x0>;
3795                                         };
3796
3797                                         compute-cb@5 {
3798                                                 compatible = "qcom,fastrpc-compute-cb";
3799                                                 reg = <5>;
3800                                                 iommus = <&apps_smmu 0x1805 0x0>;
3801                                         };
3802                                 };
3803                         };
3804                 };
3805
3806                 intc: interrupt-controller@17a00000 {
3807                         compatible = "arm,gic-v3";
3808                         #interrupt-cells = <3>;
3809                         interrupt-controller;
3810                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3811                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3812                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3813                 };
3814
3815                 watchdog@17c10000 {
3816                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3817                         reg = <0 0x17c10000 0 0x1000>;
3818                         clocks = <&sleep_clk>;
3819                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3820                 };
3821
3822                 timer@17c20000 {
3823                         #address-cells = <2>;
3824                         #size-cells = <2>;
3825                         ranges;
3826                         compatible = "arm,armv7-timer-mem";
3827                         reg = <0x0 0x17c20000 0x0 0x1000>;
3828                         clock-frequency = <19200000>;
3829
3830                         frame@17c21000 {
3831                                 frame-number = <0>;
3832                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3833                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3834                                 reg = <0x0 0x17c21000 0x0 0x1000>,
3835                                       <0x0 0x17c22000 0x0 0x1000>;
3836                         };
3837
3838                         frame@17c23000 {
3839                                 frame-number = <1>;
3840                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3841                                 reg = <0x0 0x17c23000 0x0 0x1000>;
3842                                 status = "disabled";
3843                         };
3844
3845                         frame@17c25000 {
3846                                 frame-number = <2>;
3847                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3848                                 reg = <0x0 0x17c25000 0x0 0x1000>;
3849                                 status = "disabled";
3850                         };
3851
3852                         frame@17c27000 {
3853                                 frame-number = <3>;
3854                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3855                                 reg = <0x0 0x17c27000 0x0 0x1000>;
3856                                 status = "disabled";
3857                         };
3858
3859                         frame@17c29000 {
3860                                 frame-number = <4>;
3861                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3862                                 reg = <0x0 0x17c29000 0x0 0x1000>;
3863                                 status = "disabled";
3864                         };
3865
3866                         frame@17c2b000 {
3867                                 frame-number = <5>;
3868                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3869                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
3870                                 status = "disabled";
3871                         };
3872
3873                         frame@17c2d000 {
3874                                 frame-number = <6>;
3875                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3876                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
3877                                 status = "disabled";
3878                         };
3879                 };
3880
3881                 apps_rsc: rsc@18200000 {
3882                         label = "apps_rsc";
3883                         compatible = "qcom,rpmh-rsc";
3884                         reg = <0x0 0x18200000 0x0 0x10000>,
3885                                 <0x0 0x18210000 0x0 0x10000>,
3886                                 <0x0 0x18220000 0x0 0x10000>;
3887                         reg-names = "drv-0", "drv-1", "drv-2";
3888                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3889                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3890                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3891                         qcom,tcs-offset = <0xd00>;
3892                         qcom,drv-id = <2>;
3893                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3894                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
3895
3896                         rpmhcc: clock-controller {
3897                                 compatible = "qcom,sm8250-rpmh-clk";
3898                                 #clock-cells = <1>;
3899                                 clock-names = "xo";
3900                                 clocks = <&xo_board>;
3901                         };
3902
3903                         rpmhpd: power-controller {
3904                                 compatible = "qcom,sm8250-rpmhpd";
3905                                 #power-domain-cells = <1>;
3906                                 operating-points-v2 = <&rpmhpd_opp_table>;
3907
3908                                 rpmhpd_opp_table: opp-table {
3909                                         compatible = "operating-points-v2";
3910
3911                                         rpmhpd_opp_ret: opp1 {
3912                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3913                                         };
3914
3915                                         rpmhpd_opp_min_svs: opp2 {
3916                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3917                                         };
3918
3919                                         rpmhpd_opp_low_svs: opp3 {
3920                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3921                                         };
3922
3923                                         rpmhpd_opp_svs: opp4 {
3924                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3925                                         };
3926
3927                                         rpmhpd_opp_svs_l1: opp5 {
3928                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3929                                         };
3930
3931                                         rpmhpd_opp_nom: opp6 {
3932                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3933                                         };
3934
3935                                         rpmhpd_opp_nom_l1: opp7 {
3936                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3937                                         };
3938
3939                                         rpmhpd_opp_nom_l2: opp8 {
3940                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3941                                         };
3942
3943                                         rpmhpd_opp_turbo: opp9 {
3944                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3945                                         };
3946
3947                                         rpmhpd_opp_turbo_l1: opp10 {
3948                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3949                                         };
3950                                 };
3951                         };
3952
3953                         apps_bcm_voter: bcm_voter {
3954                                 compatible = "qcom,bcm-voter";
3955                         };
3956                 };
3957
3958                 epss_l3: interconnect@18591000 {
3959                         compatible = "qcom,sm8250-epss-l3";
3960                         reg = <0 0x18590000 0 0x1000>;
3961
3962                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3963                         clock-names = "xo", "alternate";
3964
3965                         #interconnect-cells = <1>;
3966                 };
3967
3968                 cpufreq_hw: cpufreq@18591000 {
3969                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
3970                         reg = <0 0x18591000 0 0x1000>,
3971                               <0 0x18592000 0 0x1000>,
3972                               <0 0x18593000 0 0x1000>;
3973                         reg-names = "freq-domain0", "freq-domain1",
3974                                     "freq-domain2";
3975
3976                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3977                         clock-names = "xo", "alternate";
3978
3979                         #freq-domain-cells = <1>;
3980                 };
3981         };
3982
3983         timer {
3984                 compatible = "arm,armv8-timer";
3985                 interrupts = <GIC_PPI 13
3986                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3987                              <GIC_PPI 14
3988                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3989                              <GIC_PPI 11
3990                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3991                              <GIC_PPI 10
3992                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3993         };
3994
3995         thermal-zones {
3996                 cpu0-thermal {
3997                         polling-delay-passive = <250>;
3998                         polling-delay = <1000>;
3999
4000                         thermal-sensors = <&tsens0 1>;
4001
4002                         trips {
4003                                 cpu0_alert0: trip-point0 {
4004                                         temperature = <90000>;
4005                                         hysteresis = <2000>;
4006                                         type = "passive";
4007                                 };
4008
4009                                 cpu0_alert1: trip-point1 {
4010                                         temperature = <95000>;
4011                                         hysteresis = <2000>;
4012                                         type = "passive";
4013                                 };
4014
4015                                 cpu0_crit: cpu_crit {
4016                                         temperature = <110000>;
4017                                         hysteresis = <1000>;
4018                                         type = "critical";
4019                                 };
4020                         };
4021
4022                         cooling-maps {
4023                                 map0 {
4024                                         trip = <&cpu0_alert0>;
4025                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4026                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4027                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4028                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4029                                 };
4030                                 map1 {
4031                                         trip = <&cpu0_alert1>;
4032                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4033                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4034                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4035                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4036                                 };
4037                         };
4038                 };
4039
4040                 cpu1-thermal {
4041                         polling-delay-passive = <250>;
4042                         polling-delay = <1000>;
4043
4044                         thermal-sensors = <&tsens0 2>;
4045
4046                         trips {
4047                                 cpu1_alert0: trip-point0 {
4048                                         temperature = <90000>;
4049                                         hysteresis = <2000>;
4050                                         type = "passive";
4051                                 };
4052
4053                                 cpu1_alert1: trip-point1 {
4054                                         temperature = <95000>;
4055                                         hysteresis = <2000>;
4056                                         type = "passive";
4057                                 };
4058
4059                                 cpu1_crit: cpu_crit {
4060                                         temperature = <110000>;
4061                                         hysteresis = <1000>;
4062                                         type = "critical";
4063                                 };
4064                         };
4065
4066                         cooling-maps {
4067                                 map0 {
4068                                         trip = <&cpu1_alert0>;
4069                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4072                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4073                                 };
4074                                 map1 {
4075                                         trip = <&cpu1_alert1>;
4076                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4080                                 };
4081                         };
4082                 };
4083
4084                 cpu2-thermal {
4085                         polling-delay-passive = <250>;
4086                         polling-delay = <1000>;
4087
4088                         thermal-sensors = <&tsens0 3>;
4089
4090                         trips {
4091                                 cpu2_alert0: trip-point0 {
4092                                         temperature = <90000>;
4093                                         hysteresis = <2000>;
4094                                         type = "passive";
4095                                 };
4096
4097                                 cpu2_alert1: trip-point1 {
4098                                         temperature = <95000>;
4099                                         hysteresis = <2000>;
4100                                         type = "passive";
4101                                 };
4102
4103                                 cpu2_crit: cpu_crit {
4104                                         temperature = <110000>;
4105                                         hysteresis = <1000>;
4106                                         type = "critical";
4107                                 };
4108                         };
4109
4110                         cooling-maps {
4111                                 map0 {
4112                                         trip = <&cpu2_alert0>;
4113                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4114                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4117                                 };
4118                                 map1 {
4119                                         trip = <&cpu2_alert1>;
4120                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4121                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4122                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4123                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4124                                 };
4125                         };
4126                 };
4127
4128                 cpu3-thermal {
4129                         polling-delay-passive = <250>;
4130                         polling-delay = <1000>;
4131
4132                         thermal-sensors = <&tsens0 4>;
4133
4134                         trips {
4135                                 cpu3_alert0: trip-point0 {
4136                                         temperature = <90000>;
4137                                         hysteresis = <2000>;
4138                                         type = "passive";
4139                                 };
4140
4141                                 cpu3_alert1: trip-point1 {
4142                                         temperature = <95000>;
4143                                         hysteresis = <2000>;
4144                                         type = "passive";
4145                                 };
4146
4147                                 cpu3_crit: cpu_crit {
4148                                         temperature = <110000>;
4149                                         hysteresis = <1000>;
4150                                         type = "critical";
4151                                 };
4152                         };
4153
4154                         cooling-maps {
4155                                 map0 {
4156                                         trip = <&cpu3_alert0>;
4157                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4158                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4159                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4160                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4161                                 };
4162                                 map1 {
4163                                         trip = <&cpu3_alert1>;
4164                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168                                 };
4169                         };
4170                 };
4171
4172                 cpu4-top-thermal {
4173                         polling-delay-passive = <250>;
4174                         polling-delay = <1000>;
4175
4176                         thermal-sensors = <&tsens0 7>;
4177
4178                         trips {
4179                                 cpu4_top_alert0: trip-point0 {
4180                                         temperature = <90000>;
4181                                         hysteresis = <2000>;
4182                                         type = "passive";
4183                                 };
4184
4185                                 cpu4_top_alert1: trip-point1 {
4186                                         temperature = <95000>;
4187                                         hysteresis = <2000>;
4188                                         type = "passive";
4189                                 };
4190
4191                                 cpu4_top_crit: cpu_crit {
4192                                         temperature = <110000>;
4193                                         hysteresis = <1000>;
4194                                         type = "critical";
4195                                 };
4196                         };
4197
4198                         cooling-maps {
4199                                 map0 {
4200                                         trip = <&cpu4_top_alert0>;
4201                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4202                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4203                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4204                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4205                                 };
4206                                 map1 {
4207                                         trip = <&cpu4_top_alert1>;
4208                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4209                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4210                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4212                                 };
4213                         };
4214                 };
4215
4216                 cpu5-top-thermal {
4217                         polling-delay-passive = <250>;
4218                         polling-delay = <1000>;
4219
4220                         thermal-sensors = <&tsens0 8>;
4221
4222                         trips {
4223                                 cpu5_top_alert0: trip-point0 {
4224                                         temperature = <90000>;
4225                                         hysteresis = <2000>;
4226                                         type = "passive";
4227                                 };
4228
4229                                 cpu5_top_alert1: trip-point1 {
4230                                         temperature = <95000>;
4231                                         hysteresis = <2000>;
4232                                         type = "passive";
4233                                 };
4234
4235                                 cpu5_top_crit: cpu_crit {
4236                                         temperature = <110000>;
4237                                         hysteresis = <1000>;
4238                                         type = "critical";
4239                                 };
4240                         };
4241
4242                         cooling-maps {
4243                                 map0 {
4244                                         trip = <&cpu5_top_alert0>;
4245                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4246                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4247                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4248                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4249                                 };
4250                                 map1 {
4251                                         trip = <&cpu5_top_alert1>;
4252                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4253                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4254                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4255                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4256                                 };
4257                         };
4258                 };
4259
4260                 cpu6-top-thermal {
4261                         polling-delay-passive = <250>;
4262                         polling-delay = <1000>;
4263
4264                         thermal-sensors = <&tsens0 9>;
4265
4266                         trips {
4267                                 cpu6_top_alert0: trip-point0 {
4268                                         temperature = <90000>;
4269                                         hysteresis = <2000>;
4270                                         type = "passive";
4271                                 };
4272
4273                                 cpu6_top_alert1: trip-point1 {
4274                                         temperature = <95000>;
4275                                         hysteresis = <2000>;
4276                                         type = "passive";
4277                                 };
4278
4279                                 cpu6_top_crit: cpu_crit {
4280                                         temperature = <110000>;
4281                                         hysteresis = <1000>;
4282                                         type = "critical";
4283                                 };
4284                         };
4285
4286                         cooling-maps {
4287                                 map0 {
4288                                         trip = <&cpu6_top_alert0>;
4289                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4290                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4291                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4292                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4293                                 };
4294                                 map1 {
4295                                         trip = <&cpu6_top_alert1>;
4296                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4297                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4298                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4299                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4300                                 };
4301                         };
4302                 };
4303
4304                 cpu7-top-thermal {
4305                         polling-delay-passive = <250>;
4306                         polling-delay = <1000>;
4307
4308                         thermal-sensors = <&tsens0 10>;
4309
4310                         trips {
4311                                 cpu7_top_alert0: trip-point0 {
4312                                         temperature = <90000>;
4313                                         hysteresis = <2000>;
4314                                         type = "passive";
4315                                 };
4316
4317                                 cpu7_top_alert1: trip-point1 {
4318                                         temperature = <95000>;
4319                                         hysteresis = <2000>;
4320                                         type = "passive";
4321                                 };
4322
4323                                 cpu7_top_crit: cpu_crit {
4324                                         temperature = <110000>;
4325                                         hysteresis = <1000>;
4326                                         type = "critical";
4327                                 };
4328                         };
4329
4330                         cooling-maps {
4331                                 map0 {
4332                                         trip = <&cpu7_top_alert0>;
4333                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4334                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4335                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4336                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4337                                 };
4338                                 map1 {
4339                                         trip = <&cpu7_top_alert1>;
4340                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4341                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4342                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4343                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4344                                 };
4345                         };
4346                 };
4347
4348                 cpu4-bottom-thermal {
4349                         polling-delay-passive = <250>;
4350                         polling-delay = <1000>;
4351
4352                         thermal-sensors = <&tsens0 11>;
4353
4354                         trips {
4355                                 cpu4_bottom_alert0: trip-point0 {
4356                                         temperature = <90000>;
4357                                         hysteresis = <2000>;
4358                                         type = "passive";
4359                                 };
4360
4361                                 cpu4_bottom_alert1: trip-point1 {
4362                                         temperature = <95000>;
4363                                         hysteresis = <2000>;
4364                                         type = "passive";
4365                                 };
4366
4367                                 cpu4_bottom_crit: cpu_crit {
4368                                         temperature = <110000>;
4369                                         hysteresis = <1000>;
4370                                         type = "critical";
4371                                 };
4372                         };
4373
4374                         cooling-maps {
4375                                 map0 {
4376                                         trip = <&cpu4_bottom_alert0>;
4377                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4378                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4379                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4380                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4381                                 };
4382                                 map1 {
4383                                         trip = <&cpu4_bottom_alert1>;
4384                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4385                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4386                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4387                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4388                                 };
4389                         };
4390                 };
4391
4392                 cpu5-bottom-thermal {
4393                         polling-delay-passive = <250>;
4394                         polling-delay = <1000>;
4395
4396                         thermal-sensors = <&tsens0 12>;
4397
4398                         trips {
4399                                 cpu5_bottom_alert0: trip-point0 {
4400                                         temperature = <90000>;
4401                                         hysteresis = <2000>;
4402                                         type = "passive";
4403                                 };
4404
4405                                 cpu5_bottom_alert1: trip-point1 {
4406                                         temperature = <95000>;
4407                                         hysteresis = <2000>;
4408                                         type = "passive";
4409                                 };
4410
4411                                 cpu5_bottom_crit: cpu_crit {
4412                                         temperature = <110000>;
4413                                         hysteresis = <1000>;
4414                                         type = "critical";
4415                                 };
4416                         };
4417
4418                         cooling-maps {
4419                                 map0 {
4420                                         trip = <&cpu5_bottom_alert0>;
4421                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4422                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4423                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4424                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4425                                 };
4426                                 map1 {
4427                                         trip = <&cpu5_bottom_alert1>;
4428                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4429                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4430                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4431                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4432                                 };
4433                         };
4434                 };
4435
4436                 cpu6-bottom-thermal {
4437                         polling-delay-passive = <250>;
4438                         polling-delay = <1000>;
4439
4440                         thermal-sensors = <&tsens0 13>;
4441
4442                         trips {
4443                                 cpu6_bottom_alert0: trip-point0 {
4444                                         temperature = <90000>;
4445                                         hysteresis = <2000>;
4446                                         type = "passive";
4447                                 };
4448
4449                                 cpu6_bottom_alert1: trip-point1 {
4450                                         temperature = <95000>;
4451                                         hysteresis = <2000>;
4452                                         type = "passive";
4453                                 };
4454
4455                                 cpu6_bottom_crit: cpu_crit {
4456                                         temperature = <110000>;
4457                                         hysteresis = <1000>;
4458                                         type = "critical";
4459                                 };
4460                         };
4461
4462                         cooling-maps {
4463                                 map0 {
4464                                         trip = <&cpu6_bottom_alert0>;
4465                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4466                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4467                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4468                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4469                                 };
4470                                 map1 {
4471                                         trip = <&cpu6_bottom_alert1>;
4472                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4473                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4474                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476                                 };
4477                         };
4478                 };
4479
4480                 cpu7-bottom-thermal {
4481                         polling-delay-passive = <250>;
4482                         polling-delay = <1000>;
4483
4484                         thermal-sensors = <&tsens0 14>;
4485
4486                         trips {
4487                                 cpu7_bottom_alert0: trip-point0 {
4488                                         temperature = <90000>;
4489                                         hysteresis = <2000>;
4490                                         type = "passive";
4491                                 };
4492
4493                                 cpu7_bottom_alert1: trip-point1 {
4494                                         temperature = <95000>;
4495                                         hysteresis = <2000>;
4496                                         type = "passive";
4497                                 };
4498
4499                                 cpu7_bottom_crit: cpu_crit {
4500                                         temperature = <110000>;
4501                                         hysteresis = <1000>;
4502                                         type = "critical";
4503                                 };
4504                         };
4505
4506                         cooling-maps {
4507                                 map0 {
4508                                         trip = <&cpu7_bottom_alert0>;
4509                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4510                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4511                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4512                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4513                                 };
4514                                 map1 {
4515                                         trip = <&cpu7_bottom_alert1>;
4516                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4517                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4518                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4519                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4520                                 };
4521                         };
4522                 };
4523
4524                 aoss0-thermal {
4525                         polling-delay-passive = <250>;
4526                         polling-delay = <1000>;
4527
4528                         thermal-sensors = <&tsens0 0>;
4529
4530                         trips {
4531                                 aoss0_alert0: trip-point0 {
4532                                         temperature = <90000>;
4533                                         hysteresis = <2000>;
4534                                         type = "hot";
4535                                 };
4536                         };
4537                 };
4538
4539                 cluster0-thermal {
4540                         polling-delay-passive = <250>;
4541                         polling-delay = <1000>;
4542
4543                         thermal-sensors = <&tsens0 5>;
4544
4545                         trips {
4546                                 cluster0_alert0: trip-point0 {
4547                                         temperature = <90000>;
4548                                         hysteresis = <2000>;
4549                                         type = "hot";
4550                                 };
4551                                 cluster0_crit: cluster0_crit {
4552                                         temperature = <110000>;
4553                                         hysteresis = <2000>;
4554                                         type = "critical";
4555                                 };
4556                         };
4557                 };
4558
4559                 cluster1-thermal {
4560                         polling-delay-passive = <250>;
4561                         polling-delay = <1000>;
4562
4563                         thermal-sensors = <&tsens0 6>;
4564
4565                         trips {
4566                                 cluster1_alert0: trip-point0 {
4567                                         temperature = <90000>;
4568                                         hysteresis = <2000>;
4569                                         type = "hot";
4570                                 };
4571                                 cluster1_crit: cluster1_crit {
4572                                         temperature = <110000>;
4573                                         hysteresis = <2000>;
4574                                         type = "critical";
4575                                 };
4576                         };
4577                 };
4578
4579                 gpu-thermal-top {
4580                         polling-delay-passive = <250>;
4581                         polling-delay = <1000>;
4582
4583                         thermal-sensors = <&tsens0 15>;
4584
4585                         trips {
4586                                 gpu1_alert0: trip-point0 {
4587                                         temperature = <90000>;
4588                                         hysteresis = <2000>;
4589                                         type = "hot";
4590                                 };
4591                         };
4592                 };
4593
4594                 aoss1-thermal {
4595                         polling-delay-passive = <250>;
4596                         polling-delay = <1000>;
4597
4598                         thermal-sensors = <&tsens1 0>;
4599
4600                         trips {
4601                                 aoss1_alert0: trip-point0 {
4602                                         temperature = <90000>;
4603                                         hysteresis = <2000>;
4604                                         type = "hot";
4605                                 };
4606                         };
4607                 };
4608
4609                 wlan-thermal {
4610                         polling-delay-passive = <250>;
4611                         polling-delay = <1000>;
4612
4613                         thermal-sensors = <&tsens1 1>;
4614
4615                         trips {
4616                                 wlan_alert0: trip-point0 {
4617                                         temperature = <90000>;
4618                                         hysteresis = <2000>;
4619                                         type = "hot";
4620                                 };
4621                         };
4622                 };
4623
4624                 video-thermal {
4625                         polling-delay-passive = <250>;
4626                         polling-delay = <1000>;
4627
4628                         thermal-sensors = <&tsens1 2>;
4629
4630                         trips {
4631                                 video_alert0: trip-point0 {
4632                                         temperature = <90000>;
4633                                         hysteresis = <2000>;
4634                                         type = "hot";
4635                                 };
4636                         };
4637                 };
4638
4639                 mem-thermal {
4640                         polling-delay-passive = <250>;
4641                         polling-delay = <1000>;
4642
4643                         thermal-sensors = <&tsens1 3>;
4644
4645                         trips {
4646                                 mem_alert0: trip-point0 {
4647                                         temperature = <90000>;
4648                                         hysteresis = <2000>;
4649                                         type = "hot";
4650                                 };
4651                         };
4652                 };
4653
4654                 q6-hvx-thermal {
4655                         polling-delay-passive = <250>;
4656                         polling-delay = <1000>;
4657
4658                         thermal-sensors = <&tsens1 4>;
4659
4660                         trips {
4661                                 q6_hvx_alert0: trip-point0 {
4662                                         temperature = <90000>;
4663                                         hysteresis = <2000>;
4664                                         type = "hot";
4665                                 };
4666                         };
4667                 };
4668
4669                 camera-thermal {
4670                         polling-delay-passive = <250>;
4671                         polling-delay = <1000>;
4672
4673                         thermal-sensors = <&tsens1 5>;
4674
4675                         trips {
4676                                 camera_alert0: trip-point0 {
4677                                         temperature = <90000>;
4678                                         hysteresis = <2000>;
4679                                         type = "hot";
4680                                 };
4681                         };
4682                 };
4683
4684                 compute-thermal {
4685                         polling-delay-passive = <250>;
4686                         polling-delay = <1000>;
4687
4688                         thermal-sensors = <&tsens1 6>;
4689
4690                         trips {
4691                                 compute_alert0: trip-point0 {
4692                                         temperature = <90000>;
4693                                         hysteresis = <2000>;
4694                                         type = "hot";
4695                                 };
4696                         };
4697                 };
4698
4699                 npu-thermal {
4700                         polling-delay-passive = <250>;
4701                         polling-delay = <1000>;
4702
4703                         thermal-sensors = <&tsens1 7>;
4704
4705                         trips {
4706                                 npu_alert0: trip-point0 {
4707                                         temperature = <90000>;
4708                                         hysteresis = <2000>;
4709                                         type = "hot";
4710                                 };
4711                         };
4712                 };
4713
4714                 gpu-thermal-bottom {
4715                         polling-delay-passive = <250>;
4716                         polling-delay = <1000>;
4717
4718                         thermal-sensors = <&tsens1 8>;
4719
4720                         trips {
4721                                 gpu2_alert0: trip-point0 {
4722                                         temperature = <90000>;
4723                                         hysteresis = <2000>;
4724                                         type = "hot";
4725                                 };
4726                         };
4727                 };
4728         };
4729 };