1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sdm845.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
22 #include <dt-bindings/soc/qcom,apr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
71 device_type = "memory";
72 /* We expect the bootloader to fill in the size */
73 reg = <0 0x80000000 0 0>;
81 hyp_mem: memory@85700000 {
82 reg = <0 0x85700000 0 0x600000>;
86 xbl_mem: memory@85e00000 {
87 reg = <0 0x85e00000 0 0x100000>;
91 aop_mem: memory@85fc0000 {
92 reg = <0 0x85fc0000 0 0x20000>;
96 aop_cmd_db_mem: memory@85fe0000 {
97 compatible = "qcom,cmd-db";
98 reg = <0x0 0x85fe0000 0 0x20000>;
102 smem_mem: memory@86000000 {
103 reg = <0x0 0x86000000 0 0x200000>;
107 tz_mem: memory@86200000 {
108 reg = <0 0x86200000 0 0x2d00000>;
112 rmtfs_mem: memory@88f00000 {
113 compatible = "qcom,rmtfs-mem";
114 reg = <0 0x88f00000 0 0x200000>;
117 qcom,client-id = <1>;
121 qseecom_mem: memory@8ab00000 {
122 reg = <0 0x8ab00000 0 0x1400000>;
126 camera_mem: memory@8bf00000 {
127 reg = <0 0x8bf00000 0 0x500000>;
131 wlan_msa_mem: memory@8c400000 {
132 reg = <0 0x8c400000 0 0x100000>;
136 gpu_mem: memory@8c515000 {
137 reg = <0 0x8c515000 0 0x2000>;
141 ipa_fw_mem: memory@8c517000 {
142 reg = <0 0x8c517000 0 0x5a000>;
146 adsp_mem: memory@8c600000 {
147 reg = <0 0x8c600000 0 0x1a00000>;
151 mpss_region: memory@8e000000 {
152 reg = <0 0x8e000000 0 0x7800000>;
156 venus_mem: memory@95800000 {
157 reg = <0 0x95800000 0 0x500000>;
161 cdsp_mem: memory@95d00000 {
162 reg = <0 0x95d00000 0 0x800000>;
166 mba_region: memory@96500000 {
167 reg = <0 0x96500000 0 0x200000>;
171 slpi_mem: memory@96700000 {
172 reg = <0 0x96700000 0 0x1400000>;
176 spss_mem: memory@97b00000 {
177 reg = <0 0x97b00000 0 0x100000>;
183 #address-cells = <2>;
188 compatible = "qcom,kryo385";
190 enable-method = "psci";
191 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
194 capacity-dmips-mhz = <607>;
195 dynamic-power-coefficient = <100>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
197 operating-points-v2 = <&cpu0_opp_table>;
198 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
199 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
200 #cooling-cells = <2>;
201 next-level-cache = <&L2_0>;
203 compatible = "cache";
204 next-level-cache = <&L3_0>;
206 compatible = "cache";
213 compatible = "qcom,kryo385";
215 enable-method = "psci";
216 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
219 capacity-dmips-mhz = <607>;
220 dynamic-power-coefficient = <100>;
221 qcom,freq-domain = <&cpufreq_hw 0>;
222 operating-points-v2 = <&cpu0_opp_table>;
223 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
224 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
225 #cooling-cells = <2>;
226 next-level-cache = <&L2_100>;
228 compatible = "cache";
229 next-level-cache = <&L3_0>;
235 compatible = "qcom,kryo385";
237 enable-method = "psci";
238 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
241 capacity-dmips-mhz = <607>;
242 dynamic-power-coefficient = <100>;
243 qcom,freq-domain = <&cpufreq_hw 0>;
244 operating-points-v2 = <&cpu0_opp_table>;
245 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
246 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
247 #cooling-cells = <2>;
248 next-level-cache = <&L2_200>;
250 compatible = "cache";
251 next-level-cache = <&L3_0>;
257 compatible = "qcom,kryo385";
259 enable-method = "psci";
260 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
263 capacity-dmips-mhz = <607>;
264 dynamic-power-coefficient = <100>;
265 qcom,freq-domain = <&cpufreq_hw 0>;
266 operating-points-v2 = <&cpu0_opp_table>;
267 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
268 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
269 #cooling-cells = <2>;
270 next-level-cache = <&L2_300>;
272 compatible = "cache";
273 next-level-cache = <&L3_0>;
279 compatible = "qcom,kryo385";
281 enable-method = "psci";
282 capacity-dmips-mhz = <1024>;
283 cpu-idle-states = <&BIG_CPU_SLEEP_0
286 dynamic-power-coefficient = <396>;
287 qcom,freq-domain = <&cpufreq_hw 1>;
288 operating-points-v2 = <&cpu4_opp_table>;
289 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
290 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
291 #cooling-cells = <2>;
292 next-level-cache = <&L2_400>;
294 compatible = "cache";
295 next-level-cache = <&L3_0>;
301 compatible = "qcom,kryo385";
303 enable-method = "psci";
304 capacity-dmips-mhz = <1024>;
305 cpu-idle-states = <&BIG_CPU_SLEEP_0
308 dynamic-power-coefficient = <396>;
309 qcom,freq-domain = <&cpufreq_hw 1>;
310 operating-points-v2 = <&cpu4_opp_table>;
311 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
312 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
313 #cooling-cells = <2>;
314 next-level-cache = <&L2_500>;
316 compatible = "cache";
317 next-level-cache = <&L3_0>;
323 compatible = "qcom,kryo385";
325 enable-method = "psci";
326 capacity-dmips-mhz = <1024>;
327 cpu-idle-states = <&BIG_CPU_SLEEP_0
330 dynamic-power-coefficient = <396>;
331 qcom,freq-domain = <&cpufreq_hw 1>;
332 operating-points-v2 = <&cpu4_opp_table>;
333 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
334 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
335 #cooling-cells = <2>;
336 next-level-cache = <&L2_600>;
338 compatible = "cache";
339 next-level-cache = <&L3_0>;
345 compatible = "qcom,kryo385";
347 enable-method = "psci";
348 capacity-dmips-mhz = <1024>;
349 cpu-idle-states = <&BIG_CPU_SLEEP_0
352 dynamic-power-coefficient = <396>;
353 qcom,freq-domain = <&cpufreq_hw 1>;
354 operating-points-v2 = <&cpu4_opp_table>;
355 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
356 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
357 #cooling-cells = <2>;
358 next-level-cache = <&L2_700>;
360 compatible = "cache";
361 next-level-cache = <&L3_0>;
402 entry-method = "psci";
404 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
405 compatible = "arm,idle-state";
406 idle-state-name = "little-power-down";
407 arm,psci-suspend-param = <0x40000003>;
408 entry-latency-us = <350>;
409 exit-latency-us = <461>;
410 min-residency-us = <1890>;
414 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
415 compatible = "arm,idle-state";
416 idle-state-name = "little-rail-power-down";
417 arm,psci-suspend-param = <0x40000004>;
418 entry-latency-us = <360>;
419 exit-latency-us = <531>;
420 min-residency-us = <3934>;
424 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
425 compatible = "arm,idle-state";
426 idle-state-name = "big-power-down";
427 arm,psci-suspend-param = <0x40000003>;
428 entry-latency-us = <264>;
429 exit-latency-us = <621>;
430 min-residency-us = <952>;
434 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
435 compatible = "arm,idle-state";
436 idle-state-name = "big-rail-power-down";
437 arm,psci-suspend-param = <0x40000004>;
438 entry-latency-us = <702>;
439 exit-latency-us = <1061>;
440 min-residency-us = <4488>;
444 CLUSTER_SLEEP_0: cluster-sleep-0 {
445 compatible = "arm,idle-state";
446 idle-state-name = "cluster-power-down";
447 arm,psci-suspend-param = <0x400000F4>;
448 entry-latency-us = <3263>;
449 exit-latency-us = <6562>;
450 min-residency-us = <9987>;
456 cpu0_opp_table: cpu0_opp_table {
457 compatible = "operating-points-v2";
460 cpu0_opp1: opp-300000000 {
461 opp-hz = /bits/ 64 <300000000>;
462 opp-peak-kBps = <800000 4800000>;
465 cpu0_opp2: opp-403200000 {
466 opp-hz = /bits/ 64 <403200000>;
467 opp-peak-kBps = <800000 4800000>;
470 cpu0_opp3: opp-480000000 {
471 opp-hz = /bits/ 64 <480000000>;
472 opp-peak-kBps = <800000 6451200>;
475 cpu0_opp4: opp-576000000 {
476 opp-hz = /bits/ 64 <576000000>;
477 opp-peak-kBps = <800000 6451200>;
480 cpu0_opp5: opp-652800000 {
481 opp-hz = /bits/ 64 <652800000>;
482 opp-peak-kBps = <800000 7680000>;
485 cpu0_opp6: opp-748800000 {
486 opp-hz = /bits/ 64 <748800000>;
487 opp-peak-kBps = <1804000 9216000>;
490 cpu0_opp7: opp-825600000 {
491 opp-hz = /bits/ 64 <825600000>;
492 opp-peak-kBps = <1804000 9216000>;
495 cpu0_opp8: opp-902400000 {
496 opp-hz = /bits/ 64 <902400000>;
497 opp-peak-kBps = <1804000 10444800>;
500 cpu0_opp9: opp-979200000 {
501 opp-hz = /bits/ 64 <979200000>;
502 opp-peak-kBps = <1804000 11980800>;
505 cpu0_opp10: opp-1056000000 {
506 opp-hz = /bits/ 64 <1056000000>;
507 opp-peak-kBps = <1804000 11980800>;
510 cpu0_opp11: opp-1132800000 {
511 opp-hz = /bits/ 64 <1132800000>;
512 opp-peak-kBps = <2188000 13516800>;
515 cpu0_opp12: opp-1228800000 {
516 opp-hz = /bits/ 64 <1228800000>;
517 opp-peak-kBps = <2188000 15052800>;
520 cpu0_opp13: opp-1324800000 {
521 opp-hz = /bits/ 64 <1324800000>;
522 opp-peak-kBps = <2188000 16588800>;
525 cpu0_opp14: opp-1420800000 {
526 opp-hz = /bits/ 64 <1420800000>;
527 opp-peak-kBps = <3072000 18124800>;
530 cpu0_opp15: opp-1516800000 {
531 opp-hz = /bits/ 64 <1516800000>;
532 opp-peak-kBps = <3072000 19353600>;
535 cpu0_opp16: opp-1612800000 {
536 opp-hz = /bits/ 64 <1612800000>;
537 opp-peak-kBps = <4068000 19353600>;
540 cpu0_opp17: opp-1689600000 {
541 opp-hz = /bits/ 64 <1689600000>;
542 opp-peak-kBps = <4068000 20889600>;
545 cpu0_opp18: opp-1766400000 {
546 opp-hz = /bits/ 64 <1766400000>;
547 opp-peak-kBps = <4068000 22425600>;
551 cpu4_opp_table: cpu4_opp_table {
552 compatible = "operating-points-v2";
555 cpu4_opp1: opp-300000000 {
556 opp-hz = /bits/ 64 <300000000>;
557 opp-peak-kBps = <800000 4800000>;
560 cpu4_opp2: opp-403200000 {
561 opp-hz = /bits/ 64 <403200000>;
562 opp-peak-kBps = <800000 4800000>;
565 cpu4_opp3: opp-480000000 {
566 opp-hz = /bits/ 64 <480000000>;
567 opp-peak-kBps = <1804000 4800000>;
570 cpu4_opp4: opp-576000000 {
571 opp-hz = /bits/ 64 <576000000>;
572 opp-peak-kBps = <1804000 4800000>;
575 cpu4_opp5: opp-652800000 {
576 opp-hz = /bits/ 64 <652800000>;
577 opp-peak-kBps = <1804000 4800000>;
580 cpu4_opp6: opp-748800000 {
581 opp-hz = /bits/ 64 <748800000>;
582 opp-peak-kBps = <1804000 4800000>;
585 cpu4_opp7: opp-825600000 {
586 opp-hz = /bits/ 64 <825600000>;
587 opp-peak-kBps = <2188000 9216000>;
590 cpu4_opp8: opp-902400000 {
591 opp-hz = /bits/ 64 <902400000>;
592 opp-peak-kBps = <2188000 9216000>;
595 cpu4_opp9: opp-979200000 {
596 opp-hz = /bits/ 64 <979200000>;
597 opp-peak-kBps = <2188000 9216000>;
600 cpu4_opp10: opp-1056000000 {
601 opp-hz = /bits/ 64 <1056000000>;
602 opp-peak-kBps = <3072000 9216000>;
605 cpu4_opp11: opp-1132800000 {
606 opp-hz = /bits/ 64 <1132800000>;
607 opp-peak-kBps = <3072000 11980800>;
610 cpu4_opp12: opp-1209600000 {
611 opp-hz = /bits/ 64 <1209600000>;
612 opp-peak-kBps = <4068000 11980800>;
615 cpu4_opp13: opp-1286400000 {
616 opp-hz = /bits/ 64 <1286400000>;
617 opp-peak-kBps = <4068000 11980800>;
620 cpu4_opp14: opp-1363200000 {
621 opp-hz = /bits/ 64 <1363200000>;
622 opp-peak-kBps = <4068000 15052800>;
625 cpu4_opp15: opp-1459200000 {
626 opp-hz = /bits/ 64 <1459200000>;
627 opp-peak-kBps = <4068000 15052800>;
630 cpu4_opp16: opp-1536000000 {
631 opp-hz = /bits/ 64 <1536000000>;
632 opp-peak-kBps = <5412000 15052800>;
635 cpu4_opp17: opp-1612800000 {
636 opp-hz = /bits/ 64 <1612800000>;
637 opp-peak-kBps = <5412000 15052800>;
640 cpu4_opp18: opp-1689600000 {
641 opp-hz = /bits/ 64 <1689600000>;
642 opp-peak-kBps = <5412000 19353600>;
645 cpu4_opp19: opp-1766400000 {
646 opp-hz = /bits/ 64 <1766400000>;
647 opp-peak-kBps = <6220000 19353600>;
650 cpu4_opp20: opp-1843200000 {
651 opp-hz = /bits/ 64 <1843200000>;
652 opp-peak-kBps = <6220000 19353600>;
655 cpu4_opp21: opp-1920000000 {
656 opp-hz = /bits/ 64 <1920000000>;
657 opp-peak-kBps = <7216000 19353600>;
660 cpu4_opp22: opp-1996800000 {
661 opp-hz = /bits/ 64 <1996800000>;
662 opp-peak-kBps = <7216000 20889600>;
665 cpu4_opp23: opp-2092800000 {
666 opp-hz = /bits/ 64 <2092800000>;
667 opp-peak-kBps = <7216000 20889600>;
670 cpu4_opp24: opp-2169600000 {
671 opp-hz = /bits/ 64 <2169600000>;
672 opp-peak-kBps = <7216000 20889600>;
675 cpu4_opp25: opp-2246400000 {
676 opp-hz = /bits/ 64 <2246400000>;
677 opp-peak-kBps = <7216000 20889600>;
680 cpu4_opp26: opp-2323200000 {
681 opp-hz = /bits/ 64 <2323200000>;
682 opp-peak-kBps = <7216000 20889600>;
685 cpu4_opp27: opp-2400000000 {
686 opp-hz = /bits/ 64 <2400000000>;
687 opp-peak-kBps = <7216000 22425600>;
690 cpu4_opp28: opp-2476800000 {
691 opp-hz = /bits/ 64 <2476800000>;
692 opp-peak-kBps = <7216000 22425600>;
695 cpu4_opp29: opp-2553600000 {
696 opp-hz = /bits/ 64 <2553600000>;
697 opp-peak-kBps = <7216000 22425600>;
700 cpu4_opp30: opp-2649600000 {
701 opp-hz = /bits/ 64 <2649600000>;
702 opp-peak-kBps = <7216000 22425600>;
705 cpu4_opp31: opp-2745600000 {
706 opp-hz = /bits/ 64 <2745600000>;
707 opp-peak-kBps = <7216000 25497600>;
710 cpu4_opp32: opp-2803200000 {
711 opp-hz = /bits/ 64 <2803200000>;
712 opp-peak-kBps = <7216000 25497600>;
717 compatible = "arm,armv8-pmuv3";
718 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
722 compatible = "arm,armv8-timer";
723 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
724 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
725 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
726 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
731 compatible = "fixed-clock";
733 clock-frequency = <38400000>;
734 clock-output-names = "xo_board";
737 sleep_clk: sleep-clk {
738 compatible = "fixed-clock";
740 clock-frequency = <32764>;
746 compatible = "qcom,scm-sdm845", "qcom,scm";
750 adsp_pas: remoteproc-adsp {
751 compatible = "qcom,sdm845-adsp-pas";
753 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
754 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
755 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
756 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
757 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
758 interrupt-names = "wdog", "fatal", "ready",
759 "handover", "stop-ack";
761 clocks = <&rpmhcc RPMH_CXO_CLK>;
764 memory-region = <&adsp_mem>;
766 qcom,smem-states = <&adsp_smp2p_out 0>;
767 qcom,smem-state-names = "stop";
772 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
774 qcom,remote-pid = <2>;
775 mboxes = <&apss_shared 8>;
778 compatible = "qcom,apr-v2";
779 qcom,glink-channels = "apr_audio_svc";
780 qcom,apr-domain = <APR_DOMAIN_ADSP>;
781 #address-cells = <1>;
783 qcom,intents = <512 20>;
786 reg = <APR_SVC_ADSP_CORE>;
787 compatible = "qcom,q6core";
788 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
791 q6afe: apr-service@4 {
792 compatible = "qcom,q6afe";
794 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
796 compatible = "qcom,q6afe-dais";
797 #address-cells = <1>;
799 #sound-dai-cells = <1>;
803 q6asm: apr-service@7 {
804 compatible = "qcom,q6asm";
806 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
808 compatible = "qcom,q6asm-dais";
809 #address-cells = <1>;
811 #sound-dai-cells = <1>;
812 iommus = <&apps_smmu 0x1821 0x0>;
816 q6adm: apr-service@8 {
817 compatible = "qcom,q6adm";
819 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
821 compatible = "qcom,q6adm-routing";
822 #sound-dai-cells = <0>;
828 compatible = "qcom,fastrpc";
829 qcom,glink-channels = "fastrpcglink-apps-dsp";
831 #address-cells = <1>;
835 compatible = "qcom,fastrpc-compute-cb";
837 iommus = <&apps_smmu 0x1823 0x0>;
841 compatible = "qcom,fastrpc-compute-cb";
843 iommus = <&apps_smmu 0x1824 0x0>;
849 cdsp_pas: remoteproc-cdsp {
850 compatible = "qcom,sdm845-cdsp-pas";
852 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
853 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
854 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
855 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
856 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
857 interrupt-names = "wdog", "fatal", "ready",
858 "handover", "stop-ack";
860 clocks = <&rpmhcc RPMH_CXO_CLK>;
863 memory-region = <&cdsp_mem>;
865 qcom,smem-states = <&cdsp_smp2p_out 0>;
866 qcom,smem-state-names = "stop";
871 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
873 qcom,remote-pid = <5>;
874 mboxes = <&apss_shared 4>;
876 compatible = "qcom,fastrpc";
877 qcom,glink-channels = "fastrpcglink-apps-dsp";
879 #address-cells = <1>;
883 compatible = "qcom,fastrpc-compute-cb";
885 iommus = <&apps_smmu 0x1401 0x30>;
889 compatible = "qcom,fastrpc-compute-cb";
891 iommus = <&apps_smmu 0x1402 0x30>;
895 compatible = "qcom,fastrpc-compute-cb";
897 iommus = <&apps_smmu 0x1403 0x30>;
901 compatible = "qcom,fastrpc-compute-cb";
903 iommus = <&apps_smmu 0x1404 0x30>;
907 compatible = "qcom,fastrpc-compute-cb";
909 iommus = <&apps_smmu 0x1405 0x30>;
913 compatible = "qcom,fastrpc-compute-cb";
915 iommus = <&apps_smmu 0x1406 0x30>;
919 compatible = "qcom,fastrpc-compute-cb";
921 iommus = <&apps_smmu 0x1407 0x30>;
925 compatible = "qcom,fastrpc-compute-cb";
927 iommus = <&apps_smmu 0x1408 0x30>;
934 compatible = "qcom,tcsr-mutex";
935 syscon = <&tcsr_mutex_regs 0 0x1000>;
940 compatible = "qcom,smem";
941 memory-region = <&smem_mem>;
942 hwlocks = <&tcsr_mutex 3>;
946 compatible = "qcom,smp2p";
947 qcom,smem = <94>, <432>;
949 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
951 mboxes = <&apss_shared 6>;
953 qcom,local-pid = <0>;
954 qcom,remote-pid = <5>;
956 cdsp_smp2p_out: master-kernel {
957 qcom,entry-name = "master-kernel";
958 #qcom,smem-state-cells = <1>;
961 cdsp_smp2p_in: slave-kernel {
962 qcom,entry-name = "slave-kernel";
964 interrupt-controller;
965 #interrupt-cells = <2>;
970 compatible = "qcom,smp2p";
971 qcom,smem = <443>, <429>;
973 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
975 mboxes = <&apss_shared 10>;
977 qcom,local-pid = <0>;
978 qcom,remote-pid = <2>;
980 adsp_smp2p_out: master-kernel {
981 qcom,entry-name = "master-kernel";
982 #qcom,smem-state-cells = <1>;
985 adsp_smp2p_in: slave-kernel {
986 qcom,entry-name = "slave-kernel";
988 interrupt-controller;
989 #interrupt-cells = <2>;
994 compatible = "qcom,smp2p";
995 qcom,smem = <435>, <428>;
996 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
997 mboxes = <&apss_shared 14>;
998 qcom,local-pid = <0>;
999 qcom,remote-pid = <1>;
1001 modem_smp2p_out: master-kernel {
1002 qcom,entry-name = "master-kernel";
1003 #qcom,smem-state-cells = <1>;
1006 modem_smp2p_in: slave-kernel {
1007 qcom,entry-name = "slave-kernel";
1008 interrupt-controller;
1009 #interrupt-cells = <2>;
1012 ipa_smp2p_out: ipa-ap-to-modem {
1013 qcom,entry-name = "ipa";
1014 #qcom,smem-state-cells = <1>;
1017 ipa_smp2p_in: ipa-modem-to-ap {
1018 qcom,entry-name = "ipa";
1019 interrupt-controller;
1020 #interrupt-cells = <2>;
1025 compatible = "qcom,smp2p";
1026 qcom,smem = <481>, <430>;
1027 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1028 mboxes = <&apss_shared 26>;
1029 qcom,local-pid = <0>;
1030 qcom,remote-pid = <3>;
1032 slpi_smp2p_out: master-kernel {
1033 qcom,entry-name = "master-kernel";
1034 #qcom,smem-state-cells = <1>;
1037 slpi_smp2p_in: slave-kernel {
1038 qcom,entry-name = "slave-kernel";
1039 interrupt-controller;
1040 #interrupt-cells = <2>;
1045 compatible = "arm,psci-1.0";
1050 #address-cells = <2>;
1052 ranges = <0 0 0 0 0x10 0>;
1053 dma-ranges = <0 0 0 0 0x10 0>;
1054 compatible = "simple-bus";
1056 gcc: clock-controller@100000 {
1057 compatible = "qcom,gcc-sdm845";
1058 reg = <0 0x00100000 0 0x1f0000>;
1059 clocks = <&rpmhcc RPMH_CXO_CLK>,
1060 <&rpmhcc RPMH_CXO_CLK_A>,
1064 clock-names = "bi_tcxo",
1071 #power-domain-cells = <1>;
1075 compatible = "qcom,qfprom";
1076 reg = <0 0x00784000 0 0x8ff>;
1077 #address-cells = <1>;
1080 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1085 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1092 compatible = "qcom,prng-ee";
1093 reg = <0 0x00793000 0 0x1000>;
1094 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1095 clock-names = "core";
1098 qup_opp_table: qup-opp-table {
1099 compatible = "operating-points-v2";
1102 opp-hz = /bits/ 64 <50000000>;
1103 required-opps = <&rpmhpd_opp_min_svs>;
1107 opp-hz = /bits/ 64 <75000000>;
1108 required-opps = <&rpmhpd_opp_low_svs>;
1112 opp-hz = /bits/ 64 <100000000>;
1113 required-opps = <&rpmhpd_opp_svs>;
1117 opp-hz = /bits/ 64 <128000000>;
1118 required-opps = <&rpmhpd_opp_nom>;
1122 qupv3_id_0: geniqup@8c0000 {
1123 compatible = "qcom,geni-se-qup";
1124 reg = <0 0x008c0000 0 0x6000>;
1125 clock-names = "m-ahb", "s-ahb";
1126 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1127 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1128 iommus = <&apps_smmu 0x3 0x0>;
1129 #address-cells = <2>;
1132 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1133 interconnect-names = "qup-core";
1134 status = "disabled";
1137 compatible = "qcom,geni-i2c";
1138 reg = <0 0x00880000 0 0x4000>;
1140 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&qup_i2c0_default>;
1143 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1144 #address-cells = <1>;
1146 power-domains = <&rpmhpd SDM845_CX>;
1147 operating-points-v2 = <&qup_opp_table>;
1148 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1149 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1150 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1151 interconnect-names = "qup-core", "qup-config", "qup-memory";
1152 status = "disabled";
1156 compatible = "qcom,geni-spi";
1157 reg = <0 0x00880000 0 0x4000>;
1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 pinctrl-names = "default";
1161 pinctrl-0 = <&qup_spi0_default>;
1162 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1163 #address-cells = <1>;
1165 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1166 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1167 interconnect-names = "qup-core", "qup-config";
1168 status = "disabled";
1171 uart0: serial@880000 {
1172 compatible = "qcom,geni-uart";
1173 reg = <0 0x00880000 0 0x4000>;
1175 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&qup_uart0_default>;
1178 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1179 power-domains = <&rpmhpd SDM845_CX>;
1180 operating-points-v2 = <&qup_opp_table>;
1181 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1182 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1183 interconnect-names = "qup-core", "qup-config";
1184 status = "disabled";
1188 compatible = "qcom,geni-i2c";
1189 reg = <0 0x00884000 0 0x4000>;
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_i2c1_default>;
1194 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>;
1197 power-domains = <&rpmhpd SDM845_CX>;
1198 operating-points-v2 = <&qup_opp_table>;
1199 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1200 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1201 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1202 interconnect-names = "qup-core", "qup-config", "qup-memory";
1203 status = "disabled";
1207 compatible = "qcom,geni-spi";
1208 reg = <0 0x00884000 0 0x4000>;
1210 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&qup_spi1_default>;
1213 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1214 #address-cells = <1>;
1216 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1217 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1218 interconnect-names = "qup-core", "qup-config";
1219 status = "disabled";
1222 uart1: serial@884000 {
1223 compatible = "qcom,geni-uart";
1224 reg = <0 0x00884000 0 0x4000>;
1226 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&qup_uart1_default>;
1229 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1230 power-domains = <&rpmhpd SDM845_CX>;
1231 operating-points-v2 = <&qup_opp_table>;
1232 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1233 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1234 interconnect-names = "qup-core", "qup-config";
1235 status = "disabled";
1239 compatible = "qcom,geni-i2c";
1240 reg = <0 0x00888000 0 0x4000>;
1242 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&qup_i2c2_default>;
1245 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1246 #address-cells = <1>;
1248 power-domains = <&rpmhpd SDM845_CX>;
1249 operating-points-v2 = <&qup_opp_table>;
1250 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1251 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1252 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1253 interconnect-names = "qup-core", "qup-config", "qup-memory";
1254 status = "disabled";
1258 compatible = "qcom,geni-spi";
1259 reg = <0 0x00888000 0 0x4000>;
1261 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&qup_spi2_default>;
1264 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1265 #address-cells = <1>;
1267 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1268 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1269 interconnect-names = "qup-core", "qup-config";
1270 status = "disabled";
1273 uart2: serial@888000 {
1274 compatible = "qcom,geni-uart";
1275 reg = <0 0x00888000 0 0x4000>;
1277 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_uart2_default>;
1280 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1281 power-domains = <&rpmhpd SDM845_CX>;
1282 operating-points-v2 = <&qup_opp_table>;
1283 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1284 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1285 interconnect-names = "qup-core", "qup-config";
1286 status = "disabled";
1290 compatible = "qcom,geni-i2c";
1291 reg = <0 0x0088c000 0 0x4000>;
1293 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1294 pinctrl-names = "default";
1295 pinctrl-0 = <&qup_i2c3_default>;
1296 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1297 #address-cells = <1>;
1299 power-domains = <&rpmhpd SDM845_CX>;
1300 operating-points-v2 = <&qup_opp_table>;
1301 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1302 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1303 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1304 interconnect-names = "qup-core", "qup-config", "qup-memory";
1305 status = "disabled";
1309 compatible = "qcom,geni-spi";
1310 reg = <0 0x0088c000 0 0x4000>;
1312 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&qup_spi3_default>;
1315 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1316 #address-cells = <1>;
1318 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1319 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1320 interconnect-names = "qup-core", "qup-config";
1321 status = "disabled";
1324 uart3: serial@88c000 {
1325 compatible = "qcom,geni-uart";
1326 reg = <0 0x0088c000 0 0x4000>;
1328 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&qup_uart3_default>;
1331 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1332 power-domains = <&rpmhpd SDM845_CX>;
1333 operating-points-v2 = <&qup_opp_table>;
1334 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1335 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1336 interconnect-names = "qup-core", "qup-config";
1337 status = "disabled";
1341 compatible = "qcom,geni-i2c";
1342 reg = <0 0x00890000 0 0x4000>;
1344 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c4_default>;
1347 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cells = <1>;
1350 power-domains = <&rpmhpd SDM845_CX>;
1351 operating-points-v2 = <&qup_opp_table>;
1352 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1353 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1354 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1355 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356 status = "disabled";
1360 compatible = "qcom,geni-spi";
1361 reg = <0 0x00890000 0 0x4000>;
1363 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&qup_spi4_default>;
1366 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1367 #address-cells = <1>;
1369 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1370 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1371 interconnect-names = "qup-core", "qup-config";
1372 status = "disabled";
1375 uart4: serial@890000 {
1376 compatible = "qcom,geni-uart";
1377 reg = <0 0x00890000 0 0x4000>;
1379 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&qup_uart4_default>;
1382 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1383 power-domains = <&rpmhpd SDM845_CX>;
1384 operating-points-v2 = <&qup_opp_table>;
1385 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1386 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1387 interconnect-names = "qup-core", "qup-config";
1388 status = "disabled";
1392 compatible = "qcom,geni-i2c";
1393 reg = <0 0x00894000 0 0x4000>;
1395 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&qup_i2c5_default>;
1398 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1399 #address-cells = <1>;
1401 power-domains = <&rpmhpd SDM845_CX>;
1402 operating-points-v2 = <&qup_opp_table>;
1403 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1404 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1405 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1406 interconnect-names = "qup-core", "qup-config", "qup-memory";
1407 status = "disabled";
1411 compatible = "qcom,geni-spi";
1412 reg = <0 0x00894000 0 0x4000>;
1414 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_spi5_default>;
1417 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1418 #address-cells = <1>;
1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1422 interconnect-names = "qup-core", "qup-config";
1423 status = "disabled";
1426 uart5: serial@894000 {
1427 compatible = "qcom,geni-uart";
1428 reg = <0 0x00894000 0 0x4000>;
1430 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&qup_uart5_default>;
1433 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1434 power-domains = <&rpmhpd SDM845_CX>;
1435 operating-points-v2 = <&qup_opp_table>;
1436 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1437 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1438 interconnect-names = "qup-core", "qup-config";
1439 status = "disabled";
1443 compatible = "qcom,geni-i2c";
1444 reg = <0 0x00898000 0 0x4000>;
1446 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1447 pinctrl-names = "default";
1448 pinctrl-0 = <&qup_i2c6_default>;
1449 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1450 #address-cells = <1>;
1452 power-domains = <&rpmhpd SDM845_CX>;
1453 operating-points-v2 = <&qup_opp_table>;
1454 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1455 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1456 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1457 interconnect-names = "qup-core", "qup-config", "qup-memory";
1458 status = "disabled";
1462 compatible = "qcom,geni-spi";
1463 reg = <0 0x00898000 0 0x4000>;
1465 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&qup_spi6_default>;
1468 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1469 #address-cells = <1>;
1471 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1472 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1473 interconnect-names = "qup-core", "qup-config";
1474 status = "disabled";
1477 uart6: serial@898000 {
1478 compatible = "qcom,geni-uart";
1479 reg = <0 0x00898000 0 0x4000>;
1481 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1482 pinctrl-names = "default";
1483 pinctrl-0 = <&qup_uart6_default>;
1484 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1485 power-domains = <&rpmhpd SDM845_CX>;
1486 operating-points-v2 = <&qup_opp_table>;
1487 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1488 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1489 interconnect-names = "qup-core", "qup-config";
1490 status = "disabled";
1494 compatible = "qcom,geni-i2c";
1495 reg = <0 0x0089c000 0 0x4000>;
1497 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1498 pinctrl-names = "default";
1499 pinctrl-0 = <&qup_i2c7_default>;
1500 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1501 #address-cells = <1>;
1503 power-domains = <&rpmhpd SDM845_CX>;
1504 operating-points-v2 = <&qup_opp_table>;
1505 status = "disabled";
1509 compatible = "qcom,geni-spi";
1510 reg = <0 0x0089c000 0 0x4000>;
1512 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1513 pinctrl-names = "default";
1514 pinctrl-0 = <&qup_spi7_default>;
1515 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1516 #address-cells = <1>;
1518 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1519 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1520 interconnect-names = "qup-core", "qup-config";
1521 status = "disabled";
1524 uart7: serial@89c000 {
1525 compatible = "qcom,geni-uart";
1526 reg = <0 0x0089c000 0 0x4000>;
1528 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1529 pinctrl-names = "default";
1530 pinctrl-0 = <&qup_uart7_default>;
1531 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1532 power-domains = <&rpmhpd SDM845_CX>;
1533 operating-points-v2 = <&qup_opp_table>;
1534 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1535 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1536 interconnect-names = "qup-core", "qup-config";
1537 status = "disabled";
1541 qupv3_id_1: geniqup@ac0000 {
1542 compatible = "qcom,geni-se-qup";
1543 reg = <0 0x00ac0000 0 0x6000>;
1544 clock-names = "m-ahb", "s-ahb";
1545 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1546 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1547 iommus = <&apps_smmu 0x6c3 0x0>;
1548 #address-cells = <2>;
1551 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1552 interconnect-names = "qup-core";
1553 status = "disabled";
1556 compatible = "qcom,geni-i2c";
1557 reg = <0 0x00a80000 0 0x4000>;
1559 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&qup_i2c8_default>;
1562 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cells = <1>;
1565 power-domains = <&rpmhpd SDM845_CX>;
1566 operating-points-v2 = <&qup_opp_table>;
1567 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1568 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1569 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1570 interconnect-names = "qup-core", "qup-config", "qup-memory";
1571 status = "disabled";
1575 compatible = "qcom,geni-spi";
1576 reg = <0 0x00a80000 0 0x4000>;
1578 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1579 pinctrl-names = "default";
1580 pinctrl-0 = <&qup_spi8_default>;
1581 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1582 #address-cells = <1>;
1584 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1585 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1586 interconnect-names = "qup-core", "qup-config";
1587 status = "disabled";
1590 uart8: serial@a80000 {
1591 compatible = "qcom,geni-uart";
1592 reg = <0 0x00a80000 0 0x4000>;
1594 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1595 pinctrl-names = "default";
1596 pinctrl-0 = <&qup_uart8_default>;
1597 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1598 power-domains = <&rpmhpd SDM845_CX>;
1599 operating-points-v2 = <&qup_opp_table>;
1600 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1601 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1602 interconnect-names = "qup-core", "qup-config";
1603 status = "disabled";
1607 compatible = "qcom,geni-i2c";
1608 reg = <0 0x00a84000 0 0x4000>;
1610 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1611 pinctrl-names = "default";
1612 pinctrl-0 = <&qup_i2c9_default>;
1613 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1614 #address-cells = <1>;
1616 power-domains = <&rpmhpd SDM845_CX>;
1617 operating-points-v2 = <&qup_opp_table>;
1618 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1619 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1620 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1621 interconnect-names = "qup-core", "qup-config", "qup-memory";
1622 status = "disabled";
1626 compatible = "qcom,geni-spi";
1627 reg = <0 0x00a84000 0 0x4000>;
1629 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1630 pinctrl-names = "default";
1631 pinctrl-0 = <&qup_spi9_default>;
1632 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1633 #address-cells = <1>;
1635 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1636 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1637 interconnect-names = "qup-core", "qup-config";
1638 status = "disabled";
1641 uart9: serial@a84000 {
1642 compatible = "qcom,geni-debug-uart";
1643 reg = <0 0x00a84000 0 0x4000>;
1645 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1646 pinctrl-names = "default";
1647 pinctrl-0 = <&qup_uart9_default>;
1648 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1649 power-domains = <&rpmhpd SDM845_CX>;
1650 operating-points-v2 = <&qup_opp_table>;
1651 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1652 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1653 interconnect-names = "qup-core", "qup-config";
1654 status = "disabled";
1658 compatible = "qcom,geni-i2c";
1659 reg = <0 0x00a88000 0 0x4000>;
1661 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1662 pinctrl-names = "default";
1663 pinctrl-0 = <&qup_i2c10_default>;
1664 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1665 #address-cells = <1>;
1667 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-points-v2 = <&qup_opp_table>;
1669 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1670 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1671 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1672 interconnect-names = "qup-core", "qup-config", "qup-memory";
1673 status = "disabled";
1677 compatible = "qcom,geni-spi";
1678 reg = <0 0x00a88000 0 0x4000>;
1680 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1681 pinctrl-names = "default";
1682 pinctrl-0 = <&qup_spi10_default>;
1683 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1684 #address-cells = <1>;
1686 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1687 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1688 interconnect-names = "qup-core", "qup-config";
1689 status = "disabled";
1692 uart10: serial@a88000 {
1693 compatible = "qcom,geni-uart";
1694 reg = <0 0x00a88000 0 0x4000>;
1696 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1697 pinctrl-names = "default";
1698 pinctrl-0 = <&qup_uart10_default>;
1699 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1700 power-domains = <&rpmhpd SDM845_CX>;
1701 operating-points-v2 = <&qup_opp_table>;
1702 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1703 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1704 interconnect-names = "qup-core", "qup-config";
1705 status = "disabled";
1709 compatible = "qcom,geni-i2c";
1710 reg = <0 0x00a8c000 0 0x4000>;
1712 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1713 pinctrl-names = "default";
1714 pinctrl-0 = <&qup_i2c11_default>;
1715 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1716 #address-cells = <1>;
1718 power-domains = <&rpmhpd SDM845_CX>;
1719 operating-points-v2 = <&qup_opp_table>;
1720 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1721 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1722 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1723 interconnect-names = "qup-core", "qup-config", "qup-memory";
1724 status = "disabled";
1728 compatible = "qcom,geni-spi";
1729 reg = <0 0x00a8c000 0 0x4000>;
1731 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1732 pinctrl-names = "default";
1733 pinctrl-0 = <&qup_spi11_default>;
1734 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1735 #address-cells = <1>;
1737 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1738 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1739 interconnect-names = "qup-core", "qup-config";
1740 status = "disabled";
1743 uart11: serial@a8c000 {
1744 compatible = "qcom,geni-uart";
1745 reg = <0 0x00a8c000 0 0x4000>;
1747 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1748 pinctrl-names = "default";
1749 pinctrl-0 = <&qup_uart11_default>;
1750 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1751 power-domains = <&rpmhpd SDM845_CX>;
1752 operating-points-v2 = <&qup_opp_table>;
1753 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1754 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1755 interconnect-names = "qup-core", "qup-config";
1756 status = "disabled";
1760 compatible = "qcom,geni-i2c";
1761 reg = <0 0x00a90000 0 0x4000>;
1763 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1764 pinctrl-names = "default";
1765 pinctrl-0 = <&qup_i2c12_default>;
1766 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1767 #address-cells = <1>;
1769 power-domains = <&rpmhpd SDM845_CX>;
1770 operating-points-v2 = <&qup_opp_table>;
1771 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1772 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1773 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1774 interconnect-names = "qup-core", "qup-config", "qup-memory";
1775 status = "disabled";
1779 compatible = "qcom,geni-spi";
1780 reg = <0 0x00a90000 0 0x4000>;
1782 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1783 pinctrl-names = "default";
1784 pinctrl-0 = <&qup_spi12_default>;
1785 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1786 #address-cells = <1>;
1788 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1789 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1790 interconnect-names = "qup-core", "qup-config";
1791 status = "disabled";
1794 uart12: serial@a90000 {
1795 compatible = "qcom,geni-uart";
1796 reg = <0 0x00a90000 0 0x4000>;
1798 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1799 pinctrl-names = "default";
1800 pinctrl-0 = <&qup_uart12_default>;
1801 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1802 power-domains = <&rpmhpd SDM845_CX>;
1803 operating-points-v2 = <&qup_opp_table>;
1804 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1805 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1806 interconnect-names = "qup-core", "qup-config";
1807 status = "disabled";
1811 compatible = "qcom,geni-i2c";
1812 reg = <0 0x00a94000 0 0x4000>;
1814 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1815 pinctrl-names = "default";
1816 pinctrl-0 = <&qup_i2c13_default>;
1817 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1818 #address-cells = <1>;
1820 power-domains = <&rpmhpd SDM845_CX>;
1821 operating-points-v2 = <&qup_opp_table>;
1822 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1823 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1824 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1825 interconnect-names = "qup-core", "qup-config", "qup-memory";
1826 status = "disabled";
1830 compatible = "qcom,geni-spi";
1831 reg = <0 0x00a94000 0 0x4000>;
1833 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1834 pinctrl-names = "default";
1835 pinctrl-0 = <&qup_spi13_default>;
1836 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1837 #address-cells = <1>;
1839 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1840 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1841 interconnect-names = "qup-core", "qup-config";
1842 status = "disabled";
1845 uart13: serial@a94000 {
1846 compatible = "qcom,geni-uart";
1847 reg = <0 0x00a94000 0 0x4000>;
1849 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1850 pinctrl-names = "default";
1851 pinctrl-0 = <&qup_uart13_default>;
1852 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1853 power-domains = <&rpmhpd SDM845_CX>;
1854 operating-points-v2 = <&qup_opp_table>;
1855 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1856 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1857 interconnect-names = "qup-core", "qup-config";
1858 status = "disabled";
1862 compatible = "qcom,geni-i2c";
1863 reg = <0 0x00a98000 0 0x4000>;
1865 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1866 pinctrl-names = "default";
1867 pinctrl-0 = <&qup_i2c14_default>;
1868 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1869 #address-cells = <1>;
1871 power-domains = <&rpmhpd SDM845_CX>;
1872 operating-points-v2 = <&qup_opp_table>;
1873 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1874 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1875 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1876 interconnect-names = "qup-core", "qup-config", "qup-memory";
1877 status = "disabled";
1881 compatible = "qcom,geni-spi";
1882 reg = <0 0x00a98000 0 0x4000>;
1884 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1885 pinctrl-names = "default";
1886 pinctrl-0 = <&qup_spi14_default>;
1887 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1888 #address-cells = <1>;
1890 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1891 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1892 interconnect-names = "qup-core", "qup-config";
1893 status = "disabled";
1896 uart14: serial@a98000 {
1897 compatible = "qcom,geni-uart";
1898 reg = <0 0x00a98000 0 0x4000>;
1900 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1901 pinctrl-names = "default";
1902 pinctrl-0 = <&qup_uart14_default>;
1903 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1904 power-domains = <&rpmhpd SDM845_CX>;
1905 operating-points-v2 = <&qup_opp_table>;
1906 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1907 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1908 interconnect-names = "qup-core", "qup-config";
1909 status = "disabled";
1913 compatible = "qcom,geni-i2c";
1914 reg = <0 0x00a9c000 0 0x4000>;
1916 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1917 pinctrl-names = "default";
1918 pinctrl-0 = <&qup_i2c15_default>;
1919 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1920 #address-cells = <1>;
1922 power-domains = <&rpmhpd SDM845_CX>;
1923 operating-points-v2 = <&qup_opp_table>;
1924 status = "disabled";
1925 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1926 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1927 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1928 interconnect-names = "qup-core", "qup-config", "qup-memory";
1932 compatible = "qcom,geni-spi";
1933 reg = <0 0x00a9c000 0 0x4000>;
1935 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1936 pinctrl-names = "default";
1937 pinctrl-0 = <&qup_spi15_default>;
1938 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1939 #address-cells = <1>;
1941 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1942 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1943 interconnect-names = "qup-core", "qup-config";
1944 status = "disabled";
1947 uart15: serial@a9c000 {
1948 compatible = "qcom,geni-uart";
1949 reg = <0 0x00a9c000 0 0x4000>;
1951 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1952 pinctrl-names = "default";
1953 pinctrl-0 = <&qup_uart15_default>;
1954 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1955 power-domains = <&rpmhpd SDM845_CX>;
1956 operating-points-v2 = <&qup_opp_table>;
1957 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1958 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1959 interconnect-names = "qup-core", "qup-config";
1960 status = "disabled";
1964 system-cache-controller@1100000 {
1965 compatible = "qcom,sdm845-llcc";
1966 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1967 reg-names = "llcc_base", "llcc_broadcast_base";
1968 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1971 pcie0: pci@1c00000 {
1972 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1973 reg = <0 0x01c00000 0 0x2000>,
1974 <0 0x60000000 0 0xf1d>,
1975 <0 0x60000f20 0 0xa8>,
1976 <0 0x60100000 0 0x100000>;
1977 reg-names = "parf", "dbi", "elbi", "config";
1978 device_type = "pci";
1979 linux,pci-domain = <0>;
1980 bus-range = <0x00 0xff>;
1983 #address-cells = <3>;
1986 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1987 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1989 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1990 interrupt-names = "msi";
1991 #interrupt-cells = <1>;
1992 interrupt-map-mask = <0 0 0 0x7>;
1993 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1994 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1995 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1996 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1998 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1999 <&gcc GCC_PCIE_0_AUX_CLK>,
2000 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2001 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2002 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2003 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2004 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2005 clock-names = "pipe",
2013 iommus = <&apps_smmu 0x1c10 0xf>;
2014 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2015 <0x100 &apps_smmu 0x1c11 0x1>,
2016 <0x200 &apps_smmu 0x1c12 0x1>,
2017 <0x300 &apps_smmu 0x1c13 0x1>,
2018 <0x400 &apps_smmu 0x1c14 0x1>,
2019 <0x500 &apps_smmu 0x1c15 0x1>,
2020 <0x600 &apps_smmu 0x1c16 0x1>,
2021 <0x700 &apps_smmu 0x1c17 0x1>,
2022 <0x800 &apps_smmu 0x1c18 0x1>,
2023 <0x900 &apps_smmu 0x1c19 0x1>,
2024 <0xa00 &apps_smmu 0x1c1a 0x1>,
2025 <0xb00 &apps_smmu 0x1c1b 0x1>,
2026 <0xc00 &apps_smmu 0x1c1c 0x1>,
2027 <0xd00 &apps_smmu 0x1c1d 0x1>,
2028 <0xe00 &apps_smmu 0x1c1e 0x1>,
2029 <0xf00 &apps_smmu 0x1c1f 0x1>;
2031 resets = <&gcc GCC_PCIE_0_BCR>;
2032 reset-names = "pci";
2034 power-domains = <&gcc PCIE_0_GDSC>;
2036 phys = <&pcie0_lane>;
2037 phy-names = "pciephy";
2039 status = "disabled";
2042 pcie0_phy: phy@1c06000 {
2043 compatible = "qcom,sdm845-qmp-pcie-phy";
2044 reg = <0 0x01c06000 0 0x18c>;
2045 #address-cells = <2>;
2048 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2049 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2050 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2051 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2052 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2054 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2055 reset-names = "phy";
2057 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2058 assigned-clock-rates = <100000000>;
2060 status = "disabled";
2062 pcie0_lane: lanes@1c06200 {
2063 reg = <0 0x01c06200 0 0x128>,
2064 <0 0x01c06400 0 0x1fc>,
2065 <0 0x01c06800 0 0x218>,
2066 <0 0x01c06600 0 0x70>;
2067 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2068 clock-names = "pipe0";
2072 clock-output-names = "pcie_0_pipe_clk";
2076 pcie1: pci@1c08000 {
2077 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2078 reg = <0 0x01c08000 0 0x2000>,
2079 <0 0x40000000 0 0xf1d>,
2080 <0 0x40000f20 0 0xa8>,
2081 <0 0x40100000 0 0x100000>;
2082 reg-names = "parf", "dbi", "elbi", "config";
2083 device_type = "pci";
2084 linux,pci-domain = <1>;
2085 bus-range = <0x00 0xff>;
2088 #address-cells = <3>;
2091 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2092 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2094 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2095 interrupt-names = "msi";
2096 #interrupt-cells = <1>;
2097 interrupt-map-mask = <0 0 0 0x7>;
2098 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2099 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2100 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2101 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2103 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2104 <&gcc GCC_PCIE_1_AUX_CLK>,
2105 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2106 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2107 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2108 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2109 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2110 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2111 clock-names = "pipe",
2120 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2121 assigned-clock-rates = <19200000>;
2123 iommus = <&apps_smmu 0x1c00 0xf>;
2124 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2125 <0x100 &apps_smmu 0x1c01 0x1>,
2126 <0x200 &apps_smmu 0x1c02 0x1>,
2127 <0x300 &apps_smmu 0x1c03 0x1>,
2128 <0x400 &apps_smmu 0x1c04 0x1>,
2129 <0x500 &apps_smmu 0x1c05 0x1>,
2130 <0x600 &apps_smmu 0x1c06 0x1>,
2131 <0x700 &apps_smmu 0x1c07 0x1>,
2132 <0x800 &apps_smmu 0x1c08 0x1>,
2133 <0x900 &apps_smmu 0x1c09 0x1>,
2134 <0xa00 &apps_smmu 0x1c0a 0x1>,
2135 <0xb00 &apps_smmu 0x1c0b 0x1>,
2136 <0xc00 &apps_smmu 0x1c0c 0x1>,
2137 <0xd00 &apps_smmu 0x1c0d 0x1>,
2138 <0xe00 &apps_smmu 0x1c0e 0x1>,
2139 <0xf00 &apps_smmu 0x1c0f 0x1>;
2141 resets = <&gcc GCC_PCIE_1_BCR>;
2142 reset-names = "pci";
2144 power-domains = <&gcc PCIE_1_GDSC>;
2146 phys = <&pcie1_lane>;
2147 phy-names = "pciephy";
2149 status = "disabled";
2152 pcie1_phy: phy@1c0a000 {
2153 compatible = "qcom,sdm845-qhp-pcie-phy";
2154 reg = <0 0x01c0a000 0 0x800>;
2155 #address-cells = <2>;
2158 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2159 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2160 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2161 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2162 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2164 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2165 reset-names = "phy";
2167 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2168 assigned-clock-rates = <100000000>;
2170 status = "disabled";
2172 pcie1_lane: lanes@1c06200 {
2173 reg = <0 0x01c0a800 0 0x800>,
2174 <0 0x01c0a800 0 0x800>,
2175 <0 0x01c0b800 0 0x400>;
2176 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2177 clock-names = "pipe0";
2181 clock-output-names = "pcie_1_pipe_clk";
2185 mem_noc: interconnect@1380000 {
2186 compatible = "qcom,sdm845-mem-noc";
2187 reg = <0 0x01380000 0 0x27200>;
2188 #interconnect-cells = <2>;
2189 qcom,bcm-voters = <&apps_bcm_voter>;
2192 dc_noc: interconnect@14e0000 {
2193 compatible = "qcom,sdm845-dc-noc";
2194 reg = <0 0x014e0000 0 0x400>;
2195 #interconnect-cells = <2>;
2196 qcom,bcm-voters = <&apps_bcm_voter>;
2199 config_noc: interconnect@1500000 {
2200 compatible = "qcom,sdm845-config-noc";
2201 reg = <0 0x01500000 0 0x5080>;
2202 #interconnect-cells = <2>;
2203 qcom,bcm-voters = <&apps_bcm_voter>;
2206 system_noc: interconnect@1620000 {
2207 compatible = "qcom,sdm845-system-noc";
2208 reg = <0 0x01620000 0 0x18080>;
2209 #interconnect-cells = <2>;
2210 qcom,bcm-voters = <&apps_bcm_voter>;
2213 aggre1_noc: interconnect@16e0000 {
2214 compatible = "qcom,sdm845-aggre1-noc";
2215 reg = <0 0x016e0000 0 0x15080>;
2216 #interconnect-cells = <2>;
2217 qcom,bcm-voters = <&apps_bcm_voter>;
2220 aggre2_noc: interconnect@1700000 {
2221 compatible = "qcom,sdm845-aggre2-noc";
2222 reg = <0 0x01700000 0 0x1f300>;
2223 #interconnect-cells = <2>;
2224 qcom,bcm-voters = <&apps_bcm_voter>;
2227 mmss_noc: interconnect@1740000 {
2228 compatible = "qcom,sdm845-mmss-noc";
2229 reg = <0 0x01740000 0 0x1c100>;
2230 #interconnect-cells = <2>;
2231 qcom,bcm-voters = <&apps_bcm_voter>;
2234 ufs_mem_hc: ufshc@1d84000 {
2235 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2237 reg = <0 0x01d84000 0 0x2500>,
2238 <0 0x01d90000 0 0x8000>;
2239 reg-names = "std", "ice";
2240 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2241 phys = <&ufs_mem_phy_lanes>;
2242 phy-names = "ufsphy";
2243 lanes-per-direction = <2>;
2244 power-domains = <&gcc UFS_PHY_GDSC>;
2246 resets = <&gcc GCC_UFS_PHY_BCR>;
2247 reset-names = "rst";
2249 iommus = <&apps_smmu 0x100 0xf>;
2257 "tx_lane0_sync_clk",
2258 "rx_lane0_sync_clk",
2259 "rx_lane1_sync_clk",
2262 <&gcc GCC_UFS_PHY_AXI_CLK>,
2263 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2264 <&gcc GCC_UFS_PHY_AHB_CLK>,
2265 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2266 <&rpmhcc RPMH_CXO_CLK>,
2267 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2268 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2269 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2270 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2272 <50000000 200000000>,
2275 <37500000 150000000>,
2282 status = "disabled";
2285 ufs_mem_phy: phy@1d87000 {
2286 compatible = "qcom,sdm845-qmp-ufs-phy";
2287 reg = <0 0x01d87000 0 0x18c>;
2288 #address-cells = <2>;
2291 clock-names = "ref",
2293 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2294 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2296 resets = <&ufs_mem_hc 0>;
2297 reset-names = "ufsphy";
2298 status = "disabled";
2300 ufs_mem_phy_lanes: lanes@1d87400 {
2301 reg = <0 0x01d87400 0 0x108>,
2302 <0 0x01d87600 0 0x1e0>,
2303 <0 0x01d87c00 0 0x1dc>,
2304 <0 0x01d87800 0 0x108>,
2305 <0 0x01d87a00 0 0x1e0>;
2310 cryptobam: dma@1dc4000 {
2311 compatible = "qcom,bam-v1.7.0";
2312 reg = <0 0x01dc4000 0 0x24000>;
2313 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2314 clocks = <&rpmhcc 15>;
2315 clock-names = "bam_clk";
2318 qcom,controlled-remotely = <1>;
2319 iommus = <&apps_smmu 0x704 0x1>,
2320 <&apps_smmu 0x706 0x1>,
2321 <&apps_smmu 0x714 0x1>,
2322 <&apps_smmu 0x716 0x1>;
2325 crypto: crypto@1dfa000 {
2326 compatible = "qcom,crypto-v5.4";
2327 reg = <0 0x01dfa000 0 0x6000>;
2328 clocks = <&gcc GCC_CE1_AHB_CLK>,
2329 <&gcc GCC_CE1_AHB_CLK>,
2331 clock-names = "iface", "bus", "core";
2332 dmas = <&cryptobam 6>, <&cryptobam 7>;
2333 dma-names = "rx", "tx";
2334 iommus = <&apps_smmu 0x704 0x1>,
2335 <&apps_smmu 0x706 0x1>,
2336 <&apps_smmu 0x714 0x1>,
2337 <&apps_smmu 0x716 0x1>;
2341 compatible = "qcom,sdm845-ipa";
2343 iommus = <&apps_smmu 0x720 0x0>,
2344 <&apps_smmu 0x722 0x0>;
2345 reg = <0 0x1e40000 0 0x7000>,
2346 <0 0x1e47000 0 0x2000>,
2347 <0 0x1e04000 0 0x2c000>;
2348 reg-names = "ipa-reg",
2352 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2353 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2354 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2355 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2356 interrupt-names = "ipa",
2361 clocks = <&rpmhcc RPMH_IPA_CLK>;
2362 clock-names = "core";
2364 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2365 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2366 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2367 interconnect-names = "memory",
2371 qcom,smem-states = <&ipa_smp2p_out 0>,
2373 qcom,smem-state-names = "ipa-clock-enabled-valid",
2374 "ipa-clock-enabled";
2376 status = "disabled";
2379 tcsr_mutex_regs: syscon@1f40000 {
2380 compatible = "syscon";
2381 reg = <0 0x01f40000 0 0x40000>;
2384 tlmm: pinctrl@3400000 {
2385 compatible = "qcom,sdm845-pinctrl";
2386 reg = <0 0x03400000 0 0xc00000>;
2387 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 interrupt-controller;
2391 #interrupt-cells = <2>;
2392 gpio-ranges = <&tlmm 0 0 151>;
2393 wakeup-parent = <&pdc_intc>;
2395 cci0_default: cci0-default {
2397 pins = "gpio17", "gpio18";
2398 function = "cci_i2c";
2401 drive-strength = <2>; /* 2 mA */
2404 cci0_sleep: cci0-sleep {
2406 pins = "gpio17", "gpio18";
2407 function = "cci_i2c";
2409 drive-strength = <2>; /* 2 mA */
2413 cci1_default: cci1-default {
2415 pins = "gpio19", "gpio20";
2416 function = "cci_i2c";
2419 drive-strength = <2>; /* 2 mA */
2422 cci1_sleep: cci1-sleep {
2424 pins = "gpio19", "gpio20";
2425 function = "cci_i2c";
2427 drive-strength = <2>; /* 2 mA */
2431 qspi_clk: qspi-clk {
2434 function = "qspi_clk";
2438 qspi_cs0: qspi-cs0 {
2441 function = "qspi_cs";
2445 qspi_cs1: qspi-cs1 {
2448 function = "qspi_cs";
2452 qspi_data01: qspi-data01 {
2454 pins = "gpio91", "gpio92";
2455 function = "qspi_data";
2459 qspi_data12: qspi-data12 {
2461 pins = "gpio93", "gpio94";
2462 function = "qspi_data";
2466 qup_i2c0_default: qup-i2c0-default {
2468 pins = "gpio0", "gpio1";
2473 qup_i2c1_default: qup-i2c1-default {
2475 pins = "gpio17", "gpio18";
2480 qup_i2c2_default: qup-i2c2-default {
2482 pins = "gpio27", "gpio28";
2487 qup_i2c3_default: qup-i2c3-default {
2489 pins = "gpio41", "gpio42";
2494 qup_i2c4_default: qup-i2c4-default {
2496 pins = "gpio89", "gpio90";
2501 qup_i2c5_default: qup-i2c5-default {
2503 pins = "gpio85", "gpio86";
2508 qup_i2c6_default: qup-i2c6-default {
2510 pins = "gpio45", "gpio46";
2515 qup_i2c7_default: qup-i2c7-default {
2517 pins = "gpio93", "gpio94";
2522 qup_i2c8_default: qup-i2c8-default {
2524 pins = "gpio65", "gpio66";
2529 qup_i2c9_default: qup-i2c9-default {
2531 pins = "gpio6", "gpio7";
2536 qup_i2c10_default: qup-i2c10-default {
2538 pins = "gpio55", "gpio56";
2543 qup_i2c11_default: qup-i2c11-default {
2545 pins = "gpio31", "gpio32";
2550 qup_i2c12_default: qup-i2c12-default {
2552 pins = "gpio49", "gpio50";
2557 qup_i2c13_default: qup-i2c13-default {
2559 pins = "gpio105", "gpio106";
2564 qup_i2c14_default: qup-i2c14-default {
2566 pins = "gpio33", "gpio34";
2571 qup_i2c15_default: qup-i2c15-default {
2573 pins = "gpio81", "gpio82";
2578 qup_spi0_default: qup-spi0-default {
2580 pins = "gpio0", "gpio1",
2586 qup_spi1_default: qup-spi1-default {
2588 pins = "gpio17", "gpio18",
2594 qup_spi2_default: qup-spi2-default {
2596 pins = "gpio27", "gpio28",
2602 qup_spi3_default: qup-spi3-default {
2604 pins = "gpio41", "gpio42",
2610 qup_spi4_default: qup-spi4-default {
2612 pins = "gpio89", "gpio90",
2618 qup_spi5_default: qup-spi5-default {
2620 pins = "gpio85", "gpio86",
2626 qup_spi6_default: qup-spi6-default {
2628 pins = "gpio45", "gpio46",
2634 qup_spi7_default: qup-spi7-default {
2636 pins = "gpio93", "gpio94",
2642 qup_spi8_default: qup-spi8-default {
2644 pins = "gpio65", "gpio66",
2650 qup_spi9_default: qup-spi9-default {
2652 pins = "gpio6", "gpio7",
2658 qup_spi10_default: qup-spi10-default {
2660 pins = "gpio55", "gpio56",
2666 qup_spi11_default: qup-spi11-default {
2668 pins = "gpio31", "gpio32",
2674 qup_spi12_default: qup-spi12-default {
2676 pins = "gpio49", "gpio50",
2682 qup_spi13_default: qup-spi13-default {
2684 pins = "gpio105", "gpio106",
2685 "gpio107", "gpio108";
2690 qup_spi14_default: qup-spi14-default {
2692 pins = "gpio33", "gpio34",
2698 qup_spi15_default: qup-spi15-default {
2700 pins = "gpio81", "gpio82",
2706 qup_uart0_default: qup-uart0-default {
2708 pins = "gpio2", "gpio3";
2713 qup_uart1_default: qup-uart1-default {
2715 pins = "gpio19", "gpio20";
2720 qup_uart2_default: qup-uart2-default {
2722 pins = "gpio29", "gpio30";
2727 qup_uart3_default: qup-uart3-default {
2729 pins = "gpio43", "gpio44";
2734 qup_uart4_default: qup-uart4-default {
2736 pins = "gpio91", "gpio92";
2741 qup_uart5_default: qup-uart5-default {
2743 pins = "gpio87", "gpio88";
2748 qup_uart6_default: qup-uart6-default {
2750 pins = "gpio47", "gpio48";
2755 qup_uart7_default: qup-uart7-default {
2757 pins = "gpio95", "gpio96";
2762 qup_uart8_default: qup-uart8-default {
2764 pins = "gpio67", "gpio68";
2769 qup_uart9_default: qup-uart9-default {
2771 pins = "gpio4", "gpio5";
2776 qup_uart10_default: qup-uart10-default {
2778 pins = "gpio53", "gpio54";
2783 qup_uart11_default: qup-uart11-default {
2785 pins = "gpio33", "gpio34";
2790 qup_uart12_default: qup-uart12-default {
2792 pins = "gpio51", "gpio52";
2797 qup_uart13_default: qup-uart13-default {
2799 pins = "gpio107", "gpio108";
2804 qup_uart14_default: qup-uart14-default {
2806 pins = "gpio31", "gpio32";
2811 qup_uart15_default: qup-uart15-default {
2813 pins = "gpio83", "gpio84";
2818 quat_mi2s_sleep: quat_mi2s_sleep {
2820 pins = "gpio58", "gpio59";
2825 pins = "gpio58", "gpio59";
2826 drive-strength = <2>;
2832 quat_mi2s_active: quat_mi2s_active {
2834 pins = "gpio58", "gpio59";
2835 function = "qua_mi2s";
2839 pins = "gpio58", "gpio59";
2840 drive-strength = <8>;
2846 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2854 drive-strength = <2>;
2860 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2863 function = "qua_mi2s";
2868 drive-strength = <8>;
2873 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2881 drive-strength = <2>;
2887 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2890 function = "qua_mi2s";
2895 drive-strength = <8>;
2900 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2908 drive-strength = <2>;
2914 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2917 function = "qua_mi2s";
2922 drive-strength = <8>;
2927 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2935 drive-strength = <2>;
2941 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2944 function = "qua_mi2s";
2949 drive-strength = <8>;
2955 mss_pil: remoteproc@4080000 {
2956 compatible = "qcom,sdm845-mss-pil";
2957 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2958 reg-names = "qdsp6", "rmb";
2960 interrupts-extended =
2961 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2962 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2963 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2964 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2965 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2966 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2967 interrupt-names = "wdog", "fatal", "ready",
2968 "handover", "stop-ack",
2971 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2972 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2973 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2974 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2975 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2976 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2977 <&gcc GCC_PRNG_AHB_CLK>,
2978 <&rpmhcc RPMH_CXO_CLK>;
2979 clock-names = "iface", "bus", "mem", "gpll0_mss",
2980 "snoc_axi", "mnoc_axi", "prng", "xo";
2982 qcom,smem-states = <&modem_smp2p_out 0>;
2983 qcom,smem-state-names = "stop";
2985 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2986 <&pdc_reset PDC_MODEM_SYNC_RESET>;
2987 reset-names = "mss_restart", "pdc_reset";
2989 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2991 power-domains = <&aoss_qmp 2>,
2992 <&rpmhpd SDM845_CX>,
2993 <&rpmhpd SDM845_MX>,
2994 <&rpmhpd SDM845_MSS>;
2995 power-domain-names = "load_state", "cx", "mx", "mss";
2998 memory-region = <&mba_region>;
3002 memory-region = <&mpss_region>;
3006 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3008 qcom,remote-pid = <1>;
3009 mboxes = <&apss_shared 12>;
3013 gpucc: clock-controller@5090000 {
3014 compatible = "qcom,sdm845-gpucc";
3015 reg = <0 0x05090000 0 0x9000>;
3018 #power-domain-cells = <1>;
3019 clocks = <&rpmhcc RPMH_CXO_CLK>,
3020 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3021 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3022 clock-names = "bi_tcxo",
3023 "gcc_gpu_gpll0_clk_src",
3024 "gcc_gpu_gpll0_div_clk_src";
3028 compatible = "arm,coresight-stm", "arm,primecell";
3029 reg = <0 0x06002000 0 0x1000>,
3030 <0 0x16280000 0 0x180000>;
3031 reg-names = "stm-base", "stm-stimulus-base";
3033 clocks = <&aoss_qmp>;
3034 clock-names = "apb_pclk";
3047 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3048 reg = <0 0x06041000 0 0x1000>;
3050 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pclk";
3055 funnel0_out: endpoint {
3057 <&merge_funnel_in0>;
3063 #address-cells = <1>;
3068 funnel0_in7: endpoint {
3069 remote-endpoint = <&stm_out>;
3076 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3077 reg = <0 0x06043000 0 0x1000>;
3079 clocks = <&aoss_qmp>;
3080 clock-names = "apb_pclk";
3084 funnel2_out: endpoint {
3086 <&merge_funnel_in2>;
3092 #address-cells = <1>;
3097 funnel2_in5: endpoint {
3099 <&apss_merge_funnel_out>;
3106 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3107 reg = <0 0x06045000 0 0x1000>;
3109 clocks = <&aoss_qmp>;
3110 clock-names = "apb_pclk";
3114 merge_funnel_out: endpoint {
3115 remote-endpoint = <&etf_in>;
3121 #address-cells = <1>;
3126 merge_funnel_in0: endpoint {
3134 merge_funnel_in2: endpoint {
3142 replicator@6046000 {
3143 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3144 reg = <0 0x06046000 0 0x1000>;
3146 clocks = <&aoss_qmp>;
3147 clock-names = "apb_pclk";
3151 replicator_out: endpoint {
3152 remote-endpoint = <&etr_in>;
3159 replicator_in: endpoint {
3160 remote-endpoint = <&etf_out>;
3167 compatible = "arm,coresight-tmc", "arm,primecell";
3168 reg = <0 0x06047000 0 0x1000>;
3170 clocks = <&aoss_qmp>;
3171 clock-names = "apb_pclk";
3183 #address-cells = <1>;
3190 <&merge_funnel_out>;
3197 compatible = "arm,coresight-tmc", "arm,primecell";
3198 reg = <0 0x06048000 0 0x1000>;
3200 clocks = <&aoss_qmp>;
3201 clock-names = "apb_pclk";
3215 compatible = "arm,coresight-etm4x", "arm,primecell";
3216 reg = <0 0x07040000 0 0x1000>;
3220 clocks = <&aoss_qmp>;
3221 clock-names = "apb_pclk";
3222 arm,coresight-loses-context-with-cpu;
3226 etm0_out: endpoint {
3235 compatible = "arm,coresight-etm4x", "arm,primecell";
3236 reg = <0 0x07140000 0 0x1000>;
3240 clocks = <&aoss_qmp>;
3241 clock-names = "apb_pclk";
3242 arm,coresight-loses-context-with-cpu;
3246 etm1_out: endpoint {
3255 compatible = "arm,coresight-etm4x", "arm,primecell";
3256 reg = <0 0x07240000 0 0x1000>;
3260 clocks = <&aoss_qmp>;
3261 clock-names = "apb_pclk";
3262 arm,coresight-loses-context-with-cpu;
3266 etm2_out: endpoint {
3275 compatible = "arm,coresight-etm4x", "arm,primecell";
3276 reg = <0 0x07340000 0 0x1000>;
3280 clocks = <&aoss_qmp>;
3281 clock-names = "apb_pclk";
3282 arm,coresight-loses-context-with-cpu;
3286 etm3_out: endpoint {
3295 compatible = "arm,coresight-etm4x", "arm,primecell";
3296 reg = <0 0x07440000 0 0x1000>;
3300 clocks = <&aoss_qmp>;
3301 clock-names = "apb_pclk";
3302 arm,coresight-loses-context-with-cpu;
3306 etm4_out: endpoint {
3315 compatible = "arm,coresight-etm4x", "arm,primecell";
3316 reg = <0 0x07540000 0 0x1000>;
3320 clocks = <&aoss_qmp>;
3321 clock-names = "apb_pclk";
3322 arm,coresight-loses-context-with-cpu;
3326 etm5_out: endpoint {
3335 compatible = "arm,coresight-etm4x", "arm,primecell";
3336 reg = <0 0x07640000 0 0x1000>;
3340 clocks = <&aoss_qmp>;
3341 clock-names = "apb_pclk";
3342 arm,coresight-loses-context-with-cpu;
3346 etm6_out: endpoint {
3355 compatible = "arm,coresight-etm4x", "arm,primecell";
3356 reg = <0 0x07740000 0 0x1000>;
3360 clocks = <&aoss_qmp>;
3361 clock-names = "apb_pclk";
3362 arm,coresight-loses-context-with-cpu;
3366 etm7_out: endpoint {
3374 funnel@7800000 { /* APSS Funnel */
3375 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3376 reg = <0 0x07800000 0 0x1000>;
3378 clocks = <&aoss_qmp>;
3379 clock-names = "apb_pclk";
3383 apss_funnel_out: endpoint {
3385 <&apss_merge_funnel_in>;
3391 #address-cells = <1>;
3396 apss_funnel_in0: endpoint {
3404 apss_funnel_in1: endpoint {
3412 apss_funnel_in2: endpoint {
3420 apss_funnel_in3: endpoint {
3428 apss_funnel_in4: endpoint {
3436 apss_funnel_in5: endpoint {
3444 apss_funnel_in6: endpoint {
3452 apss_funnel_in7: endpoint {
3461 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3462 reg = <0 0x07810000 0 0x1000>;
3464 clocks = <&aoss_qmp>;
3465 clock-names = "apb_pclk";
3469 apss_merge_funnel_out: endpoint {
3478 apss_merge_funnel_in: endpoint {
3486 sdhc_2: sdhci@8804000 {
3487 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3488 reg = <0 0x08804000 0 0x1000>;
3490 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3491 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3492 interrupt-names = "hc_irq", "pwr_irq";
3494 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3495 <&gcc GCC_SDCC2_APPS_CLK>;
3496 clock-names = "iface", "core";
3497 iommus = <&apps_smmu 0xa0 0xf>;
3498 power-domains = <&rpmhpd SDM845_CX>;
3499 operating-points-v2 = <&sdhc2_opp_table>;
3501 status = "disabled";
3503 sdhc2_opp_table: sdhc2-opp-table {
3504 compatible = "operating-points-v2";
3507 opp-hz = /bits/ 64 <9600000>;
3508 required-opps = <&rpmhpd_opp_min_svs>;
3512 opp-hz = /bits/ 64 <19200000>;
3513 required-opps = <&rpmhpd_opp_low_svs>;
3517 opp-hz = /bits/ 64 <100000000>;
3518 required-opps = <&rpmhpd_opp_svs>;
3522 opp-hz = /bits/ 64 <201500000>;
3523 required-opps = <&rpmhpd_opp_svs_l1>;
3528 qspi_opp_table: qspi-opp-table {
3529 compatible = "operating-points-v2";
3532 opp-hz = /bits/ 64 <19200000>;
3533 required-opps = <&rpmhpd_opp_min_svs>;
3537 opp-hz = /bits/ 64 <100000000>;
3538 required-opps = <&rpmhpd_opp_low_svs>;
3542 opp-hz = /bits/ 64 <150000000>;
3543 required-opps = <&rpmhpd_opp_svs>;
3547 opp-hz = /bits/ 64 <300000000>;
3548 required-opps = <&rpmhpd_opp_nom>;
3553 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3554 reg = <0 0x088df000 0 0x600>;
3555 #address-cells = <1>;
3557 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3558 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3559 <&gcc GCC_QSPI_CORE_CLK>;
3560 clock-names = "iface", "core";
3561 power-domains = <&rpmhpd SDM845_CX>;
3562 operating-points-v2 = <&qspi_opp_table>;
3563 status = "disabled";
3566 slim: slim@171c0000 {
3567 compatible = "qcom,slim-ngd-v2.1.0";
3568 reg = <0 0x171c0000 0 0x2c000>;
3569 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3571 qcom,apps-ch-pipes = <0x780000>;
3572 qcom,ea-pc = <0x270>;
3574 dmas = <&slimbam 3>, <&slimbam 4>,
3575 <&slimbam 5>, <&slimbam 6>;
3576 dma-names = "rx", "tx", "tx2", "rx2";
3578 iommus = <&apps_smmu 0x1806 0x0>;
3579 #address-cells = <1>;
3584 #address-cells = <2>;
3588 compatible = "slim217,250";
3593 compatible = "slim217,250";
3595 slim-ifc-dev = <&wcd9340_ifd>;
3597 #sound-dai-cells = <1>;
3599 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3600 interrupt-controller;
3601 #interrupt-cells = <1>;
3604 clock-frequency = <9600000>;
3605 clock-output-names = "mclk";
3606 qcom,micbias1-millivolt = <1800>;
3607 qcom,micbias2-millivolt = <1800>;
3608 qcom,micbias3-millivolt = <1800>;
3609 qcom,micbias4-millivolt = <1800>;
3611 #address-cells = <1>;
3614 wcdgpio: gpio-controller@42 {
3615 compatible = "qcom,wcd9340-gpio";
3622 compatible = "qcom,soundwire-v1.3.0";
3624 interrupts-extended = <&wcd9340 20>;
3626 qcom,dout-ports = <6>;
3627 qcom,din-ports = <2>;
3628 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3629 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3630 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3632 #sound-dai-cells = <1>;
3633 clocks = <&wcd9340>;
3634 clock-names = "iface";
3635 #address-cells = <2>;
3647 usb_1_hsphy: phy@88e2000 {
3648 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3649 reg = <0 0x088e2000 0 0x400>;
3650 status = "disabled";
3653 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3654 <&rpmhcc RPMH_CXO_CLK>;
3655 clock-names = "cfg_ahb", "ref";
3657 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3659 nvmem-cells = <&qusb2p_hstx_trim>;
3662 usb_2_hsphy: phy@88e3000 {
3663 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3664 reg = <0 0x088e3000 0 0x400>;
3665 status = "disabled";
3668 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3669 <&rpmhcc RPMH_CXO_CLK>;
3670 clock-names = "cfg_ahb", "ref";
3672 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3674 nvmem-cells = <&qusb2s_hstx_trim>;
3677 usb_1_qmpphy: phy@88e9000 {
3678 compatible = "qcom,sdm845-qmp-usb3-phy";
3679 reg = <0 0x088e9000 0 0x18c>,
3680 <0 0x088e8000 0 0x10>;
3681 reg-names = "reg-base", "dp_com";
3682 status = "disabled";
3683 #address-cells = <2>;
3687 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3688 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3689 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3690 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3691 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3693 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3694 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3695 reset-names = "phy", "common";
3697 usb_1_ssphy: lanes@88e9200 {
3698 reg = <0 0x088e9200 0 0x128>,
3699 <0 0x088e9400 0 0x200>,
3700 <0 0x088e9c00 0 0x218>,
3701 <0 0x088e9600 0 0x128>,
3702 <0 0x088e9800 0 0x200>,
3703 <0 0x088e9a00 0 0x100>;
3706 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3707 clock-names = "pipe0";
3708 clock-output-names = "usb3_phy_pipe_clk_src";
3712 usb_2_qmpphy: phy@88eb000 {
3713 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3714 reg = <0 0x088eb000 0 0x18c>;
3715 status = "disabled";
3716 #address-cells = <2>;
3720 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3721 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3722 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3723 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3724 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3726 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3727 <&gcc GCC_USB3_PHY_SEC_BCR>;
3728 reset-names = "phy", "common";
3730 usb_2_ssphy: lane@88eb200 {
3731 reg = <0 0x088eb200 0 0x128>,
3732 <0 0x088eb400 0 0x1fc>,
3733 <0 0x088eb800 0 0x218>,
3734 <0 0x088eb600 0 0x70>;
3737 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3738 clock-names = "pipe0";
3739 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3743 usb_1: usb@a6f8800 {
3744 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3745 reg = <0 0x0a6f8800 0 0x400>;
3746 status = "disabled";
3747 #address-cells = <2>;
3752 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3753 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3754 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3755 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3756 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3757 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3760 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3761 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3762 assigned-clock-rates = <19200000>, <150000000>;
3764 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3765 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3766 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3767 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3768 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3769 "dm_hs_phy_irq", "dp_hs_phy_irq";
3771 power-domains = <&gcc USB30_PRIM_GDSC>;
3773 resets = <&gcc GCC_USB30_PRIM_BCR>;
3775 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3776 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3777 interconnect-names = "usb-ddr", "apps-usb";
3779 usb_1_dwc3: dwc3@a600000 {
3780 compatible = "snps,dwc3";
3781 reg = <0 0x0a600000 0 0xcd00>;
3782 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3783 iommus = <&apps_smmu 0x740 0>;
3784 snps,dis_u2_susphy_quirk;
3785 snps,dis_enblslpm_quirk;
3786 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3787 phy-names = "usb2-phy", "usb3-phy";
3791 usb_2: usb@a8f8800 {
3792 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3793 reg = <0 0x0a8f8800 0 0x400>;
3794 status = "disabled";
3795 #address-cells = <2>;
3800 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3801 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3802 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3803 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3804 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3805 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3808 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3809 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3810 assigned-clock-rates = <19200000>, <150000000>;
3812 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3813 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3814 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3815 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3816 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3817 "dm_hs_phy_irq", "dp_hs_phy_irq";
3819 power-domains = <&gcc USB30_SEC_GDSC>;
3821 resets = <&gcc GCC_USB30_SEC_BCR>;
3823 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3824 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3825 interconnect-names = "usb-ddr", "apps-usb";
3827 usb_2_dwc3: dwc3@a800000 {
3828 compatible = "snps,dwc3";
3829 reg = <0 0x0a800000 0 0xcd00>;
3830 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3831 iommus = <&apps_smmu 0x760 0>;
3832 snps,dis_u2_susphy_quirk;
3833 snps,dis_enblslpm_quirk;
3834 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3835 phy-names = "usb2-phy", "usb3-phy";
3839 venus: video-codec@aa00000 {
3840 compatible = "qcom,sdm845-venus-v2";
3841 reg = <0 0x0aa00000 0 0xff000>;
3842 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3843 power-domains = <&videocc VENUS_GDSC>,
3844 <&videocc VCODEC0_GDSC>,
3845 <&videocc VCODEC1_GDSC>,
3846 <&rpmhpd SDM845_CX>;
3847 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3848 operating-points-v2 = <&venus_opp_table>;
3849 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3850 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3851 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3852 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3853 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3854 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3855 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3856 clock-names = "core", "iface", "bus",
3857 "vcodec0_core", "vcodec0_bus",
3858 "vcodec1_core", "vcodec1_bus";
3859 iommus = <&apps_smmu 0x10a0 0x8>,
3860 <&apps_smmu 0x10b0 0x0>;
3861 memory-region = <&venus_mem>;
3862 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3863 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3864 interconnect-names = "video-mem", "cpu-cfg";
3867 compatible = "venus-decoder";
3871 compatible = "venus-encoder";
3874 venus_opp_table: venus-opp-table {
3875 compatible = "operating-points-v2";
3878 opp-hz = /bits/ 64 <100000000>;
3879 required-opps = <&rpmhpd_opp_min_svs>;
3883 opp-hz = /bits/ 64 <200000000>;
3884 required-opps = <&rpmhpd_opp_low_svs>;
3888 opp-hz = /bits/ 64 <320000000>;
3889 required-opps = <&rpmhpd_opp_svs>;
3893 opp-hz = /bits/ 64 <380000000>;
3894 required-opps = <&rpmhpd_opp_svs_l1>;
3898 opp-hz = /bits/ 64 <444000000>;
3899 required-opps = <&rpmhpd_opp_nom>;
3903 opp-hz = /bits/ 64 <533000097>;
3904 required-opps = <&rpmhpd_opp_turbo>;
3909 videocc: clock-controller@ab00000 {
3910 compatible = "qcom,sdm845-videocc";
3911 reg = <0 0x0ab00000 0 0x10000>;
3912 clocks = <&rpmhcc RPMH_CXO_CLK>;
3913 clock-names = "bi_tcxo";
3915 #power-domain-cells = <1>;
3919 camss: camss@a00000 {
3920 compatible = "qcom,sdm845-camss";
3922 reg = <0 0xacb3000 0 0x1000>,
3923 <0 0xacba000 0 0x1000>,
3924 <0 0xacc8000 0 0x1000>,
3925 <0 0xac65000 0 0x1000>,
3926 <0 0xac66000 0 0x1000>,
3927 <0 0xac67000 0 0x1000>,
3928 <0 0xac68000 0 0x1000>,
3929 <0 0xacaf000 0 0x4000>,
3930 <0 0xacb6000 0 0x4000>,
3931 <0 0xacc4000 0 0x4000>;
3932 reg-names = "csid0",
3943 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3944 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3945 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3946 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3947 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3948 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3949 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3950 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3951 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3952 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
3953 interrupt-names = "csid0",
3964 power-domains = <&clock_camcc IFE_0_GDSC>,
3965 <&clock_camcc IFE_1_GDSC>,
3966 <&clock_camcc TITAN_TOP_GDSC>;
3968 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3969 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
3970 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
3971 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
3972 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
3973 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
3974 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
3975 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
3976 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
3977 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
3978 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
3979 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
3980 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
3981 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
3982 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
3983 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
3984 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
3985 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
3986 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
3987 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
3988 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
3989 <&gcc GCC_CAMERA_AHB_CLK>,
3990 <&gcc GCC_CAMERA_AXI_CLK>,
3991 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3992 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
3993 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
3994 <&clock_camcc CAM_CC_IFE_0_CLK>,
3995 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
3996 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
3997 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
3998 <&clock_camcc CAM_CC_IFE_1_CLK>,
3999 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4000 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4001 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4002 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4003 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4004 clock-names = "camnoc_axi",
4015 "csiphy0_timer_src",
4018 "csiphy1_timer_src",
4021 "csiphy2_timer_src",
4024 "csiphy3_timer_src",
4041 iommus = <&apps_smmu 0x0808 0x0>,
4042 <&apps_smmu 0x0810 0x8>,
4043 <&apps_smmu 0x0c08 0x0>,
4044 <&apps_smmu 0x0c10 0x8>;
4046 status = "disabled";
4049 #address-cells = <1>;
4055 compatible = "qcom,sdm845-cci";
4056 #address-cells = <1>;
4059 reg = <0 0x0ac4a000 0 0x4000>;
4060 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4061 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4063 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4064 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4065 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4066 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4067 <&clock_camcc CAM_CC_CCI_CLK>,
4068 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4069 clock-names = "camnoc_axi",
4076 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4077 <&clock_camcc CAM_CC_CCI_CLK>;
4078 assigned-clock-rates = <80000000>, <37500000>;
4080 pinctrl-names = "default", "sleep";
4081 pinctrl-0 = <&cci0_default &cci1_default>;
4082 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4084 status = "disabled";
4086 cci_i2c0: i2c-bus@0 {
4088 clock-frequency = <1000000>;
4089 #address-cells = <1>;
4093 cci_i2c1: i2c-bus@1 {
4095 clock-frequency = <1000000>;
4096 #address-cells = <1>;
4101 clock_camcc: clock-controller@ad00000 {
4102 compatible = "qcom,sdm845-camcc";
4103 reg = <0 0x0ad00000 0 0x10000>;
4106 #power-domain-cells = <1>;
4109 dsi_opp_table: dsi-opp-table {
4110 compatible = "operating-points-v2";
4113 opp-hz = /bits/ 64 <19200000>;
4114 required-opps = <&rpmhpd_opp_min_svs>;
4118 opp-hz = /bits/ 64 <180000000>;
4119 required-opps = <&rpmhpd_opp_low_svs>;
4123 opp-hz = /bits/ 64 <275000000>;
4124 required-opps = <&rpmhpd_opp_svs>;
4128 opp-hz = /bits/ 64 <328580000>;
4129 required-opps = <&rpmhpd_opp_svs_l1>;
4133 opp-hz = /bits/ 64 <358000000>;
4134 required-opps = <&rpmhpd_opp_nom>;
4138 mdss: mdss@ae00000 {
4139 compatible = "qcom,sdm845-mdss";
4140 reg = <0 0x0ae00000 0 0x1000>;
4143 power-domains = <&dispcc MDSS_GDSC>;
4145 clocks = <&gcc GCC_DISP_AHB_CLK>,
4146 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4147 clock-names = "iface", "core";
4149 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4150 assigned-clock-rates = <300000000>;
4152 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4153 interrupt-controller;
4154 #interrupt-cells = <1>;
4156 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4157 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4158 interconnect-names = "mdp0-mem", "mdp1-mem";
4160 iommus = <&apps_smmu 0x880 0x8>,
4161 <&apps_smmu 0xc80 0x8>;
4163 status = "disabled";
4165 #address-cells = <2>;
4169 mdss_mdp: mdp@ae01000 {
4170 compatible = "qcom,sdm845-dpu";
4171 reg = <0 0x0ae01000 0 0x8f000>,
4172 <0 0x0aeb0000 0 0x2008>;
4173 reg-names = "mdp", "vbif";
4175 clocks = <&gcc GCC_DISP_AXI_CLK>,
4176 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4177 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4178 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4179 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4180 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4182 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4183 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4184 assigned-clock-rates = <300000000>,
4186 operating-points-v2 = <&mdp_opp_table>;
4187 power-domains = <&rpmhpd SDM845_CX>;
4189 interrupt-parent = <&mdss>;
4190 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4192 status = "disabled";
4195 #address-cells = <1>;
4200 dpu_intf1_out: endpoint {
4201 remote-endpoint = <&dsi0_in>;
4207 dpu_intf2_out: endpoint {
4208 remote-endpoint = <&dsi1_in>;
4213 mdp_opp_table: mdp-opp-table {
4214 compatible = "operating-points-v2";
4217 opp-hz = /bits/ 64 <19200000>;
4218 required-opps = <&rpmhpd_opp_min_svs>;
4222 opp-hz = /bits/ 64 <171428571>;
4223 required-opps = <&rpmhpd_opp_low_svs>;
4227 opp-hz = /bits/ 64 <344000000>;
4228 required-opps = <&rpmhpd_opp_svs_l1>;
4232 opp-hz = /bits/ 64 <430000000>;
4233 required-opps = <&rpmhpd_opp_nom>;
4239 compatible = "qcom,mdss-dsi-ctrl";
4240 reg = <0 0x0ae94000 0 0x400>;
4241 reg-names = "dsi_ctrl";
4243 interrupt-parent = <&mdss>;
4244 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4246 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4247 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4248 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4249 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4250 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4251 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4252 clock-names = "byte",
4258 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4259 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4261 operating-points-v2 = <&dsi_opp_table>;
4262 power-domains = <&rpmhpd SDM845_CX>;
4267 status = "disabled";
4270 #address-cells = <1>;
4276 remote-endpoint = <&dpu_intf1_out>;
4282 dsi0_out: endpoint {
4288 dsi0_phy: dsi-phy@ae94400 {
4289 compatible = "qcom,dsi-phy-10nm";
4290 reg = <0 0x0ae94400 0 0x200>,
4291 <0 0x0ae94600 0 0x280>,
4292 <0 0x0ae94a00 0 0x1e0>;
4293 reg-names = "dsi_phy",
4300 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4301 <&rpmhcc RPMH_CXO_CLK>;
4302 clock-names = "iface", "ref";
4304 status = "disabled";
4308 compatible = "qcom,mdss-dsi-ctrl";
4309 reg = <0 0x0ae96000 0 0x400>;
4310 reg-names = "dsi_ctrl";
4312 interrupt-parent = <&mdss>;
4313 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4315 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4316 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4317 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4318 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4319 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4320 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4321 clock-names = "byte",
4327 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4328 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4330 operating-points-v2 = <&dsi_opp_table>;
4331 power-domains = <&rpmhpd SDM845_CX>;
4336 status = "disabled";
4339 #address-cells = <1>;
4345 remote-endpoint = <&dpu_intf2_out>;
4351 dsi1_out: endpoint {
4357 dsi1_phy: dsi-phy@ae96400 {
4358 compatible = "qcom,dsi-phy-10nm";
4359 reg = <0 0x0ae96400 0 0x200>,
4360 <0 0x0ae96600 0 0x280>,
4361 <0 0x0ae96a00 0 0x10e>;
4362 reg-names = "dsi_phy",
4369 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4370 <&rpmhcc RPMH_CXO_CLK>;
4371 clock-names = "iface", "ref";
4373 status = "disabled";
4378 compatible = "qcom,adreno-630.2", "qcom,adreno";
4379 #stream-id-cells = <16>;
4381 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4382 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4385 * Look ma, no clocks! The GPU clocks and power are
4386 * controlled entirely by the GMU
4389 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4391 iommus = <&adreno_smmu 0>;
4393 operating-points-v2 = <&gpu_opp_table>;
4397 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4398 interconnect-names = "gfx-mem";
4400 gpu_opp_table: opp-table {
4401 compatible = "operating-points-v2";
4404 opp-hz = /bits/ 64 <710000000>;
4405 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4406 opp-peak-kBps = <7216000>;
4410 opp-hz = /bits/ 64 <675000000>;
4411 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4412 opp-peak-kBps = <7216000>;
4416 opp-hz = /bits/ 64 <596000000>;
4417 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4418 opp-peak-kBps = <6220000>;
4422 opp-hz = /bits/ 64 <520000000>;
4423 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4424 opp-peak-kBps = <6220000>;
4428 opp-hz = /bits/ 64 <414000000>;
4429 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4430 opp-peak-kBps = <4068000>;
4434 opp-hz = /bits/ 64 <342000000>;
4435 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4436 opp-peak-kBps = <2724000>;
4440 opp-hz = /bits/ 64 <257000000>;
4441 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4442 opp-peak-kBps = <1648000>;
4447 adreno_smmu: iommu@5040000 {
4448 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4449 reg = <0 0x5040000 0 0x10000>;
4451 #global-interrupts = <2>;
4452 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4454 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4455 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4456 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4457 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4458 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4459 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4460 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4461 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4462 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4463 <&gcc GCC_GPU_CFG_AHB_CLK>;
4464 clock-names = "bus", "iface";
4466 power-domains = <&gpucc GPU_CX_GDSC>;
4470 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4472 reg = <0 0x506a000 0 0x30000>,
4473 <0 0xb280000 0 0x10000>,
4474 <0 0xb480000 0 0x10000>;
4475 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4477 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4478 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4479 interrupt-names = "hfi", "gmu";
4481 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4482 <&gpucc GPU_CC_CXO_CLK>,
4483 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4484 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4485 clock-names = "gmu", "cxo", "axi", "memnoc";
4487 power-domains = <&gpucc GPU_CX_GDSC>,
4488 <&gpucc GPU_GX_GDSC>;
4489 power-domain-names = "cx", "gx";
4491 iommus = <&adreno_smmu 5>;
4493 operating-points-v2 = <&gmu_opp_table>;
4495 gmu_opp_table: opp-table {
4496 compatible = "operating-points-v2";
4499 opp-hz = /bits/ 64 <400000000>;
4500 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4504 opp-hz = /bits/ 64 <200000000>;
4505 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4510 dispcc: clock-controller@af00000 {
4511 compatible = "qcom,sdm845-dispcc";
4512 reg = <0 0x0af00000 0 0x10000>;
4513 clocks = <&rpmhcc RPMH_CXO_CLK>,
4514 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4515 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4522 clock-names = "bi_tcxo",
4523 "gcc_disp_gpll0_clk_src",
4524 "gcc_disp_gpll0_div_clk_src",
4525 "dsi0_phy_pll_out_byteclk",
4526 "dsi0_phy_pll_out_dsiclk",
4527 "dsi1_phy_pll_out_byteclk",
4528 "dsi1_phy_pll_out_dsiclk",
4529 "dp_link_clk_divsel_ten",
4530 "dp_vco_divided_clk_src_mux";
4533 #power-domain-cells = <1>;
4536 pdc_intc: interrupt-controller@b220000 {
4537 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4538 reg = <0 0x0b220000 0 0x30000>;
4539 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4540 #interrupt-cells = <2>;
4541 interrupt-parent = <&intc>;
4542 interrupt-controller;
4545 pdc_reset: reset-controller@b2e0000 {
4546 compatible = "qcom,sdm845-pdc-global";
4547 reg = <0 0x0b2e0000 0 0x20000>;
4551 tsens0: thermal-sensor@c263000 {
4552 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4553 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4554 <0 0x0c222000 0 0x1ff>; /* SROT */
4555 #qcom,sensors = <13>;
4556 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4557 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4558 interrupt-names = "uplow", "critical";
4559 #thermal-sensor-cells = <1>;
4562 tsens1: thermal-sensor@c265000 {
4563 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4564 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4565 <0 0x0c223000 0 0x1ff>; /* SROT */
4566 #qcom,sensors = <8>;
4567 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4568 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4569 interrupt-names = "uplow", "critical";
4570 #thermal-sensor-cells = <1>;
4573 aoss_reset: reset-controller@c2a0000 {
4574 compatible = "qcom,sdm845-aoss-cc";
4575 reg = <0 0x0c2a0000 0 0x31000>;
4579 aoss_qmp: power-controller@c300000 {
4580 compatible = "qcom,sdm845-aoss-qmp";
4581 reg = <0 0x0c300000 0 0x100000>;
4582 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4583 mboxes = <&apss_shared 0>;
4586 #power-domain-cells = <1>;
4589 #cooling-cells = <2>;
4593 #cooling-cells = <2>;
4597 spmi_bus: spmi@c440000 {
4598 compatible = "qcom,spmi-pmic-arb";
4599 reg = <0 0x0c440000 0 0x1100>,
4600 <0 0x0c600000 0 0x2000000>,
4601 <0 0x0e600000 0 0x100000>,
4602 <0 0x0e700000 0 0xa0000>,
4603 <0 0x0c40a000 0 0x26000>;
4604 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4605 interrupt-names = "periph_irq";
4606 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4609 #address-cells = <2>;
4611 interrupt-controller;
4612 #interrupt-cells = <4>;
4617 compatible = "simple-mfd";
4618 reg = <0 0x146bf000 0 0x1000>;
4620 #address-cells = <1>;
4623 ranges = <0 0 0x146bf000 0x1000>;
4626 compatible = "qcom,pil-reloc-info";
4631 apps_smmu: iommu@15000000 {
4632 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4633 reg = <0 0x15000000 0 0x80000>;
4635 #global-interrupts = <1>;
4636 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4637 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4638 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4639 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4640 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4641 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4642 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4643 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4644 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4645 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4646 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4647 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4648 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4649 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4650 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4651 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4652 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4653 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4654 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4655 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4656 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4657 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4658 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4659 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4660 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4661 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4662 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4663 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4664 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4665 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4666 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4667 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4668 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4669 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4670 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4671 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4672 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4673 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4674 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4675 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4676 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4677 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4678 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4679 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4680 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4681 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4682 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4683 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4684 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4685 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4686 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4687 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4688 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4689 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4690 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4691 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4692 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4693 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4694 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4695 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4696 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4697 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4698 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4699 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4700 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4703 lpasscc: clock-controller@17014000 {
4704 compatible = "qcom,sdm845-lpasscc";
4705 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4706 reg-names = "cc", "qdsp6ss";
4708 status = "disabled";
4711 gladiator_noc: interconnect@17900000 {
4712 compatible = "qcom,sdm845-gladiator-noc";
4713 reg = <0 0x17900000 0 0xd080>;
4714 #interconnect-cells = <2>;
4715 qcom,bcm-voters = <&apps_bcm_voter>;
4719 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4720 reg = <0 0x17980000 0 0x1000>;
4721 clocks = <&sleep_clk>;
4722 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4725 apss_shared: mailbox@17990000 {
4726 compatible = "qcom,sdm845-apss-shared";
4727 reg = <0 0x17990000 0 0x1000>;
4731 apps_rsc: rsc@179c0000 {
4733 compatible = "qcom,rpmh-rsc";
4734 reg = <0 0x179c0000 0 0x10000>,
4735 <0 0x179d0000 0 0x10000>,
4736 <0 0x179e0000 0 0x10000>;
4737 reg-names = "drv-0", "drv-1", "drv-2";
4738 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4739 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4740 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4741 qcom,tcs-offset = <0xd00>;
4743 qcom,tcs-config = <ACTIVE_TCS 2>,
4748 apps_bcm_voter: bcm-voter {
4749 compatible = "qcom,bcm-voter";
4752 rpmhcc: clock-controller {
4753 compatible = "qcom,sdm845-rpmh-clk";
4756 clocks = <&xo_board>;
4759 rpmhpd: power-controller {
4760 compatible = "qcom,sdm845-rpmhpd";
4761 #power-domain-cells = <1>;
4762 operating-points-v2 = <&rpmhpd_opp_table>;
4764 rpmhpd_opp_table: opp-table {
4765 compatible = "operating-points-v2";
4767 rpmhpd_opp_ret: opp1 {
4768 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4771 rpmhpd_opp_min_svs: opp2 {
4772 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4775 rpmhpd_opp_low_svs: opp3 {
4776 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4779 rpmhpd_opp_svs: opp4 {
4780 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4783 rpmhpd_opp_svs_l1: opp5 {
4784 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4787 rpmhpd_opp_nom: opp6 {
4788 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4791 rpmhpd_opp_nom_l1: opp7 {
4792 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4795 rpmhpd_opp_nom_l2: opp8 {
4796 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4799 rpmhpd_opp_turbo: opp9 {
4800 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4803 rpmhpd_opp_turbo_l1: opp10 {
4804 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4810 intc: interrupt-controller@17a00000 {
4811 compatible = "arm,gic-v3";
4812 #address-cells = <2>;
4815 #interrupt-cells = <3>;
4816 interrupt-controller;
4817 reg = <0 0x17a00000 0 0x10000>, /* GICD */
4818 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
4819 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4821 msi-controller@17a40000 {
4822 compatible = "arm,gic-v3-its";
4825 reg = <0 0x17a40000 0 0x20000>;
4826 status = "disabled";
4830 slimbam: dma-controller@17184000 {
4831 compatible = "qcom,bam-v1.7.0";
4832 qcom,controlled-remotely;
4833 reg = <0 0x17184000 0 0x2a000>;
4834 num-channels = <31>;
4835 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4839 iommus = <&apps_smmu 0x1806 0x0>;
4843 #address-cells = <2>;
4846 compatible = "arm,armv7-timer-mem";
4847 reg = <0 0x17c90000 0 0x1000>;
4851 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4852 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4853 reg = <0 0x17ca0000 0 0x1000>,
4854 <0 0x17cb0000 0 0x1000>;
4859 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4860 reg = <0 0x17cc0000 0 0x1000>;
4861 status = "disabled";
4866 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4867 reg = <0 0x17cd0000 0 0x1000>;
4868 status = "disabled";
4873 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4874 reg = <0 0x17ce0000 0 0x1000>;
4875 status = "disabled";
4880 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4881 reg = <0 0x17cf0000 0 0x1000>;
4882 status = "disabled";
4887 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4888 reg = <0 0x17d00000 0 0x1000>;
4889 status = "disabled";
4894 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4895 reg = <0 0x17d10000 0 0x1000>;
4896 status = "disabled";
4900 osm_l3: interconnect@17d41000 {
4901 compatible = "qcom,sdm845-osm-l3";
4902 reg = <0 0x17d41000 0 0x1400>;
4904 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4905 clock-names = "xo", "alternate";
4907 #interconnect-cells = <1>;
4910 cpufreq_hw: cpufreq@17d43000 {
4911 compatible = "qcom,cpufreq-hw";
4912 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4913 reg-names = "freq-domain0", "freq-domain1";
4915 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4916 clock-names = "xo", "alternate";
4918 #freq-domain-cells = <1>;
4921 wifi: wifi@18800000 {
4922 compatible = "qcom,wcn3990-wifi";
4923 status = "disabled";
4924 reg = <0 0x18800000 0 0x800000>;
4925 reg-names = "membase";
4926 memory-region = <&wlan_msa_mem>;
4927 clock-names = "cxo_ref_clk_pin";
4928 clocks = <&rpmhcc RPMH_RF_CLK2>;
4930 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4931 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4932 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4933 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4935 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4936 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4937 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4938 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4939 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4940 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4941 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4942 iommus = <&apps_smmu 0x0040 0x1>;
4948 polling-delay-passive = <250>;
4949 polling-delay = <1000>;
4951 thermal-sensors = <&tsens0 1>;
4954 cpu0_alert0: trip-point0 {
4955 temperature = <90000>;
4956 hysteresis = <2000>;
4960 cpu0_alert1: trip-point1 {
4961 temperature = <95000>;
4962 hysteresis = <2000>;
4966 cpu0_crit: cpu_crit {
4967 temperature = <110000>;
4968 hysteresis = <1000>;
4975 trip = <&cpu0_alert0>;
4976 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4977 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4978 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4979 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4982 trip = <&cpu0_alert1>;
4983 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4985 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4986 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 polling-delay-passive = <250>;
4993 polling-delay = <1000>;
4995 thermal-sensors = <&tsens0 2>;
4998 cpu1_alert0: trip-point0 {
4999 temperature = <90000>;
5000 hysteresis = <2000>;
5004 cpu1_alert1: trip-point1 {
5005 temperature = <95000>;
5006 hysteresis = <2000>;
5010 cpu1_crit: cpu_crit {
5011 temperature = <110000>;
5012 hysteresis = <1000>;
5019 trip = <&cpu1_alert0>;
5020 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5021 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5022 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5023 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5026 trip = <&cpu1_alert1>;
5027 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5028 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5029 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5030 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5036 polling-delay-passive = <250>;
5037 polling-delay = <1000>;
5039 thermal-sensors = <&tsens0 3>;
5042 cpu2_alert0: trip-point0 {
5043 temperature = <90000>;
5044 hysteresis = <2000>;
5048 cpu2_alert1: trip-point1 {
5049 temperature = <95000>;
5050 hysteresis = <2000>;
5054 cpu2_crit: cpu_crit {
5055 temperature = <110000>;
5056 hysteresis = <1000>;
5063 trip = <&cpu2_alert0>;
5064 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5065 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5066 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5067 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5070 trip = <&cpu2_alert1>;
5071 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5072 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5073 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5074 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5080 polling-delay-passive = <250>;
5081 polling-delay = <1000>;
5083 thermal-sensors = <&tsens0 4>;
5086 cpu3_alert0: trip-point0 {
5087 temperature = <90000>;
5088 hysteresis = <2000>;
5092 cpu3_alert1: trip-point1 {
5093 temperature = <95000>;
5094 hysteresis = <2000>;
5098 cpu3_crit: cpu_crit {
5099 temperature = <110000>;
5100 hysteresis = <1000>;
5107 trip = <&cpu3_alert0>;
5108 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5109 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5110 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 trip = <&cpu3_alert1>;
5115 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5116 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5117 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5124 polling-delay-passive = <250>;
5125 polling-delay = <1000>;
5127 thermal-sensors = <&tsens0 7>;
5130 cpu4_alert0: trip-point0 {
5131 temperature = <90000>;
5132 hysteresis = <2000>;
5136 cpu4_alert1: trip-point1 {
5137 temperature = <95000>;
5138 hysteresis = <2000>;
5142 cpu4_crit: cpu_crit {
5143 temperature = <110000>;
5144 hysteresis = <1000>;
5151 trip = <&cpu4_alert0>;
5152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5153 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5154 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5155 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5158 trip = <&cpu4_alert1>;
5159 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5160 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5161 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5162 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5168 polling-delay-passive = <250>;
5169 polling-delay = <1000>;
5171 thermal-sensors = <&tsens0 8>;
5174 cpu5_alert0: trip-point0 {
5175 temperature = <90000>;
5176 hysteresis = <2000>;
5180 cpu5_alert1: trip-point1 {
5181 temperature = <95000>;
5182 hysteresis = <2000>;
5186 cpu5_crit: cpu_crit {
5187 temperature = <110000>;
5188 hysteresis = <1000>;
5195 trip = <&cpu5_alert0>;
5196 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5197 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5198 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5199 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5202 trip = <&cpu5_alert1>;
5203 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5204 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5205 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5206 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5212 polling-delay-passive = <250>;
5213 polling-delay = <1000>;
5215 thermal-sensors = <&tsens0 9>;
5218 cpu6_alert0: trip-point0 {
5219 temperature = <90000>;
5220 hysteresis = <2000>;
5224 cpu6_alert1: trip-point1 {
5225 temperature = <95000>;
5226 hysteresis = <2000>;
5230 cpu6_crit: cpu_crit {
5231 temperature = <110000>;
5232 hysteresis = <1000>;
5239 trip = <&cpu6_alert0>;
5240 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5241 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5242 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5243 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5246 trip = <&cpu6_alert1>;
5247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5249 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5250 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5256 polling-delay-passive = <250>;
5257 polling-delay = <1000>;
5259 thermal-sensors = <&tsens0 10>;
5262 cpu7_alert0: trip-point0 {
5263 temperature = <90000>;
5264 hysteresis = <2000>;
5268 cpu7_alert1: trip-point1 {
5269 temperature = <95000>;
5270 hysteresis = <2000>;
5274 cpu7_crit: cpu_crit {
5275 temperature = <110000>;
5276 hysteresis = <1000>;
5283 trip = <&cpu7_alert0>;
5284 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5285 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5286 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5287 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5290 trip = <&cpu7_alert1>;
5291 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5292 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5293 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5294 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5300 polling-delay-passive = <250>;
5301 polling-delay = <1000>;
5303 thermal-sensors = <&tsens0 0>;
5306 aoss0_alert0: trip-point0 {
5307 temperature = <90000>;
5308 hysteresis = <2000>;
5315 polling-delay-passive = <250>;
5316 polling-delay = <1000>;
5318 thermal-sensors = <&tsens0 5>;
5321 cluster0_alert0: trip-point0 {
5322 temperature = <90000>;
5323 hysteresis = <2000>;
5326 cluster0_crit: cluster0_crit {
5327 temperature = <110000>;
5328 hysteresis = <2000>;
5335 polling-delay-passive = <250>;
5336 polling-delay = <1000>;
5338 thermal-sensors = <&tsens0 6>;
5341 cluster1_alert0: trip-point0 {
5342 temperature = <90000>;
5343 hysteresis = <2000>;
5346 cluster1_crit: cluster1_crit {
5347 temperature = <110000>;
5348 hysteresis = <2000>;
5355 polling-delay-passive = <250>;
5356 polling-delay = <1000>;
5358 thermal-sensors = <&tsens0 11>;
5361 gpu1_alert0: trip-point0 {
5362 temperature = <90000>;
5363 hysteresis = <2000>;
5369 gpu-thermal-bottom {
5370 polling-delay-passive = <250>;
5371 polling-delay = <1000>;
5373 thermal-sensors = <&tsens0 12>;
5376 gpu2_alert0: trip-point0 {
5377 temperature = <90000>;
5378 hysteresis = <2000>;
5385 polling-delay-passive = <250>;
5386 polling-delay = <1000>;
5388 thermal-sensors = <&tsens1 0>;
5391 aoss1_alert0: trip-point0 {
5392 temperature = <90000>;
5393 hysteresis = <2000>;
5400 polling-delay-passive = <250>;
5401 polling-delay = <1000>;
5403 thermal-sensors = <&tsens1 1>;
5406 q6_modem_alert0: trip-point0 {
5407 temperature = <90000>;
5408 hysteresis = <2000>;
5415 polling-delay-passive = <250>;
5416 polling-delay = <1000>;
5418 thermal-sensors = <&tsens1 2>;
5421 mem_alert0: trip-point0 {
5422 temperature = <90000>;
5423 hysteresis = <2000>;
5430 polling-delay-passive = <250>;
5431 polling-delay = <1000>;
5433 thermal-sensors = <&tsens1 3>;
5436 wlan_alert0: trip-point0 {
5437 temperature = <90000>;
5438 hysteresis = <2000>;
5445 polling-delay-passive = <250>;
5446 polling-delay = <1000>;
5448 thermal-sensors = <&tsens1 4>;
5451 q6_hvx_alert0: trip-point0 {
5452 temperature = <90000>;
5453 hysteresis = <2000>;
5460 polling-delay-passive = <250>;
5461 polling-delay = <1000>;
5463 thermal-sensors = <&tsens1 5>;
5466 camera_alert0: trip-point0 {
5467 temperature = <90000>;
5468 hysteresis = <2000>;
5475 polling-delay-passive = <250>;
5476 polling-delay = <1000>;
5478 thermal-sensors = <&tsens1 6>;
5481 video_alert0: trip-point0 {
5482 temperature = <90000>;
5483 hysteresis = <2000>;
5490 polling-delay-passive = <250>;
5491 polling-delay = <1000>;
5493 thermal-sensors = <&tsens1 7>;
5496 modem_alert0: trip-point0 {
5497 temperature = <90000>;
5498 hysteresis = <2000>;