arch/arm64/boot/dts/qcom/sdm660.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2018, Craig Tatlor.
   4  * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
   9
  10 / {
  11         interrupt-parent = <&intc>;
  12
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         chosen { };
  17
  18         clocks {
  19                 xo_board: xo_board {
  20                         compatible = "fixed-clock";
  21                         #clock-cells = <0>;
  22                         clock-frequency = <19200000>;
  23                         clock-output-names = "xo_board";
  24                 };
  25
  26                 sleep_clk: sleep_clk {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <32764>;
  30                         clock-output-names = "sleep_clk";
  31                 };
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 CPU0: cpu@100 {
  39                         device_type = "cpu";
  40                         compatible = "qcom,kryo260";
  41                         reg = <0x0 0x100>;
  42                         enable-method = "psci";
  43                         capacity-dmips-mhz = <1024>;
  44                         next-level-cache = <&L2_1>;
  45                         L2_1: l2-cache {
  46                                 compatible = "cache";
  47                                 cache-level = <2>;
  48                         };
  49                         L1_I_100: l1-icache {
  50                                 compatible = "cache";
  51                         };
  52                         L1_D_100: l1-dcache {
  53                                 compatible = "cache";
  54                         };
  55                 };
  56
  57                 CPU1: cpu@101 {
  58                         device_type = "cpu";
  59                         compatible = "qcom,kryo260";
  60                         reg = <0x0 0x101>;
  61                         enable-method = "psci";
  62                         capacity-dmips-mhz = <1024>;
  63                         next-level-cache = <&L2_1>;
  64                         L1_I_101: l1-icache {
  65                                 compatible = "cache";
  66                         };
  67                         L1_D_101: l1-dcache {
  68                                 compatible = "cache";
  69                         };
  70                 };
  71
  72                 CPU2: cpu@102 {
  73                         device_type = "cpu";
  74                         compatible = "qcom,kryo260";
  75                         reg = <0x0 0x102>;
  76                         enable-method = "psci";
  77                         capacity-dmips-mhz = <1024>;
  78                         next-level-cache = <&L2_1>;
  79                         L1_I_102: l1-icache {
  80                                 compatible = "cache";
  81                         };
  82                         L1_D_102: l1-dcache {
  83                                 compatible = "cache";
  84                         };
  85                 };
  86
  87                 CPU3: cpu@103 {
  88                         device_type = "cpu";
  89                         compatible = "qcom,kryo260";
  90                         reg = <0x0 0x103>;
  91                         enable-method = "psci";
  92                         capacity-dmips-mhz = <1024>;
  93                         next-level-cache = <&L2_1>;
  94                         L1_I_103: l1-icache {
  95                                 compatible = "cache";
  96                         };
  97                         L1_D_103: l1-dcache {
  98                                 compatible = "cache";
  99                         };
 100                 };
 101
 102                 CPU4: cpu@0 {
 103                         device_type = "cpu";
 104                         compatible = "qcom,kryo260";
 105                         reg = <0x0 0x0>;
 106                         enable-method = "psci";
 107                         capacity-dmips-mhz = <640>;
 108                         next-level-cache = <&L2_0>;
 109                         L2_0: l2-cache {
 110                                 compatible = "cache";
 111                                 cache-level = <2>;
 112                         };
 113                         L1_I_0: l1-icache {
 114                                 compatible = "cache";
 115                         };
 116                         L1_D_0: l1-dcache {
 117                                 compatible = "cache";
 118                         };
 119                 };
 120
 121                 CPU5: cpu@1 {
 122                         device_type = "cpu";
 123                         compatible = "qcom,kryo260";
 124                         reg = <0x0 0x1>;
 125                         enable-method = "psci";
 126                         capacity-dmips-mhz = <640>;
 127                         next-level-cache = <&L2_0>;
 128                         L1_I_1: l1-icache {
 129                                 compatible = "cache";
 130                         };
 131                         L1_D_1: l1-dcache {
 132                                 compatible = "cache";
 133                         };
 134                 };
 135
 136                 CPU6: cpu@2 {
 137                         device_type = "cpu";
 138                         compatible = "qcom,kryo260";
 139                         reg = <0x0 0x2>;
 140                         enable-method = "psci";
 141                         capacity-dmips-mhz = <640>;
 142                         next-level-cache = <&L2_0>;
 143                         L1_I_2: l1-icache {
 144                                 compatible = "cache";
 145                         };
 146                         L1_D_2: l1-dcache {
 147                                 compatible = "cache";
 148                         };
 149                 };
 150
 151                 CPU7: cpu@3 {
 152                         device_type = "cpu";
 153                         compatible = "qcom,kryo260";
 154                         reg = <0x0 0x3>;
 155                         enable-method = "psci";
 156                         capacity-dmips-mhz = <640>;
 157                         next-level-cache = <&L2_0>;
 158                         L1_I_3: l1-icache {
 159                                 compatible = "cache";
 160                         };
 161                         L1_D_3: l1-dcache {
 162                                 compatible = "cache";
 163                         };
 164                 };
 165
 166                 cpu-map {
 167                         cluster0 {
 168                                 core0 {
 169                                         cpu = <&CPU4>;
 170                                 };
 171
 172                                 core1 {
 173                                         cpu = <&CPU5>;
 174                                 };
 175
 176                                 core2 {
 177                                         cpu = <&CPU6>;
 178                                 };
 179
 180                                 core3 {
 181                                         cpu = <&CPU7>;
 182                                 };
 183                         };
 184
 185                         cluster1 {
 186                                 core0 {
 187                                         cpu = <&CPU0>;
 188                                 };
 189
 190                                 core1 {
 191                                         cpu = <&CPU1>;
 192                                 };
 193
 194                                 core2 {
 195                                         cpu = <&CPU2>;
 196                                 };
 197
 198                                 core3 {
 199                                         cpu = <&CPU3>;
 200                                 };
 201                         };
 202                 };
 203         };
 204
 205         firmware {
 206                 scm {
 207                         compatible = "qcom,scm";
 208                 };
 209         };
 210
 211         memory {
 212                 device_type = "memory";
 213                 /* We expect the bootloader to fill in the reg */
 214                 reg = <0 0 0 0>;
 215         };
 216
 217         psci {
 218                 compatible = "arm,psci-1.0";
 219                 method = "smc";
 220         };
 221
 222         timer {
 223                 compatible = "arm,armv8-timer";
 224                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 225                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 226                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 227                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 228         };
 229
 230         soc: soc {
 231                 #address-cells = <1>;
 232                 #size-cells = <1>;
 233                 ranges = <0 0 0 0xffffffff>;
 234                 compatible = "simple-bus";
 235
 236                 gcc: clock-controller@100000 {
 237                         compatible = "qcom,gcc-sdm660";
 238                         #clock-cells = <1>;
 239                         #reset-cells = <1>;
 240                         #power-domain-cells = <1>;
 241                         reg = <0x00100000 0x94000>;
 242                 };
 243
 244                 tlmm: pinctrl@3100000 {
 245                         compatible = "qcom,sdm660-pinctrl";
 246                         reg = <0x03100000 0x400000>,
 247                               <0x03500000 0x400000>,
 248                               <0x03900000 0x400000>;
 249                         reg-names = "south", "center", "north";
 250                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 251                         gpio-controller;
 252                         gpio-ranges = <&tlmm 0 0 114>;
 253                         #gpio-cells = <2>;
 254                         interrupt-controller;
 255                         #interrupt-cells = <2>;
 256
 257                         uart_console_active: uart_console_active {
 258                                 pinmux {
 259                                         pins = "gpio4", "gpio5";
 260                                         function = "blsp_uart2";
 261                                 };
 262
 263                                 pinconf {
 264                                         pins = "gpio4", "gpio5";
 265                                         drive-strength = <2>;
 266                                         bias-disable;
 267                                 };
 268                         };
 269                 };
 270
 271                 spmi_bus: spmi@800f000 {
 272                         compatible = "qcom,spmi-pmic-arb";
 273                         reg = <0x0800f000 0x1000>,
 274                               <0x08400000 0x1000000>,
 275                               <0x09400000 0x1000000>,
 276                               <0x0a400000 0x220000>,
 277                               <0x0800a000 0x3000>;
 278                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 279                         interrupt-names = "periph_irq";
 280                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 281                         qcom,ee = <0>;
 282                         qcom,channel = <0>;
 283                         #address-cells = <2>;
 284                         #size-cells = <0>;
 285                         interrupt-controller;
 286                         #interrupt-cells = <4>;
 287                         cell-index = <0>;
 288                 };
 289
 290                 blsp1_uart2: serial@c170000 {
 291                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 292                         reg = <0x0c170000 0x1000>;
 293                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 295                                  <&gcc GCC_BLSP1_AHB_CLK>;
 296                         clock-names = "core", "iface";
 297                         status = "disabled";
 298                 };
 299
 300                 timer@17920000 {
 301                         #address-cells = <1>;
 302                         #size-cells = <1>;
 303                         ranges;
 304                         compatible = "arm,armv7-timer-mem";
 305                         reg = <0x17920000 0x1000>;
 306
 307                         frame@17921000 {
 308                                 frame-number = <0>;
 309                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 310                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 311                                 reg = <0x17921000 0x1000>,
 312                                       <0x17922000 0x1000>;
 313                         };
 314
 315                         frame@17923000 {
 316                                 frame-number = <1>;
 317                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 318                                 reg = <0x17923000 0x1000>;
 319                                 status = "disabled";
 320                         };
 321
 322                         frame@17924000 {
 323                                 frame-number = <2>;
 324                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 325                                 reg = <0x17924000 0x1000>;
 326                                 status = "disabled";
 327                         };
 328
 329                         frame@17925000 {
 330                                 frame-number = <3>;
 331                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 332                                 reg = <0x17925000 0x1000>;
 333                                 status = "disabled";
 334                         };
 335
 336                         frame@17926000 {
 337                                 frame-number = <4>;
 338                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 339                                 reg = <0x17926000 0x1000>;
 340                                 status = "disabled";
 341                         };
 342
 343                         frame@17927000 {
 344                                 frame-number = <5>;
 345                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 346                                 reg = <0x17927000 0x1000>;
 347                                 status = "disabled";
 348                         };
 349
 350                         frame@17928000 {
 351                                 frame-number = <6>;
 352                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 353                                 reg = <0x17928000 0x1000>;
 354                                 status = "disabled";
 355                         };
 356                 };
 357
 358                 intc: interrupt-controller@17a00000 {
 359                         compatible = "arm,gic-v3";
 360                         reg = <0x17a00000 0x10000>,
 361                               <0x17b00000 0x100000>;
 362                         #interrupt-cells = <3>;
 363                         #address-cells = <1>;
 364                         #size-cells = <1>;
 365                         ranges;
 366                         interrupt-controller;
 367                         #redistributor-regions = <1>;
 368                         redistributor-stride = <0x0 0x20000>;
 369                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 370                 };
 371         };
 372 };