1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018, Craig Tatlor.
4 * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
5 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
6 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
7 * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
10 #include "sdm630.dtsi"
13 compatible = "qcom,adreno-512.0", "qcom,adreno";
14 operating-points-v2 = <&gpu_sdm660_opp_table>;
16 gpu_sdm660_opp_table: opp-table {
17 compatible = "operating-points-v2";
20 * 775MHz is only available on the highest speed bin
21 * Though it cannot be used for now due to interconnect
22 * framework not supporting multiple frequencies
23 * at the same opp-level
26 opp-hz = /bits/ 64 <750000000>;
27 opp-level = <RPM_SMD_LEVEL_TURBO>;
28 opp-peak-kBps = <5412000>;
29 opp-supported-hw = <0xCHECKME>;
32 * These OPPs are correct, but we are lacking support for the
33 * GPU regulator. Hence, disable them for now to prevent the
34 * platform from hanging on high graphics loads.
37 opp-hz = /bits/ 64 <700000000>;
38 opp-level = <RPM_SMD_LEVEL_TURBO>;
39 opp-peak-kBps = <5184000>;
40 opp-supported-hw = <0xFF>;
44 opp-hz = /bits/ 64 <647000000>;
45 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
46 opp-peak-kBps = <4068000>;
47 opp-supported-hw = <0xFF>;
51 opp-hz = /bits/ 64 <588000000>;
52 opp-level = <RPM_SMD_LEVEL_NOM>;
53 opp-peak-kBps = <3072000>;
54 opp-supported-hw = <0xFF>;
58 opp-hz = /bits/ 64 <465000000>;
59 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
60 opp-peak-kBps = <2724000>;
61 opp-supported-hw = <0xFF>;
65 opp-hz = /bits/ 64 <370000000>;
66 opp-level = <RPM_SMD_LEVEL_SVS>;
67 opp-peak-kBps = <2188000>;
68 opp-supported-hw = <0xFF>;
73 opp-hz = /bits/ 64 <266000000>;
74 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
75 opp-peak-kBps = <1648000>;
76 opp-supported-hw = <0xFF>;
80 opp-hz = /bits/ 64 <160000000>;
81 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
82 opp-peak-kBps = <1200000>;
83 opp-supported-hw = <0xFF>;
89 compatible = "qcom,kryo260";
90 capacity-dmips-mhz = <1024>;
91 /delete-property/ operating-points-v2;
95 compatible = "qcom,kryo260";
96 capacity-dmips-mhz = <1024>;
97 /delete-property/ operating-points-v2;
101 compatible = "qcom,kryo260";
102 capacity-dmips-mhz = <1024>;
103 /delete-property/ operating-points-v2;
107 compatible = "qcom,kryo260";
108 capacity-dmips-mhz = <1024>;
109 /delete-property/ operating-points-v2;
113 compatible = "qcom,kryo260";
114 capacity-dmips-mhz = <640>;
115 /delete-property/ operating-points-v2;
119 compatible = "qcom,kryo260";
120 capacity-dmips-mhz = <640>;
121 /delete-property/ operating-points-v2;
125 compatible = "qcom,kryo260";
126 capacity-dmips-mhz = <640>;
127 /delete-property/ operating-points-v2;
131 compatible = "qcom,kryo260";
132 capacity-dmips-mhz = <640>;
133 /delete-property/ operating-points-v2;
137 compatible = "qcom,gcc-sdm660";
141 compatible = "qcom,gpucc-sdm660";
148 mdp5_intf2_out: endpoint {
149 remote-endpoint = <&dsi1_in>;
157 compatible = "qcom,mdss-dsi-ctrl";
158 reg = <0x0c996000 0x400>;
159 reg-names = "dsi_ctrl";
161 /* DSI1 shares the OPP table with DSI0 */
162 operating-points-v2 = <&dsi_opp_table>;
163 power-domains = <&rpmpd SDM660_VDDCX>;
165 interrupt-parent = <&mdss>;
166 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
168 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
169 <&mmcc PCLK1_CLK_SRC>;
170 assigned-clock-parents = <&dsi1_phy 0>,
173 clocks = <&mmcc MDSS_MDP_CLK>,
174 <&mmcc MDSS_BYTE1_CLK>,
175 <&mmcc MDSS_BYTE1_INTF_CLK>,
176 <&mmcc MNOC_AHB_CLK>,
177 <&mmcc MDSS_AHB_CLK>,
178 <&mmcc MDSS_AXI_CLK>,
179 <&mmcc MISC_AHB_CLK>,
180 <&mmcc MDSS_PCLK1_CLK>,
181 <&mmcc MDSS_ESC1_CLK>;
182 clock-names = "mdp_core",
196 #address-cells = <1>;
202 remote-endpoint = <&mdp5_intf2_out>;
214 dsi1_phy: dsi-phy@c996400 {
215 compatible = "qcom,dsi-phy-14nm-660";
216 reg = <0x0c996400 0x100>,
219 reg-names = "dsi_phy",
226 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
227 clock-names = "iface", "ref";
232 compatible = "qcom,mmcc-sdm660";
233 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
235 <&gcc GCC_MMSS_GPLL0_CLK>,
236 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
246 compatible = "qcom,sdm660-pinctrl";
250 #qcom,sensors = <14>;