arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/mailbox/qcom-ipcc.h>
  12 #include <dt-bindings/power/qcom-aoss-qmp.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         interrupt-parent = <&intc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         clocks {
  26                 xo_board: xo-board {
  27                         compatible = "fixed-clock";
  28                         clock-frequency = <76800000>;
  29                         #clock-cells = <0>;
  30                 };
  31
  32                 sleep_clk: sleep-clk {
  33                         compatible = "fixed-clock";
  34                         clock-frequency = <32000>;
  35                         #clock-cells = <0>;
  36                 };
  37         };
  38
  39         reserved-memory {
  40                 #address-cells = <2>;
  41                 #size-cells = <2>;
  42                 ranges;
  43
  44                 aop_mem: memory@80800000 {
  45                         reg = <0x0 0x80800000 0x0 0x60000>;
  46                         no-map;
  47                 };
  48
  49                 aop_cmd_db_mem: memory@80860000 {
  50                         reg = <0x0 0x80860000 0x0 0x20000>;
  51                         compatible = "qcom,cmd-db";
  52                         no-map;
  53                 };
  54
  55                 cpucp_mem: memory@80b00000 {
  56                         no-map;
  57                         reg = <0x0 0x80b00000 0x0 0x100000>;
  58                 };
  59         };
  60
  61         cpus {
  62                 #address-cells = <2>;
  63                 #size-cells = <0>;
  64
  65                 CPU0: cpu@0 {
  66                         device_type = "cpu";
  67                         compatible = "arm,kryo";
  68                         reg = <0x0 0x0>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  71                                            &LITTLE_CPU_SLEEP_1
  72                                            &CLUSTER_SLEEP_0>;
  73                         next-level-cache = <&L2_0>;
  74                         qcom,freq-domain = <&cpufreq_hw 0>;
  75                         #cooling-cells = <2>;
  76                         L2_0: l2-cache {
  77                                 compatible = "cache";
  78                                 next-level-cache = <&L3_0>;
  79                                 L3_0: l3-cache {
  80                                         compatible = "cache";
  81                                 };
  82                         };
  83                 };
  84
  85                 CPU1: cpu@100 {
  86                         device_type = "cpu";
  87                         compatible = "arm,kryo";
  88                         reg = <0x0 0x100>;
  89                         enable-method = "psci";
  90                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  91                                            &LITTLE_CPU_SLEEP_1
  92                                            &CLUSTER_SLEEP_0>;
  93                         next-level-cache = <&L2_100>;
  94                         qcom,freq-domain = <&cpufreq_hw 0>;
  95                         #cooling-cells = <2>;
  96                         L2_100: l2-cache {
  97                                 compatible = "cache";
  98                                 next-level-cache = <&L3_0>;
  99                         };
 100                 };
 101
 102                 CPU2: cpu@200 {
 103                         device_type = "cpu";
 104                         compatible = "arm,kryo";
 105                         reg = <0x0 0x200>;
 106                         enable-method = "psci";
 107                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 108                                            &LITTLE_CPU_SLEEP_1
 109                                            &CLUSTER_SLEEP_0>;
 110                         next-level-cache = <&L2_200>;
 111                         qcom,freq-domain = <&cpufreq_hw 0>;
 112                         #cooling-cells = <2>;
 113                         L2_200: l2-cache {
 114                                 compatible = "cache";
 115                                 next-level-cache = <&L3_0>;
 116                         };
 117                 };
 118
 119                 CPU3: cpu@300 {
 120                         device_type = "cpu";
 121                         compatible = "arm,kryo";
 122                         reg = <0x0 0x300>;
 123                         enable-method = "psci";
 124                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 125                                            &LITTLE_CPU_SLEEP_1
 126                                            &CLUSTER_SLEEP_0>;
 127                         next-level-cache = <&L2_300>;
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         #cooling-cells = <2>;
 130                         L2_300: l2-cache {
 131                                 compatible = "cache";
 132                                 next-level-cache = <&L3_0>;
 133                         };
 134                 };
 135
 136                 CPU4: cpu@400 {
 137                         device_type = "cpu";
 138                         compatible = "arm,kryo";
 139                         reg = <0x0 0x400>;
 140                         enable-method = "psci";
 141                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 142                                            &BIG_CPU_SLEEP_1
 143                                            &CLUSTER_SLEEP_0>;
 144                         next-level-cache = <&L2_400>;
 145                         qcom,freq-domain = <&cpufreq_hw 1>;
 146                         #cooling-cells = <2>;
 147                         L2_400: l2-cache {
 148                                 compatible = "cache";
 149                                 next-level-cache = <&L3_0>;
 150                         };
 151                 };
 152
 153                 CPU5: cpu@500 {
 154                         device_type = "cpu";
 155                         compatible = "arm,kryo";
 156                         reg = <0x0 0x500>;
 157                         enable-method = "psci";
 158                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 159                                            &BIG_CPU_SLEEP_1
 160                                            &CLUSTER_SLEEP_0>;
 161                         next-level-cache = <&L2_500>;
 162                         qcom,freq-domain = <&cpufreq_hw 1>;
 163                         #cooling-cells = <2>;
 164                         L2_500: l2-cache {
 165                                 compatible = "cache";
 166                                 next-level-cache = <&L3_0>;
 167                         };
 168                 };
 169
 170                 CPU6: cpu@600 {
 171                         device_type = "cpu";
 172                         compatible = "arm,kryo";
 173                         reg = <0x0 0x600>;
 174                         enable-method = "psci";
 175                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 176                                            &BIG_CPU_SLEEP_1
 177                                            &CLUSTER_SLEEP_0>;
 178                         next-level-cache = <&L2_600>;
 179                         qcom,freq-domain = <&cpufreq_hw 1>;
 180                         #cooling-cells = <2>;
 181                         L2_600: l2-cache {
 182                                 compatible = "cache";
 183                                 next-level-cache = <&L3_0>;
 184                         };
 185                 };
 186
 187                 CPU7: cpu@700 {
 188                         device_type = "cpu";
 189                         compatible = "arm,kryo";
 190                         reg = <0x0 0x700>;
 191                         enable-method = "psci";
 192                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 193                                            &BIG_CPU_SLEEP_1
 194                                            &CLUSTER_SLEEP_0>;
 195                         next-level-cache = <&L2_700>;
 196                         qcom,freq-domain = <&cpufreq_hw 1>;
 197                         #cooling-cells = <2>;
 198                         L2_700: l2-cache {
 199                                 compatible = "cache";
 200                                 next-level-cache = <&L3_0>;
 201                         };
 202                 };
 203
 204                 idle-states {
 205                         entry-method = "psci";
 206
 207                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 208                                 compatible = "arm,idle-state";
 209                                 idle-state-name = "little-power-down";
 210                                 arm,psci-suspend-param = <0x40000003>;
 211                                 entry-latency-us = <549>;
 212                                 exit-latency-us = <901>;
 213                                 min-residency-us = <1774>;
 214                                 local-timer-stop;
 215                         };
 216
 217                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 218                                 compatible = "arm,idle-state";
 219                                 idle-state-name = "little-rail-power-down";
 220                                 arm,psci-suspend-param = <0x40000004>;
 221                                 entry-latency-us = <702>;
 222                                 exit-latency-us = <915>;
 223                                 min-residency-us = <4001>;
 224                                 local-timer-stop;
 225                         };
 226
 227                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 228                                 compatible = "arm,idle-state";
 229                                 idle-state-name = "big-power-down";
 230                                 arm,psci-suspend-param = <0x40000003>;
 231                                 entry-latency-us = <523>;
 232                                 exit-latency-us = <1244>;
 233                                 min-residency-us = <2207>;
 234                                 local-timer-stop;
 235                         };
 236
 237                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 238                                 compatible = "arm,idle-state";
 239                                 idle-state-name = "big-rail-power-down";
 240                                 arm,psci-suspend-param = <0x40000004>;
 241                                 entry-latency-us = <526>;
 242                                 exit-latency-us = <1854>;
 243                                 min-residency-us = <5555>;
 244                                 local-timer-stop;
 245                         };
 246
 247                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 248                                 compatible = "arm,idle-state";
 249                                 idle-state-name = "cluster-power-down";
 250                                 arm,psci-suspend-param = <0x40003444>;
 251                                 entry-latency-us = <3263>;
 252                                 exit-latency-us = <6562>;
 253                                 min-residency-us = <9926>;
 254                                 local-timer-stop;
 255                         };
 256                 };
 257         };
 258
 259         memory@80000000 {
 260                 device_type = "memory";
 261                 /* We expect the bootloader to fill in the size */
 262                 reg = <0 0x80000000 0 0>;
 263         };
 264
 265         firmware {
 266                 scm {
 267                         compatible = "qcom,scm-sc7280", "qcom,scm";
 268                 };
 269         };
 270
 271         pmu {
 272                 compatible = "arm,armv8-pmuv3";
 273                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 274         };
 275
 276         psci {
 277                 compatible = "arm,psci-1.0";
 278                 method = "smc";
 279         };
 280
 281         soc: soc@0 {
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges = <0 0 0 0 0x10 0>;
 285                 dma-ranges = <0 0 0 0 0x10 0>;
 286                 compatible = "simple-bus";
 287
 288                 gcc: clock-controller@100000 {
 289                         compatible = "qcom,gcc-sc7280";
 290                         reg = <0 0x00100000 0 0x1f0000>;
 291                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 292                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 293                                  <0>, <0>, <0>, <0>, <0>, <0>;
 294                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 295                                       "pcie_0_pipe_clk", "pcie_1_pipe-clk",
 296                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 297                                       "ufs_phy_tx_symbol_0_clk",
 298                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 299                         #clock-cells = <1>;
 300                         #reset-cells = <1>;
 301                         #power-domain-cells = <1>;
 302                 };
 303
 304                 ipcc: mailbox@408000 {
 305                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 306                         reg = <0 0x00408000 0 0x1000>;
 307                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <3>;
 310                         #mbox-cells = <2>;
 311                 };
 312
 313                 qupv3_id_0: geniqup@9c0000 {
 314                         compatible = "qcom,geni-se-qup";
 315                         reg = <0 0x009c0000 0 0x2000>;
 316                         clock-names = "m-ahb", "s-ahb";
 317                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 318                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 319                         #address-cells = <2>;
 320                         #size-cells = <2>;
 321                         ranges;
 322                         status = "disabled";
 323
 324                         uart5: serial@994000 {
 325                                 compatible = "qcom,geni-debug-uart";
 326                                 reg = <0 0x00994000 0 0x4000>;
 327                                 clock-names = "se";
 328                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 329                                 pinctrl-names = "default";
 330                                 pinctrl-0 = <&qup_uart5_default>;
 331                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 332                                 status = "disabled";
 333                         };
 334                 };
 335
 336                 stm@6002000 {
 337                         compatible = "arm,coresight-stm", "arm,primecell";
 338                         reg = <0 0x06002000 0 0x1000>,
 339                               <0 0x16280000 0 0x180000>;
 340                         reg-names = "stm-base", "stm-stimulus-base";
 341
 342                         clocks = <&aoss_qmp>;
 343                         clock-names = "apb_pclk";
 344
 345                         out-ports {
 346                                 port {
 347                                         stm_out: endpoint {
 348                                                 remote-endpoint = <&funnel0_in7>;
 349                                         };
 350                                 };
 351                         };
 352                 };
 353
 354                 funnel@6041000 {
 355                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 356                         reg = <0 0x06041000 0 0x1000>;
 357
 358                         clocks = <&aoss_qmp>;
 359                         clock-names = "apb_pclk";
 360
 361                         out-ports {
 362                                 port {
 363                                         funnel0_out: endpoint {
 364                                                 remote-endpoint = <&merge_funnel_in0>;
 365                                         };
 366                                 };
 367                         };
 368
 369                         in-ports {
 370                                 #address-cells = <1>;
 371                                 #size-cells = <0>;
 372
 373                                 port@7 {
 374                                         reg = <7>;
 375                                         funnel0_in7: endpoint {
 376                                                 remote-endpoint = <&stm_out>;
 377                                         };
 378                                 };
 379                         };
 380                 };
 381
 382                 funnel@6042000 {
 383                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 384                         reg = <0 0x06042000 0 0x1000>;
 385
 386                         clocks = <&aoss_qmp>;
 387                         clock-names = "apb_pclk";
 388
 389                         out-ports {
 390                                 port {
 391                                         funnel1_out: endpoint {
 392                                                 remote-endpoint = <&merge_funnel_in1>;
 393                                         };
 394                                 };
 395                         };
 396
 397                         in-ports {
 398                                 #address-cells = <1>;
 399                                 #size-cells = <0>;
 400
 401                                 port@4 {
 402                                         reg = <4>;
 403                                         funnel1_in4: endpoint {
 404                                                 remote-endpoint = <&apss_merge_funnel_out>;
 405                                         };
 406                                 };
 407                         };
 408                 };
 409
 410                 funnel@6045000 {
 411                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 412                         reg = <0 0x06045000 0 0x1000>;
 413
 414                         clocks = <&aoss_qmp>;
 415                         clock-names = "apb_pclk";
 416
 417                         out-ports {
 418                                 port {
 419                                         merge_funnel_out: endpoint {
 420                                                 remote-endpoint = <&swao_funnel_in>;
 421                                         };
 422                                 };
 423                         };
 424
 425                         in-ports {
 426                                 #address-cells = <1>;
 427                                 #size-cells = <0>;
 428
 429                                 port@0 {
 430                                         reg = <0>;
 431                                         merge_funnel_in0: endpoint {
 432                                                 remote-endpoint = <&funnel0_out>;
 433                                         };
 434                                 };
 435
 436                                 port@1 {
 437                                         reg = <1>;
 438                                         merge_funnel_in1: endpoint {
 439                                                 remote-endpoint = <&funnel1_out>;
 440                                         };
 441                                 };
 442                         };
 443                 };
 444
 445                 replicator@6046000 {
 446                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 447                         reg = <0 0x06046000 0 0x1000>;
 448
 449                         clocks = <&aoss_qmp>;
 450                         clock-names = "apb_pclk";
 451
 452                         out-ports {
 453                                 port {
 454                                         replicator_out: endpoint {
 455                                                 remote-endpoint = <&etr_in>;
 456                                         };
 457                                 };
 458                         };
 459
 460                         in-ports {
 461                                 port {
 462                                         replicator_in: endpoint {
 463                                                 remote-endpoint = <&swao_replicator_out>;
 464                                         };
 465                                 };
 466                         };
 467                 };
 468
 469                 etr@6048000 {
 470                         compatible = "arm,coresight-tmc", "arm,primecell";
 471                         reg = <0 0x06048000 0 0x1000>;
 472                         iommus = <&apps_smmu 0x04c0 0>;
 473
 474                         clocks = <&aoss_qmp>;
 475                         clock-names = "apb_pclk";
 476                         arm,scatter-gather;
 477
 478                         in-ports {
 479                                 port {
 480                                         etr_in: endpoint {
 481                                                 remote-endpoint = <&replicator_out>;
 482                                         };
 483                                 };
 484                         };
 485                 };
 486
 487                 funnel@6b04000 {
 488                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 489                         reg = <0 0x06b04000 0 0x1000>;
 490
 491                         clocks = <&aoss_qmp>;
 492                         clock-names = "apb_pclk";
 493
 494                         out-ports {
 495                                 port {
 496                                         swao_funnel_out: endpoint {
 497                                                 remote-endpoint = <&etf_in>;
 498                                         };
 499                                 };
 500                         };
 501
 502                         in-ports {
 503                                 #address-cells = <1>;
 504                                 #size-cells = <0>;
 505
 506                                 port@7 {
 507                                         reg = <7>;
 508                                         swao_funnel_in: endpoint {
 509                                                 remote-endpoint = <&merge_funnel_out>;
 510                                         };
 511                                 };
 512                         };
 513                 };
 514
 515                 etf@6b05000 {
 516                         compatible = "arm,coresight-tmc", "arm,primecell";
 517                         reg = <0 0x06b05000 0 0x1000>;
 518
 519                         clocks = <&aoss_qmp>;
 520                         clock-names = "apb_pclk";
 521
 522                         out-ports {
 523                                 port {
 524                                         etf_out: endpoint {
 525                                                 remote-endpoint = <&swao_replicator_in>;
 526                                         };
 527                                 };
 528                         };
 529
 530                         in-ports {
 531                                 port {
 532                                         etf_in: endpoint {
 533                                                 remote-endpoint = <&swao_funnel_out>;
 534                                         };
 535                                 };
 536                         };
 537                 };
 538
 539                 replicator@6b06000 {
 540                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 541                         reg = <0 0x06b06000 0 0x1000>;
 542
 543                         clocks = <&aoss_qmp>;
 544                         clock-names = "apb_pclk";
 545                         qcom,replicator-loses-context;
 546
 547                         out-ports {
 548                                 port {
 549                                         swao_replicator_out: endpoint {
 550                                                 remote-endpoint = <&replicator_in>;
 551                                         };
 552                                 };
 553                         };
 554
 555                         in-ports {
 556                                 port {
 557                                         swao_replicator_in: endpoint {
 558                                                 remote-endpoint = <&etf_out>;
 559                                         };
 560                                 };
 561                         };
 562                 };
 563
 564                 etm@7040000 {
 565                         compatible = "arm,coresight-etm4x", "arm,primecell";
 566                         reg = <0 0x07040000 0 0x1000>;
 567
 568                         cpu = <&CPU0>;
 569
 570                         clocks = <&aoss_qmp>;
 571                         clock-names = "apb_pclk";
 572                         arm,coresight-loses-context-with-cpu;
 573                         qcom,skip-power-up;
 574
 575                         out-ports {
 576                                 port {
 577                                         etm0_out: endpoint {
 578                                                 remote-endpoint = <&apss_funnel_in0>;
 579                                         };
 580                                 };
 581                         };
 582                 };
 583
 584                 etm@7140000 {
 585                         compatible = "arm,coresight-etm4x", "arm,primecell";
 586                         reg = <0 0x07140000 0 0x1000>;
 587
 588                         cpu = <&CPU1>;
 589
 590                         clocks = <&aoss_qmp>;
 591                         clock-names = "apb_pclk";
 592                         arm,coresight-loses-context-with-cpu;
 593                         qcom,skip-power-up;
 594
 595                         out-ports {
 596                                 port {
 597                                         etm1_out: endpoint {
 598                                                 remote-endpoint = <&apss_funnel_in1>;
 599                                         };
 600                                 };
 601                         };
 602                 };
 603
 604                 etm@7240000 {
 605                         compatible = "arm,coresight-etm4x", "arm,primecell";
 606                         reg = <0 0x07240000 0 0x1000>;
 607
 608                         cpu = <&CPU2>;
 609
 610                         clocks = <&aoss_qmp>;
 611                         clock-names = "apb_pclk";
 612                         arm,coresight-loses-context-with-cpu;
 613                         qcom,skip-power-up;
 614
 615                         out-ports {
 616                                 port {
 617                                         etm2_out: endpoint {
 618                                                 remote-endpoint = <&apss_funnel_in2>;
 619                                         };
 620                                 };
 621                         };
 622                 };
 623
 624                 etm@7340000 {
 625                         compatible = "arm,coresight-etm4x", "arm,primecell";
 626                         reg = <0 0x07340000 0 0x1000>;
 627
 628                         cpu = <&CPU3>;
 629
 630                         clocks = <&aoss_qmp>;
 631                         clock-names = "apb_pclk";
 632                         arm,coresight-loses-context-with-cpu;
 633                         qcom,skip-power-up;
 634
 635                         out-ports {
 636                                 port {
 637                                         etm3_out: endpoint {
 638                                                 remote-endpoint = <&apss_funnel_in3>;
 639                                         };
 640                                 };
 641                         };
 642                 };
 643
 644                 etm@7440000 {
 645                         compatible = "arm,coresight-etm4x", "arm,primecell";
 646                         reg = <0 0x07440000 0 0x1000>;
 647
 648                         cpu = <&CPU4>;
 649
 650                         clocks = <&aoss_qmp>;
 651                         clock-names = "apb_pclk";
 652                         arm,coresight-loses-context-with-cpu;
 653                         qcom,skip-power-up;
 654
 655                         out-ports {
 656                                 port {
 657                                         etm4_out: endpoint {
 658                                                 remote-endpoint = <&apss_funnel_in4>;
 659                                         };
 660                                 };
 661                         };
 662                 };
 663
 664                 etm@7540000 {
 665                         compatible = "arm,coresight-etm4x", "arm,primecell";
 666                         reg = <0 0x07540000 0 0x1000>;
 667
 668                         cpu = <&CPU5>;
 669
 670                         clocks = <&aoss_qmp>;
 671                         clock-names = "apb_pclk";
 672                         arm,coresight-loses-context-with-cpu;
 673                         qcom,skip-power-up;
 674
 675                         out-ports {
 676                                 port {
 677                                         etm5_out: endpoint {
 678                                                 remote-endpoint = <&apss_funnel_in5>;
 679                                         };
 680                                 };
 681                         };
 682                 };
 683
 684                 etm@7640000 {
 685                         compatible = "arm,coresight-etm4x", "arm,primecell";
 686                         reg = <0 0x07640000 0 0x1000>;
 687
 688                         cpu = <&CPU6>;
 689
 690                         clocks = <&aoss_qmp>;
 691                         clock-names = "apb_pclk";
 692                         arm,coresight-loses-context-with-cpu;
 693                         qcom,skip-power-up;
 694
 695                         out-ports {
 696                                 port {
 697                                         etm6_out: endpoint {
 698                                                 remote-endpoint = <&apss_funnel_in6>;
 699                                         };
 700                                 };
 701                         };
 702                 };
 703
 704                 etm@7740000 {
 705                         compatible = "arm,coresight-etm4x", "arm,primecell";
 706                         reg = <0 0x07740000 0 0x1000>;
 707
 708                         cpu = <&CPU7>;
 709
 710                         clocks = <&aoss_qmp>;
 711                         clock-names = "apb_pclk";
 712                         arm,coresight-loses-context-with-cpu;
 713                         qcom,skip-power-up;
 714
 715                         out-ports {
 716                                 port {
 717                                         etm7_out: endpoint {
 718                                                 remote-endpoint = <&apss_funnel_in7>;
 719                                         };
 720                                 };
 721                         };
 722                 };
 723
 724                 funnel@7800000 { /* APSS Funnel */
 725                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 726                         reg = <0 0x07800000 0 0x1000>;
 727
 728                         clocks = <&aoss_qmp>;
 729                         clock-names = "apb_pclk";
 730
 731                         out-ports {
 732                                 port {
 733                                         apss_funnel_out: endpoint {
 734                                                 remote-endpoint = <&apss_merge_funnel_in>;
 735                                         };
 736                                 };
 737                         };
 738
 739                         in-ports {
 740                                 #address-cells = <1>;
 741                                 #size-cells = <0>;
 742
 743                                 port@0 {
 744                                         reg = <0>;
 745                                         apss_funnel_in0: endpoint {
 746                                                 remote-endpoint = <&etm0_out>;
 747                                         };
 748                                 };
 749
 750                                 port@1 {
 751                                         reg = <1>;
 752                                         apss_funnel_in1: endpoint {
 753                                                 remote-endpoint = <&etm1_out>;
 754                                         };
 755                                 };
 756
 757                                 port@2 {
 758                                         reg = <2>;
 759                                         apss_funnel_in2: endpoint {
 760                                                 remote-endpoint = <&etm2_out>;
 761                                         };
 762                                 };
 763
 764                                 port@3 {
 765                                         reg = <3>;
 766                                         apss_funnel_in3: endpoint {
 767                                                 remote-endpoint = <&etm3_out>;
 768                                         };
 769                                 };
 770
 771                                 port@4 {
 772                                         reg = <4>;
 773                                         apss_funnel_in4: endpoint {
 774                                                 remote-endpoint = <&etm4_out>;
 775                                         };
 776                                 };
 777
 778                                 port@5 {
 779                                         reg = <5>;
 780                                         apss_funnel_in5: endpoint {
 781                                                 remote-endpoint = <&etm5_out>;
 782                                         };
 783                                 };
 784
 785                                 port@6 {
 786                                         reg = <6>;
 787                                         apss_funnel_in6: endpoint {
 788                                                 remote-endpoint = <&etm6_out>;
 789                                         };
 790                                 };
 791
 792                                 port@7 {
 793                                         reg = <7>;
 794                                         apss_funnel_in7: endpoint {
 795                                                 remote-endpoint = <&etm7_out>;
 796                                         };
 797                                 };
 798                         };
 799                 };
 800
 801                 funnel@7810000 {
 802                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 803                         reg = <0 0x07810000 0 0x1000>;
 804
 805                         clocks = <&aoss_qmp>;
 806                         clock-names = "apb_pclk";
 807
 808                         out-ports {
 809                                 port {
 810                                         apss_merge_funnel_out: endpoint {
 811                                                 remote-endpoint = <&funnel1_in4>;
 812                                         };
 813                                 };
 814                         };
 815
 816                         in-ports {
 817                                 port {
 818                                         apss_merge_funnel_in: endpoint {
 819                                                 remote-endpoint = <&apss_funnel_out>;
 820                                         };
 821                                 };
 822                         };
 823                 };
 824
 825                 system-cache-controller@9200000 {
 826                         compatible = "qcom,sc7280-llcc";
 827                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
 828                         reg-names = "llcc_base", "llcc_broadcast_base";
 829                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 830                 };
 831
 832                 pdc: interrupt-controller@b220000 {
 833                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
 834                         reg = <0 0x0b220000 0 0x30000>;
 835                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
 836                                           <55 306 4>, <59 312 3>, <62 374 2>,
 837                                           <64 434 2>, <66 438 3>, <69 86 1>,
 838                                           <70 520 54>, <124 609 31>, <155 63 1>,
 839                                           <156 716 12>;
 840                         #interrupt-cells = <2>;
 841                         interrupt-parent = <&intc>;
 842                         interrupt-controller;
 843                 };
 844
 845                 tsens0: thermal-sensor@c263000 {
 846                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
 847                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
 848                                 <0 0x0c222000 0 0x1ff>; /* SROT */
 849                         #qcom,sensors = <15>;
 850                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
 851                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
 852                         interrupt-names = "uplow","critical";
 853                         #thermal-sensor-cells = <1>;
 854                 };
 855
 856                 tsens1: thermal-sensor@c265000 {
 857                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
 858                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
 859                                 <0 0x0c223000 0 0x1ff>; /* SROT */
 860                         #qcom,sensors = <12>;
 861                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
 862                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
 863                         interrupt-names = "uplow","critical";
 864                         #thermal-sensor-cells = <1>;
 865                 };
 866
 867                 aoss_qmp: power-controller@c300000 {
 868                         compatible = "qcom,sc7280-aoss-qmp";
 869                         reg = <0 0x0c300000 0 0x100000>;
 870                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
 871                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
 872                                                      IRQ_TYPE_EDGE_RISING>;
 873                         mboxes = <&ipcc IPCC_CLIENT_AOP
 874                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
 875
 876                         #clock-cells = <0>;
 877                         #power-domain-cells = <1>;
 878                 };
 879
 880                 spmi_bus: spmi@c440000 {
 881                         compatible = "qcom,spmi-pmic-arb";
 882                         reg = <0 0x0c440000 0 0x1100>,
 883                               <0 0x0c600000 0 0x2000000>,
 884                               <0 0x0e600000 0 0x100000>,
 885                               <0 0x0e700000 0 0xa0000>,
 886                               <0 0x0c40a000 0 0x26000>;
 887                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 888                         interrupt-names = "periph_irq";
 889                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
 890                         qcom,ee = <0>;
 891                         qcom,channel = <0>;
 892                         #address-cells = <1>;
 893                         #size-cells = <1>;
 894                         interrupt-controller;
 895                         #interrupt-cells = <4>;
 896                 };
 897
 898                 tlmm: pinctrl@f100000 {
 899                         compatible = "qcom,sc7280-pinctrl";
 900                         reg = <0 0x0f100000 0 0x300000>;
 901                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 902                         gpio-controller;
 903                         #gpio-cells = <2>;
 904                         interrupt-controller;
 905                         #interrupt-cells = <2>;
 906                         gpio-ranges = <&tlmm 0 0 175>;
 907                         wakeup-parent = <&pdc>;
 908
 909                         qup_uart5_default: qup-uart5-default {
 910                                 pins = "gpio46", "gpio47";
 911                                 function = "qup13";
 912                         };
 913                 };
 914
 915                 apps_smmu: iommu@15000000 {
 916                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
 917                         reg = <0 0x15000000 0 0x100000>;
 918                         #iommu-cells = <2>;
 919                         #global-interrupts = <1>;
 920                         dma-coherent;
 921                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 922                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 925                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 926                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 927                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 931                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 933                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 934                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 935                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 936                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 937                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 938                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 939                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 940                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 941                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 942                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 943                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 944                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 945                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 950                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 951                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 952                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 953                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 954                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 955                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 956                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 957                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 958                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 959                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 960                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 961                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 962                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 963                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
 964                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
 965                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
 966                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
 967                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
 968                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 969                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
 970                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 971                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 972                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 973                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 974                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 975                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 976                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 977                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 978                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 979                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 980                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 981                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 982                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 983                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 984                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 985                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 986                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 987                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 988                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 989                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 990                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 991                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 992                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 993                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 994                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 995                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 996                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 997                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 998                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 999                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1000                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1001                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1002                 };
1003
1004                 intc: interrupt-controller@17a00000 {
1005                         compatible = "arm,gic-v3";
1006                         #address-cells = <2>;
1007                         #size-cells = <2>;
1008                         ranges;
1009                         #interrupt-cells = <3>;
1010                         interrupt-controller;
1011                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
1012                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
1013                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1014
1015                         gic-its@17a40000 {
1016                                 compatible = "arm,gic-v3-its";
1017                                 msi-controller;
1018                                 #msi-cells = <1>;
1019                                 reg = <0 0x17a40000 0 0x20000>;
1020                                 status = "disabled";
1021                         };
1022                 };
1023
1024                 watchdog@17c10000 {
1025                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
1026                         reg = <0 0x17c10000 0 0x1000>;
1027                         clocks = <&sleep_clk>;
1028                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1029                 };
1030
1031                 timer@17c20000 {
1032                         #address-cells = <2>;
1033                         #size-cells = <2>;
1034                         ranges;
1035                         compatible = "arm,armv7-timer-mem";
1036                         reg = <0 0x17c20000 0 0x1000>;
1037
1038                         frame@17c21000 {
1039                                 frame-number = <0>;
1040                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1041                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1042                                 reg = <0 0x17c21000 0 0x1000>,
1043                                       <0 0x17c22000 0 0x1000>;
1044                         };
1045
1046                         frame@17c23000 {
1047                                 frame-number = <1>;
1048                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1049                                 reg = <0 0x17c23000 0 0x1000>;
1050                                 status = "disabled";
1051                         };
1052
1053                         frame@17c25000 {
1054                                 frame-number = <2>;
1055                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1056                                 reg = <0 0x17c25000 0 0x1000>;
1057                                 status = "disabled";
1058                         };
1059
1060                         frame@17c27000 {
1061                                 frame-number = <3>;
1062                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1063                                 reg = <0 0x17c27000 0 0x1000>;
1064                                 status = "disabled";
1065                         };
1066
1067                         frame@17c29000 {
1068                                 frame-number = <4>;
1069                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1070                                 reg = <0 0x17c29000 0 0x1000>;
1071                                 status = "disabled";
1072                         };
1073
1074                         frame@17c2b000 {
1075                                 frame-number = <5>;
1076                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1077                                 reg = <0 0x17c2b000 0 0x1000>;
1078                                 status = "disabled";
1079                         };
1080
1081                         frame@17c2d000 {
1082                                 frame-number = <6>;
1083                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1084                                 reg = <0 0x17c2d000 0 0x1000>;
1085                                 status = "disabled";
1086                         };
1087                 };
1088
1089                 apps_rsc: rsc@18200000 {
1090                         compatible = "qcom,rpmh-rsc";
1091                         reg = <0 0x18200000 0 0x10000>,
1092                               <0 0x18210000 0 0x10000>,
1093                               <0 0x18220000 0 0x10000>;
1094                         reg-names = "drv-0", "drv-1", "drv-2";
1095                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1096                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1097                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1098                         qcom,tcs-offset = <0xd00>;
1099                         qcom,drv-id = <2>;
1100                         qcom,tcs-config = <ACTIVE_TCS  2>,
1101                                           <SLEEP_TCS   3>,
1102                                           <WAKE_TCS    3>,
1103                                           <CONTROL_TCS 1>;
1104
1105                         rpmhpd: power-controller {
1106                                 compatible = "qcom,sc7280-rpmhpd";
1107                                 #power-domain-cells = <1>;
1108                                 operating-points-v2 = <&rpmhpd_opp_table>;
1109
1110                                 rpmhpd_opp_table: opp-table {
1111                                         compatible = "operating-points-v2";
1112
1113                                         rpmhpd_opp_ret: opp1 {
1114                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1115                                         };
1116
1117                                         rpmhpd_opp_low_svs: opp2 {
1118                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1119                                         };
1120
1121                                         rpmhpd_opp_svs: opp3 {
1122                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1123                                         };
1124
1125                                         rpmhpd_opp_svs_l1: opp4 {
1126                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1127                                         };
1128
1129                                         rpmhpd_opp_svs_l2: opp5 {
1130                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1131                                         };
1132
1133                                         rpmhpd_opp_nom: opp6 {
1134                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1135                                         };
1136
1137                                         rpmhpd_opp_nom_l1: opp7 {
1138                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1139                                         };
1140
1141                                         rpmhpd_opp_turbo: opp8 {
1142                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1143                                         };
1144
1145                                         rpmhpd_opp_turbo_l1: opp9 {
1146                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1147                                         };
1148                                 };
1149                         };
1150
1151                         rpmhcc: clock-controller {
1152                                 compatible = "qcom,sc7280-rpmh-clk";
1153                                 clocks = <&xo_board>;
1154                                 clock-names = "xo";
1155                                 #clock-cells = <1>;
1156                         };
1157                 };
1158
1159                 cpufreq_hw: cpufreq@18591000 {
1160                         compatible = "qcom,cpufreq-epss";
1161                         reg = <0 0x18591000 0 0x1000>,
1162                               <0 0x18592000 0 0x1000>,
1163                               <0 0x18593000 0 0x1000>;
1164                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1165                         clock-names = "xo", "alternate";
1166                         #freq-domain-cells = <1>;
1167                 };
1168         };
1169
1170         thermal_zones: thermal-zones {
1171                 cpu0-thermal {
1172                         polling-delay-passive = <250>;
1173                         polling-delay = <0>;
1174
1175                         thermal-sensors = <&tsens0 1>;
1176
1177                         trips {
1178                                 cpu0_alert0: trip-point0 {
1179                                         temperature = <90000>;
1180                                         hysteresis = <2000>;
1181                                         type = "passive";
1182                                 };
1183
1184                                 cpu0_alert1: trip-point1 {
1185                                         temperature = <95000>;
1186                                         hysteresis = <2000>;
1187                                         type = "passive";
1188                                 };
1189
1190                                 cpu0_crit: cpu-crit {
1191                                         temperature = <110000>;
1192                                         hysteresis = <0>;
1193                                         type = "critical";
1194                                 };
1195                         };
1196
1197                         cooling-maps {
1198                                 map0 {
1199                                         trip = <&cpu0_alert0>;
1200                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1201                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1202                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1203                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1204                                 };
1205                                 map1 {
1206                                         trip = <&cpu0_alert1>;
1207                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1208                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1209                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1210                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1211                                 };
1212                         };
1213                 };
1214
1215                 cpu1-thermal {
1216                         polling-delay-passive = <250>;
1217                         polling-delay = <0>;
1218
1219                         thermal-sensors = <&tsens0 2>;
1220
1221                         trips {
1222                                 cpu1_alert0: trip-point0 {
1223                                         temperature = <90000>;
1224                                         hysteresis = <2000>;
1225                                         type = "passive";
1226                                 };
1227
1228                                 cpu1_alert1: trip-point1 {
1229                                         temperature = <95000>;
1230                                         hysteresis = <2000>;
1231                                         type = "passive";
1232                                 };
1233
1234                                 cpu1_crit: cpu-crit {
1235                                         temperature = <110000>;
1236                                         hysteresis = <0>;
1237                                         type = "critical";
1238                                 };
1239                         };
1240
1241                         cooling-maps {
1242                                 map0 {
1243                                         trip = <&cpu1_alert0>;
1244                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1245                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1246                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1247                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1248                                 };
1249                                 map1 {
1250                                         trip = <&cpu1_alert1>;
1251                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1252                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1253                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1254                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1255                                 };
1256                         };
1257                 };
1258
1259                 cpu2-thermal {
1260                         polling-delay-passive = <250>;
1261                         polling-delay = <0>;
1262
1263                         thermal-sensors = <&tsens0 3>;
1264
1265                         trips {
1266                                 cpu2_alert0: trip-point0 {
1267                                         temperature = <90000>;
1268                                         hysteresis = <2000>;
1269                                         type = "passive";
1270                                 };
1271
1272                                 cpu2_alert1: trip-point1 {
1273                                         temperature = <95000>;
1274                                         hysteresis = <2000>;
1275                                         type = "passive";
1276                                 };
1277
1278                                 cpu2_crit: cpu-crit {
1279                                         temperature = <110000>;
1280                                         hysteresis = <0>;
1281                                         type = "critical";
1282                                 };
1283                         };
1284
1285                         cooling-maps {
1286                                 map0 {
1287                                         trip = <&cpu2_alert0>;
1288                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1289                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1290                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1291                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1292                                 };
1293                                 map1 {
1294                                         trip = <&cpu2_alert1>;
1295                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1296                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1297                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1298                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1299                                 };
1300                         };
1301                 };
1302
1303                 cpu3-thermal {
1304                         polling-delay-passive = <250>;
1305                         polling-delay = <0>;
1306
1307                         thermal-sensors = <&tsens0 4>;
1308
1309                         trips {
1310                                 cpu3_alert0: trip-point0 {
1311                                         temperature = <90000>;
1312                                         hysteresis = <2000>;
1313                                         type = "passive";
1314                                 };
1315
1316                                 cpu3_alert1: trip-point1 {
1317                                         temperature = <95000>;
1318                                         hysteresis = <2000>;
1319                                         type = "passive";
1320                                 };
1321
1322                                 cpu3_crit: cpu-crit {
1323                                         temperature = <110000>;
1324                                         hysteresis = <0>;
1325                                         type = "critical";
1326                                 };
1327                         };
1328
1329                         cooling-maps {
1330                                 map0 {
1331                                         trip = <&cpu3_alert0>;
1332                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1333                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1334                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1335                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1336                                 };
1337                                 map1 {
1338                                         trip = <&cpu3_alert1>;
1339                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1340                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1341                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1342                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1343                                 };
1344                         };
1345                 };
1346
1347                 cpu4-thermal {
1348                         polling-delay-passive = <250>;
1349                         polling-delay = <0>;
1350
1351                         thermal-sensors = <&tsens0 7>;
1352
1353                         trips {
1354                                 cpu4_alert0: trip-point0 {
1355                                         temperature = <90000>;
1356                                         hysteresis = <2000>;
1357                                         type = "passive";
1358                                 };
1359
1360                                 cpu4_alert1: trip-point1 {
1361                                         temperature = <95000>;
1362                                         hysteresis = <2000>;
1363                                         type = "passive";
1364                                 };
1365
1366                                 cpu4_crit: cpu-crit {
1367                                         temperature = <110000>;
1368                                         hysteresis = <0>;
1369                                         type = "critical";
1370                                 };
1371                         };
1372
1373                         cooling-maps {
1374                                 map0 {
1375                                         trip = <&cpu4_alert0>;
1376                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1377                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1378                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1379                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1380                                 };
1381                                 map1 {
1382                                         trip = <&cpu4_alert1>;
1383                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1384                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1385                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1386                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1387                                 };
1388                         };
1389                 };
1390
1391                 cpu5-thermal {
1392                         polling-delay-passive = <250>;
1393                         polling-delay = <0>;
1394
1395                         thermal-sensors = <&tsens0 8>;
1396
1397                         trips {
1398                                 cpu5_alert0: trip-point0 {
1399                                         temperature = <90000>;
1400                                         hysteresis = <2000>;
1401                                         type = "passive";
1402                                 };
1403
1404                                 cpu5_alert1: trip-point1 {
1405                                         temperature = <95000>;
1406                                         hysteresis = <2000>;
1407                                         type = "passive";
1408                                 };
1409
1410                                 cpu5_crit: cpu-crit {
1411                                         temperature = <110000>;
1412                                         hysteresis = <0>;
1413                                         type = "critical";
1414                                 };
1415                         };
1416
1417                         cooling-maps {
1418                                 map0 {
1419                                         trip = <&cpu5_alert0>;
1420                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1421                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1422                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1423                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1424                                 };
1425                                 map1 {
1426                                         trip = <&cpu5_alert1>;
1427                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1428                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1429                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1430                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1431                                 };
1432                         };
1433                 };
1434
1435                 cpu6-thermal {
1436                         polling-delay-passive = <250>;
1437                         polling-delay = <0>;
1438
1439                         thermal-sensors = <&tsens0 9>;
1440
1441                         trips {
1442                                 cpu6_alert0: trip-point0 {
1443                                         temperature = <90000>;
1444                                         hysteresis = <2000>;
1445                                         type = "passive";
1446                                 };
1447
1448                                 cpu6_alert1: trip-point1 {
1449                                         temperature = <95000>;
1450                                         hysteresis = <2000>;
1451                                         type = "passive";
1452                                 };
1453
1454                                 cpu6_crit: cpu-crit {
1455                                         temperature = <110000>;
1456                                         hysteresis = <0>;
1457                                         type = "critical";
1458                                 };
1459                         };
1460
1461                         cooling-maps {
1462                                 map0 {
1463                                         trip = <&cpu6_alert0>;
1464                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1465                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1466                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1467                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1468                                 };
1469                                 map1 {
1470                                         trip = <&cpu6_alert1>;
1471                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1472                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1473                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1474                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1475                                 };
1476                         };
1477                 };
1478
1479                 cpu7-thermal {
1480                         polling-delay-passive = <250>;
1481                         polling-delay = <0>;
1482
1483                         thermal-sensors = <&tsens0 10>;
1484
1485                         trips {
1486                                 cpu7_alert0: trip-point0 {
1487                                         temperature = <90000>;
1488                                         hysteresis = <2000>;
1489                                         type = "passive";
1490                                 };
1491
1492                                 cpu7_alert1: trip-point1 {
1493                                         temperature = <95000>;
1494                                         hysteresis = <2000>;
1495                                         type = "passive";
1496                                 };
1497
1498                                 cpu7_crit: cpu-crit {
1499                                         temperature = <110000>;
1500                                         hysteresis = <0>;
1501                                         type = "critical";
1502                                 };
1503                         };
1504
1505                         cooling-maps {
1506                                 map0 {
1507                                         trip = <&cpu7_alert0>;
1508                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1509                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1510                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1511                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1512                                 };
1513                                 map1 {
1514                                         trip = <&cpu7_alert1>;
1515                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1516                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1517                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1518                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1519                                 };
1520                         };
1521                 };
1522
1523                 cpu8-thermal {
1524                         polling-delay-passive = <250>;
1525                         polling-delay = <0>;
1526
1527                         thermal-sensors = <&tsens0 11>;
1528
1529                         trips {
1530                                 cpu8_alert0: trip-point0 {
1531                                         temperature = <90000>;
1532                                         hysteresis = <2000>;
1533                                         type = "passive";
1534                                 };
1535
1536                                 cpu8_alert1: trip-point1 {
1537                                         temperature = <95000>;
1538                                         hysteresis = <2000>;
1539                                         type = "passive";
1540                                 };
1541
1542                                 cpu8_crit: cpu-crit {
1543                                         temperature = <110000>;
1544                                         hysteresis = <0>;
1545                                         type = "critical";
1546                                 };
1547                         };
1548
1549                         cooling-maps {
1550                                 map0 {
1551                                         trip = <&cpu8_alert0>;
1552                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1553                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1554                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1555                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1556                                 };
1557                                 map1 {
1558                                         trip = <&cpu8_alert1>;
1559                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1560                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1561                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1562                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1563                                 };
1564                         };
1565                 };
1566
1567                 cpu9-thermal {
1568                         polling-delay-passive = <250>;
1569                         polling-delay = <0>;
1570
1571                         thermal-sensors = <&tsens0 12>;
1572
1573                         trips {
1574                                 cpu9_alert0: trip-point0 {
1575                                         temperature = <90000>;
1576                                         hysteresis = <2000>;
1577                                         type = "passive";
1578                                 };
1579
1580                                 cpu9_alert1: trip-point1 {
1581                                         temperature = <95000>;
1582                                         hysteresis = <2000>;
1583                                         type = "passive";
1584                                 };
1585
1586                                 cpu9_crit: cpu-crit {
1587                                         temperature = <110000>;
1588                                         hysteresis = <0>;
1589                                         type = "critical";
1590                                 };
1591                         };
1592
1593                         cooling-maps {
1594                                 map0 {
1595                                         trip = <&cpu9_alert0>;
1596                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1597                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1598                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1599                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1600                                 };
1601                                 map1 {
1602                                         trip = <&cpu9_alert1>;
1603                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1604                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1605                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1606                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1607                                 };
1608                         };
1609                 };
1610
1611                 cpu10-thermal {
1612                         polling-delay-passive = <250>;
1613                         polling-delay = <0>;
1614
1615                         thermal-sensors = <&tsens0 13>;
1616
1617                         trips {
1618                                 cpu10_alert0: trip-point0 {
1619                                         temperature = <90000>;
1620                                         hysteresis = <2000>;
1621                                         type = "passive";
1622                                 };
1623
1624                                 cpu10_alert1: trip-point1 {
1625                                         temperature = <95000>;
1626                                         hysteresis = <2000>;
1627                                         type = "passive";
1628                                 };
1629
1630                                 cpu10_crit: cpu-crit {
1631                                         temperature = <110000>;
1632                                         hysteresis = <0>;
1633                                         type = "critical";
1634                                 };
1635                         };
1636
1637                         cooling-maps {
1638                                 map0 {
1639                                         trip = <&cpu10_alert0>;
1640                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1641                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1642                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1643                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1644                                 };
1645                                 map1 {
1646                                         trip = <&cpu10_alert1>;
1647                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1648                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1649                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1650                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1651                                 };
1652                         };
1653                 };
1654
1655                 cpu11-thermal {
1656                         polling-delay-passive = <250>;
1657                         polling-delay = <0>;
1658
1659                         thermal-sensors = <&tsens0 14>;
1660
1661                         trips {
1662                                 cpu11_alert0: trip-point0 {
1663                                         temperature = <90000>;
1664                                         hysteresis = <2000>;
1665                                         type = "passive";
1666                                 };
1667
1668                                 cpu11_alert1: trip-point1 {
1669                                         temperature = <95000>;
1670                                         hysteresis = <2000>;
1671                                         type = "passive";
1672                                 };
1673
1674                                 cpu11_crit: cpu-crit {
1675                                         temperature = <110000>;
1676                                         hysteresis = <0>;
1677                                         type = "critical";
1678                                 };
1679                         };
1680
1681                         cooling-maps {
1682                                 map0 {
1683                                         trip = <&cpu11_alert0>;
1684                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1685                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1686                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1687                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1688                                 };
1689                                 map1 {
1690                                         trip = <&cpu11_alert1>;
1691                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1692                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1693                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1694                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1695                                 };
1696                         };
1697                 };
1698
1699                 aoss0-thermal {
1700                         polling-delay-passive = <0>;
1701                         polling-delay = <0>;
1702
1703                         thermal-sensors = <&tsens0 0>;
1704
1705                         trips {
1706                                 aoss0_alert0: trip-point0 {
1707                                         temperature = <90000>;
1708                                         hysteresis = <2000>;
1709                                         type = "hot";
1710                                 };
1711
1712                                 aoss0_crit: aoss0-crit {
1713                                         temperature = <110000>;
1714                                         hysteresis = <0>;
1715                                         type = "critical";
1716                                 };
1717                         };
1718                 };
1719
1720                 aoss1-thermal {
1721                         polling-delay-passive = <0>;
1722                         polling-delay = <0>;
1723
1724                         thermal-sensors = <&tsens1 0>;
1725
1726                         trips {
1727                                 aoss1_alert0: trip-point0 {
1728                                         temperature = <90000>;
1729                                         hysteresis = <2000>;
1730                                         type = "hot";
1731                                 };
1732
1733                                 aoss1_crit: aoss1-crit {
1734                                         temperature = <110000>;
1735                                         hysteresis = <0>;
1736                                         type = "critical";
1737                                 };
1738                         };
1739                 };
1740
1741                 cpuss0-thermal {
1742                         polling-delay-passive = <0>;
1743                         polling-delay = <0>;
1744
1745                         thermal-sensors = <&tsens0 5>;
1746
1747                         trips {
1748                                 cpuss0_alert0: trip-point0 {
1749                                         temperature = <90000>;
1750                                         hysteresis = <2000>;
1751                                         type = "hot";
1752                                 };
1753                                 cpuss0_crit: cluster0-crit {
1754                                         temperature = <110000>;
1755                                         hysteresis = <0>;
1756                                         type = "critical";
1757                                 };
1758                         };
1759                 };
1760
1761                 cpuss1-thermal {
1762                         polling-delay-passive = <0>;
1763                         polling-delay = <0>;
1764
1765                         thermal-sensors = <&tsens0 6>;
1766
1767                         trips {
1768                                 cpuss1_alert0: trip-point0 {
1769                                         temperature = <90000>;
1770                                         hysteresis = <2000>;
1771                                         type = "hot";
1772                                 };
1773                                 cpuss1_crit: cluster0-crit {
1774                                         temperature = <110000>;
1775                                         hysteresis = <0>;
1776                                         type = "critical";
1777                                 };
1778                         };
1779                 };
1780
1781                 gpuss0-thermal {
1782                         polling-delay-passive = <0>;
1783                         polling-delay = <0>;
1784
1785                         thermal-sensors = <&tsens1 1>;
1786
1787                         trips {
1788                                 gpuss0_alert0: trip-point0 {
1789                                         temperature = <90000>;
1790                                         hysteresis = <2000>;
1791                                         type = "hot";
1792                                 };
1793
1794                                 gpuss0_crit: gpuss0-crit {
1795                                         temperature = <110000>;
1796                                         hysteresis = <0>;
1797                                         type = "critical";
1798                                 };
1799                         };
1800                 };
1801
1802                 gpuss1-thermal {
1803                         polling-delay-passive = <0>;
1804                         polling-delay = <0>;
1805
1806                         thermal-sensors = <&tsens1 2>;
1807
1808                         trips {
1809                                 gpuss1_alert0: trip-point0 {
1810                                         temperature = <90000>;
1811                                         hysteresis = <2000>;
1812                                         type = "hot";
1813                                 };
1814
1815                                 gpuss1_crit: gpuss1-crit {
1816                                         temperature = <110000>;
1817                                         hysteresis = <0>;
1818                                         type = "critical";
1819                                 };
1820                         };
1821                 };
1822
1823                 nspss0-thermal {
1824                         polling-delay-passive = <0>;
1825                         polling-delay = <0>;
1826
1827                         thermal-sensors = <&tsens1 3>;
1828
1829                         trips {
1830                                 nspss0_alert0: trip-point0 {
1831                                         temperature = <90000>;
1832                                         hysteresis = <2000>;
1833                                         type = "hot";
1834                                 };
1835
1836                                 nspss0_crit: nspss0-crit {
1837                                         temperature = <110000>;
1838                                         hysteresis = <0>;
1839                                         type = "critical";
1840                                 };
1841                         };
1842                 };
1843
1844                 nspss1-thermal {
1845                         polling-delay-passive = <0>;
1846                         polling-delay = <0>;
1847
1848                         thermal-sensors = <&tsens1 4>;
1849
1850                         trips {
1851                                 nspss1_alert0: trip-point0 {
1852                                         temperature = <90000>;
1853                                         hysteresis = <2000>;
1854                                         type = "hot";
1855                                 };
1856
1857                                 nspss1_crit: nspss1-crit {
1858                                         temperature = <110000>;
1859                                         hysteresis = <0>;
1860                                         type = "critical";
1861                                 };
1862                         };
1863                 };
1864
1865                 video-thermal {
1866                         polling-delay-passive = <0>;
1867                         polling-delay = <0>;
1868
1869                         thermal-sensors = <&tsens1 5>;
1870
1871                         trips {
1872                                 video_alert0: trip-point0 {
1873                                         temperature = <90000>;
1874                                         hysteresis = <2000>;
1875                                         type = "hot";
1876                                 };
1877
1878                                 video_crit: video-crit {
1879                                         temperature = <110000>;
1880                                         hysteresis = <0>;
1881                                         type = "critical";
1882                                 };
1883                         };
1884                 };
1885
1886                 ddr-thermal {
1887                         polling-delay-passive = <0>;
1888                         polling-delay = <0>;
1889
1890                         thermal-sensors = <&tsens1 6>;
1891
1892                         trips {
1893                                 ddr_alert0: trip-point0 {
1894                                         temperature = <90000>;
1895                                         hysteresis = <2000>;
1896                                         type = "hot";
1897                                 };
1898
1899                                 ddr_crit: ddr-crit {
1900                                         temperature = <110000>;
1901                                         hysteresis = <0>;
1902                                         type = "critical";
1903                                 };
1904                         };
1905                 };
1906
1907                 mdmss0-thermal {
1908                         polling-delay-passive = <0>;
1909                         polling-delay = <0>;
1910
1911                         thermal-sensors = <&tsens1 7>;
1912
1913                         trips {
1914                                 mdmss0_alert0: trip-point0 {
1915                                         temperature = <90000>;
1916                                         hysteresis = <2000>;
1917                                         type = "hot";
1918                                 };
1919
1920                                 mdmss0_crit: mdmss0-crit {
1921                                         temperature = <110000>;
1922                                         hysteresis = <0>;
1923                                         type = "critical";
1924                                 };
1925                         };
1926                 };
1927
1928                 mdmss1-thermal {
1929                         polling-delay-passive = <0>;
1930                         polling-delay = <0>;
1931
1932                         thermal-sensors = <&tsens1 8>;
1933
1934                         trips {
1935                                 mdmss1_alert0: trip-point0 {
1936                                         temperature = <90000>;
1937                                         hysteresis = <2000>;
1938                                         type = "hot";
1939                                 };
1940
1941                                 mdmss1_crit: mdmss1-crit {
1942                                         temperature = <110000>;
1943                                         hysteresis = <0>;
1944                                         type = "critical";
1945                                 };
1946                         };
1947                 };
1948
1949                 mdmss2-thermal {
1950                         polling-delay-passive = <0>;
1951                         polling-delay = <0>;
1952
1953                         thermal-sensors = <&tsens1 9>;
1954
1955                         trips {
1956                                 mdmss2_alert0: trip-point0 {
1957                                         temperature = <90000>;
1958                                         hysteresis = <2000>;
1959                                         type = "hot";
1960                                 };
1961
1962                                 mdmss2_crit: mdmss2-crit {
1963                                         temperature = <110000>;
1964                                         hysteresis = <0>;
1965                                         type = "critical";
1966                                 };
1967                         };
1968                 };
1969
1970                 mdmss3-thermal {
1971                         polling-delay-passive = <0>;
1972                         polling-delay = <0>;
1973
1974                         thermal-sensors = <&tsens1 10>;
1975
1976                         trips {
1977                                 mdmss3_alert0: trip-point0 {
1978                                         temperature = <90000>;
1979                                         hysteresis = <2000>;
1980                                         type = "hot";
1981                                 };
1982
1983                                 mdmss3_crit: mdmss3-crit {
1984                                         temperature = <110000>;
1985                                         hysteresis = <0>;
1986                                         type = "critical";
1987                                 };
1988                         };
1989                 };
1990
1991                 camera0-thermal {
1992                         polling-delay-passive = <0>;
1993                         polling-delay = <0>;
1994
1995                         thermal-sensors = <&tsens1 11>;
1996
1997                         trips {
1998                                 camera0_alert0: trip-point0 {
1999                                         temperature = <90000>;
2000                                         hysteresis = <2000>;
2001                                         type = "hot";
2002                                 };
2003
2004                                 camera0_crit: camera0-crit {
2005                                         temperature = <110000>;
2006                                         hysteresis = <0>;
2007                                         type = "critical";
2008                                 };
2009                         };
2010                 };
2011         };
2012
2013         timer {
2014                 compatible = "arm,armv8-timer";
2015                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2016                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2017                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2018                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2019         };
2020 };