arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/mailbox/qcom-ipcc.h>
  12 #include <dt-bindings/power/qcom-aoss-qmp.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         chosen { };
  23
  24         clocks {
  25                 xo_board: xo-board {
  26                         compatible = "fixed-clock";
  27                         clock-frequency = <76800000>;
  28                         #clock-cells = <0>;
  29                 };
  30
  31                 sleep_clk: sleep-clk {
  32                         compatible = "fixed-clock";
  33                         clock-frequency = <32000>;
  34                         #clock-cells = <0>;
  35                 };
  36         };
  37
  38         reserved-memory {
  39                 #address-cells = <2>;
  40                 #size-cells = <2>;
  41                 ranges;
  42
  43                 aop_mem: memory@80800000 {
  44                         reg = <0x0 0x80800000 0x0 0x60000>;
  45                         no-map;
  46                 };
  47
  48                 aop_cmd_db_mem: memory@80860000 {
  49                         reg = <0x0 0x80860000 0x0 0x20000>;
  50                         compatible = "qcom,cmd-db";
  51                         no-map;
  52                 };
  53
  54                 cpucp_mem: memory@80b00000 {
  55                         no-map;
  56                         reg = <0x0 0x80b00000 0x0 0x100000>;
  57                 };
  58         };
  59
  60         cpus {
  61                 #address-cells = <2>;
  62                 #size-cells = <0>;
  63
  64                 CPU0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,kryo";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  70                                            &LITTLE_CPU_SLEEP_1
  71                                            &CLUSTER_SLEEP_0>;
  72                         next-level-cache = <&L2_0>;
  73                         L2_0: l2-cache {
  74                                 compatible = "cache";
  75                                 next-level-cache = <&L3_0>;
  76                                 L3_0: l3-cache {
  77                                         compatible = "cache";
  78                                 };
  79                         };
  80                 };
  81
  82                 CPU1: cpu@100 {
  83                         device_type = "cpu";
  84                         compatible = "arm,kryo";
  85                         reg = <0x0 0x100>;
  86                         enable-method = "psci";
  87                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  88                                            &LITTLE_CPU_SLEEP_1
  89                                            &CLUSTER_SLEEP_0>;
  90                         next-level-cache = <&L2_100>;
  91                         L2_100: l2-cache {
  92                                 compatible = "cache";
  93                                 next-level-cache = <&L3_0>;
  94                         };
  95                 };
  96
  97                 CPU2: cpu@200 {
  98                         device_type = "cpu";
  99                         compatible = "arm,kryo";
 100                         reg = <0x0 0x200>;
 101                         enable-method = "psci";
 102                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 103                                            &LITTLE_CPU_SLEEP_1
 104                                            &CLUSTER_SLEEP_0>;
 105                         next-level-cache = <&L2_200>;
 106                         L2_200: l2-cache {
 107                                 compatible = "cache";
 108                                 next-level-cache = <&L3_0>;
 109                         };
 110                 };
 111
 112                 CPU3: cpu@300 {
 113                         device_type = "cpu";
 114                         compatible = "arm,kryo";
 115                         reg = <0x0 0x300>;
 116                         enable-method = "psci";
 117                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 118                                            &LITTLE_CPU_SLEEP_1
 119                                            &CLUSTER_SLEEP_0>;
 120                         next-level-cache = <&L2_300>;
 121                         L2_300: l2-cache {
 122                                 compatible = "cache";
 123                                 next-level-cache = <&L3_0>;
 124                         };
 125                 };
 126
 127                 CPU4: cpu@400 {
 128                         device_type = "cpu";
 129                         compatible = "arm,kryo";
 130                         reg = <0x0 0x400>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 133                                            &BIG_CPU_SLEEP_1
 134                                            &CLUSTER_SLEEP_0>;
 135                         next-level-cache = <&L2_400>;
 136                         L2_400: l2-cache {
 137                                 compatible = "cache";
 138                                 next-level-cache = <&L3_0>;
 139                         };
 140                 };
 141
 142                 CPU5: cpu@500 {
 143                         device_type = "cpu";
 144                         compatible = "arm,kryo";
 145                         reg = <0x0 0x500>;
 146                         enable-method = "psci";
 147                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 148                                            &BIG_CPU_SLEEP_1
 149                                            &CLUSTER_SLEEP_0>;
 150                         next-level-cache = <&L2_500>;
 151                         L2_500: l2-cache {
 152                                 compatible = "cache";
 153                                 next-level-cache = <&L3_0>;
 154                         };
 155                 };
 156
 157                 CPU6: cpu@600 {
 158                         device_type = "cpu";
 159                         compatible = "arm,kryo";
 160                         reg = <0x0 0x600>;
 161                         enable-method = "psci";
 162                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 163                                            &BIG_CPU_SLEEP_1
 164                                            &CLUSTER_SLEEP_0>;
 165                         next-level-cache = <&L2_600>;
 166                         L2_600: l2-cache {
 167                                 compatible = "cache";
 168                                 next-level-cache = <&L3_0>;
 169                         };
 170                 };
 171
 172                 CPU7: cpu@700 {
 173                         device_type = "cpu";
 174                         compatible = "arm,kryo";
 175                         reg = <0x0 0x700>;
 176                         enable-method = "psci";
 177                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 178                                            &BIG_CPU_SLEEP_1
 179                                            &CLUSTER_SLEEP_0>;
 180                         next-level-cache = <&L2_700>;
 181                         L2_700: l2-cache {
 182                                 compatible = "cache";
 183                                 next-level-cache = <&L3_0>;
 184                         };
 185                 };
 186
 187                 idle-states {
 188                         entry-method = "psci";
 189
 190                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 191                                 compatible = "arm,idle-state";
 192                                 idle-state-name = "little-power-down";
 193                                 arm,psci-suspend-param = <0x40000003>;
 194                                 entry-latency-us = <549>;
 195                                 exit-latency-us = <901>;
 196                                 min-residency-us = <1774>;
 197                                 local-timer-stop;
 198                         };
 199
 200                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 201                                 compatible = "arm,idle-state";
 202                                 idle-state-name = "little-rail-power-down";
 203                                 arm,psci-suspend-param = <0x40000004>;
 204                                 entry-latency-us = <702>;
 205                                 exit-latency-us = <915>;
 206                                 min-residency-us = <4001>;
 207                                 local-timer-stop;
 208                         };
 209
 210                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 211                                 compatible = "arm,idle-state";
 212                                 idle-state-name = "big-power-down";
 213                                 arm,psci-suspend-param = <0x40000003>;
 214                                 entry-latency-us = <523>;
 215                                 exit-latency-us = <1244>;
 216                                 min-residency-us = <2207>;
 217                                 local-timer-stop;
 218                         };
 219
 220                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 221                                 compatible = "arm,idle-state";
 222                                 idle-state-name = "big-rail-power-down";
 223                                 arm,psci-suspend-param = <0x40000004>;
 224                                 entry-latency-us = <526>;
 225                                 exit-latency-us = <1854>;
 226                                 min-residency-us = <5555>;
 227                                 local-timer-stop;
 228                         };
 229
 230                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 231                                 compatible = "arm,idle-state";
 232                                 idle-state-name = "cluster-power-down";
 233                                 arm,psci-suspend-param = <0x40003444>;
 234                                 entry-latency-us = <3263>;
 235                                 exit-latency-us = <6562>;
 236                                 min-residency-us = <9926>;
 237                                 local-timer-stop;
 238                         };
 239                 };
 240         };
 241
 242         memory@80000000 {
 243                 device_type = "memory";
 244                 /* We expect the bootloader to fill in the size */
 245                 reg = <0 0x80000000 0 0>;
 246         };
 247
 248         firmware {
 249                 scm {
 250                         compatible = "qcom,scm-sc7280", "qcom,scm";
 251                 };
 252         };
 253
 254         pmu {
 255                 compatible = "arm,armv8-pmuv3";
 256                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 257         };
 258
 259         psci {
 260                 compatible = "arm,psci-1.0";
 261                 method = "smc";
 262         };
 263
 264         soc: soc@0 {
 265                 #address-cells = <2>;
 266                 #size-cells = <2>;
 267                 ranges = <0 0 0 0 0x10 0>;
 268                 dma-ranges = <0 0 0 0 0x10 0>;
 269                 compatible = "simple-bus";
 270
 271                 gcc: clock-controller@100000 {
 272                         compatible = "qcom,gcc-sc7280";
 273                         reg = <0 0x00100000 0 0x1f0000>;
 274                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 275                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 276                                  <0>, <0>, <0>, <0>, <0>, <0>;
 277                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 278                                       "pcie_0_pipe_clk", "pcie_1_pipe-clk",
 279                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 280                                       "ufs_phy_tx_symbol_0_clk",
 281                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 282                         #clock-cells = <1>;
 283                         #reset-cells = <1>;
 284                         #power-domain-cells = <1>;
 285                 };
 286
 287                 ipcc: mailbox@408000 {
 288                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 289                         reg = <0 0x00408000 0 0x1000>;
 290                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 291                         interrupt-controller;
 292                         #interrupt-cells = <3>;
 293                         #mbox-cells = <2>;
 294                 };
 295
 296                 qupv3_id_0: geniqup@9c0000 {
 297                         compatible = "qcom,geni-se-qup";
 298                         reg = <0 0x009c0000 0 0x2000>;
 299                         clock-names = "m-ahb", "s-ahb";
 300                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 301                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 302                         #address-cells = <2>;
 303                         #size-cells = <2>;
 304                         ranges;
 305                         status = "disabled";
 306
 307                         uart5: serial@994000 {
 308                                 compatible = "qcom,geni-debug-uart";
 309                                 reg = <0 0x00994000 0 0x4000>;
 310                                 clock-names = "se";
 311                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 312                                 pinctrl-names = "default";
 313                                 pinctrl-0 = <&qup_uart5_default>;
 314                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 315                                 status = "disabled";
 316                         };
 317                 };
 318
 319                 stm@6002000 {
 320                         compatible = "arm,coresight-stm", "arm,primecell";
 321                         reg = <0 0x06002000 0 0x1000>,
 322                               <0 0x16280000 0 0x180000>;
 323                         reg-names = "stm-base", "stm-stimulus-base";
 324
 325                         clocks = <&aoss_qmp>;
 326                         clock-names = "apb_pclk";
 327
 328                         out-ports {
 329                                 port {
 330                                         stm_out: endpoint {
 331                                                 remote-endpoint = <&funnel0_in7>;
 332                                         };
 333                                 };
 334                         };
 335                 };
 336
 337                 funnel@6041000 {
 338                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 339                         reg = <0 0x06041000 0 0x1000>;
 340
 341                         clocks = <&aoss_qmp>;
 342                         clock-names = "apb_pclk";
 343
 344                         out-ports {
 345                                 port {
 346                                         funnel0_out: endpoint {
 347                                                 remote-endpoint = <&merge_funnel_in0>;
 348                                         };
 349                                 };
 350                         };
 351
 352                         in-ports {
 353                                 #address-cells = <1>;
 354                                 #size-cells = <0>;
 355
 356                                 port@7 {
 357                                         reg = <7>;
 358                                         funnel0_in7: endpoint {
 359                                                 remote-endpoint = <&stm_out>;
 360                                         };
 361                                 };
 362                         };
 363                 };
 364
 365                 funnel@6042000 {
 366                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 367                         reg = <0 0x06042000 0 0x1000>;
 368
 369                         clocks = <&aoss_qmp>;
 370                         clock-names = "apb_pclk";
 371
 372                         out-ports {
 373                                 port {
 374                                         funnel1_out: endpoint {
 375                                                 remote-endpoint = <&merge_funnel_in1>;
 376                                         };
 377                                 };
 378                         };
 379
 380                         in-ports {
 381                                 #address-cells = <1>;
 382                                 #size-cells = <0>;
 383
 384                                 port@4 {
 385                                         reg = <4>;
 386                                         funnel1_in4: endpoint {
 387                                                 remote-endpoint = <&apss_merge_funnel_out>;
 388                                         };
 389                                 };
 390                         };
 391                 };
 392
 393                 funnel@6045000 {
 394                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 395                         reg = <0 0x06045000 0 0x1000>;
 396
 397                         clocks = <&aoss_qmp>;
 398                         clock-names = "apb_pclk";
 399
 400                         out-ports {
 401                                 port {
 402                                         merge_funnel_out: endpoint {
 403                                                 remote-endpoint = <&swao_funnel_in>;
 404                                         };
 405                                 };
 406                         };
 407
 408                         in-ports {
 409                                 #address-cells = <1>;
 410                                 #size-cells = <0>;
 411
 412                                 port@0 {
 413                                         reg = <0>;
 414                                         merge_funnel_in0: endpoint {
 415                                                 remote-endpoint = <&funnel0_out>;
 416                                         };
 417                                 };
 418
 419                                 port@1 {
 420                                         reg = <1>;
 421                                         merge_funnel_in1: endpoint {
 422                                                 remote-endpoint = <&funnel1_out>;
 423                                         };
 424                                 };
 425                         };
 426                 };
 427
 428                 replicator@6046000 {
 429                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 430                         reg = <0 0x06046000 0 0x1000>;
 431
 432                         clocks = <&aoss_qmp>;
 433                         clock-names = "apb_pclk";
 434
 435                         out-ports {
 436                                 port {
 437                                         replicator_out: endpoint {
 438                                                 remote-endpoint = <&etr_in>;
 439                                         };
 440                                 };
 441                         };
 442
 443                         in-ports {
 444                                 port {
 445                                         replicator_in: endpoint {
 446                                                 remote-endpoint = <&swao_replicator_out>;
 447                                         };
 448                                 };
 449                         };
 450                 };
 451
 452                 etr@6048000 {
 453                         compatible = "arm,coresight-tmc", "arm,primecell";
 454                         reg = <0 0x06048000 0 0x1000>;
 455                         iommus = <&apps_smmu 0x04c0 0>;
 456
 457                         clocks = <&aoss_qmp>;
 458                         clock-names = "apb_pclk";
 459                         arm,scatter-gather;
 460
 461                         in-ports {
 462                                 port {
 463                                         etr_in: endpoint {
 464                                                 remote-endpoint = <&replicator_out>;
 465                                         };
 466                                 };
 467                         };
 468                 };
 469
 470                 funnel@6b04000 {
 471                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 472                         reg = <0 0x06b04000 0 0x1000>;
 473
 474                         clocks = <&aoss_qmp>;
 475                         clock-names = "apb_pclk";
 476
 477                         out-ports {
 478                                 port {
 479                                         swao_funnel_out: endpoint {
 480                                                 remote-endpoint = <&etf_in>;
 481                                         };
 482                                 };
 483                         };
 484
 485                         in-ports {
 486                                 #address-cells = <1>;
 487                                 #size-cells = <0>;
 488
 489                                 port@7 {
 490                                         reg = <7>;
 491                                         swao_funnel_in: endpoint {
 492                                                 remote-endpoint = <&merge_funnel_out>;
 493                                         };
 494                                 };
 495                         };
 496                 };
 497
 498                 etf@6b05000 {
 499                         compatible = "arm,coresight-tmc", "arm,primecell";
 500                         reg = <0 0x06b05000 0 0x1000>;
 501
 502                         clocks = <&aoss_qmp>;
 503                         clock-names = "apb_pclk";
 504
 505                         out-ports {
 506                                 port {
 507                                         etf_out: endpoint {
 508                                                 remote-endpoint = <&swao_replicator_in>;
 509                                         };
 510                                 };
 511                         };
 512
 513                         in-ports {
 514                                 port {
 515                                         etf_in: endpoint {
 516                                                 remote-endpoint = <&swao_funnel_out>;
 517                                         };
 518                                 };
 519                         };
 520                 };
 521
 522                 replicator@6b06000 {
 523                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 524                         reg = <0 0x06b06000 0 0x1000>;
 525
 526                         clocks = <&aoss_qmp>;
 527                         clock-names = "apb_pclk";
 528                         qcom,replicator-loses-context;
 529
 530                         out-ports {
 531                                 port {
 532                                         swao_replicator_out: endpoint {
 533                                                 remote-endpoint = <&replicator_in>;
 534                                         };
 535                                 };
 536                         };
 537
 538                         in-ports {
 539                                 port {
 540                                         swao_replicator_in: endpoint {
 541                                                 remote-endpoint = <&etf_out>;
 542                                         };
 543                                 };
 544                         };
 545                 };
 546
 547                 etm@7040000 {
 548                         compatible = "arm,coresight-etm4x", "arm,primecell";
 549                         reg = <0 0x07040000 0 0x1000>;
 550
 551                         cpu = <&CPU0>;
 552
 553                         clocks = <&aoss_qmp>;
 554                         clock-names = "apb_pclk";
 555                         arm,coresight-loses-context-with-cpu;
 556                         qcom,skip-power-up;
 557
 558                         out-ports {
 559                                 port {
 560                                         etm0_out: endpoint {
 561                                                 remote-endpoint = <&apss_funnel_in0>;
 562                                         };
 563                                 };
 564                         };
 565                 };
 566
 567                 etm@7140000 {
 568                         compatible = "arm,coresight-etm4x", "arm,primecell";
 569                         reg = <0 0x07140000 0 0x1000>;
 570
 571                         cpu = <&CPU1>;
 572
 573                         clocks = <&aoss_qmp>;
 574                         clock-names = "apb_pclk";
 575                         arm,coresight-loses-context-with-cpu;
 576                         qcom,skip-power-up;
 577
 578                         out-ports {
 579                                 port {
 580                                         etm1_out: endpoint {
 581                                                 remote-endpoint = <&apss_funnel_in1>;
 582                                         };
 583                                 };
 584                         };
 585                 };
 586
 587                 etm@7240000 {
 588                         compatible = "arm,coresight-etm4x", "arm,primecell";
 589                         reg = <0 0x07240000 0 0x1000>;
 590
 591                         cpu = <&CPU2>;
 592
 593                         clocks = <&aoss_qmp>;
 594                         clock-names = "apb_pclk";
 595                         arm,coresight-loses-context-with-cpu;
 596                         qcom,skip-power-up;
 597
 598                         out-ports {
 599                                 port {
 600                                         etm2_out: endpoint {
 601                                                 remote-endpoint = <&apss_funnel_in2>;
 602                                         };
 603                                 };
 604                         };
 605                 };
 606
 607                 etm@7340000 {
 608                         compatible = "arm,coresight-etm4x", "arm,primecell";
 609                         reg = <0 0x07340000 0 0x1000>;
 610
 611                         cpu = <&CPU3>;
 612
 613                         clocks = <&aoss_qmp>;
 614                         clock-names = "apb_pclk";
 615                         arm,coresight-loses-context-with-cpu;
 616                         qcom,skip-power-up;
 617
 618                         out-ports {
 619                                 port {
 620                                         etm3_out: endpoint {
 621                                                 remote-endpoint = <&apss_funnel_in3>;
 622                                         };
 623                                 };
 624                         };
 625                 };
 626
 627                 etm@7440000 {
 628                         compatible = "arm,coresight-etm4x", "arm,primecell";
 629                         reg = <0 0x07440000 0 0x1000>;
 630
 631                         cpu = <&CPU4>;
 632
 633                         clocks = <&aoss_qmp>;
 634                         clock-names = "apb_pclk";
 635                         arm,coresight-loses-context-with-cpu;
 636                         qcom,skip-power-up;
 637
 638                         out-ports {
 639                                 port {
 640                                         etm4_out: endpoint {
 641                                                 remote-endpoint = <&apss_funnel_in4>;
 642                                         };
 643                                 };
 644                         };
 645                 };
 646
 647                 etm@7540000 {
 648                         compatible = "arm,coresight-etm4x", "arm,primecell";
 649                         reg = <0 0x07540000 0 0x1000>;
 650
 651                         cpu = <&CPU5>;
 652
 653                         clocks = <&aoss_qmp>;
 654                         clock-names = "apb_pclk";
 655                         arm,coresight-loses-context-with-cpu;
 656                         qcom,skip-power-up;
 657
 658                         out-ports {
 659                                 port {
 660                                         etm5_out: endpoint {
 661                                                 remote-endpoint = <&apss_funnel_in5>;
 662                                         };
 663                                 };
 664                         };
 665                 };
 666
 667                 etm@7640000 {
 668                         compatible = "arm,coresight-etm4x", "arm,primecell";
 669                         reg = <0 0x07640000 0 0x1000>;
 670
 671                         cpu = <&CPU6>;
 672
 673                         clocks = <&aoss_qmp>;
 674                         clock-names = "apb_pclk";
 675                         arm,coresight-loses-context-with-cpu;
 676                         qcom,skip-power-up;
 677
 678                         out-ports {
 679                                 port {
 680                                         etm6_out: endpoint {
 681                                                 remote-endpoint = <&apss_funnel_in6>;
 682                                         };
 683                                 };
 684                         };
 685                 };
 686
 687                 etm@7740000 {
 688                         compatible = "arm,coresight-etm4x", "arm,primecell";
 689                         reg = <0 0x07740000 0 0x1000>;
 690
 691                         cpu = <&CPU7>;
 692
 693                         clocks = <&aoss_qmp>;
 694                         clock-names = "apb_pclk";
 695                         arm,coresight-loses-context-with-cpu;
 696                         qcom,skip-power-up;
 697
 698                         out-ports {
 699                                 port {
 700                                         etm7_out: endpoint {
 701                                                 remote-endpoint = <&apss_funnel_in7>;
 702                                         };
 703                                 };
 704                         };
 705                 };
 706
 707                 funnel@7800000 { /* APSS Funnel */
 708                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 709                         reg = <0 0x07800000 0 0x1000>;
 710
 711                         clocks = <&aoss_qmp>;
 712                         clock-names = "apb_pclk";
 713
 714                         out-ports {
 715                                 port {
 716                                         apss_funnel_out: endpoint {
 717                                                 remote-endpoint = <&apss_merge_funnel_in>;
 718                                         };
 719                                 };
 720                         };
 721
 722                         in-ports {
 723                                 #address-cells = <1>;
 724                                 #size-cells = <0>;
 725
 726                                 port@0 {
 727                                         reg = <0>;
 728                                         apss_funnel_in0: endpoint {
 729                                                 remote-endpoint = <&etm0_out>;
 730                                         };
 731                                 };
 732
 733                                 port@1 {
 734                                         reg = <1>;
 735                                         apss_funnel_in1: endpoint {
 736                                                 remote-endpoint = <&etm1_out>;
 737                                         };
 738                                 };
 739
 740                                 port@2 {
 741                                         reg = <2>;
 742                                         apss_funnel_in2: endpoint {
 743                                                 remote-endpoint = <&etm2_out>;
 744                                         };
 745                                 };
 746
 747                                 port@3 {
 748                                         reg = <3>;
 749                                         apss_funnel_in3: endpoint {
 750                                                 remote-endpoint = <&etm3_out>;
 751                                         };
 752                                 };
 753
 754                                 port@4 {
 755                                         reg = <4>;
 756                                         apss_funnel_in4: endpoint {
 757                                                 remote-endpoint = <&etm4_out>;
 758                                         };
 759                                 };
 760
 761                                 port@5 {
 762                                         reg = <5>;
 763                                         apss_funnel_in5: endpoint {
 764                                                 remote-endpoint = <&etm5_out>;
 765                                         };
 766                                 };
 767
 768                                 port@6 {
 769                                         reg = <6>;
 770                                         apss_funnel_in6: endpoint {
 771                                                 remote-endpoint = <&etm6_out>;
 772                                         };
 773                                 };
 774
 775                                 port@7 {
 776                                         reg = <7>;
 777                                         apss_funnel_in7: endpoint {
 778                                                 remote-endpoint = <&etm7_out>;
 779                                         };
 780                                 };
 781                         };
 782                 };
 783
 784                 funnel@7810000 {
 785                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 786                         reg = <0 0x07810000 0 0x1000>;
 787
 788                         clocks = <&aoss_qmp>;
 789                         clock-names = "apb_pclk";
 790
 791                         out-ports {
 792                                 port {
 793                                         apss_merge_funnel_out: endpoint {
 794                                                 remote-endpoint = <&funnel1_in4>;
 795                                         };
 796                                 };
 797                         };
 798
 799                         in-ports {
 800                                 port {
 801                                         apss_merge_funnel_in: endpoint {
 802                                                 remote-endpoint = <&apss_funnel_out>;
 803                                         };
 804                                 };
 805                         };
 806                 };
 807
 808                 system-cache-controller@9200000 {
 809                         compatible = "qcom,sc7280-llcc";
 810                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
 811                         reg-names = "llcc_base", "llcc_broadcast_base";
 812                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 813                 };
 814
 815                 pdc: interrupt-controller@b220000 {
 816                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
 817                         reg = <0 0x0b220000 0 0x30000>;
 818                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
 819                                           <55 306 4>, <59 312 3>, <62 374 2>,
 820                                           <64 434 2>, <66 438 3>, <69 86 1>,
 821                                           <70 520 54>, <124 609 31>, <155 63 1>,
 822                                           <156 716 12>;
 823                         #interrupt-cells = <2>;
 824                         interrupt-parent = <&intc>;
 825                         interrupt-controller;
 826                 };
 827
 828                 aoss_qmp: power-controller@c300000 {
 829                         compatible = "qcom,sc7280-aoss-qmp";
 830                         reg = <0 0x0c300000 0 0x100000>;
 831                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
 832                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
 833                                                      IRQ_TYPE_EDGE_RISING>;
 834                         mboxes = <&ipcc IPCC_CLIENT_AOP
 835                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
 836
 837                         #clock-cells = <0>;
 838                         #power-domain-cells = <1>;
 839                 };
 840
 841                 spmi_bus: spmi@c440000 {
 842                         compatible = "qcom,spmi-pmic-arb";
 843                         reg = <0 0x0c440000 0 0x1100>,
 844                               <0 0x0c600000 0 0x2000000>,
 845                               <0 0x0e600000 0 0x100000>,
 846                               <0 0x0e700000 0 0xa0000>,
 847                               <0 0x0c40a000 0 0x26000>;
 848                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 849                         interrupt-names = "periph_irq";
 850                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
 851                         qcom,ee = <0>;
 852                         qcom,channel = <0>;
 853                         #address-cells = <1>;
 854                         #size-cells = <1>;
 855                         interrupt-controller;
 856                         #interrupt-cells = <4>;
 857                 };
 858
 859                 tlmm: pinctrl@f100000 {
 860                         compatible = "qcom,sc7280-pinctrl";
 861                         reg = <0 0x0f100000 0 0x300000>;
 862                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 863                         gpio-controller;
 864                         #gpio-cells = <2>;
 865                         interrupt-controller;
 866                         #interrupt-cells = <2>;
 867                         gpio-ranges = <&tlmm 0 0 175>;
 868                         wakeup-parent = <&pdc>;
 869
 870                         qup_uart5_default: qup-uart5-default {
 871                                 pins = "gpio46", "gpio47";
 872                                 function = "qup13";
 873                         };
 874                 };
 875
 876                 apps_smmu: iommu@15000000 {
 877                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
 878                         reg = <0 0x15000000 0 0x100000>;
 879                         #iommu-cells = <2>;
 880                         #global-interrupts = <1>;
 881                         dma-coherent;
 882                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 883                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 884                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 885                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 886                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 887                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 888                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 889                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 890                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 891                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 892                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 893                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 894                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 895                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 896                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 897                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 898                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 899                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 900                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 901                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 902                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 903                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 904                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 905                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 906                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 907                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 908                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 909                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 911                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 912                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 913                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 918                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 920                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 921                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 922                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
 925                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
 926                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
 927                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
 931                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 933                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 934                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 935                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 936                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 937                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 938                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 939                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 940                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 941                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 942                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 943                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 944                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 945                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 950                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 951                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 952                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 953                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 954                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 955                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 956                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 957                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 958                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 959                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 960                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
 961                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 962                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 963                 };
 964
 965                 intc: interrupt-controller@17a00000 {
 966                         compatible = "arm,gic-v3";
 967                         #address-cells = <2>;
 968                         #size-cells = <2>;
 969                         ranges;
 970                         #interrupt-cells = <3>;
 971                         interrupt-controller;
 972                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
 973                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
 974                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 975
 976                         gic-its@17a40000 {
 977                                 compatible = "arm,gic-v3-its";
 978                                 msi-controller;
 979                                 #msi-cells = <1>;
 980                                 reg = <0 0x17a40000 0 0x20000>;
 981                                 status = "disabled";
 982                         };
 983                 };
 984
 985                 watchdog@17c10000 {
 986                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
 987                         reg = <0 0x17c10000 0 0x1000>;
 988                         clocks = <&sleep_clk>;
 989                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 990                 };
 991
 992                 timer@17c20000 {
 993                         #address-cells = <2>;
 994                         #size-cells = <2>;
 995                         ranges;
 996                         compatible = "arm,armv7-timer-mem";
 997                         reg = <0 0x17c20000 0 0x1000>;
 998
 999                         frame@17c21000 {
1000                                 frame-number = <0>;
1001                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1002                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1003                                 reg = <0 0x17c21000 0 0x1000>,
1004                                       <0 0x17c22000 0 0x1000>;
1005                         };
1006
1007                         frame@17c23000 {
1008                                 frame-number = <1>;
1009                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1010                                 reg = <0 0x17c23000 0 0x1000>;
1011                                 status = "disabled";
1012                         };
1013
1014                         frame@17c25000 {
1015                                 frame-number = <2>;
1016                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1017                                 reg = <0 0x17c25000 0 0x1000>;
1018                                 status = "disabled";
1019                         };
1020
1021                         frame@17c27000 {
1022                                 frame-number = <3>;
1023                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1024                                 reg = <0 0x17c27000 0 0x1000>;
1025                                 status = "disabled";
1026                         };
1027
1028                         frame@17c29000 {
1029                                 frame-number = <4>;
1030                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1031                                 reg = <0 0x17c29000 0 0x1000>;
1032                                 status = "disabled";
1033                         };
1034
1035                         frame@17c2b000 {
1036                                 frame-number = <5>;
1037                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1038                                 reg = <0 0x17c2b000 0 0x1000>;
1039                                 status = "disabled";
1040                         };
1041
1042                         frame@17c2d000 {
1043                                 frame-number = <6>;
1044                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1045                                 reg = <0 0x17c2d000 0 0x1000>;
1046                                 status = "disabled";
1047                         };
1048                 };
1049
1050                 apps_rsc: rsc@18200000 {
1051                         compatible = "qcom,rpmh-rsc";
1052                         reg = <0 0x18200000 0 0x10000>,
1053                               <0 0x18210000 0 0x10000>,
1054                               <0 0x18220000 0 0x10000>;
1055                         reg-names = "drv-0", "drv-1", "drv-2";
1056                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1057                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1058                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1059                         qcom,tcs-offset = <0xd00>;
1060                         qcom,drv-id = <2>;
1061                         qcom,tcs-config = <ACTIVE_TCS  2>,
1062                                           <SLEEP_TCS   3>,
1063                                           <WAKE_TCS    3>,
1064                                           <CONTROL_TCS 1>;
1065
1066                         rpmhpd: power-controller {
1067                                 compatible = "qcom,sc7280-rpmhpd";
1068                                 #power-domain-cells = <1>;
1069                                 operating-points-v2 = <&rpmhpd_opp_table>;
1070
1071                                 rpmhpd_opp_table: opp-table {
1072                                         compatible = "operating-points-v2";
1073
1074                                         rpmhpd_opp_ret: opp1 {
1075                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1076                                         };
1077
1078                                         rpmhpd_opp_low_svs: opp2 {
1079                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1080                                         };
1081
1082                                         rpmhpd_opp_svs: opp3 {
1083                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1084                                         };
1085
1086                                         rpmhpd_opp_svs_l1: opp4 {
1087                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1088                                         };
1089
1090                                         rpmhpd_opp_svs_l2: opp5 {
1091                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1092                                         };
1093
1094                                         rpmhpd_opp_nom: opp6 {
1095                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1096                                         };
1097
1098                                         rpmhpd_opp_nom_l1: opp7 {
1099                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1100                                         };
1101
1102                                         rpmhpd_opp_turbo: opp8 {
1103                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1104                                         };
1105
1106                                         rpmhpd_opp_turbo_l1: opp9 {
1107                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1108                                         };
1109                                 };
1110                         };
1111
1112                         rpmhcc: clock-controller {
1113                                 compatible = "qcom,sc7280-rpmh-clk";
1114                                 clocks = <&xo_board>;
1115                                 clock-names = "xo";
1116                                 #clock-cells = <1>;
1117                         };
1118                 };
1119         };
1120
1121         timer {
1122                 compatible = "arm,armv8-timer";
1123                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1124                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1125                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1126                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1127         };
1128 };