arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,apr.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         interrupt-parent = <&intc>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         chosen { };
  20
  21         clocks {
  22                 xo_board: xo-board {
  23                         compatible = "fixed-clock";
  24                         #clock-cells = <0>;
  25                         clock-frequency = <19200000>;
  26                         clock-output-names = "xo_board";
  27                 };
  28
  29                 sleep_clk: sleep-clk {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <32764>;
  33                         clock-output-names = "sleep_clk";
  34                 };
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 CPU0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "qcom,kryo";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         cpu-idle-states = <&CPU_SLEEP_0>;
  47                         capacity-dmips-mhz = <1024>;
  48                         clocks = <&kryocc 0>;
  49                         operating-points-v2 = <&cluster0_opp>;
  50                         #cooling-cells = <2>;
  51                         next-level-cache = <&L2_0>;
  52                         L2_0: l2-cache {
  53                               compatible = "cache";
  54                               cache-level = <2>;
  55                         };
  56                 };
  57
  58                 CPU1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "qcom,kryo";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                         capacity-dmips-mhz = <1024>;
  65                         clocks = <&kryocc 0>;
  66                         operating-points-v2 = <&cluster0_opp>;
  67                         #cooling-cells = <2>;
  68                         next-level-cache = <&L2_0>;
  69                 };
  70
  71                 CPU2: cpu@100 {
  72                         device_type = "cpu";
  73                         compatible = "qcom,kryo";
  74                         reg = <0x0 0x100>;
  75                         enable-method = "psci";
  76                         cpu-idle-states = <&CPU_SLEEP_0>;
  77                         capacity-dmips-mhz = <1024>;
  78                         clocks = <&kryocc 1>;
  79                         operating-points-v2 = <&cluster1_opp>;
  80                         #cooling-cells = <2>;
  81                         next-level-cache = <&L2_1>;
  82                         L2_1: l2-cache {
  83                               compatible = "cache";
  84                               cache-level = <2>;
  85                         };
  86                 };
  87
  88                 CPU3: cpu@101 {
  89                         device_type = "cpu";
  90                         compatible = "qcom,kryo";
  91                         reg = <0x0 0x101>;
  92                         enable-method = "psci";
  93                         cpu-idle-states = <&CPU_SLEEP_0>;
  94                         capacity-dmips-mhz = <1024>;
  95                         clocks = <&kryocc 1>;
  96                         operating-points-v2 = <&cluster1_opp>;
  97                         #cooling-cells = <2>;
  98                         next-level-cache = <&L2_1>;
  99                 };
 100
 101                 cpu-map {
 102                         cluster0 {
 103                                 core0 {
 104                                         cpu = <&CPU0>;
 105                                 };
 106
 107                                 core1 {
 108                                         cpu = <&CPU1>;
 109                                 };
 110                         };
 111
 112                         cluster1 {
 113                                 core0 {
 114                                         cpu = <&CPU2>;
 115                                 };
 116
 117                                 core1 {
 118                                         cpu = <&CPU3>;
 119                                 };
 120                         };
 121                 };
 122
 123                 idle-states {
 124                         entry-method = "psci";
 125
 126                         CPU_SLEEP_0: cpu-sleep-0 {
 127                                 compatible = "arm,idle-state";
 128                                 idle-state-name = "standalone-power-collapse";
 129                                 arm,psci-suspend-param = <0x00000004>;
 130                                 entry-latency-us = <130>;
 131                                 exit-latency-us = <80>;
 132                                 min-residency-us = <300>;
 133                         };
 134                 };
 135         };
 136
 137         cluster0_opp: opp-table-cluster0 {
 138                 compatible = "operating-points-v2-kryo-cpu";
 139                 nvmem-cells = <&speedbin_efuse>;
 140                 opp-shared;
 141
 142                 /* Nominal fmax for now */
 143                 opp-307200000 {
 144                         opp-hz = /bits/ 64 <307200000>;
 145                         opp-supported-hw = <0x77>;
 146                         clock-latency-ns = <200000>;
 147                 };
 148                 opp-422400000 {
 149                         opp-hz = /bits/ 64 <422400000>;
 150                         opp-supported-hw = <0x77>;
 151                         clock-latency-ns = <200000>;
 152                 };
 153                 opp-480000000 {
 154                         opp-hz = /bits/ 64 <480000000>;
 155                         opp-supported-hw = <0x77>;
 156                         clock-latency-ns = <200000>;
 157                 };
 158                 opp-556800000 {
 159                         opp-hz = /bits/ 64 <556800000>;
 160                         opp-supported-hw = <0x77>;
 161                         clock-latency-ns = <200000>;
 162                 };
 163                 opp-652800000 {
 164                         opp-hz = /bits/ 64 <652800000>;
 165                         opp-supported-hw = <0x77>;
 166                         clock-latency-ns = <200000>;
 167                 };
 168                 opp-729600000 {
 169                         opp-hz = /bits/ 64 <729600000>;
 170                         opp-supported-hw = <0x77>;
 171                         clock-latency-ns = <200000>;
 172                 };
 173                 opp-844800000 {
 174                         opp-hz = /bits/ 64 <844800000>;
 175                         opp-supported-hw = <0x77>;
 176                         clock-latency-ns = <200000>;
 177                 };
 178                 opp-960000000 {
 179                         opp-hz = /bits/ 64 <960000000>;
 180                         opp-supported-hw = <0x77>;
 181                         clock-latency-ns = <200000>;
 182                 };
 183                 opp-1036800000 {
 184                         opp-hz = /bits/ 64 <1036800000>;
 185                         opp-supported-hw = <0x77>;
 186                         clock-latency-ns = <200000>;
 187                 };
 188                 opp-1113600000 {
 189                         opp-hz = /bits/ 64 <1113600000>;
 190                         opp-supported-hw = <0x77>;
 191                         clock-latency-ns = <200000>;
 192                 };
 193                 opp-1190400000 {
 194                         opp-hz = /bits/ 64 <1190400000>;
 195                         opp-supported-hw = <0x77>;
 196                         clock-latency-ns = <200000>;
 197                 };
 198                 opp-1228800000 {
 199                         opp-hz = /bits/ 64 <1228800000>;
 200                         opp-supported-hw = <0x77>;
 201                         clock-latency-ns = <200000>;
 202                 };
 203                 opp-1324800000 {
 204                         opp-hz = /bits/ 64 <1324800000>;
 205                         opp-supported-hw = <0x77>;
 206                         clock-latency-ns = <200000>;
 207                 };
 208                 opp-1401600000 {
 209                         opp-hz = /bits/ 64 <1401600000>;
 210                         opp-supported-hw = <0x77>;
 211                         clock-latency-ns = <200000>;
 212                 };
 213                 opp-1478400000 {
 214                         opp-hz = /bits/ 64 <1478400000>;
 215                         opp-supported-hw = <0x77>;
 216                         clock-latency-ns = <200000>;
 217                 };
 218                 opp-1593600000 {
 219                         opp-hz = /bits/ 64 <1593600000>;
 220                         opp-supported-hw = <0x77>;
 221                         clock-latency-ns = <200000>;
 222                 };
 223         };
 224
 225         cluster1_opp: opp-table-cluster1 {
 226                 compatible = "operating-points-v2-kryo-cpu";
 227                 nvmem-cells = <&speedbin_efuse>;
 228                 opp-shared;
 229
 230                 /* Nominal fmax for now */
 231                 opp-307200000 {
 232                         opp-hz = /bits/ 64 <307200000>;
 233                         opp-supported-hw = <0x77>;
 234                         clock-latency-ns = <200000>;
 235                 };
 236                 opp-403200000 {
 237                         opp-hz = /bits/ 64 <403200000>;
 238                         opp-supported-hw = <0x77>;
 239                         clock-latency-ns = <200000>;
 240                 };
 241                 opp-480000000 {
 242                         opp-hz = /bits/ 64 <480000000>;
 243                         opp-supported-hw = <0x77>;
 244                         clock-latency-ns = <200000>;
 245                 };
 246                 opp-556800000 {
 247                         opp-hz = /bits/ 64 <556800000>;
 248                         opp-supported-hw = <0x77>;
 249                         clock-latency-ns = <200000>;
 250                 };
 251                 opp-652800000 {
 252                         opp-hz = /bits/ 64 <652800000>;
 253                         opp-supported-hw = <0x77>;
 254                         clock-latency-ns = <200000>;
 255                 };
 256                 opp-729600000 {
 257                         opp-hz = /bits/ 64 <729600000>;
 258                         opp-supported-hw = <0x77>;
 259                         clock-latency-ns = <200000>;
 260                 };
 261                 opp-806400000 {
 262                         opp-hz = /bits/ 64 <806400000>;
 263                         opp-supported-hw = <0x77>;
 264                         clock-latency-ns = <200000>;
 265                 };
 266                 opp-883200000 {
 267                         opp-hz = /bits/ 64 <883200000>;
 268                         opp-supported-hw = <0x77>;
 269                         clock-latency-ns = <200000>;
 270                 };
 271                 opp-940800000 {
 272                         opp-hz = /bits/ 64 <940800000>;
 273                         opp-supported-hw = <0x77>;
 274                         clock-latency-ns = <200000>;
 275                 };
 276                 opp-1036800000 {
 277                         opp-hz = /bits/ 64 <1036800000>;
 278                         opp-supported-hw = <0x77>;
 279                         clock-latency-ns = <200000>;
 280                 };
 281                 opp-1113600000 {
 282                         opp-hz = /bits/ 64 <1113600000>;
 283                         opp-supported-hw = <0x77>;
 284                         clock-latency-ns = <200000>;
 285                 };
 286                 opp-1190400000 {
 287                         opp-hz = /bits/ 64 <1190400000>;
 288                         opp-supported-hw = <0x77>;
 289                         clock-latency-ns = <200000>;
 290                 };
 291                 opp-1248000000 {
 292                         opp-hz = /bits/ 64 <1248000000>;
 293                         opp-supported-hw = <0x77>;
 294                         clock-latency-ns = <200000>;
 295                 };
 296                 opp-1324800000 {
 297                         opp-hz = /bits/ 64 <1324800000>;
 298                         opp-supported-hw = <0x77>;
 299                         clock-latency-ns = <200000>;
 300                 };
 301                 opp-1401600000 {
 302                         opp-hz = /bits/ 64 <1401600000>;
 303                         opp-supported-hw = <0x77>;
 304                         clock-latency-ns = <200000>;
 305                 };
 306                 opp-1478400000 {
 307                         opp-hz = /bits/ 64 <1478400000>;
 308                         opp-supported-hw = <0x77>;
 309                         clock-latency-ns = <200000>;
 310                 };
 311                 opp-1555200000 {
 312                         opp-hz = /bits/ 64 <1555200000>;
 313                         opp-supported-hw = <0x77>;
 314                         clock-latency-ns = <200000>;
 315                 };
 316                 opp-1632000000 {
 317                         opp-hz = /bits/ 64 <1632000000>;
 318                         opp-supported-hw = <0x77>;
 319                         clock-latency-ns = <200000>;
 320                 };
 321                 opp-1708800000 {
 322                         opp-hz = /bits/ 64 <1708800000>;
 323                         opp-supported-hw = <0x77>;
 324                         clock-latency-ns = <200000>;
 325                 };
 326                 opp-1785600000 {
 327                         opp-hz = /bits/ 64 <1785600000>;
 328                         opp-supported-hw = <0x77>;
 329                         clock-latency-ns = <200000>;
 330                 };
 331                 opp-1824000000 {
 332                         opp-hz = /bits/ 64 <1824000000>;
 333                         opp-supported-hw = <0x77>;
 334                         clock-latency-ns = <200000>;
 335                 };
 336                 opp-1920000000 {
 337                         opp-hz = /bits/ 64 <1920000000>;
 338                         opp-supported-hw = <0x77>;
 339                         clock-latency-ns = <200000>;
 340                 };
 341                 opp-1996800000 {
 342                         opp-hz = /bits/ 64 <1996800000>;
 343                         opp-supported-hw = <0x77>;
 344                         clock-latency-ns = <200000>;
 345                 };
 346                 opp-2073600000 {
 347                         opp-hz = /bits/ 64 <2073600000>;
 348                         opp-supported-hw = <0x77>;
 349                         clock-latency-ns = <200000>;
 350                 };
 351                 opp-2150400000 {
 352                         opp-hz = /bits/ 64 <2150400000>;
 353                         opp-supported-hw = <0x77>;
 354                         clock-latency-ns = <200000>;
 355                 };
 356         };
 357
 358         firmware {
 359                 scm {
 360                         compatible = "qcom,scm-msm8996";
 361                         qcom,dload-mode = <&tcsr 0x13000>;
 362                 };
 363         };
 364
 365         tcsr_mutex: hwlock {
 366                 compatible = "qcom,tcsr-mutex";
 367                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 368                 #hwlock-cells = <1>;
 369         };
 370
 371         memory@80000000 {
 372                 device_type = "memory";
 373                 /* We expect the bootloader to fill in the reg */
 374                 reg = <0x0 0x80000000 0x0 0x0>;
 375         };
 376
 377         psci {
 378                 compatible = "arm,psci-1.0";
 379                 method = "smc";
 380         };
 381
 382         reserved-memory {
 383                 #address-cells = <2>;
 384                 #size-cells = <2>;
 385                 ranges;
 386
 387                 mba_region: mba@91500000 {
 388                         reg = <0x0 0x91500000 0x0 0x200000>;
 389                         no-map;
 390                 };
 391
 392                 slpi_region: slpi@90b00000 {
 393                         reg = <0x0 0x90b00000 0x0 0xa00000>;
 394                         no-map;
 395                 };
 396
 397                 venus_region: venus@90400000 {
 398                         reg = <0x0 0x90400000 0x0 0x700000>;
 399                         no-map;
 400                 };
 401
 402                 adsp_region: adsp@8ea00000 {
 403                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
 404                         no-map;
 405                 };
 406
 407                 mpss_region: mpss@88800000 {
 408                         reg = <0x0 0x88800000 0x0 0x6200000>;
 409                         no-map;
 410                 };
 411
 412                 smem_mem: smem-mem@86000000 {
 413                         reg = <0x0 0x86000000 0x0 0x200000>;
 414                         no-map;
 415                 };
 416
 417                 memory@85800000 {
 418                         reg = <0x0 0x85800000 0x0 0x800000>;
 419                         no-map;
 420                 };
 421
 422                 memory@86200000 {
 423                         reg = <0x0 0x86200000 0x0 0x2600000>;
 424                         no-map;
 425                 };
 426
 427                 rmtfs@86700000 {
 428                         compatible = "qcom,rmtfs-mem";
 429
 430                         size = <0x0 0x200000>;
 431                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
 432                         no-map;
 433
 434                         qcom,client-id = <1>;
 435                         qcom,vmid = <15>;
 436                 };
 437
 438                 zap_shader_region: gpu@8f200000 {
 439                         compatible = "shared-dma-pool";
 440                         reg = <0x0 0x90b00000 0x0 0xa00000>;
 441                         no-map;
 442                 };
 443         };
 444
 445         rpm-glink {
 446                 compatible = "qcom,glink-rpm";
 447
 448                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 449
 450                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 451
 452                 mboxes = <&apcs_glb 0>;
 453
 454                 rpm_requests: rpm-requests {
 455                         compatible = "qcom,rpm-msm8996";
 456                         qcom,glink-channels = "rpm_requests";
 457
 458                         rpmcc: qcom,rpmcc {
 459                                 compatible = "qcom,rpmcc-msm8996";
 460                                 #clock-cells = <1>;
 461                         };
 462
 463                         rpmpd: power-controller {
 464                                 compatible = "qcom,msm8996-rpmpd";
 465                                 #power-domain-cells = <1>;
 466                                 operating-points-v2 = <&rpmpd_opp_table>;
 467
 468                                 rpmpd_opp_table: opp-table {
 469                                         compatible = "operating-points-v2";
 470
 471                                         rpmpd_opp1: opp1 {
 472                                                 opp-level = <1>;
 473                                         };
 474
 475                                         rpmpd_opp2: opp2 {
 476                                                 opp-level = <2>;
 477                                         };
 478
 479                                         rpmpd_opp3: opp3 {
 480                                                 opp-level = <3>;
 481                                         };
 482
 483                                         rpmpd_opp4: opp4 {
 484                                                 opp-level = <4>;
 485                                         };
 486
 487                                         rpmpd_opp5: opp5 {
 488                                                 opp-level = <5>;
 489                                         };
 490
 491                                         rpmpd_opp6: opp6 {
 492                                                 opp-level = <6>;
 493                                         };
 494                                 };
 495                         };
 496                 };
 497         };
 498
 499         smem {
 500                 compatible = "qcom,smem";
 501                 memory-region = <&smem_mem>;
 502                 hwlocks = <&tcsr_mutex 3>;
 503         };
 504
 505         smp2p-adsp {
 506                 compatible = "qcom,smp2p";
 507                 qcom,smem = <443>, <429>;
 508
 509                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 510
 511                 mboxes = <&apcs_glb 10>;
 512
 513                 qcom,local-pid = <0>;
 514                 qcom,remote-pid = <2>;
 515
 516                 smp2p_adsp_out: master-kernel {
 517                         qcom,entry-name = "master-kernel";
 518                         #qcom,smem-state-cells = <1>;
 519                 };
 520
 521                 smp2p_adsp_in: slave-kernel {
 522                         qcom,entry-name = "slave-kernel";
 523
 524                         interrupt-controller;
 525                         #interrupt-cells = <2>;
 526                 };
 527         };
 528
 529         smp2p-modem {
 530                 compatible = "qcom,smp2p";
 531                 qcom,smem = <435>, <428>;
 532
 533                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 534
 535                 mboxes = <&apcs_glb 14>;
 536
 537                 qcom,local-pid = <0>;
 538                 qcom,remote-pid = <1>;
 539
 540                 modem_smp2p_out: master-kernel {
 541                         qcom,entry-name = "master-kernel";
 542                         #qcom,smem-state-cells = <1>;
 543                 };
 544
 545                 modem_smp2p_in: slave-kernel {
 546                         qcom,entry-name = "slave-kernel";
 547
 548                         interrupt-controller;
 549                         #interrupt-cells = <2>;
 550                 };
 551         };
 552
 553         smp2p-slpi {
 554                 compatible = "qcom,smp2p";
 555                 qcom,smem = <481>, <430>;
 556
 557                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 558
 559                 mboxes = <&apcs_glb 26>;
 560
 561                 qcom,local-pid = <0>;
 562                 qcom,remote-pid = <3>;
 563
 564                 smp2p_slpi_in: slave-kernel {
 565                         qcom,entry-name = "slave-kernel";
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                 };
 569
 570                 smp2p_slpi_out: master-kernel {
 571                         qcom,entry-name = "master-kernel";
 572                         #qcom,smem-state-cells = <1>;
 573                 };
 574         };
 575
 576         soc: soc {
 577                 #address-cells = <1>;
 578                 #size-cells = <1>;
 579                 ranges = <0 0 0 0xffffffff>;
 580                 compatible = "simple-bus";
 581
 582                 pcie_phy: phy@34000 {
 583                         compatible = "qcom,msm8996-qmp-pcie-phy";
 584                         reg = <0x00034000 0x488>;
 585                         #address-cells = <1>;
 586                         #size-cells = <1>;
 587                         ranges;
 588
 589                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 590                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 591                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 592                         clock-names = "aux", "cfg_ahb", "ref";
 593
 594                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 595                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 596                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 597                         reset-names = "phy", "common", "cfg";
 598                         status = "disabled";
 599
 600                         pciephy_0: phy@35000 {
 601                                 reg = <0x00035000 0x130>,
 602                                       <0x00035200 0x200>,
 603                                       <0x00035400 0x1dc>;
 604                                 #phy-cells = <0>;
 605
 606                                 #clock-cells = <1>;
 607                                 clock-output-names = "pcie_0_pipe_clk_src";
 608                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 609                                 clock-names = "pipe0";
 610                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 611                                 reset-names = "lane0";
 612                         };
 613
 614                         pciephy_1: phy@36000 {
 615                                 reg = <0x00036000 0x130>,
 616                                       <0x00036200 0x200>,
 617                                       <0x00036400 0x1dc>;
 618                                 #phy-cells = <0>;
 619
 620                                 clock-output-names = "pcie_1_pipe_clk_src";
 621                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 622                                 clock-names = "pipe1";
 623                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 624                                 reset-names = "lane1";
 625                         };
 626
 627                         pciephy_2: phy@37000 {
 628                                 reg = <0x00037000 0x130>,
 629                                       <0x00037200 0x200>,
 630                                       <0x00037400 0x1dc>;
 631                                 #phy-cells = <0>;
 632
 633                                 clock-output-names = "pcie_2_pipe_clk_src";
 634                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 635                                 clock-names = "pipe2";
 636                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 637                                 reset-names = "lane2";
 638                         };
 639                 };
 640
 641                 rpm_msg_ram: sram@68000 {
 642                         compatible = "qcom,rpm-msg-ram";
 643                         reg = <0x00068000 0x6000>;
 644                 };
 645
 646                 qfprom@74000 {
 647                         compatible = "qcom,qfprom";
 648                         reg = <0x00074000 0x8ff>;
 649                         #address-cells = <1>;
 650                         #size-cells = <1>;
 651
 652                         qusb2p_hstx_trim: hstx_trim@24e {
 653                                 reg = <0x24e 0x2>;
 654                                 bits = <5 4>;
 655                         };
 656
 657                         qusb2s_hstx_trim: hstx_trim@24f {
 658                                 reg = <0x24f 0x1>;
 659                                 bits = <1 4>;
 660                         };
 661
 662                         speedbin_efuse: speedbin@133 {
 663                                 reg = <0x133 0x1>;
 664                                 bits = <5 3>;
 665                         };
 666                 };
 667
 668                 rng: rng@83000 {
 669                         compatible = "qcom,prng-ee";
 670                         reg = <0x00083000 0x1000>;
 671                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 672                         clock-names = "core";
 673                 };
 674
 675                 gcc: clock-controller@300000 {
 676                         compatible = "qcom,gcc-msm8996";
 677                         #clock-cells = <1>;
 678                         #reset-cells = <1>;
 679                         #power-domain-cells = <1>;
 680                         reg = <0x00300000 0x90000>;
 681
 682                         clocks = <&rpmcc RPM_SMD_BB_CLK1>,
 683                                  <&rpmcc RPM_SMD_LN_BB_CLK>,
 684                                  <&sleep_clk>;
 685                         clock-names = "cxo", "cxo2", "sleep_clk";
 686                 };
 687
 688                 tsens0: thermal-sensor@4a9000 {
 689                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 690                         reg = <0x004a9000 0x1000>, /* TM */
 691                               <0x004a8000 0x1000>; /* SROT */
 692                         #qcom,sensors = <13>;
 693                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 695                         interrupt-names = "uplow", "critical";
 696                         #thermal-sensor-cells = <1>;
 697                 };
 698
 699                 tsens1: thermal-sensor@4ad000 {
 700                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 701                         reg = <0x004ad000 0x1000>, /* TM */
 702                               <0x004ac000 0x1000>; /* SROT */
 703                         #qcom,sensors = <8>;
 704                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 706                         interrupt-names = "uplow", "critical";
 707                         #thermal-sensor-cells = <1>;
 708                 };
 709
 710                 cryptobam: dma@644000 {
 711                         compatible = "qcom,bam-v1.7.0";
 712                         reg = <0x00644000 0x24000>;
 713                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 714                         clocks = <&gcc GCC_CE1_CLK>;
 715                         clock-names = "bam_clk";
 716                         #dma-cells = <1>;
 717                         qcom,ee = <0>;
 718                         qcom,controlled-remotely;
 719                 };
 720
 721                 crypto: crypto@67a000 {
 722                         compatible = "qcom,crypto-v5.4";
 723                         reg = <0x0067a000 0x6000>;
 724                         clocks = <&gcc GCC_CE1_AHB_CLK>,
 725                                  <&gcc GCC_CE1_AXI_CLK>,
 726                                  <&gcc GCC_CE1_CLK>;
 727                         clock-names = "iface", "bus", "core";
 728                         dmas = <&cryptobam 6>, <&cryptobam 7>;
 729                         dma-names = "rx", "tx";
 730                 };
 731
 732                 tcsr_mutex_regs: syscon@740000 {
 733                         compatible = "syscon";
 734                         reg = <0x00740000 0x40000>;
 735                 };
 736
 737                 tcsr: syscon@7a0000 {
 738                         compatible = "qcom,tcsr-msm8996", "syscon";
 739                         reg = <0x007a0000 0x18000>;
 740                 };
 741
 742                 mmcc: clock-controller@8c0000 {
 743                         compatible = "qcom,mmcc-msm8996";
 744                         #clock-cells = <1>;
 745                         #reset-cells = <1>;
 746                         #power-domain-cells = <1>;
 747                         reg = <0x008c0000 0x40000>;
 748                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 749                                           <&mmcc MMPLL1_PLL>,
 750                                           <&mmcc MMPLL3_PLL>,
 751                                           <&mmcc MMPLL4_PLL>,
 752                                           <&mmcc MMPLL5_PLL>;
 753                         assigned-clock-rates = <624000000>,
 754                                                <810000000>,
 755                                                <980000000>,
 756                                                <960000000>,
 757                                                <825000000>;
 758                 };
 759
 760                 mdss: mdss@900000 {
 761                         compatible = "qcom,mdss";
 762
 763                         reg = <0x00900000 0x1000>,
 764                               <0x009b0000 0x1040>,
 765                               <0x009b8000 0x1040>;
 766                         reg-names = "mdss_phys",
 767                                     "vbif_phys",
 768                                     "vbif_nrt_phys";
 769
 770                         power-domains = <&mmcc MDSS_GDSC>;
 771                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 772
 773                         interrupt-controller;
 774                         #interrupt-cells = <1>;
 775
 776                         clocks = <&mmcc MDSS_AHB_CLK>;
 777                         clock-names = "iface";
 778
 779                         #address-cells = <1>;
 780                         #size-cells = <1>;
 781                         ranges;
 782
 783                         status = "disabled";
 784
 785                         mdp: mdp@901000 {
 786                                 compatible = "qcom,mdp5";
 787                                 reg = <0x00901000 0x90000>;
 788                                 reg-names = "mdp_phys";
 789
 790                                 interrupt-parent = <&mdss>;
 791                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 792
 793                                 clocks = <&mmcc MDSS_AHB_CLK>,
 794                                          <&mmcc MDSS_AXI_CLK>,
 795                                          <&mmcc MDSS_MDP_CLK>,
 796                                          <&mmcc SMMU_MDP_AXI_CLK>,
 797                                          <&mmcc MDSS_VSYNC_CLK>;
 798                                 clock-names = "iface",
 799                                               "bus",
 800                                               "core",
 801                                               "iommu",
 802                                               "vsync";
 803
 804                                 iommus = <&mdp_smmu 0>;
 805
 806                                 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
 807                                          <&mmcc MDSS_VSYNC_CLK>;
 808                                 assigned-clock-rates = <300000000>,
 809                                          <19200000>;
 810
 811                                 ports {
 812                                         #address-cells = <1>;
 813                                         #size-cells = <0>;
 814
 815                                         port@0 {
 816                                                 reg = <0>;
 817                                                 mdp5_intf3_out: endpoint {
 818                                                         remote-endpoint = <&hdmi_in>;
 819                                                 };
 820                                         };
 821
 822                                         port@1 {
 823                                                 reg = <1>;
 824                                                 mdp5_intf1_out: endpoint {
 825                                                         remote-endpoint = <&dsi0_in>;
 826                                                 };
 827                                         };
 828                                 };
 829                         };
 830
 831                         dsi0: dsi@994000 {
 832                                 compatible = "qcom,mdss-dsi-ctrl";
 833                                 reg = <0x00994000 0x400>;
 834                                 reg-names = "dsi_ctrl";
 835
 836                                 interrupt-parent = <&mdss>;
 837                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 838
 839                                 clocks = <&mmcc MDSS_MDP_CLK>,
 840                                          <&mmcc MDSS_BYTE0_CLK>,
 841                                          <&mmcc MDSS_AHB_CLK>,
 842                                          <&mmcc MDSS_AXI_CLK>,
 843                                          <&mmcc MMSS_MISC_AHB_CLK>,
 844                                          <&mmcc MDSS_PCLK0_CLK>,
 845                                          <&mmcc MDSS_ESC0_CLK>;
 846                                 clock-names = "mdp_core",
 847                                               "byte",
 848                                               "iface",
 849                                               "bus",
 850                                               "core_mmss",
 851                                               "pixel",
 852                                               "core";
 853
 854                                 phys = <&dsi0_phy>;
 855                                 phy-names = "dsi";
 856                                 status = "disabled";
 857
 858                                 #address-cells = <1>;
 859                                 #size-cells = <0>;
 860
 861                                 ports {
 862                                         #address-cells = <1>;
 863                                         #size-cells = <0>;
 864
 865                                         port@0 {
 866                                                 reg = <0>;
 867                                                 dsi0_in: endpoint {
 868                                                         remote-endpoint = <&mdp5_intf1_out>;
 869                                                 };
 870                                         };
 871
 872                                         port@1 {
 873                                                 reg = <1>;
 874                                                 dsi0_out: endpoint {
 875                                                 };
 876                                         };
 877                                 };
 878                         };
 879
 880                         dsi0_phy: dsi-phy@994400 {
 881                                 compatible = "qcom,dsi-phy-14nm";
 882                                 reg = <0x00994400 0x100>,
 883                                       <0x00994500 0x300>,
 884                                       <0x00994800 0x188>;
 885                                 reg-names = "dsi_phy",
 886                                             "dsi_phy_lane",
 887                                             "dsi_pll";
 888
 889                                 #clock-cells = <1>;
 890                                 #phy-cells = <0>;
 891
 892                                 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
 893                                 clock-names = "iface", "ref";
 894                                 status = "disabled";
 895                         };
 896
 897                         hdmi: hdmi-tx@9a0000 {
 898                                 compatible = "qcom,hdmi-tx-8996";
 899                                 reg =   <0x009a0000 0x50c>,
 900                                         <0x00070000 0x6158>,
 901                                         <0x009e0000 0xfff>;
 902                                 reg-names = "core_physical",
 903                                             "qfprom_physical",
 904                                             "hdcp_physical";
 905
 906                                 interrupt-parent = <&mdss>;
 907                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 908
 909                                 clocks = <&mmcc MDSS_MDP_CLK>,
 910                                          <&mmcc MDSS_AHB_CLK>,
 911                                          <&mmcc MDSS_HDMI_CLK>,
 912                                          <&mmcc MDSS_HDMI_AHB_CLK>,
 913                                          <&mmcc MDSS_EXTPCLK_CLK>;
 914                                 clock-names =
 915                                         "mdp_core",
 916                                         "iface",
 917                                         "core",
 918                                         "alt_iface",
 919                                         "extp";
 920
 921                                 phys = <&hdmi_phy>;
 922                                 phy-names = "hdmi_phy";
 923                                 #sound-dai-cells = <1>;
 924
 925                                 status = "disabled";
 926
 927                                 ports {
 928                                         #address-cells = <1>;
 929                                         #size-cells = <0>;
 930
 931                                         port@0 {
 932                                                 reg = <0>;
 933                                                 hdmi_in: endpoint {
 934                                                         remote-endpoint = <&mdp5_intf3_out>;
 935                                                 };
 936                                         };
 937                                 };
 938                         };
 939
 940                         hdmi_phy: hdmi-phy@9a0600 {
 941                                 #phy-cells = <0>;
 942                                 compatible = "qcom,hdmi-phy-8996";
 943                                 reg = <0x009a0600 0x1c4>,
 944                                       <0x009a0a00 0x124>,
 945                                       <0x009a0c00 0x124>,
 946                                       <0x009a0e00 0x124>,
 947                                       <0x009a1000 0x124>,
 948                                       <0x009a1200 0x0c8>;
 949                                 reg-names = "hdmi_pll",
 950                                             "hdmi_tx_l0",
 951                                             "hdmi_tx_l1",
 952                                             "hdmi_tx_l2",
 953                                             "hdmi_tx_l3",
 954                                             "hdmi_phy";
 955
 956                                 clocks = <&mmcc MDSS_AHB_CLK>,
 957                                          <&gcc GCC_HDMI_CLKREF_CLK>;
 958                                 clock-names = "iface",
 959                                               "ref";
 960
 961                                 status = "disabled";
 962                         };
 963                 };
 964
 965                 gpu: gpu@b00000 {
 966                         compatible = "qcom,adreno-530.2", "qcom,adreno";
 967
 968                         reg = <0x00b00000 0x3f000>;
 969                         reg-names = "kgsl_3d0_reg_memory";
 970
 971                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
 972
 973                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
 974                                 <&mmcc GPU_AHB_CLK>,
 975                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
 976                                 <&gcc GCC_BIMC_GFX_CLK>,
 977                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
 978
 979                         clock-names = "core",
 980                                 "iface",
 981                                 "rbbmtimer",
 982                                 "mem",
 983                                 "mem_iface";
 984
 985                         power-domains = <&mmcc GPU_GX_GDSC>;
 986                         iommus = <&adreno_smmu 0>;
 987
 988                         nvmem-cells = <&speedbin_efuse>;
 989                         nvmem-cell-names = "speed_bin";
 990
 991                         operating-points-v2 = <&gpu_opp_table>;
 992
 993                         status = "disabled";
 994
 995                         #cooling-cells = <2>;
 996
 997                         gpu_opp_table: opp-table {
 998                                 compatible  ="operating-points-v2";
 999
1000                                 /*
1001                                  * 624Mhz and 560Mhz are only available on speed
1002                                  * bin (1 << 0). All the rest are available on
1003                                  * all bins of the hardware
1004                                  */
1005                                 opp-624000000 {
1006                                         opp-hz = /bits/ 64 <624000000>;
1007                                         opp-supported-hw = <0x01>;
1008                                 };
1009                                 opp-560000000 {
1010                                         opp-hz = /bits/ 64 <560000000>;
1011                                         opp-supported-hw = <0x01>;
1012                                 };
1013                                 opp-510000000 {
1014                                         opp-hz = /bits/ 64 <510000000>;
1015                                         opp-supported-hw = <0xFF>;
1016                                 };
1017                                 opp-401800000 {
1018                                         opp-hz = /bits/ 64 <401800000>;
1019                                         opp-supported-hw = <0xFF>;
1020                                 };
1021                                 opp-315000000 {
1022                                         opp-hz = /bits/ 64 <315000000>;
1023                                         opp-supported-hw = <0xFF>;
1024                                 };
1025                                 opp-214000000 {
1026                                         opp-hz = /bits/ 64 <214000000>;
1027                                         opp-supported-hw = <0xFF>;
1028                                 };
1029                                 opp-133000000 {
1030                                         opp-hz = /bits/ 64 <133000000>;
1031                                         opp-supported-hw = <0xFF>;
1032                                 };
1033                         };
1034
1035                         zap-shader {
1036                                 memory-region = <&zap_shader_region>;
1037                         };
1038                 };
1039
1040                 tlmm: pinctrl@1010000 {
1041                         compatible = "qcom,msm8996-pinctrl";
1042                         reg = <0x01010000 0x300000>;
1043                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1044                         gpio-controller;
1045                         gpio-ranges = <&tlmm 0 0 150>;
1046                         #gpio-cells = <2>;
1047                         interrupt-controller;
1048                         #interrupt-cells = <2>;
1049
1050                         blsp1_spi1_default: blsp1-spi1-default {
1051                                 spi {
1052                                         pins = "gpio0", "gpio1", "gpio3";
1053                                         function = "blsp_spi1";
1054                                         drive-strength = <12>;
1055                                         bias-disable;
1056                                 };
1057
1058                                 cs {
1059                                         pins = "gpio2";
1060                                         function = "gpio";
1061                                         drive-strength = <16>;
1062                                         bias-disable;
1063                                         output-high;
1064                                 };
1065                         };
1066
1067                         blsp1_spi1_sleep: blsp1-spi1-sleep {
1068                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1069                                 function = "gpio";
1070                                 drive-strength = <2>;
1071                                 bias-pull-down;
1072                         };
1073
1074                         blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1075                                 pins = "gpio4", "gpio5";
1076                                 function = "blsp_uart8";
1077                                 drive-strength = <16>;
1078                                 bias-disable;
1079                         };
1080
1081                         blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1082                                 pins = "gpio4", "gpio5";
1083                                 function = "gpio";
1084                                 drive-strength = <2>;
1085                                 bias-disable;
1086                         };
1087
1088                         blsp2_i2c2_default: blsp2-i2c2 {
1089                                 pins = "gpio6", "gpio7";
1090                                 function = "blsp_i2c8";
1091                                 drive-strength = <16>;
1092                                 bias-disable;
1093                         };
1094
1095                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1096                                 pins = "gpio6", "gpio7";
1097                                 function = "gpio";
1098                                 drive-strength = <2>;
1099                                 bias-disable;
1100                         };
1101
1102                         cci0_default: cci0-default {
1103                                 pins = "gpio17", "gpio18";
1104                                 function = "cci_i2c";
1105                                 drive-strength = <16>;
1106                                 bias-disable;
1107                         };
1108
1109                         camera0_state_on:
1110                         camera_rear_default: camera-rear-default {
1111                                 camera0_mclk: mclk0 {
1112                                         pins = "gpio13";
1113                                         function = "cam_mclk";
1114                                         drive-strength = <16>;
1115                                         bias-disable;
1116                                 };
1117
1118                                 camera0_rst: rst {
1119                                         pins = "gpio25";
1120                                         function = "gpio";
1121                                         drive-strength = <16>;
1122                                         bias-disable;
1123                                 };
1124
1125                                 camera0_pwdn: pwdn {
1126                                         pins = "gpio26";
1127                                         function = "gpio";
1128                                         drive-strength = <16>;
1129                                         bias-disable;
1130                                 };
1131                         };
1132
1133                         cci1_default: cci1-default {
1134                                 pins = "gpio19", "gpio20";
1135                                 function = "cci_i2c";
1136                                 drive-strength = <16>;
1137                                 bias-disable;
1138                         };
1139
1140                         camera1_state_on:
1141                         camera_board_default: camera-board-default {
1142                                 mclk1 {
1143                                         pins = "gpio14";
1144                                         function = "cam_mclk";
1145                                         drive-strength = <16>;
1146                                         bias-disable;
1147                                 };
1148
1149                                 pwdn {
1150                                         pins = "gpio98";
1151                                         function = "gpio";
1152                                         drive-strength = <16>;
1153                                         bias-disable;
1154                                 };
1155
1156                                 rst {
1157                                         pins = "gpio104";
1158                                         function = "gpio";
1159                                         drive-strength = <16>;
1160                                         bias-disable;
1161                                 };
1162                         };
1163
1164                         camera2_state_on:
1165                         camera_front_default: camera-front-default {
1166                                 camera2_mclk: mclk2 {
1167                                         pins = "gpio15";
1168                                         function = "cam_mclk";
1169                                         drive-strength = <16>;
1170                                         bias-disable;
1171                                 };
1172
1173                                 camera2_rst: rst {
1174                                         pins = "gpio23";
1175                                         function = "gpio";
1176                                         drive-strength = <16>;
1177                                         bias-disable;
1178                                 };
1179
1180                                 pwdn {
1181                                         pins = "gpio133";
1182                                         function = "gpio";
1183                                         drive-strength = <16>;
1184                                         bias-disable;
1185                                 };
1186                         };
1187
1188                         pcie0_state_on: pcie0-state-on {
1189                                 perst {
1190                                         pins = "gpio35";
1191                                         function = "gpio";
1192                                         drive-strength = <2>;
1193                                         bias-pull-down;
1194                                 };
1195
1196                                 clkreq {
1197                                         pins = "gpio36";
1198                                         function = "pci_e0";
1199                                         drive-strength = <2>;
1200                                         bias-pull-up;
1201                                 };
1202
1203                                 wake {
1204                                         pins = "gpio37";
1205                                         function = "gpio";
1206                                         drive-strength = <2>;
1207                                         bias-pull-up;
1208                                 };
1209                         };
1210
1211                         pcie0_state_off: pcie0-state-off {
1212                                 perst {
1213                                         pins = "gpio35";
1214                                         function = "gpio";
1215                                         drive-strength = <2>;
1216                                         bias-pull-down;
1217                                 };
1218
1219                                 clkreq {
1220                                         pins = "gpio36";
1221                                         function = "gpio";
1222                                         drive-strength = <2>;
1223                                         bias-disable;
1224                                 };
1225
1226                                 wake {
1227                                         pins = "gpio37";
1228                                         function = "gpio";
1229                                         drive-strength = <2>;
1230                                         bias-disable;
1231                                 };
1232                         };
1233
1234                         blsp1_uart2_default: blsp1-uart2-default {
1235                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1236                                 function = "blsp_uart2";
1237                                 drive-strength = <16>;
1238                                 bias-disable;
1239                         };
1240
1241                         blsp1_uart2_sleep: blsp1-uart2-sleep {
1242                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1243                                 function = "gpio";
1244                                 drive-strength = <2>;
1245                                 bias-disable;
1246                         };
1247
1248                         blsp1_i2c3_default: blsp1-i2c2-default {
1249                                 pins = "gpio47", "gpio48";
1250                                 function = "blsp_i2c3";
1251                                 drive-strength = <16>;
1252                                 bias-disable;
1253                         };
1254
1255                         blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1256                                 pins = "gpio47", "gpio48";
1257                                 function = "gpio";
1258                                 drive-strength = <2>;
1259                                 bias-disable;
1260                         };
1261
1262                         blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1263                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1264                                 function = "blsp_uart9";
1265                                 drive-strength = <16>;
1266                                 bias-disable;
1267                         };
1268
1269                         blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1270                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1271                                 function = "blsp_uart9";
1272                                 drive-strength = <2>;
1273                                 bias-disable;
1274                         };
1275
1276                         blsp2_i2c3_default: blsp2-i2c3 {
1277                                 pins = "gpio51", "gpio52";
1278                                 function = "blsp_i2c9";
1279                                 drive-strength = <16>;
1280                                 bias-disable;
1281                         };
1282
1283                         blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1284                                 pins = "gpio51", "gpio52";
1285                                 function = "gpio";
1286                                 drive-strength = <2>;
1287                                 bias-disable;
1288                         };
1289
1290                         wcd_intr_default: wcd-intr-default{
1291                                 pins = "gpio54";
1292                                 function = "gpio";
1293                                 drive-strength = <2>;
1294                                 bias-pull-down;
1295                                 input-enable;
1296                         };
1297
1298                         blsp2_i2c1_default: blsp2-i2c1 {
1299                                 pins = "gpio55", "gpio56";
1300                                 function = "blsp_i2c7";
1301                                 drive-strength = <16>;
1302                                 bias-disable;
1303                         };
1304
1305                         blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1306                                 pins = "gpio55", "gpio56";
1307                                 function = "gpio";
1308                                 drive-strength = <2>;
1309                                 bias-disable;
1310                         };
1311
1312                         blsp2_i2c5_default: blsp2-i2c5 {
1313                                 pins = "gpio60", "gpio61";
1314                                 function = "blsp_i2c11";
1315                                 drive-strength = <2>;
1316                                 bias-disable;
1317                         };
1318
1319                         /* Sleep state for BLSP2_I2C5 is missing.. */
1320
1321                         cdc_reset_active: cdc-reset-active {
1322                                 pins = "gpio64";
1323                                 function = "gpio";
1324                                 drive-strength = <16>;
1325                                 bias-pull-down;
1326                                 output-high;
1327                         };
1328
1329                         cdc_reset_sleep: cdc-reset-sleep {
1330                                 pins = "gpio64";
1331                                 function = "gpio";
1332                                 drive-strength = <16>;
1333                                 bias-disable;
1334                                 output-low;
1335                         };
1336
1337                         blsp2_spi6_default: blsp2-spi5-default {
1338                                 spi {
1339                                         pins = "gpio85", "gpio86", "gpio88";
1340                                         function = "blsp_spi12";
1341                                         drive-strength = <12>;
1342                                         bias-disable;
1343                                 };
1344
1345                                 cs {
1346                                         pins = "gpio87";
1347                                         function = "gpio";
1348                                         drive-strength = <16>;
1349                                         bias-disable;
1350                                         output-high;
1351                                 };
1352                         };
1353
1354                         blsp2_spi6_sleep: blsp2-spi5-sleep {
1355                                 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1356                                 function = "gpio";
1357                                 drive-strength = <2>;
1358                                 bias-pull-down;
1359                         };
1360
1361                         blsp2_i2c6_default: blsp2-i2c6 {
1362                                 pins = "gpio87", "gpio88";
1363                                 function = "blsp_i2c12";
1364                                 drive-strength = <16>;
1365                                 bias-disable;
1366                         };
1367
1368                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1369                                 pins = "gpio87", "gpio88";
1370                                 function = "gpio";
1371                                 drive-strength = <2>;
1372                                 bias-disable;
1373                         };
1374
1375                         pcie1_state_on: pcie1-state-on {
1376                                 perst {
1377                                         pins = "gpio130";
1378                                         function = "gpio";
1379                                         drive-strength = <2>;
1380                                         bias-pull-down;
1381                                 };
1382
1383                                 clkreq {
1384                                         pins = "gpio131";
1385                                         function = "pci_e1";
1386                                         drive-strength = <2>;
1387                                         bias-pull-up;
1388                                 };
1389
1390                                 wake {
1391                                         pins = "gpio132";
1392                                         function = "gpio";
1393                                         drive-strength = <2>;
1394                                         bias-pull-down;
1395                                 };
1396                         };
1397
1398                         pcie1_state_off: pcie1-state-off {
1399                                 /* Perst is missing? */
1400                                 clkreq {
1401                                         pins = "gpio131";
1402                                         function = "gpio";
1403                                         drive-strength = <2>;
1404                                         bias-disable;
1405                                 };
1406
1407                                 wake {
1408                                         pins = "gpio132";
1409                                         function = "gpio";
1410                                         drive-strength = <2>;
1411                                         bias-disable;
1412                                 };
1413                         };
1414
1415                         pcie2_state_on: pcie2-state-on {
1416                                 perst {
1417                                         pins = "gpio114";
1418                                         function = "gpio";
1419                                         drive-strength = <2>;
1420                                         bias-pull-down;
1421                                 };
1422
1423                                 clkreq {
1424                                         pins = "gpio115";
1425                                         function = "pci_e2";
1426                                         drive-strength = <2>;
1427                                         bias-pull-up;
1428                                 };
1429
1430                                 wake {
1431                                         pins = "gpio116";
1432                                         function = "gpio";
1433                                         drive-strength = <2>;
1434                                         bias-pull-down;
1435                                 };
1436                         };
1437
1438                         pcie2_state_off: pcie2-state-off {
1439                                 /* Perst is missing? */
1440                                 clkreq {
1441                                         pins = "gpio115";
1442                                         function = "gpio";
1443                                         drive-strength = <2>;
1444                                         bias-disable;
1445                                 };
1446
1447                                 wake {
1448                                         pins = "gpio116";
1449                                         function = "gpio";
1450                                         drive-strength = <2>;
1451                                         bias-disable;
1452                                 };
1453                         };
1454
1455                         sdc1_state_on: sdc1-state-on {
1456                                 clk {
1457                                         pins = "sdc1_clk";
1458                                         bias-disable;
1459                                         drive-strength = <16>;
1460                                 };
1461
1462                                 cmd {
1463                                         pins = "sdc1_cmd";
1464                                         bias-pull-up;
1465                                         drive-strength = <10>;
1466                                 };
1467
1468                                 data {
1469                                         pins = "sdc1_data";
1470                                         bias-pull-up;
1471                                         drive-strength = <10>;
1472                                 };
1473
1474                                 rclk {
1475                                         pins = "sdc1_rclk";
1476                                         bias-pull-down;
1477                                 };
1478                         };
1479
1480                         sdc1_state_off: sdc1-state-off {
1481                                 clk {
1482                                         pins = "sdc1_clk";
1483                                         bias-disable;
1484                                         drive-strength = <2>;
1485                                 };
1486
1487                                 cmd {
1488                                         pins = "sdc1_cmd";
1489                                         bias-pull-up;
1490                                         drive-strength = <2>;
1491                                 };
1492
1493                                 data {
1494                                         pins = "sdc1_data";
1495                                         bias-pull-up;
1496                                         drive-strength = <2>;
1497                                 };
1498
1499                                 rclk {
1500                                         pins = "sdc1_rclk";
1501                                         bias-pull-down;
1502                                 };
1503                         };
1504
1505                         sdc2_state_on: sdc2-clk-on {
1506                                 clk {
1507                                         pins = "sdc2_clk";
1508                                         bias-disable;
1509                                         drive-strength = <16>;
1510                                 };
1511
1512                                 cmd {
1513                                         pins = "sdc2_cmd";
1514                                         bias-pull-up;
1515                                         drive-strength = <10>;
1516                                 };
1517
1518                                 data {
1519                                         pins = "sdc2_data";
1520                                         bias-pull-up;
1521                                         drive-strength = <10>;
1522                                 };
1523                         };
1524
1525                         sdc2_state_off: sdc2-clk-off {
1526                                 clk {
1527                                         pins = "sdc2_clk";
1528                                         bias-disable;
1529                                         drive-strength = <2>;
1530                                 };
1531
1532                                 cmd {
1533                                         pins = "sdc2_cmd";
1534                                         bias-pull-up;
1535                                         drive-strength = <2>;
1536                                 };
1537
1538                                 data {
1539                                         pins = "sdc2_data";
1540                                         bias-pull-up;
1541                                         drive-strength = <2>;
1542                                 };
1543                         };
1544                 };
1545
1546                 sram@290000 {
1547                         compatible = "qcom,rpm-stats";
1548                         reg = <0x00290000 0x10000>;
1549                 };
1550
1551                 spmi_bus: spmi@400f000 {
1552                         compatible = "qcom,spmi-pmic-arb";
1553                         reg = <0x0400f000 0x1000>,
1554                               <0x04400000 0x800000>,
1555                               <0x04c00000 0x800000>,
1556                               <0x05800000 0x200000>,
1557                               <0x0400a000 0x002100>;
1558                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1559                         interrupt-names = "periph_irq";
1560                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1561                         qcom,ee = <0>;
1562                         qcom,channel = <0>;
1563                         #address-cells = <2>;
1564                         #size-cells = <0>;
1565                         interrupt-controller;
1566                         #interrupt-cells = <4>;
1567                 };
1568
1569                 agnoc@0 {
1570                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1571                         compatible = "simple-pm-bus";
1572                         #address-cells = <1>;
1573                         #size-cells = <1>;
1574                         ranges;
1575
1576                         pcie0: pcie@600000 {
1577                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1578                                 status = "disabled";
1579                                 power-domains = <&gcc PCIE0_GDSC>;
1580                                 bus-range = <0x00 0xff>;
1581                                 num-lanes = <1>;
1582
1583                                 reg = <0x00600000 0x2000>,
1584                                       <0x0c000000 0xf1d>,
1585                                       <0x0c000f20 0xa8>,
1586                                       <0x0c100000 0x100000>;
1587                                 reg-names = "parf", "dbi", "elbi","config";
1588
1589                                 phys = <&pciephy_0>;
1590                                 phy-names = "pciephy";
1591
1592                                 #address-cells = <3>;
1593                                 #size-cells = <2>;
1594                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1595                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1596
1597                                 device_type = "pci";
1598
1599                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1600                                 interrupt-names = "msi";
1601                                 #interrupt-cells = <1>;
1602                                 interrupt-map-mask = <0 0 0 0x7>;
1603                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1604                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1605                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1606                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1607
1608                                 pinctrl-names = "default", "sleep";
1609                                 pinctrl-0 = <&pcie0_state_on>;
1610                                 pinctrl-1 = <&pcie0_state_off>;
1611
1612                                 linux,pci-domain = <0>;
1613
1614                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1615                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1616                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1617                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1618                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1619
1620                                 clock-names =  "pipe",
1621                                                 "aux",
1622                                                 "cfg",
1623                                                 "bus_master",
1624                                                 "bus_slave";
1625
1626                         };
1627
1628                         pcie1: pcie@608000 {
1629                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1630                                 power-domains = <&gcc PCIE1_GDSC>;
1631                                 bus-range = <0x00 0xff>;
1632                                 num-lanes = <1>;
1633
1634                                 status  = "disabled";
1635
1636                                 reg = <0x00608000 0x2000>,
1637                                       <0x0d000000 0xf1d>,
1638                                       <0x0d000f20 0xa8>,
1639                                       <0x0d100000 0x100000>;
1640
1641                                 reg-names = "parf", "dbi", "elbi","config";
1642
1643                                 phys = <&pciephy_1>;
1644                                 phy-names = "pciephy";
1645
1646                                 #address-cells = <3>;
1647                                 #size-cells = <2>;
1648                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1649                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1650
1651                                 device_type = "pci";
1652
1653                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1654                                 interrupt-names = "msi";
1655                                 #interrupt-cells = <1>;
1656                                 interrupt-map-mask = <0 0 0 0x7>;
1657                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1658                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1659                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1660                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1661
1662                                 pinctrl-names = "default", "sleep";
1663                                 pinctrl-0 = <&pcie1_state_on>;
1664                                 pinctrl-1 = <&pcie1_state_off>;
1665
1666                                 linux,pci-domain = <1>;
1667
1668                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1669                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1670                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1671                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1672                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1673
1674                                 clock-names =  "pipe",
1675                                                 "aux",
1676                                                 "cfg",
1677                                                 "bus_master",
1678                                                 "bus_slave";
1679                         };
1680
1681                         pcie2: pcie@610000 {
1682                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1683                                 power-domains = <&gcc PCIE2_GDSC>;
1684                                 bus-range = <0x00 0xff>;
1685                                 num-lanes = <1>;
1686                                 status = "disabled";
1687                                 reg = <0x00610000 0x2000>,
1688                                       <0x0e000000 0xf1d>,
1689                                       <0x0e000f20 0xa8>,
1690                                       <0x0e100000 0x100000>;
1691
1692                                 reg-names = "parf", "dbi", "elbi","config";
1693
1694                                 phys = <&pciephy_2>;
1695                                 phy-names = "pciephy";
1696
1697                                 #address-cells = <3>;
1698                                 #size-cells = <2>;
1699                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1700                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1701
1702                                 device_type = "pci";
1703
1704                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1705                                 interrupt-names = "msi";
1706                                 #interrupt-cells = <1>;
1707                                 interrupt-map-mask = <0 0 0 0x7>;
1708                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1709                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1710                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1711                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1712
1713                                 pinctrl-names = "default", "sleep";
1714                                 pinctrl-0 = <&pcie2_state_on>;
1715                                 pinctrl-1 = <&pcie2_state_off>;
1716
1717                                 linux,pci-domain = <2>;
1718                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1719                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1720                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1721                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1722                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1723
1724                                 clock-names =  "pipe",
1725                                                 "aux",
1726                                                 "cfg",
1727                                                 "bus_master",
1728                                                 "bus_slave";
1729                         };
1730                 };
1731
1732                 ufshc: ufshc@624000 {
1733                         compatible = "qcom,ufshc";
1734                         reg = <0x00624000 0x2500>;
1735                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1736
1737                         phys = <&ufsphy_lane>;
1738                         phy-names = "ufsphy";
1739
1740                         power-domains = <&gcc UFS_GDSC>;
1741
1742                         clock-names =
1743                                 "core_clk_src",
1744                                 "core_clk",
1745                                 "bus_clk",
1746                                 "bus_aggr_clk",
1747                                 "iface_clk",
1748                                 "core_clk_unipro_src",
1749                                 "core_clk_unipro",
1750                                 "core_clk_ice",
1751                                 "ref_clk",
1752                                 "tx_lane0_sync_clk",
1753                                 "rx_lane0_sync_clk";
1754                         clocks =
1755                                 <&gcc UFS_AXI_CLK_SRC>,
1756                                 <&gcc GCC_UFS_AXI_CLK>,
1757                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1758                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1759                                 <&gcc GCC_UFS_AHB_CLK>,
1760                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
1761                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1762                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
1763                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
1764                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1765                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1766                         freq-table-hz =
1767                                 <100000000 200000000>,
1768                                 <0 0>,
1769                                 <0 0>,
1770                                 <0 0>,
1771                                 <0 0>,
1772                                 <150000000 300000000>,
1773                                 <0 0>,
1774                                 <0 0>,
1775                                 <0 0>,
1776                                 <0 0>,
1777                                 <0 0>;
1778
1779                         lanes-per-direction = <1>;
1780                         #reset-cells = <1>;
1781                         status = "disabled";
1782
1783                         ufs_variant {
1784                                 compatible = "qcom,ufs_variant";
1785                         };
1786                 };
1787
1788                 ufsphy: phy@627000 {
1789                         compatible = "qcom,msm8996-qmp-ufs-phy";
1790                         reg = <0x00627000 0x1c4>;
1791                         #address-cells = <1>;
1792                         #size-cells = <1>;
1793                         ranges;
1794
1795                         clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1796                         clock-names = "ref";
1797
1798                         resets = <&ufshc 0>;
1799                         reset-names = "ufsphy";
1800                         status = "disabled";
1801
1802                         ufsphy_lane: phy@627400 {
1803                                 reg = <0x627400 0x12c>,
1804                                       <0x627600 0x200>,
1805                                       <0x627c00 0x1b4>;
1806                                 #phy-cells = <0>;
1807                         };
1808                 };
1809
1810                 camss: camss@a00000 {
1811                         compatible = "qcom,msm8996-camss";
1812                         reg = <0x00a34000 0x1000>,
1813                               <0x00a00030 0x4>,
1814                               <0x00a35000 0x1000>,
1815                               <0x00a00038 0x4>,
1816                               <0x00a36000 0x1000>,
1817                               <0x00a00040 0x4>,
1818                               <0x00a30000 0x100>,
1819                               <0x00a30400 0x100>,
1820                               <0x00a30800 0x100>,
1821                               <0x00a30c00 0x100>,
1822                               <0x00a31000 0x500>,
1823                               <0x00a00020 0x10>,
1824                               <0x00a10000 0x1000>,
1825                               <0x00a14000 0x1000>;
1826                         reg-names = "csiphy0",
1827                                 "csiphy0_clk_mux",
1828                                 "csiphy1",
1829                                 "csiphy1_clk_mux",
1830                                 "csiphy2",
1831                                 "csiphy2_clk_mux",
1832                                 "csid0",
1833                                 "csid1",
1834                                 "csid2",
1835                                 "csid3",
1836                                 "ispif",
1837                                 "csi_clk_mux",
1838                                 "vfe0",
1839                                 "vfe1";
1840                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1841                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1842                                 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1843                                 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1844                                 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1845                                 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1846                                 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1847                                 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1848                                 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1849                                 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1850                         interrupt-names = "csiphy0",
1851                                 "csiphy1",
1852                                 "csiphy2",
1853                                 "csid0",
1854                                 "csid1",
1855                                 "csid2",
1856                                 "csid3",
1857                                 "ispif",
1858                                 "vfe0",
1859                                 "vfe1";
1860                         power-domains = <&mmcc VFE0_GDSC>,
1861                                         <&mmcc VFE1_GDSC>;
1862                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1863                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1864                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1865                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1866                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1867                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1868                                 <&mmcc CAMSS_CSI0_CLK>,
1869                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1870                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1871                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1872                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1873                                 <&mmcc CAMSS_CSI1_CLK>,
1874                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1875                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1876                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1877                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1878                                 <&mmcc CAMSS_CSI2_CLK>,
1879                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1880                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1881                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1882                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1883                                 <&mmcc CAMSS_CSI3_CLK>,
1884                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1885                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1886                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1887                                 <&mmcc CAMSS_AHB_CLK>,
1888                                 <&mmcc CAMSS_VFE0_CLK>,
1889                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1890                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1891                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1892                                 <&mmcc CAMSS_VFE1_CLK>,
1893                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1894                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1895                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1896                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1897                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1898                         clock-names = "top_ahb",
1899                                 "ispif_ahb",
1900                                 "csiphy0_timer",
1901                                 "csiphy1_timer",
1902                                 "csiphy2_timer",
1903                                 "csi0_ahb",
1904                                 "csi0",
1905                                 "csi0_phy",
1906                                 "csi0_pix",
1907                                 "csi0_rdi",
1908                                 "csi1_ahb",
1909                                 "csi1",
1910                                 "csi1_phy",
1911                                 "csi1_pix",
1912                                 "csi1_rdi",
1913                                 "csi2_ahb",
1914                                 "csi2",
1915                                 "csi2_phy",
1916                                 "csi2_pix",
1917                                 "csi2_rdi",
1918                                 "csi3_ahb",
1919                                 "csi3",
1920                                 "csi3_phy",
1921                                 "csi3_pix",
1922                                 "csi3_rdi",
1923                                 "ahb",
1924                                 "vfe0",
1925                                 "csi_vfe0",
1926                                 "vfe0_ahb",
1927                                 "vfe0_stream",
1928                                 "vfe1",
1929                                 "csi_vfe1",
1930                                 "vfe1_ahb",
1931                                 "vfe1_stream",
1932                                 "vfe_ahb",
1933                                 "vfe_axi";
1934                         iommus = <&vfe_smmu 0>,
1935                                  <&vfe_smmu 1>,
1936                                  <&vfe_smmu 2>,
1937                                  <&vfe_smmu 3>;
1938                         status = "disabled";
1939                         ports {
1940                                 #address-cells = <1>;
1941                                 #size-cells = <0>;
1942                         };
1943                 };
1944
1945                 cci: cci@a0c000 {
1946                         compatible = "qcom,msm8996-cci";
1947                         #address-cells = <1>;
1948                         #size-cells = <0>;
1949                         reg = <0xa0c000 0x1000>;
1950                         interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1951                         power-domains = <&mmcc CAMSS_GDSC>;
1952                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1953                                  <&mmcc CAMSS_CCI_AHB_CLK>,
1954                                  <&mmcc CAMSS_CCI_CLK>,
1955                                  <&mmcc CAMSS_AHB_CLK>;
1956                         clock-names = "camss_top_ahb",
1957                                       "cci_ahb",
1958                                       "cci",
1959                                       "camss_ahb";
1960                         assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1961                                           <&mmcc CAMSS_CCI_CLK>;
1962                         assigned-clock-rates = <80000000>, <37500000>;
1963                         pinctrl-names = "default";
1964                         pinctrl-0 = <&cci0_default &cci1_default>;
1965                         status = "disabled";
1966
1967                         cci_i2c0: i2c-bus@0 {
1968                                 reg = <0>;
1969                                 clock-frequency = <400000>;
1970                                 #address-cells = <1>;
1971                                 #size-cells = <0>;
1972                         };
1973
1974                         cci_i2c1: i2c-bus@1 {
1975                                 reg = <1>;
1976                                 clock-frequency = <400000>;
1977                                 #address-cells = <1>;
1978                                 #size-cells = <0>;
1979                         };
1980                 };
1981
1982                 adreno_smmu: iommu@b40000 {
1983                         compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1984                         reg = <0x00b40000 0x10000>;
1985
1986                         #global-interrupts = <1>;
1987                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1988                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1989                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1990                         #iommu-cells = <1>;
1991
1992                         clocks = <&mmcc GPU_AHB_CLK>,
1993                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1994                         clock-names = "iface", "bus";
1995
1996                         power-domains = <&mmcc GPU_GDSC>;
1997                 };
1998
1999                 venus: video-codec@c00000 {
2000                         compatible = "qcom,msm8996-venus";
2001                         reg = <0x00c00000 0xff000>;
2002                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2003                         power-domains = <&mmcc VENUS_GDSC>;
2004                         clocks = <&mmcc VIDEO_CORE_CLK>,
2005                                  <&mmcc VIDEO_AHB_CLK>,
2006                                  <&mmcc VIDEO_AXI_CLK>,
2007                                  <&mmcc VIDEO_MAXI_CLK>;
2008                         clock-names = "core", "iface", "bus", "mbus";
2009                         iommus = <&venus_smmu 0x00>,
2010                                  <&venus_smmu 0x01>,
2011                                  <&venus_smmu 0x0a>,
2012                                  <&venus_smmu 0x07>,
2013                                  <&venus_smmu 0x0e>,
2014                                  <&venus_smmu 0x0f>,
2015                                  <&venus_smmu 0x08>,
2016                                  <&venus_smmu 0x09>,
2017                                  <&venus_smmu 0x0b>,
2018                                  <&venus_smmu 0x0c>,
2019                                  <&venus_smmu 0x0d>,
2020                                  <&venus_smmu 0x10>,
2021                                  <&venus_smmu 0x11>,
2022                                  <&venus_smmu 0x21>,
2023                                  <&venus_smmu 0x28>,
2024                                  <&venus_smmu 0x29>,
2025                                  <&venus_smmu 0x2b>,
2026                                  <&venus_smmu 0x2c>,
2027                                  <&venus_smmu 0x2d>,
2028                                  <&venus_smmu 0x31>;
2029                         memory-region = <&venus_region>;
2030                         status = "disabled";
2031
2032                         video-decoder {
2033                                 compatible = "venus-decoder";
2034                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2035                                 clock-names = "core";
2036                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2037                         };
2038
2039                         video-encoder {
2040                                 compatible = "venus-encoder";
2041                                 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2042                                 clock-names = "core";
2043                                 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2044                         };
2045                 };
2046
2047                 mdp_smmu: iommu@d00000 {
2048                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2049                         reg = <0x00d00000 0x10000>;
2050
2051                         #global-interrupts = <1>;
2052                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2053                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2054                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2055                         #iommu-cells = <1>;
2056                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2057                                  <&mmcc SMMU_MDP_AXI_CLK>;
2058                         clock-names = "iface", "bus";
2059
2060                         power-domains = <&mmcc MDSS_GDSC>;
2061                 };
2062
2063                 venus_smmu: iommu@d40000 {
2064                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2065                         reg = <0x00d40000 0x20000>;
2066                         #global-interrupts = <1>;
2067                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2068                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2069                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2070                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2071                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2072                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2073                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2074                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2075                         power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2076                         clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2077                                  <&mmcc SMMU_VIDEO_AXI_CLK>;
2078                         clock-names = "iface", "bus";
2079                         #iommu-cells = <1>;
2080                         status = "okay";
2081                 };
2082
2083                 vfe_smmu: iommu@da0000 {
2084                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2085                         reg = <0x00da0000 0x10000>;
2086
2087                         #global-interrupts = <1>;
2088                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2089                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2090                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2091                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2092                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2093                                  <&mmcc SMMU_VFE_AXI_CLK>;
2094                         clock-names = "iface",
2095                                       "bus";
2096                         #iommu-cells = <1>;
2097                 };
2098
2099                 lpass_q6_smmu: iommu@1600000 {
2100                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2101                         reg = <0x01600000 0x20000>;
2102                         #iommu-cells = <1>;
2103                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2104
2105                         #global-interrupts = <1>;
2106                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2107                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2108                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2109                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2110                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2111                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2112                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2113                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2114                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2115                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2116                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2117                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2118                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2119
2120                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2121                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2122                         clock-names = "iface", "bus";
2123                 };
2124
2125                 stm@3002000 {
2126                         compatible = "arm,coresight-stm", "arm,primecell";
2127                         reg = <0x3002000 0x1000>,
2128                               <0x8280000 0x180000>;
2129                         reg-names = "stm-base", "stm-stimulus-base";
2130
2131                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2132                         clock-names = "apb_pclk", "atclk";
2133
2134                         out-ports {
2135                                 port {
2136                                         stm_out: endpoint {
2137                                                 remote-endpoint =
2138                                                   <&funnel0_in>;
2139                                         };
2140                                 };
2141                         };
2142                 };
2143
2144                 tpiu@3020000 {
2145                         compatible = "arm,coresight-tpiu", "arm,primecell";
2146                         reg = <0x3020000 0x1000>;
2147
2148                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2149                         clock-names = "apb_pclk", "atclk";
2150
2151                         in-ports {
2152                                 port {
2153                                         tpiu_in: endpoint {
2154                                                 remote-endpoint =
2155                                                   <&replicator_out1>;
2156                                         };
2157                                 };
2158                         };
2159                 };
2160
2161                 funnel@3021000 {
2162                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2163                         reg = <0x3021000 0x1000>;
2164
2165                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2166                         clock-names = "apb_pclk", "atclk";
2167
2168                         in-ports {
2169                                 #address-cells = <1>;
2170                                 #size-cells = <0>;
2171
2172                                 port@7 {
2173                                         reg = <7>;
2174                                         funnel0_in: endpoint {
2175                                                 remote-endpoint =
2176                                                   <&stm_out>;
2177                                         };
2178                                 };
2179                         };
2180
2181                         out-ports {
2182                                 port {
2183                                         funnel0_out: endpoint {
2184                                                 remote-endpoint =
2185                                                   <&merge_funnel_in0>;
2186                                         };
2187                                 };
2188                         };
2189                 };
2190
2191                 funnel@3022000 {
2192                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2193                         reg = <0x3022000 0x1000>;
2194
2195                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2196                         clock-names = "apb_pclk", "atclk";
2197
2198                         in-ports {
2199                                 #address-cells = <1>;
2200                                 #size-cells = <0>;
2201
2202                                 port@6 {
2203                                         reg = <6>;
2204                                         funnel1_in: endpoint {
2205                                                 remote-endpoint =
2206                                                   <&apss_merge_funnel_out>;
2207                                         };
2208                                 };
2209                         };
2210
2211                         out-ports {
2212                                 port {
2213                                         funnel1_out: endpoint {
2214                                                 remote-endpoint =
2215                                                   <&merge_funnel_in1>;
2216                                         };
2217                                 };
2218                         };
2219                 };
2220
2221                 funnel@3023000 {
2222                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2223                         reg = <0x3023000 0x1000>;
2224
2225                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2226                         clock-names = "apb_pclk", "atclk";
2227
2228
2229                         out-ports {
2230                                 port {
2231                                         funnel2_out: endpoint {
2232                                                 remote-endpoint =
2233                                                   <&merge_funnel_in2>;
2234                                         };
2235                                 };
2236                         };
2237                 };
2238
2239                 funnel@3025000 {
2240                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2241                         reg = <0x3025000 0x1000>;
2242
2243                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2244                         clock-names = "apb_pclk", "atclk";
2245
2246                         in-ports {
2247                                 #address-cells = <1>;
2248                                 #size-cells = <0>;
2249
2250                                 port@0 {
2251                                         reg = <0>;
2252                                         merge_funnel_in0: endpoint {
2253                                                 remote-endpoint =
2254                                                   <&funnel0_out>;
2255                                         };
2256                                 };
2257
2258                                 port@1 {
2259                                         reg = <1>;
2260                                         merge_funnel_in1: endpoint {
2261                                                 remote-endpoint =
2262                                                   <&funnel1_out>;
2263                                         };
2264                                 };
2265
2266                                 port@2 {
2267                                         reg = <2>;
2268                                         merge_funnel_in2: endpoint {
2269                                                 remote-endpoint =
2270                                                   <&funnel2_out>;
2271                                         };
2272                                 };
2273                         };
2274
2275                         out-ports {
2276                                 port {
2277                                         merge_funnel_out: endpoint {
2278                                                 remote-endpoint =
2279                                                   <&etf_in>;
2280                                         };
2281                                 };
2282                         };
2283                 };
2284
2285                 replicator@3026000 {
2286                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2287                         reg = <0x3026000 0x1000>;
2288
2289                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2290                         clock-names = "apb_pclk", "atclk";
2291
2292                         in-ports {
2293                                 port {
2294                                         replicator_in: endpoint {
2295                                                 remote-endpoint =
2296                                                   <&etf_out>;
2297                                         };
2298                                 };
2299                         };
2300
2301                         out-ports {
2302                                 #address-cells = <1>;
2303                                 #size-cells = <0>;
2304
2305                                 port@0 {
2306                                         reg = <0>;
2307                                         replicator_out0: endpoint {
2308                                                 remote-endpoint =
2309                                                   <&etr_in>;
2310                                         };
2311                                 };
2312
2313                                 port@1 {
2314                                         reg = <1>;
2315                                         replicator_out1: endpoint {
2316                                                 remote-endpoint =
2317                                                   <&tpiu_in>;
2318                                         };
2319                                 };
2320                         };
2321                 };
2322
2323                 etf@3027000 {
2324                         compatible = "arm,coresight-tmc", "arm,primecell";
2325                         reg = <0x3027000 0x1000>;
2326
2327                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2328                         clock-names = "apb_pclk", "atclk";
2329
2330                         in-ports {
2331                                 port {
2332                                         etf_in: endpoint {
2333                                                 remote-endpoint =
2334                                                   <&merge_funnel_out>;
2335                                         };
2336                                 };
2337                         };
2338
2339                         out-ports {
2340                                 port {
2341                                         etf_out: endpoint {
2342                                                 remote-endpoint =
2343                                                   <&replicator_in>;
2344                                         };
2345                                 };
2346                         };
2347                 };
2348
2349                 etr@3028000 {
2350                         compatible = "arm,coresight-tmc", "arm,primecell";
2351                         reg = <0x3028000 0x1000>;
2352
2353                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2354                         clock-names = "apb_pclk", "atclk";
2355                         arm,scatter-gather;
2356
2357                         in-ports {
2358                                 port {
2359                                         etr_in: endpoint {
2360                                                 remote-endpoint =
2361                                                   <&replicator_out0>;
2362                                         };
2363                                 };
2364                         };
2365                 };
2366
2367                 debug@3810000 {
2368                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2369                         reg = <0x3810000 0x1000>;
2370
2371                         clocks = <&rpmcc RPM_QDSS_CLK>;
2372                         clock-names = "apb_pclk";
2373
2374                         cpu = <&CPU0>;
2375                 };
2376
2377                 etm@3840000 {
2378                         compatible = "arm,coresight-etm4x", "arm,primecell";
2379                         reg = <0x3840000 0x1000>;
2380
2381                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2382                         clock-names = "apb_pclk", "atclk";
2383
2384                         cpu = <&CPU0>;
2385
2386                         out-ports {
2387                                 port {
2388                                         etm0_out: endpoint {
2389                                                 remote-endpoint =
2390                                                   <&apss_funnel0_in0>;
2391                                         };
2392                                 };
2393                         };
2394                 };
2395
2396                 debug@3910000 {
2397                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2398                         reg = <0x3910000 0x1000>;
2399
2400                         clocks = <&rpmcc RPM_QDSS_CLK>;
2401                         clock-names = "apb_pclk";
2402
2403                         cpu = <&CPU1>;
2404                 };
2405
2406                 etm@3940000 {
2407                         compatible = "arm,coresight-etm4x", "arm,primecell";
2408                         reg = <0x3940000 0x1000>;
2409
2410                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2411                         clock-names = "apb_pclk", "atclk";
2412
2413                         cpu = <&CPU1>;
2414
2415                         out-ports {
2416                                 port {
2417                                         etm1_out: endpoint {
2418                                                 remote-endpoint =
2419                                                   <&apss_funnel0_in1>;
2420                                         };
2421                                 };
2422                         };
2423                 };
2424
2425                 funnel@39b0000 { /* APSS Funnel 0 */
2426                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2427                         reg = <0x39b0000 0x1000>;
2428
2429                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2430                         clock-names = "apb_pclk", "atclk";
2431
2432                         in-ports {
2433                                 #address-cells = <1>;
2434                                 #size-cells = <0>;
2435
2436                                 port@0 {
2437                                         reg = <0>;
2438                                         apss_funnel0_in0: endpoint {
2439                                                 remote-endpoint = <&etm0_out>;
2440                                         };
2441                                 };
2442
2443                                 port@1 {
2444                                         reg = <1>;
2445                                         apss_funnel0_in1: endpoint {
2446                                                 remote-endpoint = <&etm1_out>;
2447                                         };
2448                                 };
2449                         };
2450
2451                         out-ports {
2452                                 port {
2453                                         apss_funnel0_out: endpoint {
2454                                                 remote-endpoint =
2455                                                   <&apss_merge_funnel_in0>;
2456                                         };
2457                                 };
2458                         };
2459                 };
2460
2461                 debug@3a10000 {
2462                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2463                         reg = <0x3a10000 0x1000>;
2464
2465                         clocks = <&rpmcc RPM_QDSS_CLK>;
2466                         clock-names = "apb_pclk";
2467
2468                         cpu = <&CPU2>;
2469                 };
2470
2471                 etm@3a40000 {
2472                         compatible = "arm,coresight-etm4x", "arm,primecell";
2473                         reg = <0x3a40000 0x1000>;
2474
2475                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2476                         clock-names = "apb_pclk", "atclk";
2477
2478                         cpu = <&CPU2>;
2479
2480                         out-ports {
2481                                 port {
2482                                         etm2_out: endpoint {
2483                                                 remote-endpoint =
2484                                                   <&apss_funnel1_in0>;
2485                                         };
2486                                 };
2487                         };
2488                 };
2489
2490                 debug@3b10000 {
2491                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2492                         reg = <0x3b10000 0x1000>;
2493
2494                         clocks = <&rpmcc RPM_QDSS_CLK>;
2495                         clock-names = "apb_pclk";
2496
2497                         cpu = <&CPU3>;
2498                 };
2499
2500                 etm@3b40000 {
2501                         compatible = "arm,coresight-etm4x", "arm,primecell";
2502                         reg = <0x3b40000 0x1000>;
2503
2504                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2505                         clock-names = "apb_pclk", "atclk";
2506
2507                         cpu = <&CPU3>;
2508
2509                         out-ports {
2510                                 port {
2511                                         etm3_out: endpoint {
2512                                                 remote-endpoint =
2513                                                   <&apss_funnel1_in1>;
2514                                         };
2515                                 };
2516                         };
2517                 };
2518
2519                 funnel@3bb0000 { /* APSS Funnel 1 */
2520                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2521                         reg = <0x3bb0000 0x1000>;
2522
2523                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2524                         clock-names = "apb_pclk", "atclk";
2525
2526                         in-ports {
2527                                 #address-cells = <1>;
2528                                 #size-cells = <0>;
2529
2530                                 port@0 {
2531                                         reg = <0>;
2532                                         apss_funnel1_in0: endpoint {
2533                                                 remote-endpoint = <&etm2_out>;
2534                                         };
2535                                 };
2536
2537                                 port@1 {
2538                                         reg = <1>;
2539                                         apss_funnel1_in1: endpoint {
2540                                                 remote-endpoint = <&etm3_out>;
2541                                         };
2542                                 };
2543                         };
2544
2545                         out-ports {
2546                                 port {
2547                                         apss_funnel1_out: endpoint {
2548                                                 remote-endpoint =
2549                                                   <&apss_merge_funnel_in1>;
2550                                         };
2551                                 };
2552                         };
2553                 };
2554
2555                 funnel@3bc0000 {
2556                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2557                         reg = <0x3bc0000 0x1000>;
2558
2559                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2560                         clock-names = "apb_pclk", "atclk";
2561
2562                         in-ports {
2563                                 #address-cells = <1>;
2564                                 #size-cells = <0>;
2565
2566                                 port@0 {
2567                                         reg = <0>;
2568                                         apss_merge_funnel_in0: endpoint {
2569                                                 remote-endpoint =
2570                                                   <&apss_funnel0_out>;
2571                                         };
2572                                 };
2573
2574                                 port@1 {
2575                                         reg = <1>;
2576                                         apss_merge_funnel_in1: endpoint {
2577                                                 remote-endpoint =
2578                                                   <&apss_funnel1_out>;
2579                                         };
2580                                 };
2581                         };
2582
2583                         out-ports {
2584                                 port {
2585                                         apss_merge_funnel_out: endpoint {
2586                                                 remote-endpoint =
2587                                                   <&funnel1_in>;
2588                                         };
2589                                 };
2590                         };
2591                 };
2592
2593                 kryocc: clock-controller@6400000 {
2594                         compatible = "qcom,msm8996-apcc";
2595                         reg = <0x06400000 0x90000>;
2596
2597                         clock-names = "xo";
2598                         clocks = <&rpmcc RPM_SMD_BB_CLK1>;
2599
2600                         #clock-cells = <1>;
2601                 };
2602
2603                 usb3: usb@6af8800 {
2604                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2605                         reg = <0x06af8800 0x400>;
2606                         #address-cells = <1>;
2607                         #size-cells = <1>;
2608                         ranges;
2609
2610                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2611                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2612                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
2613
2614                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2615                                 <&gcc GCC_USB30_MASTER_CLK>,
2616                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2617                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2618                                 <&gcc GCC_USB30_SLEEP_CLK>,
2619                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2620
2621                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2622                                           <&gcc GCC_USB30_MASTER_CLK>;
2623                         assigned-clock-rates = <19200000>, <120000000>;
2624
2625                         power-domains = <&gcc USB30_GDSC>;
2626                         status = "disabled";
2627
2628                         usb3_dwc3: dwc3@6a00000 {
2629                                 compatible = "snps,dwc3";
2630                                 reg = <0x06a00000 0xcc00>;
2631                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2632                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2633                                 phy-names = "usb2-phy", "usb3-phy";
2634                                 snps,dis_u2_susphy_quirk;
2635                                 snps,dis_enblslpm_quirk;
2636                         };
2637                 };
2638
2639                 usb3phy: phy@7410000 {
2640                         compatible = "qcom,msm8996-qmp-usb3-phy";
2641                         reg = <0x07410000 0x1c4>;
2642                         #address-cells = <1>;
2643                         #size-cells = <1>;
2644                         ranges;
2645
2646                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2647                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2648                                 <&gcc GCC_USB3_CLKREF_CLK>;
2649                         clock-names = "aux", "cfg_ahb", "ref";
2650
2651                         resets = <&gcc GCC_USB3_PHY_BCR>,
2652                                 <&gcc GCC_USB3PHY_PHY_BCR>;
2653                         reset-names = "phy", "common";
2654                         status = "disabled";
2655
2656                         ssusb_phy_0: phy@7410200 {
2657                                 reg = <0x07410200 0x200>,
2658                                       <0x07410400 0x130>,
2659                                       <0x07410600 0x1a8>;
2660                                 #phy-cells = <0>;
2661
2662                                 #clock-cells = <1>;
2663                                 clock-output-names = "usb3_phy_pipe_clk_src";
2664                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2665                                 clock-names = "pipe0";
2666                         };
2667                 };
2668
2669                 hsusb_phy1: phy@7411000 {
2670                         compatible = "qcom,msm8996-qusb2-phy";
2671                         reg = <0x07411000 0x180>;
2672                         #phy-cells = <0>;
2673
2674                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2675                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2676                         clock-names = "cfg_ahb", "ref";
2677
2678                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2679                         nvmem-cells = <&qusb2p_hstx_trim>;
2680                         status = "disabled";
2681                 };
2682
2683                 hsusb_phy2: phy@7412000 {
2684                         compatible = "qcom,msm8996-qusb2-phy";
2685                         reg = <0x07412000 0x180>;
2686                         #phy-cells = <0>;
2687
2688                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2689                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
2690                         clock-names = "cfg_ahb", "ref";
2691
2692                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2693                         nvmem-cells = <&qusb2s_hstx_trim>;
2694                         status = "disabled";
2695                 };
2696
2697                 sdhc1: sdhci@7464900 {
2698                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
2699                         reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2700                         reg-names = "hc_mem", "core_mem";
2701
2702                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2703                                         <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2704                         interrupt-names = "hc_irq", "pwr_irq";
2705
2706                         clock-names = "iface", "core", "xo";
2707                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2708                                 <&gcc GCC_SDCC1_APPS_CLK>,
2709                                 <&rpmcc RPM_SMD_BB_CLK1>;
2710
2711                         pinctrl-names = "default", "sleep";
2712                         pinctrl-0 = <&sdc1_state_on>;
2713                         pinctrl-1 = <&sdc1_state_off>;
2714
2715                         bus-width = <8>;
2716                         non-removable;
2717                         status = "disabled";
2718                 };
2719
2720                 sdhc2: sdhci@74a4900 {
2721                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
2722                         reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2723                         reg-names = "hc_mem", "core_mem";
2724
2725                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2726                                       <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2727                         interrupt-names = "hc_irq", "pwr_irq";
2728
2729                         clock-names = "iface", "core", "xo";
2730                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2731                                 <&gcc GCC_SDCC2_APPS_CLK>,
2732                                 <&rpmcc RPM_SMD_BB_CLK1>;
2733
2734                         pinctrl-names = "default", "sleep";
2735                         pinctrl-0 = <&sdc2_state_on>;
2736                         pinctrl-1 = <&sdc2_state_off>;
2737
2738                         bus-width = <4>;
2739                         status = "disabled";
2740                  };
2741
2742                 blsp1_dma: dma-controller@7544000 {
2743                         compatible = "qcom,bam-v1.7.0";
2744                         reg = <0x07544000 0x2b000>;
2745                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2746                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2747                         clock-names = "bam_clk";
2748                         qcom,controlled-remotely;
2749                         #dma-cells = <1>;
2750                         qcom,ee = <0>;
2751                 };
2752
2753                 blsp1_uart2: serial@7570000 {
2754                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2755                         reg = <0x07570000 0x1000>;
2756                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2757                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2758                                  <&gcc GCC_BLSP1_AHB_CLK>;
2759                         clock-names = "core", "iface";
2760                         pinctrl-names = "default", "sleep";
2761                         pinctrl-0 = <&blsp1_uart2_default>;
2762                         pinctrl-1 = <&blsp1_uart2_sleep>;
2763                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2764                         dma-names = "tx", "rx";
2765                         status = "disabled";
2766                 };
2767
2768                 blsp1_spi1: spi@7575000 {
2769                         compatible = "qcom,spi-qup-v2.2.1";
2770                         reg = <0x07575000 0x600>;
2771                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2772                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2773                                  <&gcc GCC_BLSP1_AHB_CLK>;
2774                         clock-names = "core", "iface";
2775                         pinctrl-names = "default", "sleep";
2776                         pinctrl-0 = <&blsp1_spi1_default>;
2777                         pinctrl-1 = <&blsp1_spi1_sleep>;
2778                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2779                         dma-names = "tx", "rx";
2780                         #address-cells = <1>;
2781                         #size-cells = <0>;
2782                         status = "disabled";
2783                 };
2784
2785                 blsp1_i2c3: i2c@7577000 {
2786                         compatible = "qcom,i2c-qup-v2.2.1";
2787                         reg = <0x07577000 0x1000>;
2788                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2789                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2790                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2791                         clock-names = "iface", "core";
2792                         pinctrl-names = "default", "sleep";
2793                         pinctrl-0 = <&blsp1_i2c3_default>;
2794                         pinctrl-1 = <&blsp1_i2c3_sleep>;
2795                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2796                         dma-names = "tx", "rx";
2797                         #address-cells = <1>;
2798                         #size-cells = <0>;
2799                         status = "disabled";
2800                 };
2801
2802                 blsp2_dma: dma-controller@7584000 {
2803                         compatible = "qcom,bam-v1.7.0";
2804                         reg = <0x07584000 0x2b000>;
2805                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2806                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2807                         clock-names = "bam_clk";
2808                         qcom,controlled-remotely;
2809                         #dma-cells = <1>;
2810                         qcom,ee = <0>;
2811                 };
2812
2813                 blsp2_uart2: serial@75b0000 {
2814                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2815                         reg = <0x075b0000 0x1000>;
2816                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2817                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2818                                  <&gcc GCC_BLSP2_AHB_CLK>;
2819                         clock-names = "core", "iface";
2820                         status = "disabled";
2821                 };
2822
2823                 blsp2_uart3: serial@75b1000 {
2824                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2825                         reg = <0x075b1000 0x1000>;
2826                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2827                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2828                                  <&gcc GCC_BLSP2_AHB_CLK>;
2829                         clock-names = "core", "iface";
2830                         status = "disabled";
2831                 };
2832
2833                 blsp2_i2c1: i2c@75b5000 {
2834                         compatible = "qcom,i2c-qup-v2.2.1";
2835                         reg = <0x075b5000 0x1000>;
2836                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2837                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2838                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2839                         clock-names = "iface", "core";
2840                         pinctrl-names = "default", "sleep";
2841                         pinctrl-0 = <&blsp2_i2c1_default>;
2842                         pinctrl-1 = <&blsp2_i2c1_sleep>;
2843                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2844                         dma-names = "tx", "rx";
2845                         #address-cells = <1>;
2846                         #size-cells = <0>;
2847                         status = "disabled";
2848                 };
2849
2850                 blsp2_i2c2: i2c@75b6000 {
2851                         compatible = "qcom,i2c-qup-v2.2.1";
2852                         reg = <0x075b6000 0x1000>;
2853                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2854                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2855                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2856                         clock-names = "iface", "core";
2857                         pinctrl-names = "default", "sleep";
2858                         pinctrl-0 = <&blsp2_i2c2_default>;
2859                         pinctrl-1 = <&blsp2_i2c2_sleep>;
2860                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2861                         dma-names = "tx", "rx";
2862                         #address-cells = <1>;
2863                         #size-cells = <0>;
2864                         status = "disabled";
2865                 };
2866
2867                 blsp2_i2c3: i2c@75b7000 {
2868                         compatible = "qcom,i2c-qup-v2.2.1";
2869                         reg = <0x075b7000 0x1000>;
2870                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2871                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2872                                 <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
2873                         clock-names = "iface", "core";
2874                         clock-frequency = <400000>;
2875                         pinctrl-names = "default", "sleep";
2876                         pinctrl-0 = <&blsp2_i2c3_default>;
2877                         pinctrl-1 = <&blsp2_i2c3_sleep>;
2878                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2879                         dma-names = "tx", "rx";
2880                         #address-cells = <1>;
2881                         #size-cells = <0>;
2882                         status = "disabled";
2883                 };
2884
2885                 blsp2_i2c5: i2c@75b9000 {
2886                         compatible = "qcom,i2c-qup-v2.2.1";
2887                         reg = <0x75b9000 0x1000>;
2888                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2889                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2890                                 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2891                         clock-names = "iface", "core";
2892                         pinctrl-names = "default";
2893                         pinctrl-0 = <&blsp2_i2c5_default>;
2894                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2895                         dma-names = "tx", "rx";
2896                         #address-cells = <1>;
2897                         #size-cells = <0>;
2898                         status = "disabled";
2899                 };
2900
2901                 blsp2_i2c6: i2c@75ba000 {
2902                         compatible = "qcom,i2c-qup-v2.2.1";
2903                         reg = <0x75ba000 0x1000>;
2904                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2905                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2906                                 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2907                         clock-names = "iface", "core";
2908                         pinctrl-names = "default", "sleep";
2909                         pinctrl-0 = <&blsp2_i2c6_default>;
2910                         pinctrl-1 = <&blsp2_i2c6_sleep>;
2911                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2912                         dma-names = "tx", "rx";
2913                         #address-cells = <1>;
2914                         #size-cells = <0>;
2915                         status = "disabled";
2916                 };
2917
2918                 blsp2_spi6: spi@75ba000{
2919                         compatible = "qcom,spi-qup-v2.2.1";
2920                         reg = <0x075ba000 0x600>;
2921                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2922                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2923                                  <&gcc GCC_BLSP2_AHB_CLK>;
2924                         clock-names = "core", "iface";
2925                         pinctrl-names = "default", "sleep";
2926                         pinctrl-0 = <&blsp2_spi6_default>;
2927                         pinctrl-1 = <&blsp2_spi6_sleep>;
2928                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2929                         dma-names = "tx", "rx";
2930                         #address-cells = <1>;
2931                         #size-cells = <0>;
2932                         status = "disabled";
2933                 };
2934
2935                 usb2: usb@76f8800 {
2936                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2937                         reg = <0x076f8800 0x400>;
2938                         #address-cells = <1>;
2939                         #size-cells = <1>;
2940                         ranges;
2941
2942                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2943                                 <&gcc GCC_USB20_MASTER_CLK>,
2944                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2945                                 <&gcc GCC_USB20_SLEEP_CLK>,
2946                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2947
2948                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2949                                           <&gcc GCC_USB20_MASTER_CLK>;
2950                         assigned-clock-rates = <19200000>, <60000000>;
2951
2952                         power-domains = <&gcc USB30_GDSC>;
2953                         qcom,select-utmi-as-pipe-clk;
2954                         status = "disabled";
2955
2956                         dwc3@7600000 {
2957                                 compatible = "snps,dwc3";
2958                                 reg = <0x07600000 0xcc00>;
2959                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2960                                 phys = <&hsusb_phy2>;
2961                                 phy-names = "usb2-phy";
2962                                 maximum-speed = "high-speed";
2963                                 snps,dis_u2_susphy_quirk;
2964                                 snps,dis_enblslpm_quirk;
2965                         };
2966                 };
2967
2968                 slimbam: dma-controller@9184000 {
2969                         compatible = "qcom,bam-v1.7.0";
2970                         qcom,controlled-remotely;
2971                         reg = <0x09184000 0x32000>;
2972                         num-channels  = <31>;
2973                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2974                         #dma-cells = <1>;
2975                         qcom,ee = <1>;
2976                         qcom,num-ees = <2>;
2977                 };
2978
2979                 slim_msm: slim@91c0000 {
2980                         compatible = "qcom,slim-ngd-v1.5.0";
2981                         reg = <0x091c0000 0x2C000>;
2982                         reg-names = "ctrl";
2983                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2984                         dmas =  <&slimbam 3>, <&slimbam 4>,
2985                                 <&slimbam 5>, <&slimbam 6>;
2986                         dma-names = "rx", "tx", "tx2", "rx2";
2987                         #address-cells = <1>;
2988                         #size-cells = <0>;
2989                         ngd@1 {
2990                                 reg = <1>;
2991                                 #address-cells = <1>;
2992                                 #size-cells = <1>;
2993
2994                                 tasha_ifd: tas-ifd {
2995                                         compatible = "slim217,1a0";
2996                                         reg  = <0 0>;
2997                                 };
2998
2999                                 wcd9335: codec@1{
3000                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
3001                                         pinctrl-names = "default";
3002
3003                                         compatible = "slim217,1a0";
3004                                         reg  = <1 0>;
3005
3006                                         interrupt-parent = <&tlmm>;
3007                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
3008                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
3009                                         interrupt-names  = "intr1", "intr2";
3010                                         interrupt-controller;
3011                                         #interrupt-cells = <1>;
3012                                         reset-gpios = <&tlmm 64 0>;
3013
3014                                         slim-ifc-dev  = <&tasha_ifd>;
3015
3016                                         #sound-dai-cells = <1>;
3017                                 };
3018                         };
3019                 };
3020
3021                 adsp_pil: remoteproc@9300000 {
3022                         compatible = "qcom,msm8996-adsp-pil";
3023                         reg = <0x09300000 0x80000>;
3024
3025                         interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3026                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3027                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3028                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3029                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3030                         interrupt-names = "wdog", "fatal", "ready",
3031                                           "handover", "stop-ack";
3032
3033                         clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3034                         clock-names = "xo";
3035
3036                         memory-region = <&adsp_region>;
3037
3038                         qcom,smem-states = <&smp2p_adsp_out 0>;
3039                         qcom,smem-state-names = "stop";
3040
3041                         power-domains = <&rpmpd MSM8996_VDDCX>;
3042                         power-domain-names = "cx";
3043
3044                         status = "disabled";
3045
3046                         smd-edge {
3047                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3048
3049                                 label = "lpass";
3050                                 mboxes = <&apcs_glb 8>;
3051                                 qcom,smd-edge = <1>;
3052                                 qcom,remote-pid = <2>;
3053                                 #address-cells = <1>;
3054                                 #size-cells = <0>;
3055                                 apr {
3056                                         power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3057                                         compatible = "qcom,apr-v2";
3058                                         qcom,smd-channels = "apr_audio_svc";
3059                                         qcom,domain = <APR_DOMAIN_ADSP>;
3060                                         #address-cells = <1>;
3061                                         #size-cells = <0>;
3062
3063                                         q6core {
3064                                                 reg = <APR_SVC_ADSP_CORE>;
3065                                                 compatible = "qcom,q6core";
3066                                         };
3067
3068                                         q6afe: q6afe {
3069                                                 compatible = "qcom,q6afe";
3070                                                 reg = <APR_SVC_AFE>;
3071                                                 q6afedai: dais {
3072                                                         compatible = "qcom,q6afe-dais";
3073                                                         #address-cells = <1>;
3074                                                         #size-cells = <0>;
3075                                                         #sound-dai-cells = <1>;
3076                                                         hdmi@1 {
3077                                                                 reg = <1>;
3078                                                         };
3079                                                 };
3080                                         };
3081
3082                                         q6asm: q6asm {
3083                                                 compatible = "qcom,q6asm";
3084                                                 reg = <APR_SVC_ASM>;
3085                                                 q6asmdai: dais {
3086                                                         compatible = "qcom,q6asm-dais";
3087                                                         #address-cells = <1>;
3088                                                         #size-cells = <0>;
3089                                                         #sound-dai-cells = <1>;
3090                                                         iommus = <&lpass_q6_smmu 1>;
3091                                                 };
3092                                         };
3093
3094                                         q6adm: q6adm {
3095                                                 compatible = "qcom,q6adm";
3096                                                 reg = <APR_SVC_ADM>;
3097                                                 q6routing: routing {
3098                                                         compatible = "qcom,q6adm-routing";
3099                                                         #sound-dai-cells = <0>;
3100                                                 };
3101                                         };
3102                                 };
3103
3104                         };
3105                 };
3106
3107                 apcs_glb: mailbox@9820000 {
3108                         compatible = "qcom,msm8996-apcs-hmss-global";
3109                         reg = <0x09820000 0x1000>;
3110
3111                         #mbox-cells = <1>;
3112                 };
3113
3114                 timer@9840000 {
3115                         #address-cells = <1>;
3116                         #size-cells = <1>;
3117                         ranges;
3118                         compatible = "arm,armv7-timer-mem";
3119                         reg = <0x09840000 0x1000>;
3120                         clock-frequency = <19200000>;
3121
3122                         frame@9850000 {
3123                                 frame-number = <0>;
3124                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3125                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3126                                 reg = <0x09850000 0x1000>,
3127                                       <0x09860000 0x1000>;
3128                         };
3129
3130                         frame@9870000 {
3131                                 frame-number = <1>;
3132                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3133                                 reg = <0x09870000 0x1000>;
3134                                 status = "disabled";
3135                         };
3136
3137                         frame@9880000 {
3138                                 frame-number = <2>;
3139                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3140                                 reg = <0x09880000 0x1000>;
3141                                 status = "disabled";
3142                         };
3143
3144                         frame@9890000 {
3145                                 frame-number = <3>;
3146                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3147                                 reg = <0x09890000 0x1000>;
3148                                 status = "disabled";
3149                         };
3150
3151                         frame@98a0000 {
3152                                 frame-number = <4>;
3153                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3154                                 reg = <0x098a0000 0x1000>;
3155                                 status = "disabled";
3156                         };
3157
3158                         frame@98b0000 {
3159                                 frame-number = <5>;
3160                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3161                                 reg = <0x098b0000 0x1000>;
3162                                 status = "disabled";
3163                         };
3164
3165                         frame@98c0000 {
3166                                 frame-number = <6>;
3167                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3168                                 reg = <0x098c0000 0x1000>;
3169                                 status = "disabled";
3170                         };
3171                 };
3172
3173                 saw3: syscon@9a10000 {
3174                         compatible = "syscon";
3175                         reg = <0x09a10000 0x1000>;
3176                 };
3177
3178                 intc: interrupt-controller@9bc0000 {
3179                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3180                         #interrupt-cells = <3>;
3181                         interrupt-controller;
3182                         #redistributor-regions = <1>;
3183                         redistributor-stride = <0x0 0x40000>;
3184                         reg = <0x09bc0000 0x10000>,
3185                               <0x09c00000 0x100000>;
3186                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3187                 };
3188         };
3189
3190         sound: sound {
3191         };
3192
3193         thermal-zones {
3194                 cpu0-thermal {
3195                         polling-delay-passive = <250>;
3196                         polling-delay = <1000>;
3197
3198                         thermal-sensors = <&tsens0 3>;
3199
3200                         trips {
3201                                 cpu0_alert0: trip-point0 {
3202                                         temperature = <75000>;
3203                                         hysteresis = <2000>;
3204                                         type = "passive";
3205                                 };
3206
3207                                 cpu0_crit: cpu_crit {
3208                                         temperature = <110000>;
3209                                         hysteresis = <2000>;
3210                                         type = "critical";
3211                                 };
3212                         };
3213                 };
3214
3215                 cpu1-thermal {
3216                         polling-delay-passive = <250>;
3217                         polling-delay = <1000>;
3218
3219                         thermal-sensors = <&tsens0 5>;
3220
3221                         trips {
3222                                 cpu1_alert0: trip-point0 {
3223                                         temperature = <75000>;
3224                                         hysteresis = <2000>;
3225                                         type = "passive";
3226                                 };
3227
3228                                 cpu1_crit: cpu_crit {
3229                                         temperature = <110000>;
3230                                         hysteresis = <2000>;
3231                                         type = "critical";
3232                                 };
3233                         };
3234                 };
3235
3236                 cpu2-thermal {
3237                         polling-delay-passive = <250>;
3238                         polling-delay = <1000>;
3239
3240                         thermal-sensors = <&tsens0 8>;
3241
3242                         trips {
3243                                 cpu2_alert0: trip-point0 {
3244                                         temperature = <75000>;
3245                                         hysteresis = <2000>;
3246                                         type = "passive";
3247                                 };
3248
3249                                 cpu2_crit: cpu_crit {
3250                                         temperature = <110000>;
3251                                         hysteresis = <2000>;
3252                                         type = "critical";
3253                                 };
3254                         };
3255                 };
3256
3257                 cpu3-thermal {
3258                         polling-delay-passive = <250>;
3259                         polling-delay = <1000>;
3260
3261                         thermal-sensors = <&tsens0 10>;
3262
3263                         trips {
3264                                 cpu3_alert0: trip-point0 {
3265                                         temperature = <75000>;
3266                                         hysteresis = <2000>;
3267                                         type = "passive";
3268                                 };
3269
3270                                 cpu3_crit: cpu_crit {
3271                                         temperature = <110000>;
3272                                         hysteresis = <2000>;
3273                                         type = "critical";
3274                                 };
3275                         };
3276                 };
3277
3278                 gpu-top-thermal {
3279                         polling-delay-passive = <250>;
3280                         polling-delay = <1000>;
3281
3282                         thermal-sensors = <&tsens1 6>;
3283
3284                         trips {
3285                                 gpu1_alert0: trip-point0 {
3286                                         temperature = <90000>;
3287                                         hysteresis = <2000>;
3288                                         type = "passive";
3289                                 };
3290                         };
3291
3292                         cooling-maps {
3293                                 map0 {
3294                                         trip = <&gpu1_alert0>;
3295                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3296                                 };
3297                         };
3298                 };
3299
3300                 gpu-bottom-thermal {
3301                         polling-delay-passive = <250>;
3302                         polling-delay = <1000>;
3303
3304                         thermal-sensors = <&tsens1 7>;
3305
3306                         trips {
3307                                 gpu2_alert0: trip-point0 {
3308                                         temperature = <90000>;
3309                                         hysteresis = <2000>;
3310                                         type = "passive";
3311                                 };
3312                         };
3313
3314                         cooling-maps {
3315                                 map0 {
3316                                         trip = <&gpu2_alert0>;
3317                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3318                                 };
3319                         };
3320                 };
3321
3322                 m4m-thermal {
3323                         polling-delay-passive = <250>;
3324                         polling-delay = <1000>;
3325
3326                         thermal-sensors = <&tsens0 1>;
3327
3328                         trips {
3329                                 m4m_alert0: trip-point0 {
3330                                         temperature = <90000>;
3331                                         hysteresis = <2000>;
3332                                         type = "hot";
3333                                 };
3334                         };
3335                 };
3336
3337                 l3-or-venus-thermal {
3338                         polling-delay-passive = <250>;
3339                         polling-delay = <1000>;
3340
3341                         thermal-sensors = <&tsens0 2>;
3342
3343                         trips {
3344                                 l3_or_venus_alert0: trip-point0 {
3345                                         temperature = <90000>;
3346                                         hysteresis = <2000>;
3347                                         type = "hot";
3348                                 };
3349                         };
3350                 };
3351
3352                 cluster0-l2-thermal {
3353                         polling-delay-passive = <250>;
3354                         polling-delay = <1000>;
3355
3356                         thermal-sensors = <&tsens0 7>;
3357
3358                         trips {
3359                                 cluster0_l2_alert0: trip-point0 {
3360                                         temperature = <90000>;
3361                                         hysteresis = <2000>;
3362                                         type = "hot";
3363                                 };
3364                         };
3365                 };
3366
3367                 cluster1-l2-thermal {
3368                         polling-delay-passive = <250>;
3369                         polling-delay = <1000>;
3370
3371                         thermal-sensors = <&tsens0 12>;
3372
3373                         trips {
3374                                 cluster1_l2_alert0: trip-point0 {
3375                                         temperature = <90000>;
3376                                         hysteresis = <2000>;
3377                                         type = "hot";
3378                                 };
3379                         };
3380                 };
3381
3382                 camera-thermal {
3383                         polling-delay-passive = <250>;
3384                         polling-delay = <1000>;
3385
3386                         thermal-sensors = <&tsens1 1>;
3387
3388                         trips {
3389                                 camera_alert0: trip-point0 {
3390                                         temperature = <90000>;
3391                                         hysteresis = <2000>;
3392                                         type = "hot";
3393                                 };
3394                         };
3395                 };
3396
3397                 q6-dsp-thermal {
3398                         polling-delay-passive = <250>;
3399                         polling-delay = <1000>;
3400
3401                         thermal-sensors = <&tsens1 2>;
3402
3403                         trips {
3404                                 q6_dsp_alert0: trip-point0 {
3405                                         temperature = <90000>;
3406                                         hysteresis = <2000>;
3407                                         type = "hot";
3408                                 };
3409                         };
3410                 };
3411
3412                 mem-thermal {
3413                         polling-delay-passive = <250>;
3414                         polling-delay = <1000>;
3415
3416                         thermal-sensors = <&tsens1 3>;
3417
3418                         trips {
3419                                 mem_alert0: trip-point0 {
3420                                         temperature = <90000>;
3421                                         hysteresis = <2000>;
3422                                         type = "hot";
3423                                 };
3424                         };
3425                 };
3426
3427                 modemtx-thermal {
3428                         polling-delay-passive = <250>;
3429                         polling-delay = <1000>;
3430
3431                         thermal-sensors = <&tsens1 4>;
3432
3433                         trips {
3434                                 modemtx_alert0: trip-point0 {
3435                                         temperature = <90000>;
3436                                         hysteresis = <2000>;
3437                                         type = "hot";
3438                                 };
3439                         };
3440                 };
3441         };
3442
3443         timer {
3444                 compatible = "arm,armv8-timer";
3445                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3446                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3447                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3448                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3449         };
3450 };