arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,apr.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         interrupt-parent = <&intc>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         chosen { };
  20
  21         clocks {
  22                 xo_board: xo_board {
  23                         compatible = "fixed-clock";
  24                         #clock-cells = <0>;
  25                         clock-frequency = <19200000>;
  26                         clock-output-names = "xo_board";
  27                 };
  28
  29                 sleep_clk: sleep_clk {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <32764>;
  33                         clock-output-names = "sleep_clk";
  34                 };
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 CPU0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "qcom,kryo";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         cpu-idle-states = <&CPU_SLEEP_0>;
  47                         capacity-dmips-mhz = <1024>;
  48                         clocks = <&kryocc 0>;
  49                         operating-points-v2 = <&cluster0_opp>;
  50                         #cooling-cells = <2>;
  51                         next-level-cache = <&L2_0>;
  52                         L2_0: l2-cache {
  53                               compatible = "cache";
  54                               cache-level = <2>;
  55                         };
  56                 };
  57
  58                 CPU1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "qcom,kryo";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                         capacity-dmips-mhz = <1024>;
  65                         clocks = <&kryocc 0>;
  66                         operating-points-v2 = <&cluster0_opp>;
  67                         #cooling-cells = <2>;
  68                         next-level-cache = <&L2_0>;
  69                 };
  70
  71                 CPU2: cpu@100 {
  72                         device_type = "cpu";
  73                         compatible = "qcom,kryo";
  74                         reg = <0x0 0x100>;
  75                         enable-method = "psci";
  76                         cpu-idle-states = <&CPU_SLEEP_0>;
  77                         capacity-dmips-mhz = <1024>;
  78                         clocks = <&kryocc 1>;
  79                         operating-points-v2 = <&cluster1_opp>;
  80                         #cooling-cells = <2>;
  81                         next-level-cache = <&L2_1>;
  82                         L2_1: l2-cache {
  83                               compatible = "cache";
  84                               cache-level = <2>;
  85                         };
  86                 };
  87
  88                 CPU3: cpu@101 {
  89                         device_type = "cpu";
  90                         compatible = "qcom,kryo";
  91                         reg = <0x0 0x101>;
  92                         enable-method = "psci";
  93                         cpu-idle-states = <&CPU_SLEEP_0>;
  94                         capacity-dmips-mhz = <1024>;
  95                         clocks = <&kryocc 1>;
  96                         operating-points-v2 = <&cluster1_opp>;
  97                         #cooling-cells = <2>;
  98                         next-level-cache = <&L2_1>;
  99                 };
 100
 101                 cpu-map {
 102                         cluster0 {
 103                                 core0 {
 104                                         cpu = <&CPU0>;
 105                                 };
 106
 107                                 core1 {
 108                                         cpu = <&CPU1>;
 109                                 };
 110                         };
 111
 112                         cluster1 {
 113                                 core0 {
 114                                         cpu = <&CPU2>;
 115                                 };
 116
 117                                 core1 {
 118                                         cpu = <&CPU3>;
 119                                 };
 120                         };
 121                 };
 122
 123                 idle-states {
 124                         entry-method = "psci";
 125
 126                         CPU_SLEEP_0: cpu-sleep-0 {
 127                                 compatible = "arm,idle-state";
 128                                 idle-state-name = "standalone-power-collapse";
 129                                 arm,psci-suspend-param = <0x00000004>;
 130                                 entry-latency-us = <130>;
 131                                 exit-latency-us = <80>;
 132                                 min-residency-us = <300>;
 133                         };
 134                 };
 135         };
 136
 137         cluster0_opp: opp_table0 {
 138                 compatible = "operating-points-v2-kryo-cpu";
 139                 nvmem-cells = <&speedbin_efuse>;
 140                 opp-shared;
 141
 142                 /* Nominal fmax for now */
 143                 opp-307200000 {
 144                         opp-hz = /bits/ 64 <307200000>;
 145                         opp-supported-hw = <0x77>;
 146                         clock-latency-ns = <200000>;
 147                 };
 148                 opp-422400000 {
 149                         opp-hz = /bits/ 64 <422400000>;
 150                         opp-supported-hw = <0x77>;
 151                         clock-latency-ns = <200000>;
 152                 };
 153                 opp-480000000 {
 154                         opp-hz = /bits/ 64 <480000000>;
 155                         opp-supported-hw = <0x77>;
 156                         clock-latency-ns = <200000>;
 157                 };
 158                 opp-556800000 {
 159                         opp-hz = /bits/ 64 <556800000>;
 160                         opp-supported-hw = <0x77>;
 161                         clock-latency-ns = <200000>;
 162                 };
 163                 opp-652800000 {
 164                         opp-hz = /bits/ 64 <652800000>;
 165                         opp-supported-hw = <0x77>;
 166                         clock-latency-ns = <200000>;
 167                 };
 168                 opp-729600000 {
 169                         opp-hz = /bits/ 64 <729600000>;
 170                         opp-supported-hw = <0x77>;
 171                         clock-latency-ns = <200000>;
 172                 };
 173                 opp-844800000 {
 174                         opp-hz = /bits/ 64 <844800000>;
 175                         opp-supported-hw = <0x77>;
 176                         clock-latency-ns = <200000>;
 177                 };
 178                 opp-960000000 {
 179                         opp-hz = /bits/ 64 <960000000>;
 180                         opp-supported-hw = <0x77>;
 181                         clock-latency-ns = <200000>;
 182                 };
 183                 opp-1036800000 {
 184                         opp-hz = /bits/ 64 <1036800000>;
 185                         opp-supported-hw = <0x77>;
 186                         clock-latency-ns = <200000>;
 187                 };
 188                 opp-1113600000 {
 189                         opp-hz = /bits/ 64 <1113600000>;
 190                         opp-supported-hw = <0x77>;
 191                         clock-latency-ns = <200000>;
 192                 };
 193                 opp-1190400000 {
 194                         opp-hz = /bits/ 64 <1190400000>;
 195                         opp-supported-hw = <0x77>;
 196                         clock-latency-ns = <200000>;
 197                 };
 198                 opp-1228800000 {
 199                         opp-hz = /bits/ 64 <1228800000>;
 200                         opp-supported-hw = <0x77>;
 201                         clock-latency-ns = <200000>;
 202                 };
 203                 opp-1324800000 {
 204                         opp-hz = /bits/ 64 <1324800000>;
 205                         opp-supported-hw = <0x77>;
 206                         clock-latency-ns = <200000>;
 207                 };
 208                 opp-1401600000 {
 209                         opp-hz = /bits/ 64 <1401600000>;
 210                         opp-supported-hw = <0x77>;
 211                         clock-latency-ns = <200000>;
 212                 };
 213                 opp-1478400000 {
 214                         opp-hz = /bits/ 64 <1478400000>;
 215                         opp-supported-hw = <0x77>;
 216                         clock-latency-ns = <200000>;
 217                 };
 218                 opp-1593600000 {
 219                         opp-hz = /bits/ 64 <1593600000>;
 220                         opp-supported-hw = <0x77>;
 221                         clock-latency-ns = <200000>;
 222                 };
 223         };
 224
 225         cluster1_opp: opp_table1 {
 226                 compatible = "operating-points-v2-kryo-cpu";
 227                 nvmem-cells = <&speedbin_efuse>;
 228                 opp-shared;
 229
 230                 /* Nominal fmax for now */
 231                 opp-307200000 {
 232                         opp-hz = /bits/ 64 <307200000>;
 233                         opp-supported-hw = <0x77>;
 234                         clock-latency-ns = <200000>;
 235                 };
 236                 opp-403200000 {
 237                         opp-hz = /bits/ 64 <403200000>;
 238                         opp-supported-hw = <0x77>;
 239                         clock-latency-ns = <200000>;
 240                 };
 241                 opp-480000000 {
 242                         opp-hz = /bits/ 64 <480000000>;
 243                         opp-supported-hw = <0x77>;
 244                         clock-latency-ns = <200000>;
 245                 };
 246                 opp-556800000 {
 247                         opp-hz = /bits/ 64 <556800000>;
 248                         opp-supported-hw = <0x77>;
 249                         clock-latency-ns = <200000>;
 250                 };
 251                 opp-652800000 {
 252                         opp-hz = /bits/ 64 <652800000>;
 253                         opp-supported-hw = <0x77>;
 254                         clock-latency-ns = <200000>;
 255                 };
 256                 opp-729600000 {
 257                         opp-hz = /bits/ 64 <729600000>;
 258                         opp-supported-hw = <0x77>;
 259                         clock-latency-ns = <200000>;
 260                 };
 261                 opp-806400000 {
 262                         opp-hz = /bits/ 64 <806400000>;
 263                         opp-supported-hw = <0x77>;
 264                         clock-latency-ns = <200000>;
 265                 };
 266                 opp-883200000 {
 267                         opp-hz = /bits/ 64 <883200000>;
 268                         opp-supported-hw = <0x77>;
 269                         clock-latency-ns = <200000>;
 270                 };
 271                 opp-940800000 {
 272                         opp-hz = /bits/ 64 <940800000>;
 273                         opp-supported-hw = <0x77>;
 274                         clock-latency-ns = <200000>;
 275                 };
 276                 opp-1036800000 {
 277                         opp-hz = /bits/ 64 <1036800000>;
 278                         opp-supported-hw = <0x77>;
 279                         clock-latency-ns = <200000>;
 280                 };
 281                 opp-1113600000 {
 282                         opp-hz = /bits/ 64 <1113600000>;
 283                         opp-supported-hw = <0x77>;
 284                         clock-latency-ns = <200000>;
 285                 };
 286                 opp-1190400000 {
 287                         opp-hz = /bits/ 64 <1190400000>;
 288                         opp-supported-hw = <0x77>;
 289                         clock-latency-ns = <200000>;
 290                 };
 291                 opp-1248000000 {
 292                         opp-hz = /bits/ 64 <1248000000>;
 293                         opp-supported-hw = <0x77>;
 294                         clock-latency-ns = <200000>;
 295                 };
 296                 opp-1324800000 {
 297                         opp-hz = /bits/ 64 <1324800000>;
 298                         opp-supported-hw = <0x77>;
 299                         clock-latency-ns = <200000>;
 300                 };
 301                 opp-1401600000 {
 302                         opp-hz = /bits/ 64 <1401600000>;
 303                         opp-supported-hw = <0x77>;
 304                         clock-latency-ns = <200000>;
 305                 };
 306                 opp-1478400000 {
 307                         opp-hz = /bits/ 64 <1478400000>;
 308                         opp-supported-hw = <0x77>;
 309                         clock-latency-ns = <200000>;
 310                 };
 311                 opp-1555200000 {
 312                         opp-hz = /bits/ 64 <1555200000>;
 313                         opp-supported-hw = <0x77>;
 314                         clock-latency-ns = <200000>;
 315                 };
 316                 opp-1632000000 {
 317                         opp-hz = /bits/ 64 <1632000000>;
 318                         opp-supported-hw = <0x77>;
 319                         clock-latency-ns = <200000>;
 320                 };
 321                 opp-1708800000 {
 322                         opp-hz = /bits/ 64 <1708800000>;
 323                         opp-supported-hw = <0x77>;
 324                         clock-latency-ns = <200000>;
 325                 };
 326                 opp-1785600000 {
 327                         opp-hz = /bits/ 64 <1785600000>;
 328                         opp-supported-hw = <0x77>;
 329                         clock-latency-ns = <200000>;
 330                 };
 331                 opp-1824000000 {
 332                         opp-hz = /bits/ 64 <1824000000>;
 333                         opp-supported-hw = <0x77>;
 334                         clock-latency-ns = <200000>;
 335                 };
 336                 opp-1920000000 {
 337                         opp-hz = /bits/ 64 <1920000000>;
 338                         opp-supported-hw = <0x77>;
 339                         clock-latency-ns = <200000>;
 340                 };
 341                 opp-1996800000 {
 342                         opp-hz = /bits/ 64 <1996800000>;
 343                         opp-supported-hw = <0x77>;
 344                         clock-latency-ns = <200000>;
 345                 };
 346                 opp-2073600000 {
 347                         opp-hz = /bits/ 64 <2073600000>;
 348                         opp-supported-hw = <0x77>;
 349                         clock-latency-ns = <200000>;
 350                 };
 351                 opp-2150400000 {
 352                         opp-hz = /bits/ 64 <2150400000>;
 353                         opp-supported-hw = <0x77>;
 354                         clock-latency-ns = <200000>;
 355                 };
 356         };
 357
 358         firmware {
 359                 scm {
 360                         compatible = "qcom,scm-msm8996";
 361                         qcom,dload-mode = <&tcsr 0x13000>;
 362                 };
 363         };
 364
 365         tcsr_mutex: hwlock {
 366                 compatible = "qcom,tcsr-mutex";
 367                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 368                 #hwlock-cells = <1>;
 369         };
 370
 371         memory {
 372                 device_type = "memory";
 373                 /* We expect the bootloader to fill in the reg */
 374                 reg = <0 0 0 0>;
 375         };
 376
 377         psci {
 378                 compatible = "arm,psci-1.0";
 379                 method = "smc";
 380         };
 381
 382         reserved-memory {
 383                 #address-cells = <2>;
 384                 #size-cells = <2>;
 385                 ranges;
 386
 387                 mba_region: mba@91500000 {
 388                         reg = <0x0 0x91500000 0x0 0x200000>;
 389                         no-map;
 390                 };
 391
 392                 slpi_region: slpi@90b00000 {
 393                         reg = <0x0 0x90b00000 0x0 0xa00000>;
 394                         no-map;
 395                 };
 396
 397                 venus_region: venus@90400000 {
 398                         reg = <0x0 0x90400000 0x0 0x700000>;
 399                         no-map;
 400                 };
 401
 402                 adsp_region: adsp@8ea00000 {
 403                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
 404                         no-map;
 405                 };
 406
 407                 mpss_region: mpss@88800000 {
 408                         reg = <0x0 0x88800000 0x0 0x6200000>;
 409                         no-map;
 410                 };
 411
 412                 smem_mem: smem-mem@86000000 {
 413                         reg = <0x0 0x86000000 0x0 0x200000>;
 414                         no-map;
 415                 };
 416
 417                 memory@85800000 {
 418                         reg = <0x0 0x85800000 0x0 0x800000>;
 419                         no-map;
 420                 };
 421
 422                 memory@86200000 {
 423                         reg = <0x0 0x86200000 0x0 0x2600000>;
 424                         no-map;
 425                 };
 426
 427                 rmtfs@86700000 {
 428                         compatible = "qcom,rmtfs-mem";
 429
 430                         size = <0x0 0x200000>;
 431                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
 432                         no-map;
 433
 434                         qcom,client-id = <1>;
 435                         qcom,vmid = <15>;
 436                 };
 437
 438                 zap_shader_region: gpu@8f200000 {
 439                         compatible = "shared-dma-pool";
 440                         reg = <0x0 0x90b00000 0x0 0xa00000>;
 441                         no-map;
 442                 };
 443         };
 444
 445         rpm-glink {
 446                 compatible = "qcom,glink-rpm";
 447
 448                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 449
 450                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 451
 452                 mboxes = <&apcs_glb 0>;
 453
 454                 rpm_requests: rpm-requests {
 455                         compatible = "qcom,rpm-msm8996";
 456                         qcom,glink-channels = "rpm_requests";
 457
 458                         rpmcc: qcom,rpmcc {
 459                                 compatible = "qcom,rpmcc-msm8996";
 460                                 #clock-cells = <1>;
 461                         };
 462
 463                         rpmpd: power-controller {
 464                                 compatible = "qcom,msm8996-rpmpd";
 465                                 #power-domain-cells = <1>;
 466                                 operating-points-v2 = <&rpmpd_opp_table>;
 467
 468                                 rpmpd_opp_table: opp-table {
 469                                         compatible = "operating-points-v2";
 470
 471                                         rpmpd_opp1: opp1 {
 472                                                 opp-level = <1>;
 473                                         };
 474
 475                                         rpmpd_opp2: opp2 {
 476                                                 opp-level = <2>;
 477                                         };
 478
 479                                         rpmpd_opp3: opp3 {
 480                                                 opp-level = <3>;
 481                                         };
 482
 483                                         rpmpd_opp4: opp4 {
 484                                                 opp-level = <4>;
 485                                         };
 486
 487                                         rpmpd_opp5: opp5 {
 488                                                 opp-level = <5>;
 489                                         };
 490
 491                                         rpmpd_opp6: opp6 {
 492                                                 opp-level = <6>;
 493                                         };
 494                                 };
 495                         };
 496                 };
 497         };
 498
 499         smem {
 500                 compatible = "qcom,smem";
 501                 memory-region = <&smem_mem>;
 502                 hwlocks = <&tcsr_mutex 3>;
 503         };
 504
 505         smp2p-adsp {
 506                 compatible = "qcom,smp2p";
 507                 qcom,smem = <443>, <429>;
 508
 509                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 510
 511                 mboxes = <&apcs_glb 10>;
 512
 513                 qcom,local-pid = <0>;
 514                 qcom,remote-pid = <2>;
 515
 516                 smp2p_adsp_out: master-kernel {
 517                         qcom,entry-name = "master-kernel";
 518                         #qcom,smem-state-cells = <1>;
 519                 };
 520
 521                 smp2p_adsp_in: slave-kernel {
 522                         qcom,entry-name = "slave-kernel";
 523
 524                         interrupt-controller;
 525                         #interrupt-cells = <2>;
 526                 };
 527         };
 528
 529         smp2p-modem {
 530                 compatible = "qcom,smp2p";
 531                 qcom,smem = <435>, <428>;
 532
 533                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 534
 535                 mboxes = <&apcs_glb 14>;
 536
 537                 qcom,local-pid = <0>;
 538                 qcom,remote-pid = <1>;
 539
 540                 modem_smp2p_out: master-kernel {
 541                         qcom,entry-name = "master-kernel";
 542                         #qcom,smem-state-cells = <1>;
 543                 };
 544
 545                 modem_smp2p_in: slave-kernel {
 546                         qcom,entry-name = "slave-kernel";
 547
 548                         interrupt-controller;
 549                         #interrupt-cells = <2>;
 550                 };
 551         };
 552
 553         smp2p-slpi {
 554                 compatible = "qcom,smp2p";
 555                 qcom,smem = <481>, <430>;
 556
 557                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 558
 559                 mboxes = <&apcs_glb 26>;
 560
 561                 qcom,local-pid = <0>;
 562                 qcom,remote-pid = <3>;
 563
 564                 smp2p_slpi_in: slave-kernel {
 565                         qcom,entry-name = "slave-kernel";
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                 };
 569
 570                 smp2p_slpi_out: master-kernel {
 571                         qcom,entry-name = "master-kernel";
 572                         #qcom,smem-state-cells = <1>;
 573                 };
 574         };
 575
 576         soc: soc {
 577                 #address-cells = <1>;
 578                 #size-cells = <1>;
 579                 ranges = <0 0 0 0xffffffff>;
 580                 compatible = "simple-bus";
 581
 582                 pcie_phy: phy@34000 {
 583                         compatible = "qcom,msm8996-qmp-pcie-phy";
 584                         reg = <0x00034000 0x488>;
 585                         #clock-cells = <1>;
 586                         #address-cells = <1>;
 587                         #size-cells = <1>;
 588                         ranges;
 589
 590                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 591                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 592                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 593                         clock-names = "aux", "cfg_ahb", "ref";
 594
 595                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 596                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 597                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 598                         reset-names = "phy", "common", "cfg";
 599                         status = "disabled";
 600
 601                         pciephy_0: lane@35000 {
 602                                 reg = <0x00035000 0x130>,
 603                                       <0x00035200 0x200>,
 604                                       <0x00035400 0x1dc>;
 605                                 #phy-cells = <0>;
 606
 607                                 clock-output-names = "pcie_0_pipe_clk_src";
 608                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 609                                 clock-names = "pipe0";
 610                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 611                                 reset-names = "lane0";
 612                         };
 613
 614                         pciephy_1: lane@36000 {
 615                                 reg = <0x00036000 0x130>,
 616                                       <0x00036200 0x200>,
 617                                       <0x00036400 0x1dc>;
 618                                 #phy-cells = <0>;
 619
 620                                 clock-output-names = "pcie_1_pipe_clk_src";
 621                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 622                                 clock-names = "pipe1";
 623                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 624                                 reset-names = "lane1";
 625                         };
 626
 627                         pciephy_2: lane@37000 {
 628                                 reg = <0x00037000 0x130>,
 629                                       <0x00037200 0x200>,
 630                                       <0x00037400 0x1dc>;
 631                                 #phy-cells = <0>;
 632
 633                                 clock-output-names = "pcie_2_pipe_clk_src";
 634                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 635                                 clock-names = "pipe2";
 636                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 637                                 reset-names = "lane2";
 638                         };
 639                 };
 640
 641                 rpm_msg_ram: memory@68000 {
 642                         compatible = "qcom,rpm-msg-ram";
 643                         reg = <0x00068000 0x6000>;
 644                 };
 645
 646                 qfprom@74000 {
 647                         compatible = "qcom,qfprom";
 648                         reg = <0x00074000 0x8ff>;
 649                         #address-cells = <1>;
 650                         #size-cells = <1>;
 651
 652                         qusb2p_hstx_trim: hstx_trim@24e {
 653                                 reg = <0x24e 0x2>;
 654                                 bits = <5 4>;
 655                         };
 656
 657                         qusb2s_hstx_trim: hstx_trim@24f {
 658                                 reg = <0x24f 0x1>;
 659                                 bits = <1 4>;
 660                         };
 661
 662                         speedbin_efuse: speedbin@133 {
 663                                 reg = <0x133 0x1>;
 664                                 bits = <5 3>;
 665                         };
 666                 };
 667
 668                 rng: rng@83000 {
 669                         compatible = "qcom,prng-ee";
 670                         reg = <0x00083000 0x1000>;
 671                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 672                         clock-names = "core";
 673                 };
 674
 675                 gcc: clock-controller@300000 {
 676                         compatible = "qcom,gcc-msm8996";
 677                         #clock-cells = <1>;
 678                         #reset-cells = <1>;
 679                         #power-domain-cells = <1>;
 680                         reg = <0x00300000 0x90000>;
 681
 682                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
 683                         clock-names = "cxo2";
 684                 };
 685
 686                 tsens0: thermal-sensor@4a9000 {
 687                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 688                         reg = <0x004a9000 0x1000>, /* TM */
 689                               <0x004a8000 0x1000>; /* SROT */
 690                         #qcom,sensors = <13>;
 691                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 693                         interrupt-names = "uplow", "critical";
 694                         #thermal-sensor-cells = <1>;
 695                 };
 696
 697                 tsens1: thermal-sensor@4ad000 {
 698                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 699                         reg = <0x004ad000 0x1000>, /* TM */
 700                               <0x004ac000 0x1000>; /* SROT */
 701                         #qcom,sensors = <8>;
 702                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 703                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 704                         interrupt-names = "uplow", "critical";
 705                         #thermal-sensor-cells = <1>;
 706                 };
 707
 708                 tcsr_mutex_regs: syscon@740000 {
 709                         compatible = "syscon";
 710                         reg = <0x00740000 0x40000>;
 711                 };
 712
 713                 tcsr: syscon@7a0000 {
 714                         compatible = "qcom,tcsr-msm8996", "syscon";
 715                         reg = <0x007a0000 0x18000>;
 716                 };
 717
 718                 mmcc: clock-controller@8c0000 {
 719                         compatible = "qcom,mmcc-msm8996";
 720                         #clock-cells = <1>;
 721                         #reset-cells = <1>;
 722                         #power-domain-cells = <1>;
 723                         reg = <0x008c0000 0x40000>;
 724                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 725                                           <&mmcc MMPLL1_PLL>,
 726                                           <&mmcc MMPLL3_PLL>,
 727                                           <&mmcc MMPLL4_PLL>,
 728                                           <&mmcc MMPLL5_PLL>;
 729                         assigned-clock-rates = <624000000>,
 730                                                <810000000>,
 731                                                <980000000>,
 732                                                <960000000>,
 733                                                <825000000>;
 734                 };
 735
 736                 mdss: mdss@900000 {
 737                         compatible = "qcom,mdss";
 738
 739                         reg = <0x00900000 0x1000>,
 740                               <0x009b0000 0x1040>,
 741                               <0x009b8000 0x1040>;
 742                         reg-names = "mdss_phys",
 743                                     "vbif_phys",
 744                                     "vbif_nrt_phys";
 745
 746                         power-domains = <&mmcc MDSS_GDSC>;
 747                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 748
 749                         interrupt-controller;
 750                         #interrupt-cells = <1>;
 751
 752                         clocks = <&mmcc MDSS_AHB_CLK>;
 753                         clock-names = "iface";
 754
 755                         #address-cells = <1>;
 756                         #size-cells = <1>;
 757                         ranges;
 758
 759                         status = "disabled";
 760
 761                         mdp: mdp@901000 {
 762                                 compatible = "qcom,mdp5";
 763                                 reg = <0x00901000 0x90000>;
 764                                 reg-names = "mdp_phys";
 765
 766                                 interrupt-parent = <&mdss>;
 767                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 768
 769                                 clocks = <&mmcc MDSS_AHB_CLK>,
 770                                          <&mmcc MDSS_AXI_CLK>,
 771                                          <&mmcc MDSS_MDP_CLK>,
 772                                          <&mmcc SMMU_MDP_AXI_CLK>,
 773                                          <&mmcc MDSS_VSYNC_CLK>;
 774                                 clock-names = "iface",
 775                                               "bus",
 776                                               "core",
 777                                               "iommu",
 778                                               "vsync";
 779
 780                                 iommus = <&mdp_smmu 0>;
 781
 782                                 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
 783                                          <&mmcc MDSS_VSYNC_CLK>;
 784                                 assigned-clock-rates = <300000000>,
 785                                          <19200000>;
 786
 787                                 ports {
 788                                         #address-cells = <1>;
 789                                         #size-cells = <0>;
 790
 791                                         port@0 {
 792                                                 reg = <0>;
 793                                                 mdp5_intf3_out: endpoint {
 794                                                         remote-endpoint = <&hdmi_in>;
 795                                                 };
 796                                         };
 797
 798                                         port@1 {
 799                                                 reg = <1>;
 800                                                 mdp5_intf1_out: endpoint {
 801                                                         remote-endpoint = <&dsi0_in>;
 802                                                 };
 803                                         };
 804                                 };
 805                         };
 806
 807                         dsi0: dsi@994000 {
 808                                 compatible = "qcom,mdss-dsi-ctrl";
 809                                 reg = <0x00994000 0x400>;
 810                                 reg-names = "dsi_ctrl";
 811
 812                                 interrupt-parent = <&mdss>;
 813                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 814
 815                                 clocks = <&mmcc MDSS_MDP_CLK>,
 816                                          <&mmcc MDSS_BYTE0_CLK>,
 817                                          <&mmcc MDSS_AHB_CLK>,
 818                                          <&mmcc MDSS_AXI_CLK>,
 819                                          <&mmcc MMSS_MISC_AHB_CLK>,
 820                                          <&mmcc MDSS_PCLK0_CLK>,
 821                                          <&mmcc MDSS_ESC0_CLK>;
 822                                 clock-names = "mdp_core",
 823                                               "byte",
 824                                               "iface",
 825                                               "bus",
 826                                               "core_mmss",
 827                                               "pixel",
 828                                               "core";
 829
 830                                 phys = <&dsi0_phy>;
 831                                 phy-names = "dsi";
 832                                 status = "disabled";
 833
 834                                 #address-cells = <1>;
 835                                 #size-cells = <0>;
 836
 837                                 ports {
 838                                         #address-cells = <1>;
 839                                         #size-cells = <0>;
 840
 841                                         port@0 {
 842                                                 reg = <0>;
 843                                                 dsi0_in: endpoint {
 844                                                         remote-endpoint = <&mdp5_intf1_out>;
 845                                                 };
 846                                         };
 847
 848                                         port@1 {
 849                                                 reg = <1>;
 850                                                 dsi0_out: endpoint {
 851                                                 };
 852                                         };
 853                                 };
 854                         };
 855
 856                         dsi0_phy: dsi-phy@994400 {
 857                                 compatible = "qcom,dsi-phy-14nm";
 858                                 reg = <0x00994400 0x100>,
 859                                       <0x00994500 0x300>,
 860                                       <0x00994800 0x188>;
 861                                 reg-names = "dsi_phy",
 862                                             "dsi_phy_lane",
 863                                             "dsi_pll";
 864
 865                                 #clock-cells = <1>;
 866                                 #phy-cells = <0>;
 867
 868                                 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
 869                                 clock-names = "iface", "ref";
 870                                 status = "disabled";
 871                         };
 872
 873                         hdmi: hdmi-tx@9a0000 {
 874                                 compatible = "qcom,hdmi-tx-8996";
 875                                 reg =   <0x009a0000 0x50c>,
 876                                         <0x00070000 0x6158>,
 877                                         <0x009e0000 0xfff>;
 878                                 reg-names = "core_physical",
 879                                             "qfprom_physical",
 880                                             "hdcp_physical";
 881
 882                                 interrupt-parent = <&mdss>;
 883                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 884
 885                                 clocks = <&mmcc MDSS_MDP_CLK>,
 886                                          <&mmcc MDSS_AHB_CLK>,
 887                                          <&mmcc MDSS_HDMI_CLK>,
 888                                          <&mmcc MDSS_HDMI_AHB_CLK>,
 889                                          <&mmcc MDSS_EXTPCLK_CLK>;
 890                                 clock-names =
 891                                         "mdp_core",
 892                                         "iface",
 893                                         "core",
 894                                         "alt_iface",
 895                                         "extp";
 896
 897                                 phys = <&hdmi_phy>;
 898                                 phy-names = "hdmi_phy";
 899                                 #sound-dai-cells = <1>;
 900
 901                                 ports {
 902                                         #address-cells = <1>;
 903                                         #size-cells = <0>;
 904
 905                                         port@0 {
 906                                                 reg = <0>;
 907                                                 hdmi_in: endpoint {
 908                                                         remote-endpoint = <&mdp5_intf3_out>;
 909                                                 };
 910                                         };
 911                                 };
 912                         };
 913
 914                         hdmi_phy: hdmi-phy@9a0600 {
 915                                 #phy-cells = <0>;
 916                                 compatible = "qcom,hdmi-phy-8996";
 917                                 reg = <0x009a0600 0x1c4>,
 918                                       <0x009a0a00 0x124>,
 919                                       <0x009a0c00 0x124>,
 920                                       <0x009a0e00 0x124>,
 921                                       <0x009a1000 0x124>,
 922                                       <0x009a1200 0x0c8>;
 923                                 reg-names = "hdmi_pll",
 924                                             "hdmi_tx_l0",
 925                                             "hdmi_tx_l1",
 926                                             "hdmi_tx_l2",
 927                                             "hdmi_tx_l3",
 928                                             "hdmi_phy";
 929
 930                                 clocks = <&mmcc MDSS_AHB_CLK>,
 931                                          <&gcc GCC_HDMI_CLKREF_CLK>;
 932                                 clock-names = "iface",
 933                                               "ref";
 934                         };
 935                 };
 936
 937                 gpu: gpu@b00000 {
 938                         compatible = "qcom,adreno-530.2", "qcom,adreno";
 939                         #stream-id-cells = <16>;
 940
 941                         reg = <0x00b00000 0x3f000>;
 942                         reg-names = "kgsl_3d0_reg_memory";
 943
 944                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
 945
 946                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
 947                                 <&mmcc GPU_AHB_CLK>,
 948                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
 949                                 <&gcc GCC_BIMC_GFX_CLK>,
 950                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
 951
 952                         clock-names = "core",
 953                                 "iface",
 954                                 "rbbmtimer",
 955                                 "mem",
 956                                 "mem_iface";
 957
 958                         power-domains = <&mmcc GPU_GX_GDSC>;
 959                         iommus = <&adreno_smmu 0>;
 960
 961                         nvmem-cells = <&speedbin_efuse>;
 962                         nvmem-cell-names = "speed_bin";
 963
 964                         qcom,gpu-quirk-two-pass-use-wfi;
 965                         qcom,gpu-quirk-fault-detect-mask;
 966
 967                         operating-points-v2 = <&gpu_opp_table>;
 968
 969                         status = "disabled";
 970
 971                         gpu_opp_table: opp-table {
 972                                 compatible  ="operating-points-v2";
 973
 974                                 /*
 975                                  * 624Mhz and 560Mhz are only available on speed
 976                                  * bin (1 << 0). All the rest are available on
 977                                  * all bins of the hardware
 978                                  */
 979                                 opp-624000000 {
 980                                         opp-hz = /bits/ 64 <624000000>;
 981                                         opp-supported-hw = <0x01>;
 982                                 };
 983                                 opp-560000000 {
 984                                         opp-hz = /bits/ 64 <560000000>;
 985                                         opp-supported-hw = <0x01>;
 986                                 };
 987                                 opp-510000000 {
 988                                         opp-hz = /bits/ 64 <510000000>;
 989                                         opp-supported-hw = <0xFF>;
 990                                 };
 991                                 opp-401800000 {
 992                                         opp-hz = /bits/ 64 <401800000>;
 993                                         opp-supported-hw = <0xFF>;
 994                                 };
 995                                 opp-315000000 {
 996                                         opp-hz = /bits/ 64 <315000000>;
 997                                         opp-supported-hw = <0xFF>;
 998                                 };
 999                                 opp-214000000 {
1000                                         opp-hz = /bits/ 64 <214000000>;
1001                                         opp-supported-hw = <0xFF>;
1002                                 };
1003                                 opp-133000000 {
1004                                         opp-hz = /bits/ 64 <133000000>;
1005                                         opp-supported-hw = <0xFF>;
1006                                 };
1007                         };
1008
1009                         zap-shader {
1010                                 memory-region = <&zap_shader_region>;
1011                         };
1012                 };
1013
1014                 tlmm: pinctrl@1010000 {
1015                         compatible = "qcom,msm8996-pinctrl";
1016                         reg = <0x01010000 0x300000>;
1017                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1018                         gpio-controller;
1019                         gpio-ranges = <&tlmm 0 0 150>;
1020                         #gpio-cells = <2>;
1021                         interrupt-controller;
1022                         #interrupt-cells = <2>;
1023
1024                         blsp1_spi1_default: blsp1-spi1-default {
1025                                 spi {
1026                                         pins = "gpio0", "gpio1", "gpio3";
1027                                         function = "blsp_spi1";
1028                                         drive-strength = <12>;
1029                                         bias-disable;
1030                                 };
1031
1032                                 cs {
1033                                         pins = "gpio2";
1034                                         function = "gpio";
1035                                         drive-strength = <16>;
1036                                         bias-disable;
1037                                         output-high;
1038                                 };
1039                         };
1040
1041                         blsp1_spi1_sleep: blsp1-spi1-sleep {
1042                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1043                                 function = "gpio";
1044                                 drive-strength = <2>;
1045                                 bias-pull-down;
1046                         };
1047
1048                         blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1049                                 pins = "gpio4", "gpio5";
1050                                 function = "blsp_uart8";
1051                                 drive-strength = <16>;
1052                                 bias-disable;
1053                         };
1054
1055                         blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1056                                 pins = "gpio4", "gpio5";
1057                                 function = "gpio";
1058                                 drive-strength = <2>;
1059                                 bias-disable;
1060                         };
1061
1062                         blsp2_i2c2_default: blsp2-i2c2 {
1063                                 pins = "gpio6", "gpio7";
1064                                 function = "blsp_i2c8";
1065                                 drive-strength = <16>;
1066                                 bias-disable;
1067                         };
1068
1069                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1070                                 pins = "gpio6", "gpio7";
1071                                 function = "gpio";
1072                                 drive-strength = <2>;
1073                                 bias-disable;
1074                         };
1075
1076                         cci0_default: cci0-default {
1077                                 pins = "gpio17", "gpio18";
1078                                 function = "cci_i2c";
1079                                 drive-strength = <16>;
1080                                 bias-disable;
1081                         };
1082
1083                         camera0_state_on:
1084                         camera_rear_default: camera-rear-default {
1085                                 mclk0 {
1086                                         pins = "gpio13";
1087                                         function = "cam_mclk";
1088                                         drive-strength = <16>;
1089                                         bias-disable;
1090                                 };
1091
1092                                 rst {
1093                                         pins = "gpio25";
1094                                         function = "gpio";
1095                                         drive-strength = <16>;
1096                                         bias-disable;
1097                                 };
1098
1099                                 pwdn {
1100                                         pins = "gpio26";
1101                                         function = "gpio";
1102                                         drive-strength = <16>;
1103                                         bias-disable;
1104                                 };
1105                         };
1106
1107                         cci1_default: cci1-default {
1108                                 pins = "gpio19", "gpio20";
1109                                 function = "cci_i2c";
1110                                 drive-strength = <16>;
1111                                 bias-disable;
1112                         };
1113
1114                         camera1_state_on:
1115                         camera_board_default: camera-board-default {
1116                                 mclk1 {
1117                                         pins = "gpio14";
1118                                         function = "cam_mclk";
1119                                         drive-strength = <16>;
1120                                         bias-disable;
1121                                 };
1122
1123                                 pwdn {
1124                                         pins = "gpio98";
1125                                         function = "gpio";
1126                                         drive-strength = <16>;
1127                                         bias-disable;
1128                                 };
1129
1130                                 rst {
1131                                         pins = "gpio104";
1132                                         function = "gpio";
1133                                         drive-strength = <16>;
1134                                         bias-disable;
1135                                 };
1136                         };
1137
1138                         camera2_state_on:
1139                         camera_front_default: camera-front-default {
1140                                 mclk2 {
1141                                         pins = "gpio15";
1142                                         function = "cam_mclk";
1143                                         drive-strength = <16>;
1144                                         bias-disable;
1145                                 };
1146
1147                                 rst {
1148                                         pins = "gpio23";
1149                                         function = "gpio";
1150                                         drive-strength = <16>;
1151                                         bias-disable;
1152                                 };
1153
1154                                 pwdn {
1155                                         pins = "gpio133";
1156                                         function = "gpio";
1157                                         drive-strength = <16>;
1158                                         bias-disable;
1159                                 };
1160                         };
1161
1162                         pcie0_state_on: pcie0-state-on {
1163                                 perst {
1164                                         pins = "gpio35";
1165                                         function = "gpio";
1166                                         drive-strength = <2>;
1167                                         bias-pull-down;
1168                                 };
1169
1170                                 clkreq {
1171                                         pins = "gpio36";
1172                                         function = "pci_e0";
1173                                         drive-strength = <2>;
1174                                         bias-pull-up;
1175                                 };
1176
1177                                 wake {
1178                                         pins = "gpio37";
1179                                         function = "gpio";
1180                                         drive-strength = <2>;
1181                                         bias-pull-up;
1182                                 };
1183                         };
1184
1185                         pcie0_state_off: pcie0-state-off {
1186                                 perst {
1187                                         pins = "gpio35";
1188                                         function = "gpio";
1189                                         drive-strength = <2>;
1190                                         bias-pull-down;
1191                                 };
1192
1193                                 clkreq {
1194                                         pins = "gpio36";
1195                                         function = "gpio";
1196                                         drive-strength = <2>;
1197                                         bias-disable;
1198                                 };
1199
1200                                 wake {
1201                                         pins = "gpio37";
1202                                         function = "gpio";
1203                                         drive-strength = <2>;
1204                                         bias-disable;
1205                                 };
1206                         };
1207
1208                         blsp1_i2c3_default: blsp1-i2c2-default {
1209                                 pins = "gpio47", "gpio48";
1210                                 function = "blsp_i2c3";
1211                                 drive-strength = <16>;
1212                                 bias-disable = <0>;
1213                         };
1214
1215                         blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1216                                 pins = "gpio47", "gpio48";
1217                                 function = "gpio";
1218                                 drive-strength = <2>;
1219                                 bias-disable = <0>;
1220                         };
1221
1222                         blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1223                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1224                                 function = "blsp_uart9";
1225                                 drive-strength = <16>;
1226                                 bias-disable;
1227                         };
1228
1229                         blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1230                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1231                                 function = "blsp_uart9";
1232                                 drive-strength = <2>;
1233                                 bias-disable;
1234                         };
1235
1236                         wcd_intr_default: wcd-intr-default{
1237                                 pins = "gpio54";
1238                                 function = "gpio";
1239                                 drive-strength = <2>;
1240                                 bias-pull-down;
1241                                 input-enable;
1242                         };
1243
1244                         blsp2_i2c1_default: blsp2-i2c1 {
1245                                 pins = "gpio55", "gpio56";
1246                                 function = "blsp_i2c7";
1247                                 drive-strength = <16>;
1248                                 bias-disable;
1249                         };
1250
1251                         blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1252                                 pins = "gpio55", "gpio56";
1253                                 function = "gpio";
1254                                 drive-strength = <2>;
1255                                 bias-disable;
1256                         };
1257
1258                         blsp2_i2c5_default: blsp2-i2c5 {
1259                                 pins = "gpio60", "gpio61";
1260                                 function = "blsp_i2c11";
1261                                 drive-strength = <2>;
1262                                 bias-disable;
1263                         };
1264
1265                         /* Sleep state for BLSP2_I2C5 is missing.. */
1266
1267                         cdc_reset_active: cdc-reset-active {
1268                                 pins = "gpio64";
1269                                 function = "gpio";
1270                                 drive-strength = <16>;
1271                                 bias-pull-down;
1272                                 output-high;
1273                         };
1274
1275                         cdc_reset_sleep: cdc-reset-sleep {
1276                                 pins = "gpio64";
1277                                 function = "gpio";
1278                                 drive-strength = <16>;
1279                                 bias-disable;
1280                                 output-low;
1281                         };
1282
1283                         blsp2_spi6_default: blsp2-spi5-default {
1284                                 spi {
1285                                         pins = "gpio85", "gpio86", "gpio88";
1286                                         function = "blsp_spi12";
1287                                         drive-strength = <12>;
1288                                         bias-disable;
1289                                 };
1290
1291                                 cs {
1292                                         pins = "gpio87";
1293                                         function = "gpio";
1294                                         drive-strength = <16>;
1295                                         bias-disable;
1296                                         output-high;
1297                                 };
1298                         };
1299
1300                         blsp2_spi6_sleep: blsp2-spi5-sleep {
1301                                 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1302                                 function = "gpio";
1303                                 drive-strength = <2>;
1304                                 bias-pull-down;
1305                         };
1306
1307                         blsp2_i2c6_default: blsp2-i2c6 {
1308                                 pins = "gpio87", "gpio88";
1309                                 function = "blsp_i2c12";
1310                                 drive-strength = <16>;
1311                                 bias-disable;
1312                         };
1313
1314                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1315                                 pins = "gpio87", "gpio88";
1316                                 function = "gpio";
1317                                 drive-strength = <2>;
1318                                 bias-disable;
1319                         };
1320
1321                         pcie1_state_on: pcie1-state-on {
1322                                 perst {
1323                                         pins = "gpio130";
1324                                         function = "gpio";
1325                                         drive-strength = <2>;
1326                                         bias-pull-down;
1327                                 };
1328
1329                                 clkreq {
1330                                         pins = "gpio131";
1331                                         function = "pci_e1";
1332                                         drive-strength = <2>;
1333                                         bias-pull-up;
1334                                 };
1335
1336                                 wake {
1337                                         pins = "gpio132";
1338                                         function = "gpio";
1339                                         drive-strength = <2>;
1340                                         bias-pull-down;
1341                                 };
1342                         };
1343
1344                         pcie1_state_off: pcie1-state-off {
1345                                 /* Perst is missing? */
1346                                 clkreq {
1347                                         pins = "gpio131";
1348                                         function = "gpio";
1349                                         drive-strength = <2>;
1350                                         bias-disable;
1351                                 };
1352
1353                                 wake {
1354                                         pins = "gpio132";
1355                                         function = "gpio";
1356                                         drive-strength = <2>;
1357                                         bias-disable;
1358                                 };
1359                         };
1360
1361                         pcie2_state_on: pcie2-state-on {
1362                                 perst {
1363                                         pins = "gpio114";
1364                                         function = "gpio";
1365                                         drive-strength = <2>;
1366                                         bias-pull-down;
1367                                 };
1368
1369                                 clkreq {
1370                                         pins = "gpio115";
1371                                         function = "pci_e2";
1372                                         drive-strength = <2>;
1373                                         bias-pull-up;
1374                                 };
1375
1376                                 wake {
1377                                         pins = "gpio116";
1378                                         function = "gpio";
1379                                         drive-strength = <2>;
1380                                         bias-pull-down;
1381                                 };
1382                         };
1383
1384                         pcie2_state_off: pcie2-state-off {
1385                                 /* Perst is missing? */
1386                                 clkreq {
1387                                         pins = "gpio115";
1388                                         function = "gpio";
1389                                         drive-strength = <2>;
1390                                         bias-disable;
1391                                 };
1392
1393                                 wake {
1394                                         pins = "gpio116";
1395                                         function = "gpio";
1396                                         drive-strength = <2>;
1397                                         bias-disable;
1398                                 };
1399                         };
1400
1401                         sdc1_state_on: sdc1-state-on {
1402                                 clk {
1403                                         pins = "sdc1_clk";
1404                                         bias-disable;
1405                                         drive-strength = <16>;
1406                                 };
1407
1408                                 cmd {
1409                                         pins = "sdc1_cmd";
1410                                         bias-pull-up;
1411                                         drive-strength = <10>;
1412                                 };
1413
1414                                 data {
1415                                         pins = "sdc1_data";
1416                                         bias-pull-up;
1417                                         drive-strength = <10>;
1418                                 };
1419
1420                                 rclk {
1421                                         pins = "sdc1_rclk";
1422                                         bias-pull-down;
1423                                 };
1424                         };
1425
1426                         sdc1_state_off: sdc1-state-off {
1427                                 clk {
1428                                         pins = "sdc1_clk";
1429                                         bias-disable;
1430                                         drive-strength = <2>;
1431                                 };
1432
1433                                 cmd {
1434                                         pins = "sdc1_cmd";
1435                                         bias-pull-up;
1436                                         drive-strength = <2>;
1437                                 };
1438
1439                                 data {
1440                                         pins = "sdc1_data";
1441                                         bias-pull-up;
1442                                         drive-strength = <2>;
1443                                 };
1444
1445                                 rclk {
1446                                         pins = "sdc1_rclk";
1447                                         bias-pull-down;
1448                                 };
1449                         };
1450
1451                         sdc2_state_on: sdc2-clk-on {
1452                                 clk {
1453                                         pins = "sdc2_clk";
1454                                         bias-disable;
1455                                         drive-strength = <16>;
1456                                 };
1457
1458                                 cmd {
1459                                         pins = "sdc2_cmd";
1460                                         bias-pull-up;
1461                                         drive-strength = <10>;
1462                                 };
1463
1464                                 data {
1465                                         pins = "sdc2_data";
1466                                         bias-pull-up;
1467                                         drive-strength = <10>;
1468                                 };
1469                         };
1470
1471                         sdc2_state_off: sdc2-clk-off {
1472                                 clk {
1473                                         pins = "sdc2_clk";
1474                                         bias-disable;
1475                                         drive-strength = <2>;
1476                                 };
1477
1478                                 cmd {
1479                                         pins = "sdc2_cmd";
1480                                         bias-pull-up;
1481                                         drive-strength = <2>;
1482                                 };
1483
1484                                 data {
1485                                         pins = "sdc2_data";
1486                                         bias-pull-up;
1487                                         drive-strength = <2>;
1488                                 };
1489                         };
1490                 };
1491
1492                 spmi_bus: qcom,spmi@400f000 {
1493                         compatible = "qcom,spmi-pmic-arb";
1494                         reg = <0x0400f000 0x1000>,
1495                               <0x04400000 0x800000>,
1496                               <0x04c00000 0x800000>,
1497                               <0x05800000 0x200000>,
1498                               <0x0400a000 0x002100>;
1499                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1500                         interrupt-names = "periph_irq";
1501                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1502                         qcom,ee = <0>;
1503                         qcom,channel = <0>;
1504                         #address-cells = <2>;
1505                         #size-cells = <0>;
1506                         interrupt-controller;
1507                         #interrupt-cells = <4>;
1508                 };
1509
1510                 agnoc@0 {
1511                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1512                         compatible = "simple-pm-bus";
1513                         #address-cells = <1>;
1514                         #size-cells = <1>;
1515                         ranges;
1516
1517                         pcie0: pcie@600000 {
1518                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1519                                 status = "disabled";
1520                                 power-domains = <&gcc PCIE0_GDSC>;
1521                                 bus-range = <0x00 0xff>;
1522                                 num-lanes = <1>;
1523
1524                                 reg = <0x00600000 0x2000>,
1525                                       <0x0c000000 0xf1d>,
1526                                       <0x0c000f20 0xa8>,
1527                                       <0x0c100000 0x100000>;
1528                                 reg-names = "parf", "dbi", "elbi","config";
1529
1530                                 phys = <&pciephy_0>;
1531                                 phy-names = "pciephy";
1532
1533                                 #address-cells = <3>;
1534                                 #size-cells = <2>;
1535                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1536                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1537
1538                                 device_type = "pci";
1539
1540                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1541                                 interrupt-names = "msi";
1542                                 #interrupt-cells = <1>;
1543                                 interrupt-map-mask = <0 0 0 0x7>;
1544                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1545                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1546                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1547                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1548
1549                                 pinctrl-names = "default", "sleep";
1550                                 pinctrl-0 = <&pcie0_state_on>;
1551                                 pinctrl-1 = <&pcie0_state_off>;
1552
1553                                 linux,pci-domain = <0>;
1554
1555                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1556                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1557                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1558                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1559                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1560
1561                                 clock-names =  "pipe",
1562                                                 "aux",
1563                                                 "cfg",
1564                                                 "bus_master",
1565                                                 "bus_slave";
1566
1567                         };
1568
1569                         pcie1: pcie@608000 {
1570                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1571                                 power-domains = <&gcc PCIE1_GDSC>;
1572                                 bus-range = <0x00 0xff>;
1573                                 num-lanes = <1>;
1574
1575                                 status  = "disabled";
1576
1577                                 reg = <0x00608000 0x2000>,
1578                                       <0x0d000000 0xf1d>,
1579                                       <0x0d000f20 0xa8>,
1580                                       <0x0d100000 0x100000>;
1581
1582                                 reg-names = "parf", "dbi", "elbi","config";
1583
1584                                 phys = <&pciephy_1>;
1585                                 phy-names = "pciephy";
1586
1587                                 #address-cells = <3>;
1588                                 #size-cells = <2>;
1589                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1590                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1591
1592                                 device_type = "pci";
1593
1594                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1595                                 interrupt-names = "msi";
1596                                 #interrupt-cells = <1>;
1597                                 interrupt-map-mask = <0 0 0 0x7>;
1598                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1599                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1600                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1601                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1602
1603                                 pinctrl-names = "default", "sleep";
1604                                 pinctrl-0 = <&pcie1_state_on>;
1605                                 pinctrl-1 = <&pcie1_state_off>;
1606
1607                                 linux,pci-domain = <1>;
1608
1609                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1610                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1611                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1612                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1613                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1614
1615                                 clock-names =  "pipe",
1616                                                 "aux",
1617                                                 "cfg",
1618                                                 "bus_master",
1619                                                 "bus_slave";
1620                         };
1621
1622                         pcie2: pcie@610000 {
1623                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1624                                 power-domains = <&gcc PCIE2_GDSC>;
1625                                 bus-range = <0x00 0xff>;
1626                                 num-lanes = <1>;
1627                                 status = "disabled";
1628                                 reg = <0x00610000 0x2000>,
1629                                       <0x0e000000 0xf1d>,
1630                                       <0x0e000f20 0xa8>,
1631                                       <0x0e100000 0x100000>;
1632
1633                                 reg-names = "parf", "dbi", "elbi","config";
1634
1635                                 phys = <&pciephy_2>;
1636                                 phy-names = "pciephy";
1637
1638                                 #address-cells = <3>;
1639                                 #size-cells = <2>;
1640                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1641                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1642
1643                                 device_type = "pci";
1644
1645                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1646                                 interrupt-names = "msi";
1647                                 #interrupt-cells = <1>;
1648                                 interrupt-map-mask = <0 0 0 0x7>;
1649                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1650                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1651                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1652                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1653
1654                                 pinctrl-names = "default", "sleep";
1655                                 pinctrl-0 = <&pcie2_state_on>;
1656                                 pinctrl-1 = <&pcie2_state_off>;
1657
1658                                 linux,pci-domain = <2>;
1659                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1660                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1661                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1662                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1663                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1664
1665                                 clock-names =  "pipe",
1666                                                 "aux",
1667                                                 "cfg",
1668                                                 "bus_master",
1669                                                 "bus_slave";
1670                         };
1671                 };
1672
1673                 ufshc: ufshc@624000 {
1674                         compatible = "qcom,ufshc";
1675                         reg = <0x00624000 0x2500>;
1676                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1677
1678                         phys = <&ufsphy_lane>;
1679                         phy-names = "ufsphy";
1680
1681                         power-domains = <&gcc UFS_GDSC>;
1682
1683                         clock-names =
1684                                 "core_clk_src",
1685                                 "core_clk",
1686                                 "bus_clk",
1687                                 "bus_aggr_clk",
1688                                 "iface_clk",
1689                                 "core_clk_unipro_src",
1690                                 "core_clk_unipro",
1691                                 "core_clk_ice",
1692                                 "ref_clk",
1693                                 "tx_lane0_sync_clk",
1694                                 "rx_lane0_sync_clk";
1695                         clocks =
1696                                 <&gcc UFS_AXI_CLK_SRC>,
1697                                 <&gcc GCC_UFS_AXI_CLK>,
1698                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1699                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1700                                 <&gcc GCC_UFS_AHB_CLK>,
1701                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
1702                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1703                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
1704                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
1705                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1706                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1707                         freq-table-hz =
1708                                 <100000000 200000000>,
1709                                 <0 0>,
1710                                 <0 0>,
1711                                 <0 0>,
1712                                 <0 0>,
1713                                 <150000000 300000000>,
1714                                 <0 0>,
1715                                 <0 0>,
1716                                 <0 0>,
1717                                 <0 0>,
1718                                 <0 0>;
1719
1720                         lanes-per-direction = <1>;
1721                         #reset-cells = <1>;
1722                         status = "disabled";
1723
1724                         ufs_variant {
1725                                 compatible = "qcom,ufs_variant";
1726                         };
1727                 };
1728
1729                 ufsphy: phy@627000 {
1730                         compatible = "qcom,msm8996-qmp-ufs-phy";
1731                         reg = <0x00627000 0x1c4>;
1732                         #address-cells = <1>;
1733                         #size-cells = <1>;
1734                         ranges;
1735
1736                         clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1737                         clock-names = "ref";
1738
1739                         resets = <&ufshc 0>;
1740                         reset-names = "ufsphy";
1741                         status = "disabled";
1742
1743                         ufsphy_lane: lanes@627400 {
1744                                 reg = <0x627400 0x12c>,
1745                                       <0x627600 0x200>,
1746                                       <0x627c00 0x1b4>;
1747                                 #phy-cells = <0>;
1748                         };
1749                 };
1750
1751                 camss: camss@a00000 {
1752                         compatible = "qcom,msm8996-camss";
1753                         reg = <0x00a34000 0x1000>,
1754                               <0x00a00030 0x4>,
1755                               <0x00a35000 0x1000>,
1756                               <0x00a00038 0x4>,
1757                               <0x00a36000 0x1000>,
1758                               <0x00a00040 0x4>,
1759                               <0x00a30000 0x100>,
1760                               <0x00a30400 0x100>,
1761                               <0x00a30800 0x100>,
1762                               <0x00a30c00 0x100>,
1763                               <0x00a31000 0x500>,
1764                               <0x00a00020 0x10>,
1765                               <0x00a10000 0x1000>,
1766                               <0x00a14000 0x1000>;
1767                         reg-names = "csiphy0",
1768                                 "csiphy0_clk_mux",
1769                                 "csiphy1",
1770                                 "csiphy1_clk_mux",
1771                                 "csiphy2",
1772                                 "csiphy2_clk_mux",
1773                                 "csid0",
1774                                 "csid1",
1775                                 "csid2",
1776                                 "csid3",
1777                                 "ispif",
1778                                 "csi_clk_mux",
1779                                 "vfe0",
1780                                 "vfe1";
1781                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1782                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1783                                 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1784                                 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1785                                 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1786                                 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1787                                 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1788                                 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1789                                 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1790                                 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1791                         interrupt-names = "csiphy0",
1792                                 "csiphy1",
1793                                 "csiphy2",
1794                                 "csid0",
1795                                 "csid1",
1796                                 "csid2",
1797                                 "csid3",
1798                                 "ispif",
1799                                 "vfe0",
1800                                 "vfe1";
1801                         power-domains = <&mmcc VFE0_GDSC>,
1802                                         <&mmcc VFE1_GDSC>;
1803                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1804                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1805                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1806                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1807                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1808                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1809                                 <&mmcc CAMSS_CSI0_CLK>,
1810                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1811                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1812                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1813                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1814                                 <&mmcc CAMSS_CSI1_CLK>,
1815                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1816                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1817                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1818                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1819                                 <&mmcc CAMSS_CSI2_CLK>,
1820                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1821                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1822                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1823                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1824                                 <&mmcc CAMSS_CSI3_CLK>,
1825                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1826                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1827                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1828                                 <&mmcc CAMSS_AHB_CLK>,
1829                                 <&mmcc CAMSS_VFE0_CLK>,
1830                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1831                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1832                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1833                                 <&mmcc CAMSS_VFE1_CLK>,
1834                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1835                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1836                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1837                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1838                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1839                         clock-names = "top_ahb",
1840                                 "ispif_ahb",
1841                                 "csiphy0_timer",
1842                                 "csiphy1_timer",
1843                                 "csiphy2_timer",
1844                                 "csi0_ahb",
1845                                 "csi0",
1846                                 "csi0_phy",
1847                                 "csi0_pix",
1848                                 "csi0_rdi",
1849                                 "csi1_ahb",
1850                                 "csi1",
1851                                 "csi1_phy",
1852                                 "csi1_pix",
1853                                 "csi1_rdi",
1854                                 "csi2_ahb",
1855                                 "csi2",
1856                                 "csi2_phy",
1857                                 "csi2_pix",
1858                                 "csi2_rdi",
1859                                 "csi3_ahb",
1860                                 "csi3",
1861                                 "csi3_phy",
1862                                 "csi3_pix",
1863                                 "csi3_rdi",
1864                                 "ahb",
1865                                 "vfe0",
1866                                 "csi_vfe0",
1867                                 "vfe0_ahb",
1868                                 "vfe0_stream",
1869                                 "vfe1",
1870                                 "csi_vfe1",
1871                                 "vfe1_ahb",
1872                                 "vfe1_stream",
1873                                 "vfe_ahb",
1874                                 "vfe_axi";
1875                         iommus = <&vfe_smmu 0>,
1876                                  <&vfe_smmu 1>,
1877                                  <&vfe_smmu 2>,
1878                                  <&vfe_smmu 3>;
1879                         status = "disabled";
1880                         ports {
1881                                 #address-cells = <1>;
1882                                 #size-cells = <0>;
1883                         };
1884                 };
1885
1886                 cci: cci@a0c000 {
1887                         compatible = "qcom,msm8996-cci";
1888                         #address-cells = <1>;
1889                         #size-cells = <0>;
1890                         reg = <0xa0c000 0x1000>;
1891                         interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1892                         power-domains = <&mmcc CAMSS_GDSC>;
1893                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1894                                  <&mmcc CAMSS_CCI_AHB_CLK>,
1895                                  <&mmcc CAMSS_CCI_CLK>,
1896                                  <&mmcc CAMSS_AHB_CLK>;
1897                         clock-names = "camss_top_ahb",
1898                                       "cci_ahb",
1899                                       "cci",
1900                                       "camss_ahb";
1901                         assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1902                                           <&mmcc CAMSS_CCI_CLK>;
1903                         assigned-clock-rates = <80000000>, <37500000>;
1904                         pinctrl-names = "default";
1905                         pinctrl-0 = <&cci0_default &cci1_default>;
1906                         status = "disabled";
1907
1908                         cci_i2c0: i2c-bus@0 {
1909                                 reg = <0>;
1910                                 clock-frequency = <400000>;
1911                                 #address-cells = <1>;
1912                                 #size-cells = <0>;
1913                         };
1914
1915                         cci_i2c1: i2c-bus@1 {
1916                                 reg = <1>;
1917                                 clock-frequency = <400000>;
1918                                 #address-cells = <1>;
1919                                 #size-cells = <0>;
1920                         };
1921                 };
1922
1923                 adreno_smmu: iommu@b40000 {
1924                         compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1925                         reg = <0x00b40000 0x10000>;
1926
1927                         #global-interrupts = <1>;
1928                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1929                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1930                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1931                         #iommu-cells = <1>;
1932
1933                         clocks = <&mmcc GPU_AHB_CLK>,
1934                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1935                         clock-names = "iface", "bus";
1936
1937                         power-domains = <&mmcc GPU_GDSC>;
1938                 };
1939
1940                 venus: video-codec@c00000 {
1941                         compatible = "qcom,msm8996-venus";
1942                         reg = <0x00c00000 0xff000>;
1943                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1944                         power-domains = <&mmcc VENUS_GDSC>;
1945                         clocks = <&mmcc VIDEO_CORE_CLK>,
1946                                  <&mmcc VIDEO_AHB_CLK>,
1947                                  <&mmcc VIDEO_AXI_CLK>,
1948                                  <&mmcc VIDEO_MAXI_CLK>;
1949                         clock-names = "core", "iface", "bus", "mbus";
1950                         iommus = <&venus_smmu 0x00>,
1951                                  <&venus_smmu 0x01>,
1952                                  <&venus_smmu 0x0a>,
1953                                  <&venus_smmu 0x07>,
1954                                  <&venus_smmu 0x0e>,
1955                                  <&venus_smmu 0x0f>,
1956                                  <&venus_smmu 0x08>,
1957                                  <&venus_smmu 0x09>,
1958                                  <&venus_smmu 0x0b>,
1959                                  <&venus_smmu 0x0c>,
1960                                  <&venus_smmu 0x0d>,
1961                                  <&venus_smmu 0x10>,
1962                                  <&venus_smmu 0x11>,
1963                                  <&venus_smmu 0x21>,
1964                                  <&venus_smmu 0x28>,
1965                                  <&venus_smmu 0x29>,
1966                                  <&venus_smmu 0x2b>,
1967                                  <&venus_smmu 0x2c>,
1968                                  <&venus_smmu 0x2d>,
1969                                  <&venus_smmu 0x31>;
1970                         memory-region = <&venus_region>;
1971                         status = "disabled";
1972
1973                         video-decoder {
1974                                 compatible = "venus-decoder";
1975                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1976                                 clock-names = "core";
1977                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1978                         };
1979
1980                         video-encoder {
1981                                 compatible = "venus-encoder";
1982                                 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1983                                 clock-names = "core";
1984                                 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1985                         };
1986                 };
1987
1988                 mdp_smmu: iommu@d00000 {
1989                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1990                         reg = <0x00d00000 0x10000>;
1991
1992                         #global-interrupts = <1>;
1993                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1994                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1995                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1996                         #iommu-cells = <1>;
1997                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1998                                  <&mmcc SMMU_MDP_AXI_CLK>;
1999                         clock-names = "iface", "bus";
2000
2001                         power-domains = <&mmcc MDSS_GDSC>;
2002                 };
2003
2004                 venus_smmu: iommu@d40000 {
2005                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2006                         reg = <0x00d40000 0x20000>;
2007                         #global-interrupts = <1>;
2008                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2009                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2010                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2011                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2012                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2013                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2014                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2015                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2016                         power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2017                         clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2018                                  <&mmcc SMMU_VIDEO_AXI_CLK>;
2019                         clock-names = "iface", "bus";
2020                         #iommu-cells = <1>;
2021                         status = "okay";
2022                 };
2023
2024                 vfe_smmu: iommu@da0000 {
2025                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2026                         reg = <0x00da0000 0x10000>;
2027
2028                         #global-interrupts = <1>;
2029                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2030                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2031                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2032                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2033                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2034                                  <&mmcc SMMU_VFE_AXI_CLK>;
2035                         clock-names = "iface",
2036                                       "bus";
2037                         #iommu-cells = <1>;
2038                 };
2039
2040                 lpass_q6_smmu: iommu@1600000 {
2041                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2042                         reg = <0x01600000 0x20000>;
2043                         #iommu-cells = <1>;
2044                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2045
2046                         #global-interrupts = <1>;
2047                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2048                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2049                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2050                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2051                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2052                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2053                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2054                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2055                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2056                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2057                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2058                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2059                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2060
2061                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2062                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2063                         clock-names = "iface", "bus";
2064                 };
2065
2066                 stm@3002000 {
2067                         compatible = "arm,coresight-stm", "arm,primecell";
2068                         reg = <0x3002000 0x1000>,
2069                               <0x8280000 0x180000>;
2070                         reg-names = "stm-base", "stm-stimulus-base";
2071
2072                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2073                         clock-names = "apb_pclk", "atclk";
2074
2075                         out-ports {
2076                                 port {
2077                                         stm_out: endpoint {
2078                                                 remote-endpoint =
2079                                                   <&funnel0_in>;
2080                                         };
2081                                 };
2082                         };
2083                 };
2084
2085                 tpiu@3020000 {
2086                         compatible = "arm,coresight-tpiu", "arm,primecell";
2087                         reg = <0x3020000 0x1000>;
2088
2089                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2090                         clock-names = "apb_pclk", "atclk";
2091
2092                         in-ports {
2093                                 port {
2094                                         tpiu_in: endpoint {
2095                                                 remote-endpoint =
2096                                                   <&replicator_out1>;
2097                                         };
2098                                 };
2099                         };
2100                 };
2101
2102                 funnel@3021000 {
2103                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2104                         reg = <0x3021000 0x1000>;
2105
2106                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2107                         clock-names = "apb_pclk", "atclk";
2108
2109                         in-ports {
2110                                 #address-cells = <1>;
2111                                 #size-cells = <0>;
2112
2113                                 port@7 {
2114                                         reg = <7>;
2115                                         funnel0_in: endpoint {
2116                                                 remote-endpoint =
2117                                                   <&stm_out>;
2118                                         };
2119                                 };
2120                         };
2121
2122                         out-ports {
2123                                 port {
2124                                         funnel0_out: endpoint {
2125                                                 remote-endpoint =
2126                                                   <&merge_funnel_in0>;
2127                                         };
2128                                 };
2129                         };
2130                 };
2131
2132                 funnel@3022000 {
2133                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2134                         reg = <0x3022000 0x1000>;
2135
2136                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2137                         clock-names = "apb_pclk", "atclk";
2138
2139                         in-ports {
2140                                 #address-cells = <1>;
2141                                 #size-cells = <0>;
2142
2143                                 port@6 {
2144                                         reg = <6>;
2145                                         funnel1_in: endpoint {
2146                                                 remote-endpoint =
2147                                                   <&apss_merge_funnel_out>;
2148                                         };
2149                                 };
2150                         };
2151
2152                         out-ports {
2153                                 port {
2154                                         funnel1_out: endpoint {
2155                                                 remote-endpoint =
2156                                                   <&merge_funnel_in1>;
2157                                         };
2158                                 };
2159                         };
2160                 };
2161
2162                 funnel@3023000 {
2163                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2164                         reg = <0x3023000 0x1000>;
2165
2166                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2167                         clock-names = "apb_pclk", "atclk";
2168
2169
2170                         out-ports {
2171                                 port {
2172                                         funnel2_out: endpoint {
2173                                                 remote-endpoint =
2174                                                   <&merge_funnel_in2>;
2175                                         };
2176                                 };
2177                         };
2178                 };
2179
2180                 funnel@3025000 {
2181                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2182                         reg = <0x3025000 0x1000>;
2183
2184                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2185                         clock-names = "apb_pclk", "atclk";
2186
2187                         in-ports {
2188                                 #address-cells = <1>;
2189                                 #size-cells = <0>;
2190
2191                                 port@0 {
2192                                         reg = <0>;
2193                                         merge_funnel_in0: endpoint {
2194                                                 remote-endpoint =
2195                                                   <&funnel0_out>;
2196                                         };
2197                                 };
2198
2199                                 port@1 {
2200                                         reg = <1>;
2201                                         merge_funnel_in1: endpoint {
2202                                                 remote-endpoint =
2203                                                   <&funnel1_out>;
2204                                         };
2205                                 };
2206
2207                                 port@2 {
2208                                         reg = <2>;
2209                                         merge_funnel_in2: endpoint {
2210                                                 remote-endpoint =
2211                                                   <&funnel2_out>;
2212                                         };
2213                                 };
2214                         };
2215
2216                         out-ports {
2217                                 port {
2218                                         merge_funnel_out: endpoint {
2219                                                 remote-endpoint =
2220                                                   <&etf_in>;
2221                                         };
2222                                 };
2223                         };
2224                 };
2225
2226                 replicator@3026000 {
2227                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2228                         reg = <0x3026000 0x1000>;
2229
2230                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2231                         clock-names = "apb_pclk", "atclk";
2232
2233                         in-ports {
2234                                 port {
2235                                         replicator_in: endpoint {
2236                                                 remote-endpoint =
2237                                                   <&etf_out>;
2238                                         };
2239                                 };
2240                         };
2241
2242                         out-ports {
2243                                 #address-cells = <1>;
2244                                 #size-cells = <0>;
2245
2246                                 port@0 {
2247                                         reg = <0>;
2248                                         replicator_out0: endpoint {
2249                                                 remote-endpoint =
2250                                                   <&etr_in>;
2251                                         };
2252                                 };
2253
2254                                 port@1 {
2255                                         reg = <1>;
2256                                         replicator_out1: endpoint {
2257                                                 remote-endpoint =
2258                                                   <&tpiu_in>;
2259                                         };
2260                                 };
2261                         };
2262                 };
2263
2264                 etf@3027000 {
2265                         compatible = "arm,coresight-tmc", "arm,primecell";
2266                         reg = <0x3027000 0x1000>;
2267
2268                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2269                         clock-names = "apb_pclk", "atclk";
2270
2271                         in-ports {
2272                                 port {
2273                                         etf_in: endpoint {
2274                                                 remote-endpoint =
2275                                                   <&merge_funnel_out>;
2276                                         };
2277                                 };
2278                         };
2279
2280                         out-ports {
2281                                 port {
2282                                         etf_out: endpoint {
2283                                                 remote-endpoint =
2284                                                   <&replicator_in>;
2285                                         };
2286                                 };
2287                         };
2288                 };
2289
2290                 etr@3028000 {
2291                         compatible = "arm,coresight-tmc", "arm,primecell";
2292                         reg = <0x3028000 0x1000>;
2293
2294                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2295                         clock-names = "apb_pclk", "atclk";
2296                         arm,scatter-gather;
2297
2298                         in-ports {
2299                                 port {
2300                                         etr_in: endpoint {
2301                                                 remote-endpoint =
2302                                                   <&replicator_out0>;
2303                                         };
2304                                 };
2305                         };
2306                 };
2307
2308                 debug@3810000 {
2309                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2310                         reg = <0x3810000 0x1000>;
2311
2312                         clocks = <&rpmcc RPM_QDSS_CLK>;
2313                         clock-names = "apb_pclk";
2314
2315                         cpu = <&CPU0>;
2316                 };
2317
2318                 etm@3840000 {
2319                         compatible = "arm,coresight-etm4x", "arm,primecell";
2320                         reg = <0x3840000 0x1000>;
2321
2322                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2323                         clock-names = "apb_pclk", "atclk";
2324
2325                         cpu = <&CPU0>;
2326
2327                         out-ports {
2328                                 port {
2329                                         etm0_out: endpoint {
2330                                                 remote-endpoint =
2331                                                   <&apss_funnel0_in0>;
2332                                         };
2333                                 };
2334                         };
2335                 };
2336
2337                 debug@3910000 {
2338                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2339                         reg = <0x3910000 0x1000>;
2340
2341                         clocks = <&rpmcc RPM_QDSS_CLK>;
2342                         clock-names = "apb_pclk";
2343
2344                         cpu = <&CPU1>;
2345                 };
2346
2347                 etm@3940000 {
2348                         compatible = "arm,coresight-etm4x", "arm,primecell";
2349                         reg = <0x3940000 0x1000>;
2350
2351                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2352                         clock-names = "apb_pclk", "atclk";
2353
2354                         cpu = <&CPU1>;
2355
2356                         out-ports {
2357                                 port {
2358                                         etm1_out: endpoint {
2359                                                 remote-endpoint =
2360                                                   <&apss_funnel0_in1>;
2361                                         };
2362                                 };
2363                         };
2364                 };
2365
2366                 funnel@39b0000 { /* APSS Funnel 0 */
2367                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2368                         reg = <0x39b0000 0x1000>;
2369
2370                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2371                         clock-names = "apb_pclk", "atclk";
2372
2373                         in-ports {
2374                                 #address-cells = <1>;
2375                                 #size-cells = <0>;
2376
2377                                 port@0 {
2378                                         reg = <0>;
2379                                         apss_funnel0_in0: endpoint {
2380                                                 remote-endpoint = <&etm0_out>;
2381                                         };
2382                                 };
2383
2384                                 port@1 {
2385                                         reg = <1>;
2386                                         apss_funnel0_in1: endpoint {
2387                                                 remote-endpoint = <&etm1_out>;
2388                                         };
2389                                 };
2390                         };
2391
2392                         out-ports {
2393                                 port {
2394                                         apss_funnel0_out: endpoint {
2395                                                 remote-endpoint =
2396                                                   <&apss_merge_funnel_in0>;
2397                                         };
2398                                 };
2399                         };
2400                 };
2401
2402                 debug@3a10000 {
2403                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2404                         reg = <0x3a10000 0x1000>;
2405
2406                         clocks = <&rpmcc RPM_QDSS_CLK>;
2407                         clock-names = "apb_pclk";
2408
2409                         cpu = <&CPU2>;
2410                 };
2411
2412                 etm@3a40000 {
2413                         compatible = "arm,coresight-etm4x", "arm,primecell";
2414                         reg = <0x3a40000 0x1000>;
2415
2416                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2417                         clock-names = "apb_pclk", "atclk";
2418
2419                         cpu = <&CPU2>;
2420
2421                         out-ports {
2422                                 port {
2423                                         etm2_out: endpoint {
2424                                                 remote-endpoint =
2425                                                   <&apss_funnel1_in0>;
2426                                         };
2427                                 };
2428                         };
2429                 };
2430
2431                 debug@3b10000 {
2432                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2433                         reg = <0x3b10000 0x1000>;
2434
2435                         clocks = <&rpmcc RPM_QDSS_CLK>;
2436                         clock-names = "apb_pclk";
2437
2438                         cpu = <&CPU3>;
2439                 };
2440
2441                 etm@3b40000 {
2442                         compatible = "arm,coresight-etm4x", "arm,primecell";
2443                         reg = <0x3b40000 0x1000>;
2444
2445                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2446                         clock-names = "apb_pclk", "atclk";
2447
2448                         cpu = <&CPU3>;
2449
2450                         out-ports {
2451                                 port {
2452                                         etm3_out: endpoint {
2453                                                 remote-endpoint =
2454                                                   <&apss_funnel1_in1>;
2455                                         };
2456                                 };
2457                         };
2458                 };
2459
2460                 funnel@3bb0000 { /* APSS Funnel 1 */
2461                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2462                         reg = <0x3bb0000 0x1000>;
2463
2464                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2465                         clock-names = "apb_pclk", "atclk";
2466
2467                         in-ports {
2468                                 #address-cells = <1>;
2469                                 #size-cells = <0>;
2470
2471                                 port@0 {
2472                                         reg = <0>;
2473                                         apss_funnel1_in0: endpoint {
2474                                                 remote-endpoint = <&etm2_out>;
2475                                         };
2476                                 };
2477
2478                                 port@1 {
2479                                         reg = <1>;
2480                                         apss_funnel1_in1: endpoint {
2481                                                 remote-endpoint = <&etm3_out>;
2482                                         };
2483                                 };
2484                         };
2485
2486                         out-ports {
2487                                 port {
2488                                         apss_funnel1_out: endpoint {
2489                                                 remote-endpoint =
2490                                                   <&apss_merge_funnel_in1>;
2491                                         };
2492                                 };
2493                         };
2494                 };
2495
2496                 funnel@3bc0000 {
2497                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2498                         reg = <0x3bc0000 0x1000>;
2499
2500                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2501                         clock-names = "apb_pclk", "atclk";
2502
2503                         in-ports {
2504                                 #address-cells = <1>;
2505                                 #size-cells = <0>;
2506
2507                                 port@0 {
2508                                         reg = <0>;
2509                                         apss_merge_funnel_in0: endpoint {
2510                                                 remote-endpoint =
2511                                                   <&apss_funnel0_out>;
2512                                         };
2513                                 };
2514
2515                                 port@1 {
2516                                         reg = <1>;
2517                                         apss_merge_funnel_in1: endpoint {
2518                                                 remote-endpoint =
2519                                                   <&apss_funnel1_out>;
2520                                         };
2521                                 };
2522                         };
2523
2524                         out-ports {
2525                                 port {
2526                                         apss_merge_funnel_out: endpoint {
2527                                                 remote-endpoint =
2528                                                   <&funnel1_in>;
2529                                         };
2530                                 };
2531                         };
2532                 };
2533
2534                 kryocc: clock-controller@6400000 {
2535                         compatible = "qcom,msm8996-apcc";
2536                         reg = <0x06400000 0x90000>;
2537
2538                         clock-names = "xo";
2539                         clocks = <&xo_board>;
2540
2541                         #clock-cells = <1>;
2542                 };
2543
2544                 usb3: usb@6af8800 {
2545                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2546                         reg = <0x06af8800 0x400>;
2547                         #address-cells = <1>;
2548                         #size-cells = <1>;
2549                         ranges;
2550
2551                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2552                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2553                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
2554
2555                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2556                                 <&gcc GCC_USB30_MASTER_CLK>,
2557                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2558                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2559                                 <&gcc GCC_USB30_SLEEP_CLK>,
2560                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2561
2562                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2563                                           <&gcc GCC_USB30_MASTER_CLK>;
2564                         assigned-clock-rates = <19200000>, <120000000>;
2565
2566                         power-domains = <&gcc USB30_GDSC>;
2567                         status = "disabled";
2568
2569                         dwc3@6a00000 {
2570                                 compatible = "snps,dwc3";
2571                                 reg = <0x06a00000 0xcc00>;
2572                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2573                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2574                                 phy-names = "usb2-phy", "usb3-phy";
2575                                 snps,dis_u2_susphy_quirk;
2576                                 snps,dis_enblslpm_quirk;
2577                         };
2578                 };
2579
2580                 usb3phy: phy@7410000 {
2581                         compatible = "qcom,msm8996-qmp-usb3-phy";
2582                         reg = <0x07410000 0x1c4>;
2583                         #clock-cells = <1>;
2584                         #address-cells = <1>;
2585                         #size-cells = <1>;
2586                         ranges;
2587
2588                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2589                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2590                                 <&gcc GCC_USB3_CLKREF_CLK>;
2591                         clock-names = "aux", "cfg_ahb", "ref";
2592
2593                         resets = <&gcc GCC_USB3_PHY_BCR>,
2594                                 <&gcc GCC_USB3PHY_PHY_BCR>;
2595                         reset-names = "phy", "common";
2596                         status = "disabled";
2597
2598                         ssusb_phy_0: lane@7410200 {
2599                                 reg = <0x07410200 0x200>,
2600                                       <0x07410400 0x130>,
2601                                       <0x07410600 0x1a8>;
2602                                 #phy-cells = <0>;
2603
2604                                 clock-output-names = "usb3_phy_pipe_clk_src";
2605                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2606                                 clock-names = "pipe0";
2607                         };
2608                 };
2609
2610                 hsusb_phy1: phy@7411000 {
2611                         compatible = "qcom,msm8996-qusb2-phy";
2612                         reg = <0x07411000 0x180>;
2613                         #phy-cells = <0>;
2614
2615                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2616                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2617                         clock-names = "cfg_ahb", "ref";
2618
2619                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2620                         nvmem-cells = <&qusb2p_hstx_trim>;
2621                         status = "disabled";
2622                 };
2623
2624                 hsusb_phy2: phy@7412000 {
2625                         compatible = "qcom,msm8996-qusb2-phy";
2626                         reg = <0x07412000 0x180>;
2627                         #phy-cells = <0>;
2628
2629                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2630                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
2631                         clock-names = "cfg_ahb", "ref";
2632
2633                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2634                         nvmem-cells = <&qusb2s_hstx_trim>;
2635                         status = "disabled";
2636                 };
2637
2638                 sdhc1: sdhci@7464900 {
2639                         compatible = "qcom,sdhci-msm-v4";
2640                         reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2641                         reg-names = "hc_mem", "core_mem";
2642
2643                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2644                                         <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2645                         interrupt-names = "hc_irq", "pwr_irq";
2646
2647                         clock-names = "iface", "core", "xo";
2648                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2649                                 <&gcc GCC_SDCC1_APPS_CLK>,
2650                                 <&xo_board>;
2651
2652                         pinctrl-names = "default", "sleep";
2653                         pinctrl-0 = <&sdc1_state_on>;
2654                         pinctrl-1 = <&sdc1_state_off>;
2655
2656                         bus-width = <8>;
2657                         non-removable;
2658                         status = "disabled";
2659                 };
2660
2661                 sdhc2: sdhci@74a4900 {
2662                         compatible = "qcom,sdhci-msm-v4";
2663                         reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2664                         reg-names = "hc_mem", "core_mem";
2665
2666                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2667                                       <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2668                         interrupt-names = "hc_irq", "pwr_irq";
2669
2670                         clock-names = "iface", "core", "xo";
2671                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2672                                 <&gcc GCC_SDCC2_APPS_CLK>,
2673                                 <&xo_board>;
2674
2675                         pinctrl-names = "default", "sleep";
2676                         pinctrl-0 = <&sdc2_state_on>;
2677                         pinctrl-1 = <&sdc2_state_off>;
2678
2679                         bus-width = <4>;
2680                         status = "disabled";
2681                  };
2682
2683                 blsp1_dma: dma@7544000 {
2684                         compatible = "qcom,bam-v1.7.0";
2685                         reg = <0x07544000 0x2b000>;
2686                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2687                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2688                         clock-names = "bam_clk";
2689                         qcom,controlled-remotely;
2690                         #dma-cells = <1>;
2691                         qcom,ee = <0>;
2692                 };
2693
2694                 blsp1_uart2: serial@7570000 {
2695                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2696                         reg = <0x07570000 0x1000>;
2697                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2698                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2699                                  <&gcc GCC_BLSP1_AHB_CLK>;
2700                         clock-names = "core", "iface";
2701                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2702                         dma-names = "tx", "rx";
2703                         status = "disabled";
2704                 };
2705
2706                 blsp1_spi1: spi@7575000 {
2707                         compatible = "qcom,spi-qup-v2.2.1";
2708                         reg = <0x07575000 0x600>;
2709                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2710                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2711                                  <&gcc GCC_BLSP1_AHB_CLK>;
2712                         clock-names = "core", "iface";
2713                         pinctrl-names = "default", "sleep";
2714                         pinctrl-0 = <&blsp1_spi1_default>;
2715                         pinctrl-1 = <&blsp1_spi1_sleep>;
2716                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2717                         dma-names = "tx", "rx";
2718                         #address-cells = <1>;
2719                         #size-cells = <0>;
2720                         status = "disabled";
2721                 };
2722
2723                 blsp1_i2c3: i2c@7577000 {
2724                         compatible = "qcom,i2c-qup-v2.2.1";
2725                         reg = <0x07577000 0x1000>;
2726                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2727                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2728                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2729                         clock-names = "iface", "core";
2730                         pinctrl-names = "default", "sleep";
2731                         pinctrl-0 = <&blsp1_i2c3_default>;
2732                         pinctrl-1 = <&blsp1_i2c3_sleep>;
2733                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2734                         dma-names = "tx", "rx";
2735                         #address-cells = <1>;
2736                         #size-cells = <0>;
2737                         status = "disabled";
2738                 };
2739
2740                 blsp2_dma: dma@7584000 {
2741                         compatible = "qcom,bam-v1.7.0";
2742                         reg = <0x07584000 0x2b000>;
2743                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2744                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2745                         clock-names = "bam_clk";
2746                         qcom,controlled-remotely;
2747                         #dma-cells = <1>;
2748                         qcom,ee = <0>;
2749                 };
2750
2751                 blsp2_uart2: serial@75b0000 {
2752                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2753                         reg = <0x075b0000 0x1000>;
2754                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2755                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2756                                  <&gcc GCC_BLSP2_AHB_CLK>;
2757                         clock-names = "core", "iface";
2758                         status = "disabled";
2759                 };
2760
2761                 blsp2_uart3: serial@75b1000 {
2762                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2763                         reg = <0x075b1000 0x1000>;
2764                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2765                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2766                                  <&gcc GCC_BLSP2_AHB_CLK>;
2767                         clock-names = "core", "iface";
2768                         status = "disabled";
2769                 };
2770
2771                 blsp2_i2c1: i2c@75b5000 {
2772                         compatible = "qcom,i2c-qup-v2.2.1";
2773                         reg = <0x075b5000 0x1000>;
2774                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2775                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2776                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2777                         clock-names = "iface", "core";
2778                         pinctrl-names = "default", "sleep";
2779                         pinctrl-0 = <&blsp2_i2c1_default>;
2780                         pinctrl-1 = <&blsp2_i2c1_sleep>;
2781                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2782                         dma-names = "tx", "rx";
2783                         #address-cells = <1>;
2784                         #size-cells = <0>;
2785                         status = "disabled";
2786                 };
2787
2788                 blsp2_i2c2: i2c@75b6000 {
2789                         compatible = "qcom,i2c-qup-v2.2.1";
2790                         reg = <0x075b6000 0x1000>;
2791                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2792                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2793                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2794                         clock-names = "iface", "core";
2795                         pinctrl-names = "default", "sleep";
2796                         pinctrl-0 = <&blsp2_i2c2_default>;
2797                         pinctrl-1 = <&blsp2_i2c2_sleep>;
2798                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2799                         dma-names = "tx", "rx";
2800                         #address-cells = <1>;
2801                         #size-cells = <0>;
2802                         status = "disabled";
2803                 };
2804
2805                 blsp2_i2c5: i2c@75b9000 {
2806                         compatible = "qcom,i2c-qup-v2.2.1";
2807                         reg = <0x75b9000 0x1000>;
2808                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2809                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2810                                 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2811                         clock-names = "iface", "core";
2812                         pinctrl-names = "default";
2813                         pinctrl-0 = <&blsp2_i2c5_default>;
2814                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2815                         dma-names = "tx", "rx";
2816                         #address-cells = <1>;
2817                         #size-cells = <0>;
2818                         status = "disabled";
2819                 };
2820
2821                 blsp2_i2c6: i2c@75ba000 {
2822                         compatible = "qcom,i2c-qup-v2.2.1";
2823                         reg = <0x75ba000 0x1000>;
2824                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2825                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2826                                 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2827                         clock-names = "iface", "core";
2828                         pinctrl-names = "default", "sleep";
2829                         pinctrl-0 = <&blsp2_i2c6_default>;
2830                         pinctrl-1 = <&blsp2_i2c6_sleep>;
2831                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2832                         dma-names = "tx", "rx";
2833                         #address-cells = <1>;
2834                         #size-cells = <0>;
2835                         status = "disabled";
2836                 };
2837
2838                 blsp2_spi6: spi@75ba000{
2839                         compatible = "qcom,spi-qup-v2.2.1";
2840                         reg = <0x075ba000 0x600>;
2841                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2842                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2843                                  <&gcc GCC_BLSP2_AHB_CLK>;
2844                         clock-names = "core", "iface";
2845                         pinctrl-names = "default", "sleep";
2846                         pinctrl-0 = <&blsp2_spi6_default>;
2847                         pinctrl-1 = <&blsp2_spi6_sleep>;
2848                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2849                         dma-names = "tx", "rx";
2850                         #address-cells = <1>;
2851                         #size-cells = <0>;
2852                         status = "disabled";
2853                 };
2854
2855                 usb2: usb@76f8800 {
2856                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2857                         reg = <0x076f8800 0x400>;
2858                         #address-cells = <1>;
2859                         #size-cells = <1>;
2860                         ranges;
2861
2862                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2863                                 <&gcc GCC_USB20_MASTER_CLK>,
2864                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2865                                 <&gcc GCC_USB20_SLEEP_CLK>,
2866                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2867
2868                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2869                                           <&gcc GCC_USB20_MASTER_CLK>;
2870                         assigned-clock-rates = <19200000>, <60000000>;
2871
2872                         power-domains = <&gcc USB30_GDSC>;
2873                         qcom,select-utmi-as-pipe-clk;
2874                         status = "disabled";
2875
2876                         dwc3@7600000 {
2877                                 compatible = "snps,dwc3";
2878                                 reg = <0x07600000 0xcc00>;
2879                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2880                                 phys = <&hsusb_phy2>;
2881                                 phy-names = "usb2-phy";
2882                                 maximum-speed = "high-speed";
2883                                 snps,dis_u2_susphy_quirk;
2884                                 snps,dis_enblslpm_quirk;
2885                         };
2886                 };
2887
2888                 slimbam: dma-controller@9184000 {
2889                         compatible = "qcom,bam-v1.7.0";
2890                         qcom,controlled-remotely;
2891                         reg = <0x09184000 0x32000>;
2892                         num-channels  = <31>;
2893                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2894                         #dma-cells = <1>;
2895                         qcom,ee = <1>;
2896                         qcom,num-ees = <2>;
2897                 };
2898
2899                 slim_msm: slim@91c0000 {
2900                         compatible = "qcom,slim-ngd-v1.5.0";
2901                         reg = <0x091c0000 0x2C000>;
2902                         reg-names = "ctrl";
2903                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2904                         dmas =  <&slimbam 3>, <&slimbam 4>,
2905                                 <&slimbam 5>, <&slimbam 6>;
2906                         dma-names = "rx", "tx", "tx2", "rx2";
2907                         #address-cells = <1>;
2908                         #size-cells = <0>;
2909                         ngd@1 {
2910                                 reg = <1>;
2911                                 #address-cells = <1>;
2912                                 #size-cells = <1>;
2913
2914                                 tasha_ifd: tas-ifd {
2915                                         compatible = "slim217,1a0";
2916                                         reg  = <0 0>;
2917                                 };
2918
2919                                 wcd9335: codec@1{
2920                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2921                                         pinctrl-names = "default";
2922
2923                                         compatible = "slim217,1a0";
2924                                         reg  = <1 0>;
2925
2926                                         interrupt-parent = <&tlmm>;
2927                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2928                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
2929                                         interrupt-names  = "intr1", "intr2";
2930                                         interrupt-controller;
2931                                         #interrupt-cells = <1>;
2932                                         reset-gpios = <&tlmm 64 0>;
2933
2934                                         slim-ifc-dev  = <&tasha_ifd>;
2935
2936                                         #sound-dai-cells = <1>;
2937                                 };
2938                         };
2939                 };
2940
2941                 adsp_pil: remoteproc@9300000 {
2942                         compatible = "qcom,msm8996-adsp-pil";
2943                         reg = <0x09300000 0x80000>;
2944
2945                         interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2946                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2947                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2948                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2949                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2950                         interrupt-names = "wdog", "fatal", "ready",
2951                                           "handover", "stop-ack";
2952
2953                         clocks = <&xo_board>;
2954                         clock-names = "xo";
2955
2956                         memory-region = <&adsp_region>;
2957
2958                         qcom,smem-states = <&smp2p_adsp_out 0>;
2959                         qcom,smem-state-names = "stop";
2960
2961                         power-domains = <&rpmpd MSM8996_VDDCX>;
2962                         power-domain-names = "cx";
2963
2964                         status = "disabled";
2965
2966                         smd-edge {
2967                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2968
2969                                 label = "lpass";
2970                                 mboxes = <&apcs_glb 8>;
2971                                 qcom,smd-edge = <1>;
2972                                 qcom,remote-pid = <2>;
2973                                 #address-cells = <1>;
2974                                 #size-cells = <0>;
2975                                 apr {
2976                                         power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2977                                         compatible = "qcom,apr-v2";
2978                                         qcom,smd-channels = "apr_audio_svc";
2979                                         qcom,apr-domain = <APR_DOMAIN_ADSP>;
2980                                         #address-cells = <1>;
2981                                         #size-cells = <0>;
2982
2983                                         q6core {
2984                                                 reg = <APR_SVC_ADSP_CORE>;
2985                                                 compatible = "qcom,q6core";
2986                                         };
2987
2988                                         q6afe: q6afe {
2989                                                 compatible = "qcom,q6afe";
2990                                                 reg = <APR_SVC_AFE>;
2991                                                 q6afedai: dais {
2992                                                         compatible = "qcom,q6afe-dais";
2993                                                         #address-cells = <1>;
2994                                                         #size-cells = <0>;
2995                                                         #sound-dai-cells = <1>;
2996                                                         hdmi@1 {
2997                                                                 reg = <1>;
2998                                                         };
2999                                                 };
3000                                         };
3001
3002                                         q6asm: q6asm {
3003                                                 compatible = "qcom,q6asm";
3004                                                 reg = <APR_SVC_ASM>;
3005                                                 q6asmdai: dais {
3006                                                         compatible = "qcom,q6asm-dais";
3007                                                         #address-cells = <1>;
3008                                                         #size-cells = <0>;
3009                                                         #sound-dai-cells = <1>;
3010                                                         iommus = <&lpass_q6_smmu 1>;
3011                                                 };
3012                                         };
3013
3014                                         q6adm: q6adm {
3015                                                 compatible = "qcom,q6adm";
3016                                                 reg = <APR_SVC_ADM>;
3017                                                 q6routing: routing {
3018                                                         compatible = "qcom,q6adm-routing";
3019                                                         #sound-dai-cells = <0>;
3020                                                 };
3021                                         };
3022                                 };
3023
3024                         };
3025                 };
3026
3027                 apcs_glb: mailbox@9820000 {
3028                         compatible = "qcom,msm8996-apcs-hmss-global";
3029                         reg = <0x09820000 0x1000>;
3030
3031                         #mbox-cells = <1>;
3032                 };
3033
3034                 timer@9840000 {
3035                         #address-cells = <1>;
3036                         #size-cells = <1>;
3037                         ranges;
3038                         compatible = "arm,armv7-timer-mem";
3039                         reg = <0x09840000 0x1000>;
3040                         clock-frequency = <19200000>;
3041
3042                         frame@9850000 {
3043                                 frame-number = <0>;
3044                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3045                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3046                                 reg = <0x09850000 0x1000>,
3047                                       <0x09860000 0x1000>;
3048                         };
3049
3050                         frame@9870000 {
3051                                 frame-number = <1>;
3052                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3053                                 reg = <0x09870000 0x1000>;
3054                                 status = "disabled";
3055                         };
3056
3057                         frame@9880000 {
3058                                 frame-number = <2>;
3059                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3060                                 reg = <0x09880000 0x1000>;
3061                                 status = "disabled";
3062                         };
3063
3064                         frame@9890000 {
3065                                 frame-number = <3>;
3066                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3067                                 reg = <0x09890000 0x1000>;
3068                                 status = "disabled";
3069                         };
3070
3071                         frame@98a0000 {
3072                                 frame-number = <4>;
3073                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3074                                 reg = <0x098a0000 0x1000>;
3075                                 status = "disabled";
3076                         };
3077
3078                         frame@98b0000 {
3079                                 frame-number = <5>;
3080                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3081                                 reg = <0x098b0000 0x1000>;
3082                                 status = "disabled";
3083                         };
3084
3085                         frame@98c0000 {
3086                                 frame-number = <6>;
3087                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3088                                 reg = <0x098c0000 0x1000>;
3089                                 status = "disabled";
3090                         };
3091                 };
3092
3093                 saw3: syscon@9a10000 {
3094                         compatible = "syscon";
3095                         reg = <0x09a10000 0x1000>;
3096                 };
3097
3098                 intc: interrupt-controller@9bc0000 {
3099                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3100                         #interrupt-cells = <3>;
3101                         interrupt-controller;
3102                         #redistributor-regions = <1>;
3103                         redistributor-stride = <0x0 0x40000>;
3104                         reg = <0x09bc0000 0x10000>,
3105                               <0x09c00000 0x100000>;
3106                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3107                 };
3108         };
3109
3110         sound: sound {
3111         };
3112
3113         thermal-zones {
3114                 cpu0-thermal {
3115                         polling-delay-passive = <250>;
3116                         polling-delay = <1000>;
3117
3118                         thermal-sensors = <&tsens0 3>;
3119
3120                         trips {
3121                                 cpu0_alert0: trip-point0 {
3122                                         temperature = <75000>;
3123                                         hysteresis = <2000>;
3124                                         type = "passive";
3125                                 };
3126
3127                                 cpu0_crit: cpu_crit {
3128                                         temperature = <110000>;
3129                                         hysteresis = <2000>;
3130                                         type = "critical";
3131                                 };
3132                         };
3133                 };
3134
3135                 cpu1-thermal {
3136                         polling-delay-passive = <250>;
3137                         polling-delay = <1000>;
3138
3139                         thermal-sensors = <&tsens0 5>;
3140
3141                         trips {
3142                                 cpu1_alert0: trip-point0 {
3143                                         temperature = <75000>;
3144                                         hysteresis = <2000>;
3145                                         type = "passive";
3146                                 };
3147
3148                                 cpu1_crit: cpu_crit {
3149                                         temperature = <110000>;
3150                                         hysteresis = <2000>;
3151                                         type = "critical";
3152                                 };
3153                         };
3154                 };
3155
3156                 cpu2-thermal {
3157                         polling-delay-passive = <250>;
3158                         polling-delay = <1000>;
3159
3160                         thermal-sensors = <&tsens0 8>;
3161
3162                         trips {
3163                                 cpu2_alert0: trip-point0 {
3164                                         temperature = <75000>;
3165                                         hysteresis = <2000>;
3166                                         type = "passive";
3167                                 };
3168
3169                                 cpu2_crit: cpu_crit {
3170                                         temperature = <110000>;
3171                                         hysteresis = <2000>;
3172                                         type = "critical";
3173                                 };
3174                         };
3175                 };
3176
3177                 cpu3-thermal {
3178                         polling-delay-passive = <250>;
3179                         polling-delay = <1000>;
3180
3181                         thermal-sensors = <&tsens0 10>;
3182
3183                         trips {
3184                                 cpu3_alert0: trip-point0 {
3185                                         temperature = <75000>;
3186                                         hysteresis = <2000>;
3187                                         type = "passive";
3188                                 };
3189
3190                                 cpu3_crit: cpu_crit {
3191                                         temperature = <110000>;
3192                                         hysteresis = <2000>;
3193                                         type = "critical";
3194                                 };
3195                         };
3196                 };
3197
3198                 gpu-thermal-top {
3199                         polling-delay-passive = <250>;
3200                         polling-delay = <1000>;
3201
3202                         thermal-sensors = <&tsens1 6>;
3203
3204                         trips {
3205                                 gpu1_alert0: trip-point0 {
3206                                         temperature = <90000>;
3207                                         hysteresis = <2000>;
3208                                         type = "hot";
3209                                 };
3210                         };
3211                 };
3212
3213                 gpu-thermal-bottom {
3214                         polling-delay-passive = <250>;
3215                         polling-delay = <1000>;
3216
3217                         thermal-sensors = <&tsens1 7>;
3218
3219                         trips {
3220                                 gpu2_alert0: trip-point0 {
3221                                         temperature = <90000>;
3222                                         hysteresis = <2000>;
3223                                         type = "hot";
3224                                 };
3225                         };
3226                 };
3227
3228                 m4m-thermal {
3229                         polling-delay-passive = <250>;
3230                         polling-delay = <1000>;
3231
3232                         thermal-sensors = <&tsens0 1>;
3233
3234                         trips {
3235                                 m4m_alert0: trip-point0 {
3236                                         temperature = <90000>;
3237                                         hysteresis = <2000>;
3238                                         type = "hot";
3239                                 };
3240                         };
3241                 };
3242
3243                 l3-or-venus-thermal {
3244                         polling-delay-passive = <250>;
3245                         polling-delay = <1000>;
3246
3247                         thermal-sensors = <&tsens0 2>;
3248
3249                         trips {
3250                                 l3_or_venus_alert0: trip-point0 {
3251                                         temperature = <90000>;
3252                                         hysteresis = <2000>;
3253                                         type = "hot";
3254                                 };
3255                         };
3256                 };
3257
3258                 cluster0-l2-thermal {
3259                         polling-delay-passive = <250>;
3260                         polling-delay = <1000>;
3261
3262                         thermal-sensors = <&tsens0 7>;
3263
3264                         trips {
3265                                 cluster0_l2_alert0: trip-point0 {
3266                                         temperature = <90000>;
3267                                         hysteresis = <2000>;
3268                                         type = "hot";
3269                                 };
3270                         };
3271                 };
3272
3273                 cluster1-l2-thermal {
3274                         polling-delay-passive = <250>;
3275                         polling-delay = <1000>;
3276
3277                         thermal-sensors = <&tsens0 12>;
3278
3279                         trips {
3280                                 cluster1_l2_alert0: trip-point0 {
3281                                         temperature = <90000>;
3282                                         hysteresis = <2000>;
3283                                         type = "hot";
3284                                 };
3285                         };
3286                 };
3287
3288                 camera-thermal {
3289                         polling-delay-passive = <250>;
3290                         polling-delay = <1000>;
3291
3292                         thermal-sensors = <&tsens1 1>;
3293
3294                         trips {
3295                                 camera_alert0: trip-point0 {
3296                                         temperature = <90000>;
3297                                         hysteresis = <2000>;
3298                                         type = "hot";
3299                                 };
3300                         };
3301                 };
3302
3303                 q6-dsp-thermal {
3304                         polling-delay-passive = <250>;
3305                         polling-delay = <1000>;
3306
3307                         thermal-sensors = <&tsens1 2>;
3308
3309                         trips {
3310                                 q6_dsp_alert0: trip-point0 {
3311                                         temperature = <90000>;
3312                                         hysteresis = <2000>;
3313                                         type = "hot";
3314                                 };
3315                         };
3316                 };
3317
3318                 mem-thermal {
3319                         polling-delay-passive = <250>;
3320                         polling-delay = <1000>;
3321
3322                         thermal-sensors = <&tsens1 3>;
3323
3324                         trips {
3325                                 mem_alert0: trip-point0 {
3326                                         temperature = <90000>;
3327                                         hysteresis = <2000>;
3328                                         type = "hot";
3329                                 };
3330                         };
3331                 };
3332
3333                 modemtx-thermal {
3334                         polling-delay-passive = <250>;
3335                         polling-delay = <1000>;
3336
3337                         thermal-sensors = <&tsens1 4>;
3338
3339                         trips {
3340                                 modemtx_alert0: trip-point0 {
3341                                         temperature = <90000>;
3342                                         hysteresis = <2000>;
3343                                         type = "hot";
3344                                 };
3345                         };
3346                 };
3347         };
3348
3349         timer {
3350                 compatible = "arm,armv8-timer";
3351                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3352                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3353                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3354                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3355         };
3356 };