arch/arm64/boot/dts/qcom/msm8994.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
   7 #include <dt-bindings/power/qcom-rpmpd.h>
   8
   9 / {
  10         interrupt-parent = <&intc>;
  11
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         chosen { };
  16
  17         clocks {
  18                 xo_board: xo_board {
  19                         compatible = "fixed-clock";
  20                         #clock-cells = <0>;
  21                         clock-frequency = <19200000>;
  22                 };
  23
  24                 sleep_clk: sleep_clk {
  25                         compatible = "fixed-clock";
  26                         #clock-cells = <0>;
  27                         clock-frequency = <32768>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <2>;
  33                 #size-cells = <0>;
  34
  35                 CPU0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         reg = <0x0 0x0>;
  39                         enable-method = "psci";
  40                         next-level-cache = <&L2_0>;
  41                         L2_0: l2-cache {
  42                                 compatible = "cache";
  43                                 cache-level = <2>;
  44                         };
  45                 };
  46
  47                 CPU1: cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         reg = <0x0 0x1>;
  51                         enable-method = "psci";
  52                         next-level-cache = <&L2_0>;
  53                 };
  54
  55                 CPU2: cpu@2 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         reg = <0x0 0x2>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&L2_0>;
  61                 };
  62
  63                 CPU3: cpu@3 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53";
  66                         reg = <0x0 0x3>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&L2_0>;
  69                 };
  70
  71                 CPU4: cpu@100 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a57";
  74                         reg = <0x0 0x100>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&L2_1>;
  77                         L2_1: l2-cache {
  78                                 compatible = "cache";
  79                                 cache-level = <2>;
  80                         };
  81                 };
  82
  83                 CPU5: cpu@101 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a57";
  86                         reg = <0x0 0x101>;
  87                         enable-method = "psci";
  88                         next-level-cache = <&L2_1>;
  89                 };
  90
  91                 CPU6: cpu@102 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a57";
  94                         reg = <0x0 0x101>;
  95                         enable-method = "psci";
  96                         next-level-cache = <&L2_1>;
  97                 };
  98
  99                 CPU7: cpu@103 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a57";
 102                         reg = <0x0 0x101>;
 103                         enable-method = "psci";
 104                         next-level-cache = <&L2_1>;
 105                 };
 106
 107                 cpu-map {
 108                         cluster0 {
 109                                 core0 {
 110                                         cpu = <&CPU0>;
 111                                 };
 112
 113                                 core1 {
 114                                         cpu = <&CPU1>;
 115                                 };
 116
 117                                 core2 {
 118                                         cpu = <&CPU2>;
 119                                 };
 120
 121                                 core3 {
 122                                         cpu = <&CPU3>;
 123                                 };
 124                         };
 125
 126                         cluster1 {
 127                                 core0 {
 128                                         cpu = <&CPU4>;
 129                                 };
 130
 131                                 core1 {
 132                                         cpu = <&CPU5>;
 133                                 };
 134
 135                                 cpu6_map: core2 {
 136                                         cpu = <&CPU6>;
 137                                 };
 138
 139                                 cpu7_map: core3 {
 140                                         cpu = <&CPU7>;
 141                                 };
 142                         };
 143                 };
 144         };
 145
 146         firmware {
 147                 scm {
 148                         compatible = "qcom,scm-msm8994", "qcom,scm";
 149                 };
 150         };
 151
 152         memory@80000000 {
 153                 device_type = "memory";
 154                 /* We expect the bootloader to fill in the reg */
 155                 reg = <0 0x80000000 0 0>;
 156         };
 157
 158         tcsr_mutex: hwlock {
 159                 compatible = "qcom,tcsr-mutex";
 160                 syscon = <&tcsr_mutex_regs 0 0x80>;
 161                 #hwlock-cells = <1>;
 162         };
 163
 164         pmu {
 165                 compatible = "arm,cortex-a53-pmu";
 166                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
 167         };
 168
 169         psci {
 170                 compatible = "arm,psci-0.2";
 171                 method = "hvc";
 172         };
 173
 174         reserved-memory {
 175                 #address-cells = <2>;
 176                 #size-cells = <2>;
 177                 ranges;
 178
 179                 dfps_data_mem: dfps_data_mem@3400000 {
 180                         reg = <0 0x03400000 0 0x1000>;
 181                         no-map;
 182                 };
 183
 184                 cont_splash_mem: memory@3800000 {
 185                         reg = <0 0x03800000 0 0x2400000>;
 186                         no-map;
 187                 };
 188
 189                 smem_mem: smem_region@6a00000 {
 190                         reg = <0 0x06a00000 0 0x200000>;
 191                         no-map;
 192                 };
 193
 194                 mpss_mem: memory@7000000 {
 195                         reg = <0 0x07000000 0 0x5a00000>;
 196                         no-map;
 197                 };
 198
 199                 peripheral_region: memory@ca00000 {
 200                         reg = <0 0x0ca00000 0 0x1f00000>;
 201                         no-map;
 202                 };
 203
 204                 rmtfs_mem: memory@c6400000 {
 205                         compatible = "qcom,rmtfs-mem";
 206                         reg = <0 0xc6400000 0 0x180000>;
 207                         no-map;
 208
 209                         qcom,client-id = <1>;
 210                 };
 211
 212                 mba_mem: memory@c6700000 {
 213                         reg = <0 0xc6700000 0 0x100000>;
 214                         no-map;
 215                 };
 216
 217                 audio_mem: memory@c7000000 {
 218                         reg = <0 0xc7000000 0 0x800000>;
 219                         no-map;
 220                 };
 221
 222                 adsp_mem: memory@c9400000 {
 223                         reg = <0 0xc9400000 0 0x3f00000>;
 224                         no-map;
 225                 };
 226         };
 227
 228         smd {
 229                 compatible = "qcom,smd";
 230                 rpm {
 231                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 232                         qcom,ipc = <&apcs 8 0>;
 233                         qcom,smd-edge = <15>;
 234                         qcom,local-pid = <0>;
 235                         qcom,remote-pid = <6>;
 236
 237                         rpm_requests: rpm-requests {
 238                                 compatible = "qcom,rpm-msm8994";
 239                                 qcom,smd-channels = "rpm_requests";
 240
 241                                 rpmcc: rpmcc {
 242                                         compatible = "qcom,rpmcc-msm8994";
 243                                         #clock-cells = <1>;
 244                                 };
 245
 246                                 rpmpd: power-controller {
 247                                         compatible = "qcom,msm8994-rpmpd";
 248                                         #power-domain-cells = <1>;
 249                                         operating-points-v2 = <&rpmpd_opp_table>;
 250
 251                                         rpmpd_opp_table: opp-table {
 252                                                 compatible = "operating-points-v2";
 253
 254                                                 rpmpd_opp_ret: opp1 {
 255                                                         opp-level = <1>;
 256                                                 };
 257                                                 rpmpd_opp_svs_krait: opp2 {
 258                                                         opp-level = <2>;
 259                                                 };
 260                                                 rpmpd_opp_svs_soc: opp3 {
 261                                                         opp-level = <3>;
 262                                                 };
 263                                                 rpmpd_opp_nom: opp4 {
 264                                                         opp-level = <4>;
 265                                                 };
 266                                                 rpmpd_opp_turbo: opp5 {
 267                                                         opp-level = <5>;
 268                                                 };
 269                                                 rpmpd_opp_super_turbo: opp6 {
 270                                                         opp-level = <6>;
 271                                                 };
 272                                         };
 273                                 };
 274                         };
 275                 };
 276         };
 277
 278         smem {
 279                 compatible = "qcom,smem";
 280                 memory-region = <&smem_mem>;
 281                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 282                 hwlocks = <&tcsr_mutex 3>;
 283         };
 284
 285         smp2p-lpass {
 286                 compatible = "qcom,smp2p";
 287                 qcom,smem = <443>, <429>;
 288
 289                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 290
 291                 qcom,ipc = <&apcs 8 10>;
 292
 293                 qcom,local-pid = <0>;
 294                 qcom,remote-pid = <2>;
 295
 296                 adsp_smp2p_out: master-kernel {
 297                         qcom,entry-name = "master-kernel";
 298                         #qcom,smem-state-cells = <1>;
 299                 };
 300
 301                 adsp_smp2p_in: slave-kernel {
 302                         qcom,entry-name = "slave-kernel";
 303
 304                         interrupt-controller;
 305                         #interrupt-cells = <2>;
 306                 };
 307         };
 308
 309         smp2p-modem {
 310                 compatible = "qcom,smp2p";
 311                 qcom,smem = <435>, <428>;
 312
 313                 interrupt-parent = <&intc>;
 314                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 315
 316                 qcom,ipc = <&apcs 8 14>;
 317
 318                 qcom,local-pid = <0>;
 319                 qcom,remote-pid = <1>;
 320
 321                 modem_smp2p_out: master-kernel {
 322                         qcom,entry-name = "master-kernel";
 323                         #qcom,smem-state-cells = <1>;
 324                 };
 325
 326                 modem_smp2p_in: slave-kernel {
 327                         qcom,entry-name = "slave-kernel";
 328
 329                         interrupt-controller;
 330                         #interrupt-cells = <2>;
 331                 };
 332         };
 333
 334         soc: soc {
 335
 336                 #address-cells = <1>;
 337                 #size-cells = <1>;
 338                 ranges = <0 0 0 0xffffffff>;
 339                 compatible = "simple-bus";
 340
 341                 intc: interrupt-controller@f9000000 {
 342                         compatible = "qcom,msm-qgic2";
 343                         interrupt-controller;
 344                         #interrupt-cells = <3>;
 345                         reg = <0xf9000000 0x1000>,
 346                               <0xf9002000 0x1000>;
 347                 };
 348
 349                 apcs: mailbox@f900d000 {
 350                         compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
 351                         reg = <0xf900d000 0x2000>;
 352                         #mbox-cells = <1>;
 353                 };
 354
 355                 timer@f9020000 {
 356                         #address-cells = <1>;
 357                         #size-cells = <1>;
 358                         ranges;
 359                         compatible = "arm,armv7-timer-mem";
 360                         reg = <0xf9020000 0x1000>;
 361
 362                         frame@f9021000 {
 363                                 frame-number = <0>;
 364                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 365                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 366                                 reg = <0xf9021000 0x1000>,
 367                                       <0xf9022000 0x1000>;
 368                         };
 369
 370                         frame@f9023000 {
 371                                 frame-number = <1>;
 372                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 373                                 reg = <0xf9023000 0x1000>;
 374                                 status = "disabled";
 375                         };
 376
 377                         frame@f9024000 {
 378                                 frame-number = <2>;
 379                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 380                                 reg = <0xf9024000 0x1000>;
 381                                 status = "disabled";
 382                         };
 383
 384                         frame@f9025000 {
 385                                 frame-number = <3>;
 386                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 387                                 reg = <0xf9025000 0x1000>;
 388                                 status = "disabled";
 389                         };
 390
 391                         frame@f9026000 {
 392                                 frame-number = <4>;
 393                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 394                                 reg = <0xf9026000 0x1000>;
 395                                 status = "disabled";
 396                         };
 397
 398                         frame@f9027000 {
 399                                 frame-number = <5>;
 400                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 401                                 reg = <0xf9027000 0x1000>;
 402                                 status = "disabled";
 403                         };
 404
 405                         frame@f9028000 {
 406                                 frame-number = <6>;
 407                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 408                                 reg = <0xf9028000 0x1000>;
 409                                 status = "disabled";
 410                         };
 411                 };
 412
 413                 usb3: usb@f92f8800 {
 414                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 415                         reg = <0xf92f8800 0x400>;
 416                         #address-cells = <1>;
 417                         #size-cells = <1>;
 418                         ranges;
 419
 420                         clocks = <&gcc GCC_USB30_MASTER_CLK>,
 421                                  <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 422                                  <&gcc GCC_USB30_SLEEP_CLK>,
 423                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
 424                         clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
 425
 426                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 427                                           <&gcc GCC_USB30_MASTER_CLK>;
 428                         assigned-clock-rates = <19200000>, <120000000>;
 429
 430                         power-domains = <&gcc USB30_GDSC>;
 431                         qcom,select-utmi-as-pipe-clk;
 432
 433                         dwc3@f9200000 {
 434                                 compatible = "snps,dwc3";
 435                                 reg = <0xf9200000 0xcc00>;
 436                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 437                                 snps,dis_u2_susphy_quirk;
 438                                 snps,dis_enblslpm_quirk;
 439                                 maximum-speed = "high-speed";
 440                                 dr_mode = "peripheral";
 441                         };
 442                 };
 443
 444                 sdhc1: sdhci@f9824900 {
 445                         compatible = "qcom,sdhci-msm-v4";
 446                         reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
 447                         reg-names = "hc_mem", "core_mem";
 448
 449                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 450                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 451                         interrupt-names = "hc_irq", "pwr_irq";
 452
 453                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 454                                  <&gcc GCC_SDCC1_AHB_CLK>,
 455                                  <&xo_board>;
 456                         clock-names = "core", "iface", "xo";
 457
 458                         pinctrl-names = "default", "sleep";
 459                         pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
 460                         pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
 461
 462                         bus-width = <8>;
 463                         non-removable;
 464                         status = "disabled";
 465                 };
 466
 467                 sdhc2: sdhci@f98a4900 {
 468                         compatible = "qcom,sdhci-msm-v4";
 469                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 470                         reg-names = "hc_mem", "core_mem";
 471
 472                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 473                                 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 474                         interrupt-names = "hc_irq", "pwr_irq";
 475
 476                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 477                                 <&gcc GCC_SDCC2_AHB_CLK>,
 478                                 <&xo_board>;
 479                         clock-names = "core", "iface", "xo";
 480
 481                         pinctrl-names = "default", "sleep";
 482                         pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
 483                         pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
 484
 485                         cd-gpios = <&tlmm 100 0>;
 486                         bus-width = <4>;
 487                         status = "disabled";
 488                 };
 489
 490                 blsp1_dma: dma-controller@f9904000 {
 491                         compatible = "qcom,bam-v1.7.0";
 492                         reg = <0xf9904000 0x19000>;
 493                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 495                         clock-names = "bam_clk";
 496                         #dma-cells = <1>;
 497                         qcom,ee = <0>;
 498                         qcom,controlled-remotely;
 499                         num-channels = <18>;
 500                         qcom,num-ees = <4>;
 501                 };
 502
 503                 blsp1_uart2: serial@f991e000 {
 504                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 505                         reg = <0xf991e000 0x1000>;
 506                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 507                         clock-names = "core", "iface";
 508                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 509                                  <&gcc GCC_BLSP1_AHB_CLK>;
 510                         pinctrl-names = "default", "sleep";
 511                         pinctrl-0 = <&blsp1_uart2_default>;
 512                         pinctrl-1 = <&blsp1_uart2_sleep>;
 513                         status = "disabled";
 514                 };
 515
 516                 blsp1_i2c1: i2c@f9923000 {
 517                         compatible = "qcom,i2c-qup-v2.2.1";
 518                         reg = <0xf9923000 0x500>;
 519                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 521                                                 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 522                         clock-names = "iface", "core";
 523                         clock-frequency = <400000>;
 524                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
 525                         dma-names = "tx", "rx";
 526                         pinctrl-names = "default", "sleep";
 527                         pinctrl-0 = <&i2c1_default>;
 528                         pinctrl-1 = <&i2c1_sleep>;
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         status = "disabled";
 532                 };
 533
 534                 blsp1_spi1: spi@f9923000 {
 535                         compatible = "qcom,spi-qup-v2.2.1";
 536                         reg = <0xf9923000 0x500>;
 537                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 539                                  <&gcc GCC_BLSP1_AHB_CLK>;
 540                         clock-names = "core", "iface";
 541                         spi-max-frequency = <19200000>;
 542                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
 543                         dma-names = "tx", "rx";
 544                         pinctrl-names = "default", "sleep";
 545                         pinctrl-0 = <&blsp1_spi1_default>;
 546                         pinctrl-1 = <&blsp1_spi1_sleep>;
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         status = "disabled";
 550                 };
 551
 552                 blsp1_i2c2: i2c@f9924000 {
 553                         compatible = "qcom,i2c-qup-v2.2.1";
 554                         reg = <0xf9924000 0x500>;
 555                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 557                                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 558                         clock-names = "iface", "core";
 559                         clock-frequency = <400000>;
 560                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
 561                         dma-names = "tx", "rx";
 562                         pinctrl-names = "default", "sleep";
 563                         pinctrl-0 = <&i2c2_default>;
 564                         pinctrl-1 = <&i2c2_sleep>;
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         status = "disabled";
 568                 };
 569
 570                 /* I2C3 doesn't exist */
 571
 572                 blsp1_i2c4: i2c@f9926000 {
 573                         compatible = "qcom,i2c-qup-v2.2.1";
 574                         reg = <0xf9926000 0x500>;
 575                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 577                                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 578                         clock-names = "iface", "core";
 579                         clock-frequency = <400000>;
 580                         dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
 581                         dma-names = "tx", "rx";
 582                         pinctrl-names = "default", "sleep";
 583                         pinctrl-0 = <&i2c4_default>;
 584                         pinctrl-1 = <&i2c4_sleep>;
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         status = "disabled";
 588                 };
 589
 590                 blsp1_i2c5: i2c@f9927000 {
 591                         compatible = "qcom,i2c-qup-v2.2.1";
 592                         reg = <0xf9927000 0x500>;
 593                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 594                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 595                                                 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
 596                         clock-names = "iface", "core";
 597                         clock-frequency = <400000>;
 598                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 599                         dma-names = "tx", "rx";
 600                         pinctrl-names = "default", "sleep";
 601                         pinctrl-0 = <&i2c5_default>;
 602                         pinctrl-1 = <&i2c5_sleep>;
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         status = "disabled";
 606                 };
 607
 608                 blsp1_i2c6: i2c@f9928000 {
 609                         compatible = "qcom,i2c-qup-v2.2.1";
 610                         reg = <0xf9928000 0x500>;
 611                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 613                                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 614                         clock-names = "iface", "core";
 615                         clock-frequency = <400000>;
 616                         dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
 617                         dma-names = "tx", "rx";
 618                         pinctrl-names = "default", "sleep";
 619                         pinctrl-0 = <&i2c6_default>;
 620                         pinctrl-1 = <&i2c6_sleep>;
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623                         status = "disabled";
 624                 };
 625
 626                 blsp2_dma: dma-controller@f9944000 {
 627                         compatible = "qcom,bam-v1.7.0";
 628                         reg = <0xf9944000 0x19000>;
 629                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 631                         clock-names = "bam_clk";
 632                         #dma-cells = <1>;
 633                         qcom,ee = <0>;
 634                         qcom,controlled-remotely;
 635                         num-channels = <18>;
 636                         qcom,num-ees = <4>;
 637                 };
 638
 639                 blsp2_uart2: serial@f995e000 {
 640                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 641                         reg = <0xf995e000 0x1000>;
 642                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 643                         clock-names = "core", "iface";
 644                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 645                                         <&gcc GCC_BLSP2_AHB_CLK>;
 646                         dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
 647                         dma-names = "tx", "rx";
 648                         pinctrl-names = "default", "sleep";
 649                         pinctrl-0 = <&blsp2_uart2_default>;
 650                         pinctrl-1 = <&blsp2_uart2_sleep>;
 651                         status = "disabled";
 652                 };
 653
 654                 blsp2_i2c1: i2c@f9963000 {
 655                         compatible = "qcom,i2c-qup-v2.2.1";
 656                         reg = <0xf9963000 0x500>;
 657                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 658                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 659                                         <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 660                         clock-names = "iface", "core";
 661                         clock-frequency = <400000>;
 662                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
 663                         dma-names = "tx", "rx";
 664                         pinctrl-names = "default", "sleep";
 665                         pinctrl-0 = <&i2c7_default>;
 666                         pinctrl-1 = <&i2c7_sleep>;
 667                         #address-cells = <1>;
 668                         #size-cells = <0>;
 669                         status = "disabled";
 670                 };
 671
 672                 blsp2_spi4: spi@f9966000 {
 673                         compatible = "qcom,spi-qup-v2.2.1";
 674                         reg = <0xf9966000 0x500>;
 675                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 676                         clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
 677                                  <&gcc GCC_BLSP2_AHB_CLK>;
 678                         clock-names = "core", "iface";
 679                         spi-max-frequency = <19200000>;
 680                         dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
 681                         dma-names = "tx", "rx";
 682                         pinctrl-names = "default", "sleep";
 683                         pinctrl-0 = <&blsp2_spi10_default>;
 684                         pinctrl-1 = <&blsp2_spi10_sleep>;
 685                         #address-cells = <1>;
 686                         #size-cells = <0>;
 687                         status = "disabled";
 688                 };
 689
 690                 blsp2_i2c5: i2c@f9967000 {
 691                         compatible = "qcom,i2c-qup-v2.2.1";
 692                         reg = <0xf9967000 0x500>;
 693                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 694                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 695                                                 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
 696                         clock-names = "iface", "core";
 697                         clock-frequency = <355000>;
 698                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 699                         dma-names = "tx", "rx";
 700                         pinctrl-names = "default", "sleep";
 701                         pinctrl-0 = <&i2c11_default>;
 702                         pinctrl-1 = <&i2c11_sleep>;
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                         status = "disabled";
 706                 };
 707
 708                 gcc: clock-controller@fc400000 {
 709                         compatible = "qcom,gcc-msm8994";
 710                         #clock-cells = <1>;
 711                         #reset-cells = <1>;
 712                         #power-domain-cells = <1>;
 713                         reg = <0xfc400000 0x2000>;
 714                 };
 715
 716                 rpm_msg_ram: memory@fc428000 {
 717                         compatible = "qcom,rpm-msg-ram";
 718                         reg = <0xfc428000 0x4000>;
 719                 };
 720
 721                 restart@fc4ab000 {
 722                         compatible = "qcom,pshold";
 723                         reg = <0xfc4ab000 0x4>;
 724                 };
 725
 726                 spmi_bus: spmi@fc4c0000 {
 727                         compatible = "qcom,spmi-pmic-arb";
 728                         reg = <0xfc4cf000 0x1000>,
 729                               <0xfc4cb000 0x1000>,
 730                               <0xfc4ca000 0x1000>;
 731                         reg-names = "core", "intr", "cnfg";
 732                         interrupt-names = "periph_irq";
 733                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 734                         qcom,ee = <0>;
 735                         qcom,channel = <0>;
 736                         #address-cells = <2>;
 737                         #size-cells = <0>;
 738                         interrupt-controller;
 739                         #interrupt-cells = <4>;
 740                 };
 741
 742                 tcsr_mutex_regs: syscon@fd484000 {
 743                         compatible = "syscon";
 744                         reg = <0xfd484000 0x2000>;
 745                 };
 746
 747                 tlmm: pinctrl@fd510000 {
 748                         compatible = "qcom,msm8994-pinctrl";
 749                         reg = <0xfd510000 0x4000>;
 750                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 751                         gpio-controller;
 752                         gpio-ranges = <&tlmm 0 0 146>;
 753                         #gpio-cells = <2>;
 754                         interrupt-controller;
 755                         #interrupt-cells = <2>;
 756
 757                         blsp1_uart2_default: blsp1-uart2-default {
 758                                 function = "blsp_uart2";
 759                                 pins = "gpio4", "gpio5";
 760                                 drive-strength = <16>;
 761                                 bias-disable;
 762                         };
 763
 764                         blsp1_uart2_sleep: blsp1-uart2-sleep {
 765                                 function = "gpio";
 766                                 pins = "gpio4", "gpio5";
 767                                 drive-strength = <2>;
 768                                 bias-pull-down;
 769                         };
 770
 771                         blsp2_uart2_default: blsp2-uart2-default {
 772                                 function = "blsp_uart8";
 773                                 pins = "gpio45", "gpio46",
 774                                                 "gpio47", "gpio48";
 775                                 drive-strength = <16>;
 776                                 bias-disable;
 777                         };
 778
 779                         blsp2_uart2_sleep: blsp2-uart2-sleep {
 780                                 function = "gpio";
 781                                 pins = "gpio45", "gpio46",
 782                                                 "gpio47", "gpio48";
 783                                 drive-strength = <2>;
 784                                 bias-disable;
 785                         };
 786
 787                         i2c1_default: i2c1-default {
 788                                 function = "blsp_i2c1";
 789                                 pins = "gpio2", "gpio3";
 790                                 drive-strength = <2>;
 791                                 bias-disable;
 792                         };
 793
 794                         i2c1_sleep: i2c1-sleep {
 795                                 function = "gpio";
 796                                 pins = "gpio2", "gpio3";
 797                                 drive-strength = <2>;
 798                                 bias-disable;
 799                         };
 800
 801                         i2c2_default: i2c2-default {
 802                                 function = "blsp_i2c2";
 803                                 pins = "gpio6", "gpio7";
 804                                 drive-strength = <2>;
 805                                 bias-disable;
 806                         };
 807
 808                         i2c2_sleep: i2c2-sleep {
 809                                 function = "gpio";
 810                                 pins = "gpio6", "gpio7";
 811                                 drive-strength = <2>;
 812                                 bias-disable;
 813                         };
 814
 815                         i2c4_default: i2c4-default {
 816                                 function = "blsp_i2c4";
 817                                 pins = "gpio19", "gpio20";
 818                                 drive-strength = <2>;
 819                                 bias-disable;
 820                         };
 821
 822                         i2c4_sleep: i2c4-sleep {
 823                                 function = "gpio";
 824                                 pins = "gpio19", "gpio20";
 825                                 drive-strength = <2>;
 826                                 bias-pull-down;
 827                                 input-enable;
 828                         };
 829
 830                         i2c5_default: i2c5-default {
 831                                 function = "blsp_i2c5";
 832                                 pins = "gpio23", "gpio24";
 833                                 drive-strength = <2>;
 834                                 bias-disable;
 835                         };
 836
 837                         i2c5_sleep: i2c5-sleep {
 838                                 function = "gpio";
 839                                 pins = "gpio23", "gpio24";
 840                                 drive-strength = <2>;
 841                                 bias-disable;
 842                         };
 843
 844                         i2c6_default: i2c6-default {
 845                                 function = "blsp_i2c6";
 846                                 pins = "gpio28", "gpio27";
 847                                 drive-strength = <2>;
 848                                 bias-disable;
 849                         };
 850
 851                         i2c6_sleep: i2c6-sleep {
 852                                 function = "gpio";
 853                                 pins = "gpio28", "gpio27";
 854                                 drive-strength = <2>;
 855                                 bias-disable;
 856                         };
 857
 858                         i2c7_default: i2c7-default {
 859                                 function = "blsp_i2c7";
 860                                 pins = "gpio44", "gpio43";
 861                                 drive-strength = <2>;
 862                                 bias-disable;
 863                         };
 864
 865                         i2c7_sleep: i2c7-sleep {
 866                                 function = "gpio";
 867                                 pins = "gpio44", "gpio43";
 868                                 drive-strength = <2>;
 869                                 bias-disable;
 870                         };
 871
 872                         blsp2_spi10_default: blsp2-spi10-default {
 873                                 default {
 874                                         function = "blsp_spi10";
 875                                         pins = "gpio53", "gpio54", "gpio55";
 876                                         drive-strength = <10>;
 877                                         bias-pull-down;
 878                                 };
 879                                 cs {
 880                                         function = "gpio";
 881                                         pins = "gpio55";
 882                                         drive-strength = <2>;
 883                                         bias-disable;
 884                                 };
 885                         };
 886
 887                         blsp2_spi10_sleep: blsp2-spi10-sleep {
 888                                 pins = "gpio53", "gpio54", "gpio55";
 889                                 drive-strength = <2>;
 890                                 bias-disable;
 891                         };
 892
 893                         i2c11_default: i2c11-default {
 894                                 function = "blsp_i2c11";
 895                                 pins = "gpio83", "gpio84";
 896                                 drive-strength = <2>;
 897                                 bias-disable;
 898                         };
 899
 900                         i2c11_sleep: i2c11-sleep {
 901                                 function = "gpio";
 902                                 pins = "gpio83", "gpio84";
 903                                 drive-strength = <2>;
 904                                 bias-disable;
 905                         };
 906
 907                         blsp1_spi1_default: blsp1-spi1-default {
 908                                 default {
 909                                         function = "blsp_spi1";
 910                                         pins = "gpio0", "gpio1", "gpio3";
 911                                         drive-strength = <10>;
 912                                         bias-pull-down;
 913                                 };
 914                                 cs {
 915                                         function = "gpio";
 916                                         pins = "gpio8";
 917                                         drive-strength = <2>;
 918                                         bias-disable;
 919                                 };
 920                         };
 921
 922                         blsp1_spi1_sleep: blsp1-spi1-sleep {
 923                                 pins = "gpio0", "gpio1", "gpio3";
 924                                 drive-strength = <2>;
 925                                 bias-disable;
 926                         };
 927
 928                         sdc1_clk_on: clk-on {
 929                                 pins = "sdc1_clk";
 930                                 bias-disable;
 931                                 drive-strength = <16>;
 932                         };
 933
 934                         sdc1_clk_off: clk-off {
 935                                 pins = "sdc1_clk";
 936                                 bias-disable;
 937                                 drive-strength = <2>;
 938                         };
 939
 940                         sdc1_cmd_on: cmd-on {
 941                                 pins = "sdc1_cmd";
 942                                 bias-pull-up;
 943                                 drive-strength = <8>;
 944                         };
 945
 946                         sdc1_cmd_off: cmd-off {
 947                                 pins = "sdc1_cmd";
 948                                 bias-pull-up;
 949                                 drive-strength = <2>;
 950                         };
 951
 952                         sdc1_data_on: data-on {
 953                                 pins = "sdc1_data";
 954                                 bias-pull-up;
 955                                 drive-strength = <8>;
 956                         };
 957
 958                         sdc1_data_off: data-off {
 959                                 pins = "sdc1_data";
 960                                 bias-pull-up;
 961                                 drive-strength = <2>;
 962                         };
 963
 964                         sdc1_rclk_on: rclk-on {
 965                                 pins = "sdc1_rclk";
 966                                 bias-pull-down;
 967                         };
 968
 969                         sdc1_rclk_off: rclk-off {
 970                                 pins = "sdc1_rclk";
 971                                 bias-pull-down;
 972                         };
 973
 974                         sdc2_clk_on: sdc2-clk-on {
 975                                 pins = "sdc2_clk";
 976                                 bias-disable;
 977                                 drive-strength = <10>;
 978                         };
 979
 980                         sdc2_clk_off: sdc2-clk-off {
 981                                 pins = "sdc2_clk";
 982                                 bias-disable;
 983                                 drive-strength = <2>;
 984                         };
 985
 986                         sdc2_cmd_on: sdc2-cmd-on {
 987                                 pins = "sdc2_cmd";
 988                                 bias-pull-up;
 989                                 drive-strength = <10>;
 990                         };
 991
 992                         sdc2_cmd_off: sdc2-cmd-off {
 993                                 pins = "sdc2_cmd";
 994                                 bias-pull-up;
 995                                 drive-strength = <2>;
 996                         };
 997
 998                         sdc2_data_on: sdc2-data-on {
 999                                 pins = "sdc2_data";
1000                                 bias-pull-up;
1001                                 drive-strength = <10>;
1002                         };
1003
1004                         sdc2_data_off: sdc2-data-off {
1005                                 pins = "sdc2_data";
1006                                 bias-pull-up;
1007                                 drive-strength = <2>;
1008                         };
1009                 };
1010         };
1011
1012         timer: timer {
1013                 compatible = "arm,armv8-timer";
1014                 interrupts = <GIC_PPI 2 0xff08>,
1015                              <GIC_PPI 3 0xff08>,
1016                              <GIC_PPI 4 0xff08>,
1017                              <GIC_PPI 1 0xff08>;
1018         };
1019
1020         vph_pwr: vph-pwr-regulator {
1021                 compatible = "regulator-fixed";
1022                 regulator-name = "vph_pwr";
1023
1024                 regulator-min-microvolt = <3600000>;
1025                 regulator-max-microvolt = <3600000>;
1026
1027                 regulator-always-on;
1028         };
1029 };
1030