arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/arm/coresight-cti-dt.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/interconnect/qcom,msm8916.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  23                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  24         };
  25
  26         chosen { };
  27
  28         memory@80000000 {
  29                 device_type = "memory";
  30                 /* We expect the bootloader to fill in the reg */
  31                 reg = <0 0x80000000 0 0>;
  32         };
  33
  34         reserved-memory {
  35                 #address-cells = <2>;
  36                 #size-cells = <2>;
  37                 ranges;
  38
  39                 tz-apps@86000000 {
  40                         reg = <0x0 0x86000000 0x0 0x300000>;
  41                         no-map;
  42                 };
  43
  44                 smem_mem: smem_region@86300000 {
  45                         reg = <0x0 0x86300000 0x0 0x100000>;
  46                         no-map;
  47                 };
  48
  49                 hypervisor@86400000 {
  50                         reg = <0x0 0x86400000 0x0 0x100000>;
  51                         no-map;
  52                 };
  53
  54                 tz@86500000 {
  55                         reg = <0x0 0x86500000 0x0 0x180000>;
  56                         no-map;
  57                 };
  58
  59                 reserved@86680000 {
  60                         reg = <0x0 0x86680000 0x0 0x80000>;
  61                         no-map;
  62                 };
  63
  64                 rmtfs@86700000 {
  65                         compatible = "qcom,rmtfs-mem";
  66                         reg = <0x0 0x86700000 0x0 0xe0000>;
  67                         no-map;
  68
  69                         qcom,client-id = <1>;
  70                 };
  71
  72                 rfsa@867e0000 {
  73                         reg = <0x0 0x867e0000 0x0 0x20000>;
  74                         no-map;
  75                 };
  76
  77                 mpss_mem: mpss@86800000 {
  78                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  79                         no-map;
  80                 };
  81
  82                 wcnss_mem: wcnss@89300000 {
  83                         reg = <0x0 0x89300000 0x0 0x600000>;
  84                         no-map;
  85                 };
  86
  87                 venus_mem: venus@89900000 {
  88                         reg = <0x0 0x89900000 0x0 0x600000>;
  89                         no-map;
  90                 };
  91
  92                 mba_mem: mba@8ea00000 {
  93                         no-map;
  94                         reg = <0 0x8ea00000 0 0x100000>;
  95                 };
  96         };
  97
  98         clocks {
  99                 xo_board: xo-board {
 100                         compatible = "fixed-clock";
 101                         #clock-cells = <0>;
 102                         clock-frequency = <19200000>;
 103                 };
 104
 105                 sleep_clk: sleep-clk {
 106                         compatible = "fixed-clock";
 107                         #clock-cells = <0>;
 108                         clock-frequency = <32768>;
 109                 };
 110         };
 111
 112         cpus {
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115
 116                 CPU0: cpu@0 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a53";
 119                         reg = <0x0>;
 120                         next-level-cache = <&L2_0>;
 121                         enable-method = "psci";
 122                         clocks = <&apcs>;
 123                         operating-points-v2 = <&cpu_opp_table>;
 124                         #cooling-cells = <2>;
 125                         power-domains = <&CPU_PD0>;
 126                         power-domain-names = "psci";
 127                 };
 128
 129                 CPU1: cpu@1 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53";
 132                         reg = <0x1>;
 133                         next-level-cache = <&L2_0>;
 134                         enable-method = "psci";
 135                         clocks = <&apcs>;
 136                         operating-points-v2 = <&cpu_opp_table>;
 137                         #cooling-cells = <2>;
 138                         power-domains = <&CPU_PD1>;
 139                         power-domain-names = "psci";
 140                 };
 141
 142                 CPU2: cpu@2 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53";
 145                         reg = <0x2>;
 146                         next-level-cache = <&L2_0>;
 147                         enable-method = "psci";
 148                         clocks = <&apcs>;
 149                         operating-points-v2 = <&cpu_opp_table>;
 150                         #cooling-cells = <2>;
 151                         power-domains = <&CPU_PD2>;
 152                         power-domain-names = "psci";
 153                 };
 154
 155                 CPU3: cpu@3 {
 156                         device_type = "cpu";
 157                         compatible = "arm,cortex-a53";
 158                         reg = <0x3>;
 159                         next-level-cache = <&L2_0>;
 160                         enable-method = "psci";
 161                         clocks = <&apcs>;
 162                         operating-points-v2 = <&cpu_opp_table>;
 163                         #cooling-cells = <2>;
 164                         power-domains = <&CPU_PD3>;
 165                         power-domain-names = "psci";
 166                 };
 167
 168                 L2_0: l2-cache {
 169                         compatible = "cache";
 170                         cache-level = <2>;
 171                 };
 172
 173                 idle-states {
 174                         entry-method = "psci";
 175
 176                         CPU_SLEEP_0: cpu-sleep-0 {
 177                                 compatible = "arm,idle-state";
 178                                 idle-state-name = "standalone-power-collapse";
 179                                 arm,psci-suspend-param = <0x40000002>;
 180                                 entry-latency-us = <130>;
 181                                 exit-latency-us = <150>;
 182                                 min-residency-us = <2000>;
 183                                 local-timer-stop;
 184                         };
 185                 };
 186
 187                 domain-idle-states {
 188
 189                         CLUSTER_RET: cluster-retention {
 190                                 compatible = "domain-idle-state";
 191                                 arm,psci-suspend-param = <0x41000012>;
 192                                 entry-latency-us = <500>;
 193                                 exit-latency-us = <500>;
 194                                 min-residency-us = <2000>;
 195                         };
 196
 197                         CLUSTER_PWRDN: cluster-gdhs {
 198                                 compatible = "domain-idle-state";
 199                                 arm,psci-suspend-param = <0x41000032>;
 200                                 entry-latency-us = <2000>;
 201                                 exit-latency-us = <2000>;
 202                                 min-residency-us = <6000>;
 203                         };
 204                 };
 205         };
 206
 207         cpu_opp_table: cpu-opp-table {
 208                 compatible = "operating-points-v2";
 209                 opp-shared;
 210
 211                 opp-200000000 {
 212                         opp-hz = /bits/ 64 <200000000>;
 213                 };
 214                 opp-400000000 {
 215                         opp-hz = /bits/ 64 <400000000>;
 216                 };
 217                 opp-800000000 {
 218                         opp-hz = /bits/ 64 <800000000>;
 219                 };
 220                 opp-998400000 {
 221                         opp-hz = /bits/ 64 <998400000>;
 222                 };
 223         };
 224
 225         firmware {
 226                 scm: scm {
 227                         compatible = "qcom,scm-msm8916", "qcom,scm";
 228                         clocks = <&gcc GCC_CRYPTO_CLK>,
 229                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 230                                  <&gcc GCC_CRYPTO_AHB_CLK>;
 231                         clock-names = "core", "bus", "iface";
 232                         #reset-cells = <1>;
 233
 234                         qcom,dload-mode = <&tcsr 0x6100>;
 235                 };
 236         };
 237
 238         pmu {
 239                 compatible = "arm,cortex-a53-pmu";
 240                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 241         };
 242
 243         psci {
 244                 compatible = "arm,psci-1.0";
 245                 method = "smc";
 246
 247                 CPU_PD0: power-domain-cpu0 {
 248                         #power-domain-cells = <0>;
 249                         power-domains = <&CLUSTER_PD>;
 250                         domain-idle-states = <&CPU_SLEEP_0>;
 251                 };
 252
 253                 CPU_PD1: power-domain-cpu1 {
 254                         #power-domain-cells = <0>;
 255                         power-domains = <&CLUSTER_PD>;
 256                         domain-idle-states = <&CPU_SLEEP_0>;
 257                 };
 258
 259                 CPU_PD2: power-domain-cpu2 {
 260                         #power-domain-cells = <0>;
 261                         power-domains = <&CLUSTER_PD>;
 262                         domain-idle-states = <&CPU_SLEEP_0>;
 263                 };
 264
 265                 CPU_PD3: power-domain-cpu3 {
 266                         #power-domain-cells = <0>;
 267                         power-domains = <&CLUSTER_PD>;
 268                         domain-idle-states = <&CPU_SLEEP_0>;
 269                 };
 270
 271                 CLUSTER_PD: power-domain-cluster {
 272                         #power-domain-cells = <0>;
 273                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
 274                 };
 275         };
 276
 277         smd {
 278                 compatible = "qcom,smd";
 279
 280                 rpm {
 281                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 282                         qcom,ipc = <&apcs 8 0>;
 283                         qcom,smd-edge = <15>;
 284
 285                         rpm_requests: rpm-requests {
 286                                 compatible = "qcom,rpm-msm8916";
 287                                 qcom,smd-channels = "rpm_requests";
 288
 289                                 rpmcc: clock-controller {
 290                                         compatible = "qcom,rpmcc-msm8916";
 291                                         #clock-cells = <1>;
 292                                 };
 293
 294                                 rpmpd: power-controller {
 295                                         compatible = "qcom,msm8916-rpmpd";
 296                                         #power-domain-cells = <1>;
 297                                         operating-points-v2 = <&rpmpd_opp_table>;
 298
 299                                         rpmpd_opp_table: opp-table {
 300                                                 compatible = "operating-points-v2";
 301
 302                                                 rpmpd_opp_ret: opp1 {
 303                                                         opp-level = <1>;
 304                                                 };
 305                                                 rpmpd_opp_svs_krait: opp2 {
 306                                                         opp-level = <2>;
 307                                                 };
 308                                                 rpmpd_opp_svs_soc: opp3 {
 309                                                         opp-level = <3>;
 310                                                 };
 311                                                 rpmpd_opp_nom: opp4 {
 312                                                         opp-level = <4>;
 313                                                 };
 314                                                 rpmpd_opp_turbo: opp5 {
 315                                                         opp-level = <5>;
 316                                                 };
 317                                                 rpmpd_opp_super_turbo: opp6 {
 318                                                         opp-level = <6>;
 319                                                 };
 320                                         };
 321                                 };
 322                         };
 323                 };
 324         };
 325
 326         smem {
 327                 compatible = "qcom,smem";
 328
 329                 memory-region = <&smem_mem>;
 330                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 331
 332                 hwlocks = <&tcsr_mutex 3>;
 333         };
 334
 335         smp2p-hexagon {
 336                 compatible = "qcom,smp2p";
 337                 qcom,smem = <435>, <428>;
 338
 339                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 340
 341                 qcom,ipc = <&apcs 8 14>;
 342
 343                 qcom,local-pid = <0>;
 344                 qcom,remote-pid = <1>;
 345
 346                 hexagon_smp2p_out: master-kernel {
 347                         qcom,entry-name = "master-kernel";
 348
 349                         #qcom,smem-state-cells = <1>;
 350                 };
 351
 352                 hexagon_smp2p_in: slave-kernel {
 353                         qcom,entry-name = "slave-kernel";
 354
 355                         interrupt-controller;
 356                         #interrupt-cells = <2>;
 357                 };
 358         };
 359
 360         smp2p-wcnss {
 361                 compatible = "qcom,smp2p";
 362                 qcom,smem = <451>, <431>;
 363
 364                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 365
 366                 qcom,ipc = <&apcs 8 18>;
 367
 368                 qcom,local-pid = <0>;
 369                 qcom,remote-pid = <4>;
 370
 371                 wcnss_smp2p_out: master-kernel {
 372                         qcom,entry-name = "master-kernel";
 373
 374                         #qcom,smem-state-cells = <1>;
 375                 };
 376
 377                 wcnss_smp2p_in: slave-kernel {
 378                         qcom,entry-name = "slave-kernel";
 379
 380                         interrupt-controller;
 381                         #interrupt-cells = <2>;
 382                 };
 383         };
 384
 385         smsm {
 386                 compatible = "qcom,smsm";
 387
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390
 391                 qcom,ipc-1 = <&apcs 8 13>;
 392                 qcom,ipc-3 = <&apcs 8 19>;
 393
 394                 apps_smsm: apps@0 {
 395                         reg = <0>;
 396
 397                         #qcom,smem-state-cells = <1>;
 398                 };
 399
 400                 hexagon_smsm: hexagon@1 {
 401                         reg = <1>;
 402                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 403
 404                         interrupt-controller;
 405                         #interrupt-cells = <2>;
 406                 };
 407
 408                 wcnss_smsm: wcnss@6 {
 409                         reg = <6>;
 410                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 411
 412                         interrupt-controller;
 413                         #interrupt-cells = <2>;
 414                 };
 415         };
 416
 417         soc: soc {
 418                 #address-cells = <1>;
 419                 #size-cells = <1>;
 420                 ranges = <0 0 0 0xffffffff>;
 421                 compatible = "simple-bus";
 422
 423                 rng@22000 {
 424                         compatible = "qcom,prng";
 425                         reg = <0x00022000 0x200>;
 426                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 427                         clock-names = "core";
 428                 };
 429
 430                 restart@4ab000 {
 431                         compatible = "qcom,pshold";
 432                         reg = <0x004ab000 0x4>;
 433                 };
 434
 435                 qfprom: qfprom@5c000 {
 436                         compatible = "qcom,qfprom";
 437                         reg = <0x0005c000 0x1000>;
 438                         #address-cells = <1>;
 439                         #size-cells = <1>;
 440                         tsens_caldata: caldata@d0 {
 441                                 reg = <0xd0 0x8>;
 442                         };
 443                         tsens_calsel: calsel@ec {
 444                                 reg = <0xec 0x4>;
 445                         };
 446                 };
 447
 448                 rpm_msg_ram: memory@60000 {
 449                         compatible = "qcom,rpm-msg-ram";
 450                         reg = <0x00060000 0x8000>;
 451                 };
 452
 453                 bimc: interconnect@400000 {
 454                         compatible = "qcom,msm8916-bimc";
 455                         reg = <0x00400000 0x62000>;
 456                         #interconnect-cells = <1>;
 457                         clock-names = "bus", "bus_a";
 458                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 459                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 460                 };
 461
 462                 tsens: thermal-sensor@4a9000 {
 463                         compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
 464                         reg = <0x004a9000 0x1000>, /* TM */
 465                               <0x004a8000 0x1000>; /* SROT */
 466                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 467                         nvmem-cell-names = "calib", "calib_sel";
 468                         #qcom,sensors = <5>;
 469                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 470                         interrupt-names = "uplow";
 471                         #thermal-sensor-cells = <1>;
 472                 };
 473
 474                 pcnoc: interconnect@500000 {
 475                         compatible = "qcom,msm8916-pcnoc";
 476                         reg = <0x00500000 0x11000>;
 477                         #interconnect-cells = <1>;
 478                         clock-names = "bus", "bus_a";
 479                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
 480                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
 481                 };
 482
 483                 snoc: interconnect@580000 {
 484                         compatible = "qcom,msm8916-snoc";
 485                         reg = <0x00580000 0x14000>;
 486                         #interconnect-cells = <1>;
 487                         clock-names = "bus", "bus_a";
 488                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 489                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 490                 };
 491
 492                 /* System CTIs */
 493                 /* CTI 0 - TMC connections */
 494                 cti0: cti@810000 {
 495                         compatible = "arm,coresight-cti", "arm,primecell";
 496                         reg = <0x00810000 0x1000>;
 497
 498                         clocks = <&rpmcc RPM_QDSS_CLK>;
 499                         clock-names = "apb_pclk";
 500
 501                         status = "disabled";
 502                 };
 503
 504                 /* CTI 1 - TPIU connections */
 505                 cti1: cti@811000 {
 506                         compatible = "arm,coresight-cti", "arm,primecell";
 507                         reg = <0x00811000 0x1000>;
 508
 509                         clocks = <&rpmcc RPM_QDSS_CLK>;
 510                         clock-names = "apb_pclk";
 511
 512                         status = "disabled";
 513                 };
 514
 515                 /* CTIs 2-11 - no information - not instantiated */
 516
 517                 tpiu: tpiu@820000 {
 518                         compatible = "arm,coresight-tpiu", "arm,primecell";
 519                         reg = <0x00820000 0x1000>;
 520
 521                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 522                         clock-names = "apb_pclk", "atclk";
 523
 524                         status = "disabled";
 525
 526                         in-ports {
 527                                 port {
 528                                         tpiu_in: endpoint {
 529                                                 remote-endpoint = <&replicator_out1>;
 530                                         };
 531                                 };
 532                         };
 533                 };
 534
 535                 funnel0: funnel@821000 {
 536                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 537                         reg = <0x00821000 0x1000>;
 538
 539                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 540                         clock-names = "apb_pclk", "atclk";
 541
 542                         status = "disabled";
 543
 544                         in-ports {
 545                                 #address-cells = <1>;
 546                                 #size-cells = <0>;
 547
 548                                 /*
 549                                  * Not described input ports:
 550                                  * 0 - connected to Resource and Power Manger CPU ETM
 551                                  * 1 - not-connected
 552                                  * 2 - connected to Modem CPU ETM
 553                                  * 3 - not-connected
 554                                  * 5 - not-connected
 555                                  * 6 - connected trought funnel to Wireless CPU ETM
 556                                  * 7 - connected to STM component
 557                                  */
 558
 559                                 port@4 {
 560                                         reg = <4>;
 561                                         funnel0_in4: endpoint {
 562                                                 remote-endpoint = <&funnel1_out>;
 563                                         };
 564                                 };
 565                         };
 566
 567                         out-ports {
 568                                 port {
 569                                         funnel0_out: endpoint {
 570                                                 remote-endpoint = <&etf_in>;
 571                                         };
 572                                 };
 573                         };
 574                 };
 575
 576                 replicator: replicator@824000 {
 577                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 578                         reg = <0x00824000 0x1000>;
 579
 580                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 581                         clock-names = "apb_pclk", "atclk";
 582
 583                         status = "disabled";
 584
 585                         out-ports {
 586                                 #address-cells = <1>;
 587                                 #size-cells = <0>;
 588
 589                                 port@0 {
 590                                         reg = <0>;
 591                                         replicator_out0: endpoint {
 592                                                 remote-endpoint = <&etr_in>;
 593                                         };
 594                                 };
 595                                 port@1 {
 596                                         reg = <1>;
 597                                         replicator_out1: endpoint {
 598                                                 remote-endpoint = <&tpiu_in>;
 599                                         };
 600                                 };
 601                         };
 602
 603                         in-ports {
 604                                 port {
 605                                         replicator_in: endpoint {
 606                                                 remote-endpoint = <&etf_out>;
 607                                         };
 608                                 };
 609                         };
 610                 };
 611
 612                 etf: etf@825000 {
 613                         compatible = "arm,coresight-tmc", "arm,primecell";
 614                         reg = <0x00825000 0x1000>;
 615
 616                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 617                         clock-names = "apb_pclk", "atclk";
 618
 619                         status = "disabled";
 620
 621                         in-ports {
 622                                 port {
 623                                         etf_in: endpoint {
 624                                                 remote-endpoint = <&funnel0_out>;
 625                                         };
 626                                 };
 627                         };
 628
 629                         out-ports {
 630                                 port {
 631                                         etf_out: endpoint {
 632                                                 remote-endpoint = <&replicator_in>;
 633                                         };
 634                                 };
 635                         };
 636                 };
 637
 638                 etr: etr@826000 {
 639                         compatible = "arm,coresight-tmc", "arm,primecell";
 640                         reg = <0x00826000 0x1000>;
 641
 642                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 643                         clock-names = "apb_pclk", "atclk";
 644
 645                         status = "disabled";
 646
 647                         in-ports {
 648                                 port {
 649                                         etr_in: endpoint {
 650                                                 remote-endpoint = <&replicator_out0>;
 651                                         };
 652                                 };
 653                         };
 654                 };
 655
 656                 funnel1: funnel@841000 {        /* APSS funnel only 4 inputs are used */
 657                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 658                         reg = <0x00841000 0x1000>;
 659
 660                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 661                         clock-names = "apb_pclk", "atclk";
 662
 663                         status = "disabled";
 664
 665                         in-ports {
 666                                 #address-cells = <1>;
 667                                 #size-cells = <0>;
 668
 669                                 port@0 {
 670                                         reg = <0>;
 671                                         funnel1_in0: endpoint {
 672                                                 remote-endpoint = <&etm0_out>;
 673                                         };
 674                                 };
 675                                 port@1 {
 676                                         reg = <1>;
 677                                         funnel1_in1: endpoint {
 678                                                 remote-endpoint = <&etm1_out>;
 679                                         };
 680                                 };
 681                                 port@2 {
 682                                         reg = <2>;
 683                                         funnel1_in2: endpoint {
 684                                                 remote-endpoint = <&etm2_out>;
 685                                         };
 686                                 };
 687                                 port@3 {
 688                                         reg = <3>;
 689                                         funnel1_in3: endpoint {
 690                                                 remote-endpoint = <&etm3_out>;
 691                                         };
 692                                 };
 693                         };
 694
 695                         out-ports {
 696                                 port {
 697                                         funnel1_out: endpoint {
 698                                                 remote-endpoint = <&funnel0_in4>;
 699                                         };
 700                                 };
 701                         };
 702                 };
 703
 704                 debug0: debug@850000 {
 705                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 706                         reg = <0x00850000 0x1000>;
 707                         clocks = <&rpmcc RPM_QDSS_CLK>;
 708                         clock-names = "apb_pclk";
 709                         cpu = <&CPU0>;
 710                         status = "disabled";
 711                 };
 712
 713                 debug1: debug@852000 {
 714                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 715                         reg = <0x00852000 0x1000>;
 716                         clocks = <&rpmcc RPM_QDSS_CLK>;
 717                         clock-names = "apb_pclk";
 718                         cpu = <&CPU1>;
 719                         status = "disabled";
 720                 };
 721
 722                 debug2: debug@854000 {
 723                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 724                         reg = <0x00854000 0x1000>;
 725                         clocks = <&rpmcc RPM_QDSS_CLK>;
 726                         clock-names = "apb_pclk";
 727                         cpu = <&CPU2>;
 728                         status = "disabled";
 729                 };
 730
 731                 debug3: debug@856000 {
 732                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 733                         reg = <0x00856000 0x1000>;
 734                         clocks = <&rpmcc RPM_QDSS_CLK>;
 735                         clock-names = "apb_pclk";
 736                         cpu = <&CPU3>;
 737                         status = "disabled";
 738                 };
 739
 740                 /* Core CTIs; CTIs 12-15 */
 741                 /* CTI - CPU-0 */
 742                 cti12: cti@858000 {
 743                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 744                                      "arm,primecell";
 745                         reg = <0x00858000 0x1000>;
 746
 747                         clocks = <&rpmcc RPM_QDSS_CLK>;
 748                         clock-names = "apb_pclk";
 749
 750                         cpu = <&CPU0>;
 751                         arm,cs-dev-assoc = <&etm0>;
 752
 753                         status = "disabled";
 754                 };
 755
 756                 /* CTI - CPU-1 */
 757                 cti13: cti@859000 {
 758                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 759                                      "arm,primecell";
 760                         reg = <0x00859000 0x1000>;
 761
 762                         clocks = <&rpmcc RPM_QDSS_CLK>;
 763                         clock-names = "apb_pclk";
 764
 765                         cpu = <&CPU1>;
 766                         arm,cs-dev-assoc = <&etm1>;
 767
 768                         status = "disabled";
 769                 };
 770
 771                 /* CTI - CPU-2 */
 772                 cti14: cti@85a000 {
 773                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 774                                      "arm,primecell";
 775                         reg = <0x0085a000 0x1000>;
 776
 777                         clocks = <&rpmcc RPM_QDSS_CLK>;
 778                         clock-names = "apb_pclk";
 779
 780                         cpu = <&CPU2>;
 781                         arm,cs-dev-assoc = <&etm2>;
 782
 783                         status = "disabled";
 784                 };
 785
 786                 /* CTI - CPU-3 */
 787                 cti15: cti@85b000 {
 788                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 789                                      "arm,primecell";
 790                         reg = <0x0085b000 0x1000>;
 791
 792                         clocks = <&rpmcc RPM_QDSS_CLK>;
 793                         clock-names = "apb_pclk";
 794
 795                         cpu = <&CPU3>;
 796                         arm,cs-dev-assoc = <&etm3>;
 797
 798                         status = "disabled";
 799                 };
 800
 801                 etm0: etm@85c000 {
 802                         compatible = "arm,coresight-etm4x", "arm,primecell";
 803                         reg = <0x0085c000 0x1000>;
 804
 805                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 806                         clock-names = "apb_pclk", "atclk";
 807                         arm,coresight-loses-context-with-cpu;
 808
 809                         cpu = <&CPU0>;
 810
 811                         status = "disabled";
 812
 813                         out-ports {
 814                                 port {
 815                                         etm0_out: endpoint {
 816                                                 remote-endpoint = <&funnel1_in0>;
 817                                         };
 818                                 };
 819                         };
 820                 };
 821
 822                 etm1: etm@85d000 {
 823                         compatible = "arm,coresight-etm4x", "arm,primecell";
 824                         reg = <0x0085d000 0x1000>;
 825
 826                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 827                         clock-names = "apb_pclk", "atclk";
 828                         arm,coresight-loses-context-with-cpu;
 829
 830                         cpu = <&CPU1>;
 831
 832                         status = "disabled";
 833
 834                         out-ports {
 835                                 port {
 836                                         etm1_out: endpoint {
 837                                                 remote-endpoint = <&funnel1_in1>;
 838                                         };
 839                                 };
 840                         };
 841                 };
 842
 843                 etm2: etm@85e000 {
 844                         compatible = "arm,coresight-etm4x", "arm,primecell";
 845                         reg = <0x0085e000 0x1000>;
 846
 847                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 848                         clock-names = "apb_pclk", "atclk";
 849                         arm,coresight-loses-context-with-cpu;
 850
 851                         cpu = <&CPU2>;
 852
 853                         status = "disabled";
 854
 855                         out-ports {
 856                                 port {
 857                                         etm2_out: endpoint {
 858                                                 remote-endpoint = <&funnel1_in2>;
 859                                         };
 860                                 };
 861                         };
 862                 };
 863
 864                 etm3: etm@85f000 {
 865                         compatible = "arm,coresight-etm4x", "arm,primecell";
 866                         reg = <0x0085f000 0x1000>;
 867
 868                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 869                         clock-names = "apb_pclk", "atclk";
 870                         arm,coresight-loses-context-with-cpu;
 871
 872                         cpu = <&CPU3>;
 873
 874                         status = "disabled";
 875
 876                         out-ports {
 877                                 port {
 878                                         etm3_out: endpoint {
 879                                                 remote-endpoint = <&funnel1_in3>;
 880                                         };
 881                                 };
 882                         };
 883                 };
 884
 885                 msmgpio: pinctrl@1000000 {
 886                         compatible = "qcom,msm8916-pinctrl";
 887                         reg = <0x01000000 0x300000>;
 888                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 889                         gpio-controller;
 890                         gpio-ranges = <&msmgpio 0 0 122>;
 891                         #gpio-cells = <2>;
 892                         interrupt-controller;
 893                         #interrupt-cells = <2>;
 894                 };
 895
 896                 gcc: clock-controller@1800000 {
 897                         compatible = "qcom,gcc-msm8916";
 898                         #clock-cells = <1>;
 899                         #reset-cells = <1>;
 900                         #power-domain-cells = <1>;
 901                         reg = <0x01800000 0x80000>;
 902                 };
 903
 904                 tcsr_mutex: hwlock@1905000 {
 905                         compatible = "qcom,tcsr-mutex";
 906                         reg = <0x01905000 0x20000>;
 907                         #hwlock-cells = <1>;
 908                 };
 909
 910                 tcsr: syscon@1937000 {
 911                         compatible = "qcom,tcsr-msm8916", "syscon";
 912                         reg = <0x01937000 0x30000>;
 913                 };
 914
 915                 mdss: mdss@1a00000 {
 916                         status = "disabled";
 917                         compatible = "qcom,mdss";
 918                         reg = <0x01a00000 0x1000>,
 919                               <0x01ac8000 0x3000>;
 920                         reg-names = "mdss_phys", "vbif_phys";
 921
 922                         power-domains = <&gcc MDSS_GDSC>;
 923
 924                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 925                                  <&gcc GCC_MDSS_AXI_CLK>,
 926                                  <&gcc GCC_MDSS_VSYNC_CLK>;
 927                         clock-names = "iface",
 928                                       "bus",
 929                                       "vsync";
 930
 931                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 932
 933                         interrupt-controller;
 934                         #interrupt-cells = <1>;
 935
 936                         #address-cells = <1>;
 937                         #size-cells = <1>;
 938                         ranges;
 939
 940                         mdp: mdp@1a01000 {
 941                                 compatible = "qcom,mdp5";
 942                                 reg = <0x01a01000 0x89000>;
 943                                 reg-names = "mdp_phys";
 944
 945                                 interrupt-parent = <&mdss>;
 946                                 interrupts = <0>;
 947
 948                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 949                                          <&gcc GCC_MDSS_AXI_CLK>,
 950                                          <&gcc GCC_MDSS_MDP_CLK>,
 951                                          <&gcc GCC_MDSS_VSYNC_CLK>;
 952                                 clock-names = "iface",
 953                                               "bus",
 954                                               "core",
 955                                               "vsync";
 956
 957                                 iommus = <&apps_iommu 4>;
 958
 959                                 ports {
 960                                         #address-cells = <1>;
 961                                         #size-cells = <0>;
 962
 963                                         port@0 {
 964                                                 reg = <0>;
 965                                                 mdp5_intf1_out: endpoint {
 966                                                         remote-endpoint = <&dsi0_in>;
 967                                                 };
 968                                         };
 969                                 };
 970                         };
 971
 972                         dsi0: dsi@1a98000 {
 973                                 compatible = "qcom,mdss-dsi-ctrl";
 974                                 reg = <0x01a98000 0x25c>;
 975                                 reg-names = "dsi_ctrl";
 976
 977                                 interrupt-parent = <&mdss>;
 978                                 interrupts = <4>;
 979
 980                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
 981                                                   <&gcc PCLK0_CLK_SRC>;
 982                                 assigned-clock-parents = <&dsi_phy0 0>,
 983                                                          <&dsi_phy0 1>;
 984
 985                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 986                                          <&gcc GCC_MDSS_AHB_CLK>,
 987                                          <&gcc GCC_MDSS_AXI_CLK>,
 988                                          <&gcc GCC_MDSS_BYTE0_CLK>,
 989                                          <&gcc GCC_MDSS_PCLK0_CLK>,
 990                                          <&gcc GCC_MDSS_ESC0_CLK>;
 991                                 clock-names = "mdp_core",
 992                                               "iface",
 993                                               "bus",
 994                                               "byte",
 995                                               "pixel",
 996                                               "core";
 997                                 phys = <&dsi_phy0>;
 998                                 phy-names = "dsi-phy";
 999
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002
1003                                 ports {
1004                                         #address-cells = <1>;
1005                                         #size-cells = <0>;
1006
1007                                         port@0 {
1008                                                 reg = <0>;
1009                                                 dsi0_in: endpoint {
1010                                                         remote-endpoint = <&mdp5_intf1_out>;
1011                                                 };
1012                                         };
1013
1014                                         port@1 {
1015                                                 reg = <1>;
1016                                                 dsi0_out: endpoint {
1017                                                 };
1018                                         };
1019                                 };
1020                         };
1021
1022                         dsi_phy0: dsi-phy@1a98300 {
1023                                 compatible = "qcom,dsi-phy-28nm-lp";
1024                                 reg = <0x01a98300 0xd4>,
1025                                       <0x01a98500 0x280>,
1026                                       <0x01a98780 0x30>;
1027                                 reg-names = "dsi_pll",
1028                                             "dsi_phy",
1029                                             "dsi_phy_regulator";
1030
1031                                 #clock-cells = <1>;
1032                                 #phy-cells = <0>;
1033
1034                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1035                                          <&xo_board>;
1036                                 clock-names = "iface", "ref";
1037                         };
1038                 };
1039
1040                 camss: camss@1b00000 {
1041                         compatible = "qcom,msm8916-camss";
1042                         reg = <0x01b0ac00 0x200>,
1043                                 <0x01b00030 0x4>,
1044                                 <0x01b0b000 0x200>,
1045                                 <0x01b00038 0x4>,
1046                                 <0x01b08000 0x100>,
1047                                 <0x01b08400 0x100>,
1048                                 <0x01b0a000 0x500>,
1049                                 <0x01b00020 0x10>,
1050                                 <0x01b10000 0x1000>;
1051                         reg-names = "csiphy0",
1052                                 "csiphy0_clk_mux",
1053                                 "csiphy1",
1054                                 "csiphy1_clk_mux",
1055                                 "csid0",
1056                                 "csid1",
1057                                 "ispif",
1058                                 "csi_clk_mux",
1059                                 "vfe0";
1060                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1061                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1062                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1063                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1064                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1065                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1066                         interrupt-names = "csiphy0",
1067                                 "csiphy1",
1068                                 "csid0",
1069                                 "csid1",
1070                                 "ispif",
1071                                 "vfe0";
1072                         power-domains = <&gcc VFE_GDSC>;
1073                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1074                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1075                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1076                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1077                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1078                                 <&gcc GCC_CAMSS_CSI0_CLK>,
1079                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1080                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1081                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1082                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1083                                 <&gcc GCC_CAMSS_CSI1_CLK>,
1084                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1085                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1086                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1087                                 <&gcc GCC_CAMSS_AHB_CLK>,
1088                                 <&gcc GCC_CAMSS_VFE0_CLK>,
1089                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1090                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1091                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1092                         clock-names = "top_ahb",
1093                                 "ispif_ahb",
1094                                 "csiphy0_timer",
1095                                 "csiphy1_timer",
1096                                 "csi0_ahb",
1097                                 "csi0",
1098                                 "csi0_phy",
1099                                 "csi0_pix",
1100                                 "csi0_rdi",
1101                                 "csi1_ahb",
1102                                 "csi1",
1103                                 "csi1_phy",
1104                                 "csi1_pix",
1105                                 "csi1_rdi",
1106                                 "ahb",
1107                                 "vfe0",
1108                                 "csi_vfe0",
1109                                 "vfe_ahb",
1110                                 "vfe_axi";
1111                         iommus = <&apps_iommu 3>;
1112                         status = "disabled";
1113                         ports {
1114                                 #address-cells = <1>;
1115                                 #size-cells = <0>;
1116                         };
1117                 };
1118
1119                 cci: cci@1b0c000 {
1120                         compatible = "qcom,msm8916-cci";
1121                         #address-cells = <1>;
1122                         #size-cells = <0>;
1123                         reg = <0x01b0c000 0x1000>;
1124                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1125                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1126                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1127                                 <&gcc GCC_CAMSS_CCI_CLK>,
1128                                 <&gcc GCC_CAMSS_AHB_CLK>;
1129                         clock-names = "camss_top_ahb", "cci_ahb",
1130                                           "cci", "camss_ahb";
1131                         assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1132                                           <&gcc GCC_CAMSS_CCI_CLK>;
1133                         assigned-clock-rates = <80000000>, <19200000>;
1134                         pinctrl-names = "default";
1135                         pinctrl-0 = <&cci0_default>;
1136                         status = "disabled";
1137
1138                         cci_i2c0: i2c-bus@0 {
1139                                 reg = <0>;
1140                                 clock-frequency = <400000>;
1141                                 #address-cells = <1>;
1142                                 #size-cells = <0>;
1143                         };
1144                 };
1145
1146                 gpu@1c00000 {
1147                         compatible = "qcom,adreno-306.0", "qcom,adreno";
1148                         reg = <0x01c00000 0x20000>;
1149                         reg-names = "kgsl_3d0_reg_memory";
1150                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1151                         interrupt-names = "kgsl_3d0_irq";
1152                         clock-names =
1153                             "core",
1154                             "iface",
1155                             "mem",
1156                             "mem_iface",
1157                             "alt_mem_iface",
1158                             "gfx3d";
1159                         clocks =
1160                             <&gcc GCC_OXILI_GFX3D_CLK>,
1161                             <&gcc GCC_OXILI_AHB_CLK>,
1162                             <&gcc GCC_OXILI_GMEM_CLK>,
1163                             <&gcc GCC_BIMC_GFX_CLK>,
1164                             <&gcc GCC_BIMC_GPU_CLK>,
1165                             <&gcc GFX3D_CLK_SRC>;
1166                         power-domains = <&gcc OXILI_GDSC>;
1167                         operating-points-v2 = <&gpu_opp_table>;
1168                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1169
1170                         gpu_opp_table: opp-table {
1171                                 compatible = "operating-points-v2";
1172
1173                                 opp-400000000 {
1174                                         opp-hz = /bits/ 64 <400000000>;
1175                                 };
1176                                 opp-19200000 {
1177                                         opp-hz = /bits/ 64 <19200000>;
1178                                 };
1179                         };
1180                 };
1181
1182                 venus: video-codec@1d00000 {
1183                         compatible = "qcom,msm8916-venus";
1184                         reg = <0x01d00000 0xff000>;
1185                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1186                         power-domains = <&gcc VENUS_GDSC>;
1187                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1188                                  <&gcc GCC_VENUS0_AHB_CLK>,
1189                                  <&gcc GCC_VENUS0_AXI_CLK>;
1190                         clock-names = "core", "iface", "bus";
1191                         iommus = <&apps_iommu 5>;
1192                         memory-region = <&venus_mem>;
1193                         status = "okay";
1194
1195                         video-decoder {
1196                                 compatible = "venus-decoder";
1197                         };
1198
1199                         video-encoder {
1200                                 compatible = "venus-encoder";
1201                         };
1202                 };
1203
1204                 apps_iommu: iommu@1ef0000 {
1205                         #address-cells = <1>;
1206                         #size-cells = <1>;
1207                         #iommu-cells = <1>;
1208                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1209                         ranges = <0 0x01e20000 0x40000>;
1210                         reg = <0x01ef0000 0x3000>;
1211                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1212                                  <&gcc GCC_APSS_TCU_CLK>;
1213                         clock-names = "iface", "bus";
1214                         qcom,iommu-secure-id = <17>;
1215
1216                         // vfe:
1217                         iommu-ctx@3000 {
1218                                 compatible = "qcom,msm-iommu-v1-sec";
1219                                 reg = <0x3000 0x1000>;
1220                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1221                         };
1222
1223                         // mdp_0:
1224                         iommu-ctx@4000 {
1225                                 compatible = "qcom,msm-iommu-v1-ns";
1226                                 reg = <0x4000 0x1000>;
1227                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1228                         };
1229
1230                         // venus_ns:
1231                         iommu-ctx@5000 {
1232                                 compatible = "qcom,msm-iommu-v1-sec";
1233                                 reg = <0x5000 0x1000>;
1234                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1235                         };
1236                 };
1237
1238                 gpu_iommu: iommu@1f08000 {
1239                         #address-cells = <1>;
1240                         #size-cells = <1>;
1241                         #iommu-cells = <1>;
1242                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1243                         ranges = <0 0x01f08000 0x10000>;
1244                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1245                                  <&gcc GCC_GFX_TCU_CLK>;
1246                         clock-names = "iface", "bus";
1247                         qcom,iommu-secure-id = <18>;
1248
1249                         // gfx3d_user:
1250                         iommu-ctx@1000 {
1251                                 compatible = "qcom,msm-iommu-v1-ns";
1252                                 reg = <0x1000 0x1000>;
1253                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1254                         };
1255
1256                         // gfx3d_priv:
1257                         iommu-ctx@2000 {
1258                                 compatible = "qcom,msm-iommu-v1-ns";
1259                                 reg = <0x2000 0x1000>;
1260                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1261                         };
1262                 };
1263
1264                 spmi_bus: spmi@200f000 {
1265                         compatible = "qcom,spmi-pmic-arb";
1266                         reg = <0x0200f000 0x001000>,
1267                               <0x02400000 0x400000>,
1268                               <0x02c00000 0x400000>,
1269                               <0x03800000 0x200000>,
1270                               <0x0200a000 0x002100>;
1271                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1272                         interrupt-names = "periph_irq";
1273                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1274                         qcom,ee = <0>;
1275                         qcom,channel = <0>;
1276                         #address-cells = <2>;
1277                         #size-cells = <0>;
1278                         interrupt-controller;
1279                         #interrupt-cells = <4>;
1280                 };
1281
1282                 mpss: remoteproc@4080000 {
1283                         compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1284                         reg = <0x04080000 0x100>,
1285                               <0x04020000 0x040>;
1286
1287                         reg-names = "qdsp6", "rmb";
1288
1289                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1290                                               <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1291                                               <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1292                                               <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1293                                               <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1294                         interrupt-names = "wdog", "fatal", "ready",
1295                                           "handover", "stop-ack";
1296
1297                         power-domains = <&rpmpd MSM8916_VDDCX>,
1298                                         <&rpmpd MSM8916_VDDMX>;
1299                         power-domain-names = "cx", "mx";
1300
1301                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1302                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1303                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1304                                  <&xo_board>;
1305                         clock-names = "iface", "bus", "mem", "xo";
1306
1307                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1308                         qcom,smem-state-names = "stop";
1309
1310                         resets = <&scm 0>;
1311                         reset-names = "mss_restart";
1312
1313                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1314
1315                         status = "disabled";
1316
1317                         mba {
1318                                 memory-region = <&mba_mem>;
1319                         };
1320
1321                         mpss {
1322                                 memory-region = <&mpss_mem>;
1323                         };
1324
1325                         smd-edge {
1326                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1327
1328                                 qcom,smd-edge = <0>;
1329                                 qcom,ipc = <&apcs 8 12>;
1330                                 qcom,remote-pid = <1>;
1331
1332                                 label = "hexagon";
1333
1334                                 fastrpc {
1335                                         compatible = "qcom,fastrpc";
1336                                         qcom,smd-channels = "fastrpcsmd-apps-dsp";
1337                                         label = "adsp";
1338
1339                                         #address-cells = <1>;
1340                                         #size-cells = <0>;
1341
1342                                         cb@1 {
1343                                                 compatible = "qcom,fastrpc-compute-cb";
1344                                                 reg = <1>;
1345                                         };
1346                                 };
1347                         };
1348                 };
1349
1350                 sound: sound@7702000 {
1351                         status = "disabled";
1352                         compatible = "qcom,apq8016-sbc-sndcard";
1353                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
1354                         reg-names = "mic-iomux", "spkr-iomux";
1355                 };
1356
1357                 lpass: audio-controller@7708000 {
1358                         status = "disabled";
1359                         compatible = "qcom,lpass-cpu-apq8016";
1360                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1361                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1362                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1363                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1364                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1365                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1366                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1367
1368                         clock-names = "ahbix-clk",
1369                                         "pcnoc-mport-clk",
1370                                         "pcnoc-sway-clk",
1371                                         "mi2s-bit-clk0",
1372                                         "mi2s-bit-clk1",
1373                                         "mi2s-bit-clk2",
1374                                         "mi2s-bit-clk3";
1375                         #sound-dai-cells = <1>;
1376
1377                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1378                         interrupt-names = "lpass-irq-lpaif";
1379                         reg = <0x07708000 0x10000>;
1380                         reg-names = "lpass-lpaif";
1381
1382                         #address-cells = <1>;
1383                         #size-cells = <0>;
1384                 };
1385
1386                 lpass_codec: audio-codec@771c000 {
1387                         compatible = "qcom,msm8916-wcd-digital-codec";
1388                         reg = <0x0771c000 0x400>;
1389                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1390                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
1391                         clock-names = "ahbix-clk", "mclk";
1392                         #sound-dai-cells = <1>;
1393                 };
1394
1395                 sdhc_1: sdhci@7824000 {
1396                         compatible = "qcom,sdhci-msm-v4";
1397                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1398                         reg-names = "hc_mem", "core_mem";
1399
1400                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1401                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1402                         interrupt-names = "hc_irq", "pwr_irq";
1403                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1404                                  <&gcc GCC_SDCC1_AHB_CLK>,
1405                                  <&xo_board>;
1406                         clock-names = "core", "iface", "xo";
1407                         mmc-ddr-1_8v;
1408                         bus-width = <8>;
1409                         non-removable;
1410                         status = "disabled";
1411                 };
1412
1413                 sdhc_2: sdhci@7864000 {
1414                         compatible = "qcom,sdhci-msm-v4";
1415                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1416                         reg-names = "hc_mem", "core_mem";
1417
1418                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1419                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1420                         interrupt-names = "hc_irq", "pwr_irq";
1421                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1422                                  <&gcc GCC_SDCC2_AHB_CLK>,
1423                                  <&xo_board>;
1424                         clock-names = "core", "iface", "xo";
1425                         bus-width = <4>;
1426                         status = "disabled";
1427                 };
1428
1429                 blsp_dma: dma-controller@7884000 {
1430                         compatible = "qcom,bam-v1.7.0";
1431                         reg = <0x07884000 0x23000>;
1432                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1433                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1434                         clock-names = "bam_clk";
1435                         #dma-cells = <1>;
1436                         qcom,ee = <0>;
1437                         status = "disabled";
1438                 };
1439
1440                 blsp1_uart1: serial@78af000 {
1441                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1442                         reg = <0x078af000 0x200>;
1443                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1444                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1445                         clock-names = "core", "iface";
1446                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
1447                         dma-names = "rx", "tx";
1448                         pinctrl-names = "default", "sleep";
1449                         pinctrl-0 = <&blsp1_uart1_default>;
1450                         pinctrl-1 = <&blsp1_uart1_sleep>;
1451                         status = "disabled";
1452                 };
1453
1454                 blsp1_uart2: serial@78b0000 {
1455                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1456                         reg = <0x078b0000 0x200>;
1457                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1458                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1459                         clock-names = "core", "iface";
1460                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
1461                         dma-names = "rx", "tx";
1462                         pinctrl-names = "default", "sleep";
1463                         pinctrl-0 = <&blsp1_uart2_default>;
1464                         pinctrl-1 = <&blsp1_uart2_sleep>;
1465                         status = "disabled";
1466                 };
1467
1468                 blsp_i2c1: i2c@78b5000 {
1469                         compatible = "qcom,i2c-qup-v2.2.1";
1470                         reg = <0x078b5000 0x500>;
1471                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1472                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1473                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
1474                         clock-names = "iface", "core";
1475                         pinctrl-names = "default", "sleep";
1476                         pinctrl-0 = <&i2c1_default>;
1477                         pinctrl-1 = <&i2c1_sleep>;
1478                         #address-cells = <1>;
1479                         #size-cells = <0>;
1480                         status = "disabled";
1481                 };
1482
1483                 blsp_spi1: spi@78b5000 {
1484                         compatible = "qcom,spi-qup-v2.2.1";
1485                         reg = <0x078b5000 0x500>;
1486                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1487                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1488                                  <&gcc GCC_BLSP1_AHB_CLK>;
1489                         clock-names = "core", "iface";
1490                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
1491                         dma-names = "rx", "tx";
1492                         pinctrl-names = "default", "sleep";
1493                         pinctrl-0 = <&spi1_default>;
1494                         pinctrl-1 = <&spi1_sleep>;
1495                         #address-cells = <1>;
1496                         #size-cells = <0>;
1497                         status = "disabled";
1498                 };
1499
1500                 blsp_i2c2: i2c@78b6000 {
1501                         compatible = "qcom,i2c-qup-v2.2.1";
1502                         reg = <0x078b6000 0x500>;
1503                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1504                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1505                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
1506                         clock-names = "iface", "core";
1507                         pinctrl-names = "default", "sleep";
1508                         pinctrl-0 = <&i2c2_default>;
1509                         pinctrl-1 = <&i2c2_sleep>;
1510                         #address-cells = <1>;
1511                         #size-cells = <0>;
1512                         status = "disabled";
1513                 };
1514
1515                 blsp_spi2: spi@78b6000 {
1516                         compatible = "qcom,spi-qup-v2.2.1";
1517                         reg = <0x078b6000 0x500>;
1518                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1519                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1520                                  <&gcc GCC_BLSP1_AHB_CLK>;
1521                         clock-names = "core", "iface";
1522                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
1523                         dma-names = "rx", "tx";
1524                         pinctrl-names = "default", "sleep";
1525                         pinctrl-0 = <&spi2_default>;
1526                         pinctrl-1 = <&spi2_sleep>;
1527                         #address-cells = <1>;
1528                         #size-cells = <0>;
1529                         status = "disabled";
1530                 };
1531
1532                 blsp_i2c3: i2c@78b7000 {
1533                         compatible = "qcom,i2c-qup-v2.2.1";
1534                         reg = <0x078b7000 0x500>;
1535                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1536                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1537                                  <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1538                         clock-names = "iface", "core";
1539                         pinctrl-names = "default", "sleep";
1540                         pinctrl-0 = <&i2c3_default>;
1541                         pinctrl-1 = <&i2c3_sleep>;
1542                         #address-cells = <1>;
1543                         #size-cells = <0>;
1544                         status = "disabled";
1545                 };
1546
1547                 blsp_spi3: spi@78b7000 {
1548                         compatible = "qcom,spi-qup-v2.2.1";
1549                         reg = <0x078b7000 0x500>;
1550                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1551                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1552                                  <&gcc GCC_BLSP1_AHB_CLK>;
1553                         clock-names = "core", "iface";
1554                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
1555                         dma-names = "rx", "tx";
1556                         pinctrl-names = "default", "sleep";
1557                         pinctrl-0 = <&spi3_default>;
1558                         pinctrl-1 = <&spi3_sleep>;
1559                         #address-cells = <1>;
1560                         #size-cells = <0>;
1561                         status = "disabled";
1562                 };
1563
1564                 blsp_i2c4: i2c@78b8000 {
1565                         compatible = "qcom,i2c-qup-v2.2.1";
1566                         reg = <0x078b8000 0x500>;
1567                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1568                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1569                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1570                         clock-names = "iface", "core";
1571                         pinctrl-names = "default", "sleep";
1572                         pinctrl-0 = <&i2c4_default>;
1573                         pinctrl-1 = <&i2c4_sleep>;
1574                         #address-cells = <1>;
1575                         #size-cells = <0>;
1576                         status = "disabled";
1577                 };
1578
1579                 blsp_spi4: spi@78b8000 {
1580                         compatible = "qcom,spi-qup-v2.2.1";
1581                         reg = <0x078b8000 0x500>;
1582                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1583                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1584                                  <&gcc GCC_BLSP1_AHB_CLK>;
1585                         clock-names = "core", "iface";
1586                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
1587                         dma-names = "rx", "tx";
1588                         pinctrl-names = "default", "sleep";
1589                         pinctrl-0 = <&spi4_default>;
1590                         pinctrl-1 = <&spi4_sleep>;
1591                         #address-cells = <1>;
1592                         #size-cells = <0>;
1593                         status = "disabled";
1594                 };
1595
1596                 blsp_i2c5: i2c@78b9000 {
1597                         compatible = "qcom,i2c-qup-v2.2.1";
1598                         reg = <0x078b9000 0x500>;
1599                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1600                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1601                                  <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
1602                         clock-names = "iface", "core";
1603                         pinctrl-names = "default", "sleep";
1604                         pinctrl-0 = <&i2c5_default>;
1605                         pinctrl-1 = <&i2c5_sleep>;
1606                         #address-cells = <1>;
1607                         #size-cells = <0>;
1608                         status = "disabled";
1609                 };
1610
1611                 blsp_spi5: spi@78b9000 {
1612                         compatible = "qcom,spi-qup-v2.2.1";
1613                         reg = <0x078b9000 0x500>;
1614                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1615                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1616                                  <&gcc GCC_BLSP1_AHB_CLK>;
1617                         clock-names = "core", "iface";
1618                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
1619                         dma-names = "rx", "tx";
1620                         pinctrl-names = "default", "sleep";
1621                         pinctrl-0 = <&spi5_default>;
1622                         pinctrl-1 = <&spi5_sleep>;
1623                         #address-cells = <1>;
1624                         #size-cells = <0>;
1625                         status = "disabled";
1626                 };
1627
1628                 blsp_i2c6: i2c@78ba000 {
1629                         compatible = "qcom,i2c-qup-v2.2.1";
1630                         reg = <0x078ba000 0x500>;
1631                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1632                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1633                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
1634                         clock-names = "iface", "core";
1635                         pinctrl-names = "default", "sleep";
1636                         pinctrl-0 = <&i2c6_default>;
1637                         pinctrl-1 = <&i2c6_sleep>;
1638                         #address-cells = <1>;
1639                         #size-cells = <0>;
1640                         status = "disabled";
1641                 };
1642
1643                 blsp_spi6: spi@78ba000 {
1644                         compatible = "qcom,spi-qup-v2.2.1";
1645                         reg = <0x078ba000 0x500>;
1646                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1647                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1648                                  <&gcc GCC_BLSP1_AHB_CLK>;
1649                         clock-names = "core", "iface";
1650                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
1651                         dma-names = "rx", "tx";
1652                         pinctrl-names = "default", "sleep";
1653                         pinctrl-0 = <&spi6_default>;
1654                         pinctrl-1 = <&spi6_sleep>;
1655                         #address-cells = <1>;
1656                         #size-cells = <0>;
1657                         status = "disabled";
1658                 };
1659
1660                 usb: usb@78d9000 {
1661                         compatible = "qcom,ci-hdrc";
1662                         reg = <0x078d9000 0x200>,
1663                               <0x078d9200 0x200>;
1664                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1665                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1666                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1667                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
1668                         clock-names = "iface", "core";
1669                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1670                         assigned-clock-rates = <80000000>;
1671                         resets = <&gcc GCC_USB_HS_BCR>;
1672                         reset-names = "core";
1673                         phy_type = "ulpi";
1674                         dr_mode = "otg";
1675                         hnp-disable;
1676                         srp-disable;
1677                         adp-disable;
1678                         ahb-burst-config = <0>;
1679                         phy-names = "usb-phy";
1680                         phys = <&usb_hs_phy>;
1681                         status = "disabled";
1682                         #reset-cells = <1>;
1683
1684                         ulpi {
1685                                 usb_hs_phy: phy {
1686                                         compatible = "qcom,usb-hs-phy-msm8916",
1687                                                      "qcom,usb-hs-phy";
1688                                         #phy-cells = <0>;
1689                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1690                                         clock-names = "ref", "sleep";
1691                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1692                                         reset-names = "phy", "por";
1693                                         qcom,init-seq = /bits/ 8 <0x0 0x44
1694                                                 0x1 0x6b 0x2 0x24 0x3 0x13>;
1695                                 };
1696                         };
1697                 };
1698
1699                 pronto: remoteproc@a21b000 {
1700                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1701                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1702                         reg-names = "ccu", "dxe", "pmu";
1703
1704                         memory-region = <&wcnss_mem>;
1705
1706                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1707                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1708                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1709                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1710                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1711                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1712
1713                         power-domains = <&rpmpd MSM8916_VDDCX>,
1714                                         <&rpmpd MSM8916_VDDMX>;
1715                         power-domain-names = "cx", "mx";
1716
1717                         qcom,state = <&wcnss_smp2p_out 0>;
1718                         qcom,state-names = "stop";
1719
1720                         pinctrl-names = "default";
1721                         pinctrl-0 = <&wcnss_pin_a>;
1722
1723                         status = "disabled";
1724
1725                         iris {
1726                                 compatible = "qcom,wcn3620";
1727
1728                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1729                                 clock-names = "xo";
1730                         };
1731
1732                         smd-edge {
1733                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1734
1735                                 qcom,ipc = <&apcs 8 17>;
1736                                 qcom,smd-edge = <6>;
1737                                 qcom,remote-pid = <4>;
1738
1739                                 label = "pronto";
1740
1741                                 wcnss {
1742                                         compatible = "qcom,wcnss";
1743                                         qcom,smd-channels = "WCNSS_CTRL";
1744
1745                                         qcom,mmio = <&pronto>;
1746
1747                                         bt {
1748                                                 compatible = "qcom,wcnss-bt";
1749                                         };
1750
1751                                         wifi {
1752                                                 compatible = "qcom,wcnss-wlan";
1753
1754                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1755                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1756                                                 interrupt-names = "tx", "rx";
1757
1758                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1759                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1760                                         };
1761                                 };
1762                         };
1763                 };
1764
1765                 intc: interrupt-controller@b000000 {
1766                         compatible = "qcom,msm-qgic2";
1767                         interrupt-controller;
1768                         #interrupt-cells = <3>;
1769                         reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1770                               <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1771                         interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1772                 };
1773
1774                 apcs: mailbox@b011000 {
1775                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1776                         reg = <0x0b011000 0x1000>;
1777                         #mbox-cells = <1>;
1778                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1779                         clock-names = "pll", "aux";
1780                         #clock-cells = <0>;
1781                 };
1782
1783                 a53pll: clock@b016000 {
1784                         compatible = "qcom,msm8916-a53pll";
1785                         reg = <0x0b016000 0x40>;
1786                         #clock-cells = <0>;
1787                 };
1788
1789                 timer@b020000 {
1790                         #address-cells = <1>;
1791                         #size-cells = <1>;
1792                         ranges;
1793                         compatible = "arm,armv7-timer-mem";
1794                         reg = <0x0b020000 0x1000>;
1795                         clock-frequency = <19200000>;
1796
1797                         frame@b021000 {
1798                                 frame-number = <0>;
1799                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1800                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1801                                 reg = <0x0b021000 0x1000>,
1802                                       <0x0b022000 0x1000>;
1803                         };
1804
1805                         frame@b023000 {
1806                                 frame-number = <1>;
1807                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1808                                 reg = <0x0b023000 0x1000>;
1809                                 status = "disabled";
1810                         };
1811
1812                         frame@b024000 {
1813                                 frame-number = <2>;
1814                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1815                                 reg = <0x0b024000 0x1000>;
1816                                 status = "disabled";
1817                         };
1818
1819                         frame@b025000 {
1820                                 frame-number = <3>;
1821                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1822                                 reg = <0x0b025000 0x1000>;
1823                                 status = "disabled";
1824                         };
1825
1826                         frame@b026000 {
1827                                 frame-number = <4>;
1828                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1829                                 reg = <0x0b026000 0x1000>;
1830                                 status = "disabled";
1831                         };
1832
1833                         frame@b027000 {
1834                                 frame-number = <5>;
1835                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1836                                 reg = <0x0b027000 0x1000>;
1837                                 status = "disabled";
1838                         };
1839
1840                         frame@b028000 {
1841                                 frame-number = <6>;
1842                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1843                                 reg = <0x0b028000 0x1000>;
1844                                 status = "disabled";
1845                         };
1846                 };
1847         };
1848
1849         thermal-zones {
1850                 cpu0-1-thermal {
1851                         polling-delay-passive = <250>;
1852                         polling-delay = <1000>;
1853
1854                         thermal-sensors = <&tsens 5>;
1855
1856                         trips {
1857                                 cpu0_1_alert0: trip-point0 {
1858                                         temperature = <75000>;
1859                                         hysteresis = <2000>;
1860                                         type = "passive";
1861                                 };
1862                                 cpu0_1_crit: cpu_crit {
1863                                         temperature = <110000>;
1864                                         hysteresis = <2000>;
1865                                         type = "critical";
1866                                 };
1867                         };
1868
1869                         cooling-maps {
1870                                 map0 {
1871                                         trip = <&cpu0_1_alert0>;
1872                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1873                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1874                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1875                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1876                                 };
1877                         };
1878                 };
1879
1880                 cpu2-3-thermal {
1881                         polling-delay-passive = <250>;
1882                         polling-delay = <1000>;
1883
1884                         thermal-sensors = <&tsens 4>;
1885
1886                         trips {
1887                                 cpu2_3_alert0: trip-point0 {
1888                                         temperature = <75000>;
1889                                         hysteresis = <2000>;
1890                                         type = "passive";
1891                                 };
1892                                 cpu2_3_crit: cpu_crit {
1893                                         temperature = <110000>;
1894                                         hysteresis = <2000>;
1895                                         type = "critical";
1896                                 };
1897                         };
1898
1899                         cooling-maps {
1900                                 map0 {
1901                                         trip = <&cpu2_3_alert0>;
1902                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1903                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1904                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1905                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1906                                 };
1907                         };
1908                 };
1909
1910                 gpu-thermal {
1911                         polling-delay-passive = <250>;
1912                         polling-delay = <1000>;
1913
1914                         thermal-sensors = <&tsens 2>;
1915
1916                         trips {
1917                                 gpu_alert0: trip-point0 {
1918                                         temperature = <75000>;
1919                                         hysteresis = <2000>;
1920                                         type = "passive";
1921                                 };
1922                                 gpu_crit: gpu_crit {
1923                                         temperature = <95000>;
1924                                         hysteresis = <2000>;
1925                                         type = "critical";
1926                                 };
1927                         };
1928                 };
1929
1930                 camera-thermal {
1931                         polling-delay-passive = <250>;
1932                         polling-delay = <1000>;
1933
1934                         thermal-sensors = <&tsens 1>;
1935
1936                         trips {
1937                                 cam_alert0: trip-point0 {
1938                                         temperature = <75000>;
1939                                         hysteresis = <2000>;
1940                                         type = "hot";
1941                                 };
1942                         };
1943                 };
1944
1945                 modem-thermal {
1946                         polling-delay-passive = <250>;
1947                         polling-delay = <1000>;
1948
1949                         thermal-sensors = <&tsens 0>;
1950
1951                         trips {
1952                                 modem_alert0: trip-point0 {
1953                                         temperature = <85000>;
1954                                         hysteresis = <2000>;
1955                                         type = "hot";
1956                                 };
1957                         };
1958                 };
1959
1960         };
1961
1962         timer {
1963                 compatible = "arm,armv8-timer";
1964                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1965                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1966                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1967                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1968         };
1969 };
1970
1971 #include "msm8916-pins.dtsi"