arch/arm64/boot/dts/nvidia/tegra234.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <dt-bindings/clock/tegra234-clock.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/reset/tegra234-reset.h>
   7
   8 / {
   9         compatible = "nvidia,tegra234";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         bus@0 {
  15                 compatible = "simple-bus";
  16                 #address-cells = <1>;
  17                 #size-cells = <1>;
  18
  19                 ranges = <0x0 0x0 0x0 0x40000000>;
  20
  21                 misc@100000 {
  22                         compatible = "nvidia,tegra234-misc";
  23                         reg = <0x00100000 0xf000>,
  24                               <0x0010f000 0x1000>;
  25                         status = "okay";
  26                 };
  27
  28                 uarta: serial@3100000 {
  29                         compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
  30                         reg = <0x03100000 0x10000>;
  31                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  32                         clocks = <&bpmp TEGRA234_CLK_UARTA>;
  33                         clock-names = "serial";
  34                         resets = <&bpmp TEGRA234_RESET_UARTA>;
  35                         reset-names = "serial";
  36                         status = "disabled";
  37                 };
  38
  39                 mmc@3460000 {
  40                         compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
  41                         reg = <0x03460000 0x20000>;
  42                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  43                         clocks = <&bpmp TEGRA234_CLK_SDMMC4>;
  44                         clock-names = "sdhci";
  45                         resets = <&bpmp TEGRA234_RESET_SDMMC4>;
  46                         reset-names = "sdhci";
  47                         dma-coherent;
  48                         status = "disabled";
  49                 };
  50
  51                 fuse@3810000 {
  52                         compatible = "nvidia,tegra234-efuse";
  53                         reg = <0x03810000 0x10000>;
  54                         clocks = <&bpmp TEGRA234_CLK_FUSE>;
  55                         clock-names = "fuse";
  56                 };
  57
  58                 hsp_top0: hsp@3c00000 {
  59                         compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
  60                         reg = <0x03c00000 0xa0000>;
  61                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
  62                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  63                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  64                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  65                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  66                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  67                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  70                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
  71                                           "shared3", "shared4", "shared5", "shared6",
  72                                           "shared7";
  73                         #mbox-cells = <2>;
  74                 };
  75
  76                 hsp_aon: hsp@c150000 {
  77                         compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
  78                         reg = <0x0c150000 0x90000>;
  79                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
  83                         /*
  84                          * Shared interrupt 0 is routed only to AON/SPE, so
  85                          * we only have 4 shared interrupts for the CCPLEX.
  86                          */
  87                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
  88                         #mbox-cells = <2>;
  89                 };
  90
  91                 rtc@c2a0000 {
  92                         compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
  93                         reg = <0x0c2a0000 0x10000>;
  94                         interrupt-parent = <&pmc>;
  95                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
  96                         status = "disabled";
  97                 };
  98
  99                 pmc: pmc@c360000 {
 100                         compatible = "nvidia,tegra234-pmc";
 101                         reg = <0x0c360000 0x10000>,
 102                               <0x0c370000 0x10000>,
 103                               <0x0c380000 0x10000>,
 104                               <0x0c390000 0x10000>,
 105                               <0x0c3a0000 0x10000>;
 106                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
 107
 108                         #interrupt-cells = <2>;
 109                         interrupt-controller;
 110                 };
 111
 112                 gic: interrupt-controller@f400000 {
 113                         compatible = "arm,gic-v3";
 114                         reg = <0x0f400000 0x010000>, /* GICD */
 115                               <0x0f440000 0x200000>; /* GICR */
 116                         interrupt-parent = <&gic>;
 117                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 118
 119                         #redistributor-regions = <1>;
 120                         #interrupt-cells = <3>;
 121                         interrupt-controller;
 122                 };
 123         };
 124
 125         sysram@40000000 {
 126                 compatible = "nvidia,tegra234-sysram", "mmio-sram";
 127                 reg = <0x0 0x40000000 0x0 0x50000>;
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 ranges = <0x0 0x0 0x40000000 0x50000>;
 131
 132                 cpu_bpmp_tx: shmem@4e000 {
 133                         reg = <0x4e000 0x1000>;
 134                         label = "cpu-bpmp-tx";
 135                         pool;
 136                 };
 137
 138                 cpu_bpmp_rx: shmem@4f000 {
 139                         reg = <0x4f000 0x1000>;
 140                         label = "cpu-bpmp-rx";
 141                         pool;
 142                 };
 143         };
 144
 145         bpmp: bpmp {
 146                 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
 147                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
 148                                     TEGRA_HSP_DB_MASTER_BPMP>;
 149                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
 150                 #clock-cells = <1>;
 151                 #reset-cells = <1>;
 152                 #power-domain-cells = <1>;
 153
 154                 bpmp_i2c: i2c {
 155                         compatible = "nvidia,tegra186-bpmp-i2c";
 156                         nvidia,bpmp-bus-id = <5>;
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                 };
 160         };
 161
 162         cpus {
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165
 166                 cpu@0 {
 167                         device_type = "cpu";
 168                         reg = <0x000>;
 169
 170                         enable-method = "psci";
 171                 };
 172         };
 173
 174         psci {
 175                 compatible = "arm,psci-1.0";
 176                 status = "okay";
 177                 method = "smc";
 178         };
 179
 180         timer {
 181                 compatible = "arm,armv8-timer";
 182                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 183                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 184                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 185                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 186                 interrupt-parent = <&gic>;
 187                 always-on;
 188         };
 189 };