arch/arm64/boot/dts/nvidia/tegra210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra210-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra210-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   7 #include <dt-bindings/reset/tegra210-car.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/thermal/tegra124-soctherm.h>
  10 #include <dt-bindings/soc/tegra-pmc.h>
  11
  12 / {
  13         compatible = "nvidia,tegra210";
  14         interrupt-parent = <&lic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         pcie@1003000 {
  19                 compatible = "nvidia,tegra210-pcie";
  20                 device_type = "pci";
  21                 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
  22                       <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
  23                       <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  24                 reg-names = "pads", "afi", "cs";
  25                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  26                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  27                 interrupt-names = "intr", "msi";
  28
  29                 #interrupt-cells = <1>;
  30                 interrupt-map-mask = <0 0 0 0>;
  31                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  32
  33                 bus-range = <0x00 0xff>;
  34                 #address-cells = <3>;
  35                 #size-cells = <2>;
  36
  37                 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
  38                          <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
  39                          <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
  40                          <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
  41                          <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  42
  43                 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
  44                          <&tegra_car TEGRA210_CLK_AFI>,
  45                          <&tegra_car TEGRA210_CLK_PLL_E>,
  46                          <&tegra_car TEGRA210_CLK_CML0>;
  47                 clock-names = "pex", "afi", "pll_e", "cml";
  48                 resets = <&tegra_car 70>,
  49                          <&tegra_car 72>,
  50                          <&tegra_car 74>;
  51                 reset-names = "pex", "afi", "pcie_x";
  52
  53                 pinctrl-names = "default", "idle";
  54                 pinctrl-0 = <&pex_dpd_disable>;
  55                 pinctrl-1 = <&pex_dpd_enable>;
  56
  57                 status = "disabled";
  58
  59                 pci@1,0 {
  60                         device_type = "pci";
  61                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  62                         reg = <0x000800 0 0 0 0>;
  63                         bus-range = <0x00 0xff>;
  64                         status = "disabled";
  65
  66                         #address-cells = <3>;
  67                         #size-cells = <2>;
  68                         ranges;
  69
  70                         nvidia,num-lanes = <4>;
  71                 };
  72
  73                 pci@2,0 {
  74                         device_type = "pci";
  75                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  76                         reg = <0x001000 0 0 0 0>;
  77                         bus-range = <0x00 0xff>;
  78                         status = "disabled";
  79
  80                         #address-cells = <3>;
  81                         #size-cells = <2>;
  82                         ranges;
  83
  84                         nvidia,num-lanes = <1>;
  85                 };
  86         };
  87
  88         host1x@50000000 {
  89                 compatible = "nvidia,tegra210-host1x";
  90                 reg = <0x0 0x50000000 0x0 0x00034000>;
  91                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  92                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  93                 interrupt-names = "syncpt", "host1x";
  94                 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
  95                 clock-names = "host1x";
  96                 resets = <&tegra_car 28>;
  97                 reset-names = "host1x";
  98
  99                 #address-cells = <2>;
 100                 #size-cells = <2>;
 101
 102                 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
 103
 104                 iommus = <&mc TEGRA_SWGROUP_HC>;
 105
 106                 dpaux1: dpaux@54040000 {
 107                         compatible = "nvidia,tegra210-dpaux";
 108                         reg = <0x0 0x54040000 0x0 0x00040000>;
 109                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 110                         clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
 111                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 112                         clock-names = "dpaux", "parent";
 113                         resets = <&tegra_car 207>;
 114                         reset-names = "dpaux";
 115                         power-domains = <&pd_sor>;
 116                         status = "disabled";
 117
 118                         state_dpaux1_aux: pinmux-aux {
 119                                 groups = "dpaux-io";
 120                                 function = "aux";
 121                         };
 122
 123                         state_dpaux1_i2c: pinmux-i2c {
 124                                 groups = "dpaux-io";
 125                                 function = "i2c";
 126                         };
 127
 128                         state_dpaux1_off: pinmux-off {
 129                                 groups = "dpaux-io";
 130                                 function = "off";
 131                         };
 132
 133                         i2c-bus {
 134                                 #address-cells = <1>;
 135                                 #size-cells = <0>;
 136                         };
 137                 };
 138
 139                 vi@54080000 {
 140                         compatible = "nvidia,tegra210-vi";
 141                         reg = <0x0 0x54080000 0x0 0x700>;
 142                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 143                         status = "disabled";
 144                         assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
 145                         assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
 146
 147                         clocks = <&tegra_car TEGRA210_CLK_VI>;
 148                         power-domains = <&pd_venc>;
 149
 150                         #address-cells = <1>;
 151                         #size-cells = <1>;
 152
 153                         ranges = <0x0 0x0 0x54080000 0x2000>;
 154
 155                         csi@838 {
 156                                 compatible = "nvidia,tegra210-csi";
 157                                 reg = <0x838 0x1300>;
 158                                 status = "disabled";
 159                                 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
 160                                                   <&tegra_car TEGRA210_CLK_CILCD>,
 161                                                   <&tegra_car TEGRA210_CLK_CILE>,
 162                                                   <&tegra_car TEGRA210_CLK_CSI_TPG>;
 163                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
 164                                                          <&tegra_car TEGRA210_CLK_PLL_P>,
 165                                                          <&tegra_car TEGRA210_CLK_PLL_P>;
 166                                 assigned-clock-rates = <102000000>,
 167                                                        <102000000>,
 168                                                        <102000000>,
 169                                                        <972000000>;
 170
 171                                 clocks = <&tegra_car TEGRA210_CLK_CSI>,
 172                                          <&tegra_car TEGRA210_CLK_CILAB>,
 173                                          <&tegra_car TEGRA210_CLK_CILCD>,
 174                                          <&tegra_car TEGRA210_CLK_CILE>,
 175                                          <&tegra_car TEGRA210_CLK_CSI_TPG>;
 176                                 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
 177                                 power-domains = <&pd_sor>;
 178                         };
 179                 };
 180
 181                 tsec@54100000 {
 182                         compatible = "nvidia,tegra210-tsec";
 183                         reg = <0x0 0x54100000 0x0 0x00040000>;
 184                 };
 185
 186                 dc@54200000 {
 187                         compatible = "nvidia,tegra210-dc";
 188                         reg = <0x0 0x54200000 0x0 0x00040000>;
 189                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 190                         clocks = <&tegra_car TEGRA210_CLK_DISP1>;
 191                         clock-names = "dc";
 192                         resets = <&tegra_car 27>;
 193                         reset-names = "dc";
 194
 195                         iommus = <&mc TEGRA_SWGROUP_DC>;
 196
 197                         nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 198                         nvidia,head = <0>;
 199                 };
 200
 201                 dc@54240000 {
 202                         compatible = "nvidia,tegra210-dc";
 203                         reg = <0x0 0x54240000 0x0 0x00040000>;
 204                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 205                         clocks = <&tegra_car TEGRA210_CLK_DISP2>;
 206                         clock-names = "dc";
 207                         resets = <&tegra_car 26>;
 208                         reset-names = "dc";
 209
 210                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 211
 212                         nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 213                         nvidia,head = <1>;
 214                 };
 215
 216                 dsia: dsi@54300000 {
 217                         compatible = "nvidia,tegra210-dsi";
 218                         reg = <0x0 0x54300000 0x0 0x00040000>;
 219                         clocks = <&tegra_car TEGRA210_CLK_DSIA>,
 220                                  <&tegra_car TEGRA210_CLK_DSIALP>,
 221                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 222                         clock-names = "dsi", "lp", "parent";
 223                         resets = <&tegra_car 48>;
 224                         reset-names = "dsi";
 225                         power-domains = <&pd_sor>;
 226                         nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
 227
 228                         status = "disabled";
 229
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                 };
 233
 234                 vic@54340000 {
 235                         compatible = "nvidia,tegra210-vic";
 236                         reg = <0x0 0x54340000 0x0 0x00040000>;
 237                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 239                         clock-names = "vic";
 240                         resets = <&tegra_car 178>;
 241                         reset-names = "vic";
 242
 243                         iommus = <&mc TEGRA_SWGROUP_VIC>;
 244                         power-domains = <&pd_vic>;
 245                 };
 246
 247                 nvjpg@54380000 {
 248                         compatible = "nvidia,tegra210-nvjpg";
 249                         reg = <0x0 0x54380000 0x0 0x00040000>;
 250                         status = "disabled";
 251                 };
 252
 253                 dsib: dsi@54400000 {
 254                         compatible = "nvidia,tegra210-dsi";
 255                         reg = <0x0 0x54400000 0x0 0x00040000>;
 256                         clocks = <&tegra_car TEGRA210_CLK_DSIB>,
 257                                  <&tegra_car TEGRA210_CLK_DSIBLP>,
 258                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 259                         clock-names = "dsi", "lp", "parent";
 260                         resets = <&tegra_car 82>;
 261                         reset-names = "dsi";
 262                         power-domains = <&pd_sor>;
 263                         nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
 264
 265                         status = "disabled";
 266
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                 };
 270
 271                 nvdec@54480000 {
 272                         compatible = "nvidia,tegra210-nvdec";
 273                         reg = <0x0 0x54480000 0x0 0x00040000>;
 274                         status = "disabled";
 275                 };
 276
 277                 nvenc@544c0000 {
 278                         compatible = "nvidia,tegra210-nvenc";
 279                         reg = <0x0 0x544c0000 0x0 0x00040000>;
 280                         status = "disabled";
 281                 };
 282
 283                 tsec@54500000 {
 284                         compatible = "nvidia,tegra210-tsec";
 285                         reg = <0x0 0x54500000 0x0 0x00040000>;
 286                         status = "disabled";
 287                 };
 288
 289                 sor0: sor@54540000 {
 290                         compatible = "nvidia,tegra210-sor";
 291                         reg = <0x0 0x54540000 0x0 0x00040000>;
 292                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 294                                  <&tegra_car TEGRA210_CLK_SOR0_OUT>,
 295                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
 296                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 297                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 298                         clock-names = "sor", "out", "parent", "dp", "safe";
 299                         resets = <&tegra_car 182>;
 300                         reset-names = "sor";
 301                         pinctrl-0 = <&state_dpaux_aux>;
 302                         pinctrl-1 = <&state_dpaux_i2c>;
 303                         pinctrl-2 = <&state_dpaux_off>;
 304                         pinctrl-names = "aux", "i2c", "off";
 305                         power-domains = <&pd_sor>;
 306                         status = "disabled";
 307                 };
 308
 309                 sor1: sor@54580000 {
 310                         compatible = "nvidia,tegra210-sor1";
 311                         reg = <0x0 0x54580000 0x0 0x00040000>;
 312                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&tegra_car TEGRA210_CLK_SOR1>,
 314                                  <&tegra_car TEGRA210_CLK_SOR1_OUT>,
 315                                  <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
 316                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 317                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 318                         clock-names = "sor", "out", "parent", "dp", "safe";
 319                         resets = <&tegra_car 183>;
 320                         reset-names = "sor";
 321                         pinctrl-0 = <&state_dpaux1_aux>;
 322                         pinctrl-1 = <&state_dpaux1_i2c>;
 323                         pinctrl-2 = <&state_dpaux1_off>;
 324                         pinctrl-names = "aux", "i2c", "off";
 325                         power-domains = <&pd_sor>;
 326                         status = "disabled";
 327                 };
 328
 329                 dpaux: dpaux@545c0000 {
 330                         compatible = "nvidia,tegra210-dpaux";
 331                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 332                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
 334                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 335                         clock-names = "dpaux", "parent";
 336                         resets = <&tegra_car 181>;
 337                         reset-names = "dpaux";
 338                         power-domains = <&pd_sor>;
 339                         status = "disabled";
 340
 341                         state_dpaux_aux: pinmux-aux {
 342                                 groups = "dpaux-io";
 343                                 function = "aux";
 344                         };
 345
 346                         state_dpaux_i2c: pinmux-i2c {
 347                                 groups = "dpaux-io";
 348                                 function = "i2c";
 349                         };
 350
 351                         state_dpaux_off: pinmux-off {
 352                                 groups = "dpaux-io";
 353                                 function = "off";
 354                         };
 355
 356                         i2c-bus {
 357                                 #address-cells = <1>;
 358                                 #size-cells = <0>;
 359                         };
 360                 };
 361
 362                 isp@54600000 {
 363                         compatible = "nvidia,tegra210-isp";
 364                         reg = <0x0 0x54600000 0x0 0x00040000>;
 365                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&tegra_car TEGRA210_CLK_ISPA>;
 367                         resets = <&tegra_car 23>;
 368                         reset-names = "isp";
 369                         status = "disabled";
 370                 };
 371
 372                 isp@54680000 {
 373                         compatible = "nvidia,tegra210-isp";
 374                         reg = <0x0 0x54680000 0x0 0x00040000>;
 375                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 376                         clocks = <&tegra_car TEGRA210_CLK_ISPB>;
 377                         resets = <&tegra_car 3>;
 378                         reset-names = "isp";
 379                         status = "disabled";
 380                 };
 381
 382                 i2c@546c0000 {
 383                         compatible = "nvidia,tegra210-i2c-vi";
 384                         reg = <0x0 0x546c0000 0x0 0x00040000>;
 385                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
 387                                  <&tegra_car TEGRA210_CLK_I2CSLOW>;
 388                         clock-names = "div-clk", "slow";
 389                         resets = <&tegra_car 208>;
 390                         reset-names = "i2c";
 391                         power-domains = <&pd_venc>;
 392                         status = "disabled";
 393
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                 };
 397         };
 398
 399         gic: interrupt-controller@50041000 {
 400                 compatible = "arm,gic-400";
 401                 #interrupt-cells = <3>;
 402                 interrupt-controller;
 403                 reg = <0x0 0x50041000 0x0 0x1000>,
 404                       <0x0 0x50042000 0x0 0x2000>,
 405                       <0x0 0x50044000 0x0 0x2000>,
 406                       <0x0 0x50046000 0x0 0x2000>;
 407                 interrupts = <GIC_PPI 9
 408                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 409                 interrupt-parent = <&gic>;
 410         };
 411
 412         gpu@57000000 {
 413                 compatible = "nvidia,gm20b";
 414                 reg = <0x0 0x57000000 0x0 0x01000000>,
 415                       <0x0 0x58000000 0x0 0x01000000>;
 416                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 417                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 418                 interrupt-names = "stall", "nonstall";
 419                 clocks = <&tegra_car TEGRA210_CLK_GPU>,
 420                          <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
 421                          <&tegra_car TEGRA210_CLK_PLL_G_REF>;
 422                 clock-names = "gpu", "pwr", "ref";
 423                 resets = <&tegra_car 184>;
 424                 reset-names = "gpu";
 425
 426                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 427
 428                 status = "disabled";
 429         };
 430
 431         lic: interrupt-controller@60004000 {
 432                 compatible = "nvidia,tegra210-ictlr";
 433                 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
 434                       <0x0 0x60004100 0x0 0x40>, /* secondary controller */
 435                       <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
 436                       <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
 437                       <0x0 0x60004400 0x0 0x40>, /* quinary controller */
 438                       <0x0 0x60004500 0x0 0x40>; /* senary controller */
 439                 interrupt-controller;
 440                 #interrupt-cells = <3>;
 441                 interrupt-parent = <&gic>;
 442         };
 443
 444         timer@60005000 {
 445                 compatible = "nvidia,tegra210-timer";
 446                 reg = <0x0 0x60005000 0x0 0x400>;
 447                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 448                              <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 449                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 450                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 451                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 452                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 453                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 454                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 455                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 456                              <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 457                              <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 458                              <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 459                              <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 460                              <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
 462                 clock-names = "timer";
 463         };
 464
 465         tegra_car: clock@60006000 {
 466                 compatible = "nvidia,tegra210-car";
 467                 reg = <0x0 0x60006000 0x0 0x1000>;
 468                 #clock-cells = <1>;
 469                 #reset-cells = <1>;
 470         };
 471
 472         flow-controller@60007000 {
 473                 compatible = "nvidia,tegra210-flowctrl";
 474                 reg = <0x0 0x60007000 0x0 0x1000>;
 475         };
 476
 477         gpio: gpio@6000d000 {
 478                 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
 479                 reg = <0x0 0x6000d000 0x0 0x1000>;
 480                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 481                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 482                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 483                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 484                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 485                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 486                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 487                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 488                 #gpio-cells = <2>;
 489                 gpio-controller;
 490                 #interrupt-cells = <2>;
 491                 interrupt-controller;
 492         };
 493
 494         apbdma: dma@60020000 {
 495                 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
 496                 reg = <0x0 0x60020000 0x0 0x1400>;
 497                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 498                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 499                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 500                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 501                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 502                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 503                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 504                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 505                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 506                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 507                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 508                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 509                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 510                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 511                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 512                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 513                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 514                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 515                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 516                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 517                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 518                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 519                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 520                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 521                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 522                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 523                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 524                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 525                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 526                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 527                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 528                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 529                 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
 530                 clock-names = "dma";
 531                 resets = <&tegra_car 34>;
 532                 reset-names = "dma";
 533                 #dma-cells = <1>;
 534         };
 535
 536         apbmisc@70000800 {
 537                 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
 538                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 539                       <0x0 0x70000008 0x0 0x04>;   /* Strapping options */
 540         };
 541
 542         pinmux: pinmux@700008d4 {
 543                 compatible = "nvidia,tegra210-pinmux";
 544                 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
 545                       <0x0 0x70003000 0x0 0x294>; /* Mux registers */
 546                 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
 547                         sdmmc1 {
 548                                 nvidia,pins = "drive_sdmmc1";
 549                                 nvidia,pull-down-strength = <0x8>;
 550                                 nvidia,pull-up-strength = <0x8>;
 551                         };
 552                 };
 553                 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
 554                         sdmmc1 {
 555                                 nvidia,pins = "drive_sdmmc1";
 556                                 nvidia,pull-down-strength = <0x4>;
 557                                 nvidia,pull-up-strength = <0x3>;
 558                         };
 559                 };
 560                 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
 561                         sdmmc2 {
 562                                 nvidia,pins = "drive_sdmmc2";
 563                                 nvidia,pull-down-strength = <0x10>;
 564                                 nvidia,pull-up-strength = <0x10>;
 565                         };
 566                 };
 567                 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
 568                         sdmmc3 {
 569                                 nvidia,pins = "drive_sdmmc3";
 570                                 nvidia,pull-down-strength = <0x8>;
 571                                 nvidia,pull-up-strength = <0x8>;
 572                         };
 573                 };
 574                 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
 575                         sdmmc3 {
 576                                 nvidia,pins = "drive_sdmmc3";
 577                                 nvidia,pull-down-strength = <0x4>;
 578                                 nvidia,pull-up-strength = <0x3>;
 579                         };
 580                 };
 581                 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
 582                         sdmmc4 {
 583                                 nvidia,pins = "drive_sdmmc4";
 584                                 nvidia,pull-down-strength = <0x10>;
 585                                 nvidia,pull-up-strength = <0x10>;
 586                         };
 587                 };
 588         };
 589
 590         /*
 591          * There are two serial driver i.e. 8250 based simple serial
 592          * driver and APB DMA based serial driver for higher baudrate
 593          * and performance. To enable the 8250 based driver, the compatible
 594          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 595          * the APB DMA based serial driver, the compatible is
 596          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 597          */
 598         uarta: serial@70006000 {
 599                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 600                 reg = <0x0 0x70006000 0x0 0x40>;
 601                 reg-shift = <2>;
 602                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
 604                 clock-names = "serial";
 605                 resets = <&tegra_car 6>;
 606                 reset-names = "serial";
 607                 dmas = <&apbdma 8>, <&apbdma 8>;
 608                 dma-names = "rx", "tx";
 609                 status = "disabled";
 610         };
 611
 612         uartb: serial@70006040 {
 613                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 614                 reg = <0x0 0x70006040 0x0 0x40>;
 615                 reg-shift = <2>;
 616                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
 618                 clock-names = "serial";
 619                 resets = <&tegra_car 7>;
 620                 reset-names = "serial";
 621                 dmas = <&apbdma 9>, <&apbdma 9>;
 622                 dma-names = "rx", "tx";
 623                 status = "disabled";
 624         };
 625
 626         uartc: serial@70006200 {
 627                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 628                 reg = <0x0 0x70006200 0x0 0x40>;
 629                 reg-shift = <2>;
 630                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 631                 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
 632                 clock-names = "serial";
 633                 resets = <&tegra_car 55>;
 634                 reset-names = "serial";
 635                 dmas = <&apbdma 10>, <&apbdma 10>;
 636                 dma-names = "rx", "tx";
 637                 status = "disabled";
 638         };
 639
 640         uartd: serial@70006300 {
 641                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 642                 reg = <0x0 0x70006300 0x0 0x40>;
 643                 reg-shift = <2>;
 644                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
 646                 clock-names = "serial";
 647                 resets = <&tegra_car 65>;
 648                 reset-names = "serial";
 649                 dmas = <&apbdma 19>, <&apbdma 19>;
 650                 dma-names = "rx", "tx";
 651                 status = "disabled";
 652         };
 653
 654         pwm: pwm@7000a000 {
 655                 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
 656                 reg = <0x0 0x7000a000 0x0 0x100>;
 657                 #pwm-cells = <2>;
 658                 clocks = <&tegra_car TEGRA210_CLK_PWM>;
 659                 clock-names = "pwm";
 660                 resets = <&tegra_car 17>;
 661                 reset-names = "pwm";
 662                 status = "disabled";
 663         };
 664
 665         i2c@7000c000 {
 666                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 667                 reg = <0x0 0x7000c000 0x0 0x100>;
 668                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
 672                 clock-names = "div-clk";
 673                 resets = <&tegra_car 12>;
 674                 reset-names = "i2c";
 675                 dmas = <&apbdma 21>, <&apbdma 21>;
 676                 dma-names = "rx", "tx";
 677                 status = "disabled";
 678         };
 679
 680         i2c@7000c400 {
 681                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 682                 reg = <0x0 0x7000c400 0x0 0x100>;
 683                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 684                 #address-cells = <1>;
 685                 #size-cells = <0>;
 686                 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
 687                 clock-names = "div-clk";
 688                 resets = <&tegra_car 54>;
 689                 reset-names = "i2c";
 690                 dmas = <&apbdma 22>, <&apbdma 22>;
 691                 dma-names = "rx", "tx";
 692                 status = "disabled";
 693         };
 694
 695         i2c@7000c500 {
 696                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 697                 reg = <0x0 0x7000c500 0x0 0x100>;
 698                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
 702                 clock-names = "div-clk";
 703                 resets = <&tegra_car 67>;
 704                 reset-names = "i2c";
 705                 dmas = <&apbdma 23>, <&apbdma 23>;
 706                 dma-names = "rx", "tx";
 707                 status = "disabled";
 708         };
 709
 710         i2c@7000c700 {
 711                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 712                 reg = <0x0 0x7000c700 0x0 0x100>;
 713                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 714                 #address-cells = <1>;
 715                 #size-cells = <0>;
 716                 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
 717                 clock-names = "div-clk";
 718                 resets = <&tegra_car 103>;
 719                 reset-names = "i2c";
 720                 dmas = <&apbdma 26>, <&apbdma 26>;
 721                 dma-names = "rx", "tx";
 722                 pinctrl-0 = <&state_dpaux1_i2c>;
 723                 pinctrl-1 = <&state_dpaux1_off>;
 724                 pinctrl-names = "default", "idle";
 725                 status = "disabled";
 726         };
 727
 728         i2c@7000d000 {
 729                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 730                 reg = <0x0 0x7000d000 0x0 0x100>;
 731                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 732                 #address-cells = <1>;
 733                 #size-cells = <0>;
 734                 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
 735                 clock-names = "div-clk";
 736                 resets = <&tegra_car 47>;
 737                 reset-names = "i2c";
 738                 dmas = <&apbdma 24>, <&apbdma 24>;
 739                 dma-names = "rx", "tx";
 740                 status = "disabled";
 741         };
 742
 743         i2c@7000d100 {
 744                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 745                 reg = <0x0 0x7000d100 0x0 0x100>;
 746                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 747                 #address-cells = <1>;
 748                 #size-cells = <0>;
 749                 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
 750                 clock-names = "div-clk";
 751                 resets = <&tegra_car 166>;
 752                 reset-names = "i2c";
 753                 dmas = <&apbdma 30>, <&apbdma 30>;
 754                 dma-names = "rx", "tx";
 755                 pinctrl-0 = <&state_dpaux_i2c>;
 756                 pinctrl-1 = <&state_dpaux_off>;
 757                 pinctrl-names = "default", "idle";
 758                 status = "disabled";
 759         };
 760
 761         spi@7000d400 {
 762                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 763                 reg = <0x0 0x7000d400 0x0 0x200>;
 764                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 765                 #address-cells = <1>;
 766                 #size-cells = <0>;
 767                 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
 768                 clock-names = "spi";
 769                 resets = <&tegra_car 41>;
 770                 reset-names = "spi";
 771                 dmas = <&apbdma 15>, <&apbdma 15>;
 772                 dma-names = "rx", "tx";
 773                 status = "disabled";
 774         };
 775
 776         spi@7000d600 {
 777                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 778                 reg = <0x0 0x7000d600 0x0 0x200>;
 779                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 780                 #address-cells = <1>;
 781                 #size-cells = <0>;
 782                 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
 783                 clock-names = "spi";
 784                 resets = <&tegra_car 44>;
 785                 reset-names = "spi";
 786                 dmas = <&apbdma 16>, <&apbdma 16>;
 787                 dma-names = "rx", "tx";
 788                 status = "disabled";
 789         };
 790
 791         spi@7000d800 {
 792                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 793                 reg = <0x0 0x7000d800 0x0 0x200>;
 794                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 795                 #address-cells = <1>;
 796                 #size-cells = <0>;
 797                 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
 798                 clock-names = "spi";
 799                 resets = <&tegra_car 46>;
 800                 reset-names = "spi";
 801                 dmas = <&apbdma 17>, <&apbdma 17>;
 802                 dma-names = "rx", "tx";
 803                 status = "disabled";
 804         };
 805
 806         spi@7000da00 {
 807                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 808                 reg = <0x0 0x7000da00 0x0 0x200>;
 809                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 810                 #address-cells = <1>;
 811                 #size-cells = <0>;
 812                 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
 813                 clock-names = "spi";
 814                 resets = <&tegra_car 68>;
 815                 reset-names = "spi";
 816                 dmas = <&apbdma 18>, <&apbdma 18>;
 817                 dma-names = "rx", "tx";
 818                 status = "disabled";
 819         };
 820
 821         rtc@7000e000 {
 822                 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
 823                 reg = <0x0 0x7000e000 0x0 0x100>;
 824                 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
 825                 interrupt-parent = <&tegra_pmc>;
 826                 clocks = <&tegra_car TEGRA210_CLK_RTC>;
 827                 clock-names = "rtc";
 828         };
 829
 830         tegra_pmc: pmc@7000e400 {
 831                 compatible = "nvidia,tegra210-pmc";
 832                 reg = <0x0 0x7000e400 0x0 0x400>;
 833                 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 834                 clock-names = "pclk", "clk32k_in";
 835                 #clock-cells = <1>;
 836                 #interrupt-cells = <2>;
 837                 interrupt-controller;
 838
 839                 powergates {
 840                         pd_audio: aud {
 841                                 clocks = <&tegra_car TEGRA210_CLK_APE>,
 842                                          <&tegra_car TEGRA210_CLK_APB2APE>;
 843                                 resets = <&tegra_car 198>;
 844                                 #power-domain-cells = <0>;
 845                         };
 846
 847                         pd_sor: sor {
 848                                 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 849                                          <&tegra_car TEGRA210_CLK_SOR1>,
 850                                          <&tegra_car TEGRA210_CLK_CILAB>,
 851                                          <&tegra_car TEGRA210_CLK_CILCD>,
 852                                          <&tegra_car TEGRA210_CLK_CILE>,
 853                                          <&tegra_car TEGRA210_CLK_DSIA>,
 854                                          <&tegra_car TEGRA210_CLK_DSIB>,
 855                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 856                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 857                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 858                                 resets = <&tegra_car TEGRA210_CLK_SOR0>,
 859                                          <&tegra_car TEGRA210_CLK_SOR1>,
 860                                          <&tegra_car TEGRA210_CLK_DSIA>,
 861                                          <&tegra_car TEGRA210_CLK_DSIB>,
 862                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 863                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 864                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 865                                 #power-domain-cells = <0>;
 866                         };
 867
 868                         pd_xusbss: xusba {
 869                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 870                                 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 871                                 #power-domain-cells = <0>;
 872                         };
 873
 874                         pd_xusbdev: xusbb {
 875                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
 876                                 resets = <&tegra_car 95>;
 877                                 #power-domain-cells = <0>;
 878                         };
 879
 880                         pd_xusbhost: xusbc {
 881                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 882                                 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 883                                 #power-domain-cells = <0>;
 884                         };
 885
 886                         pd_vic: vic {
 887                                 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 888                                 clock-names = "vic";
 889                                 resets = <&tegra_car 178>;
 890                                 reset-names = "vic";
 891                                 #power-domain-cells = <0>;
 892                         };
 893
 894                         pd_venc: venc {
 895                                 clocks = <&tegra_car TEGRA210_CLK_VI>,
 896                                          <&tegra_car TEGRA210_CLK_CSI>;
 897                                 resets = <&mc TEGRA210_MC_RESET_VI>,
 898                                          <&tegra_car 20>,
 899                                          <&tegra_car 52>;
 900                                 #power-domain-cells = <0>;
 901                         };
 902                 };
 903
 904                 sdmmc1_3v3: sdmmc1-3v3 {
 905                         pins = "sdmmc1";
 906                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 907                 };
 908
 909                 sdmmc1_1v8: sdmmc1-1v8 {
 910                         pins = "sdmmc1";
 911                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 912                 };
 913
 914                 sdmmc3_3v3: sdmmc3-3v3 {
 915                         pins = "sdmmc3";
 916                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 917                 };
 918
 919                 sdmmc3_1v8: sdmmc3-1v8 {
 920                         pins = "sdmmc3";
 921                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 922                 };
 923
 924                 pex_dpd_disable: pex_en {
 925                         pex-dpd-disable {
 926                                 pins = "pex-bias", "pex-clk1", "pex-clk2";
 927                                 low-power-disable;
 928                         };
 929                 };
 930
 931                 pex_dpd_enable: pex_dis {
 932                         pex-dpd-enable {
 933                                 pins = "pex-bias", "pex-clk1", "pex-clk2";
 934                                 low-power-enable;
 935                         };
 936                 };
 937         };
 938
 939         fuse@7000f800 {
 940                 compatible = "nvidia,tegra210-efuse";
 941                 reg = <0x0 0x7000f800 0x0 0x400>;
 942                 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
 943                 clock-names = "fuse";
 944                 resets = <&tegra_car 39>;
 945                 reset-names = "fuse";
 946         };
 947
 948         mc: memory-controller@70019000 {
 949                 compatible = "nvidia,tegra210-mc";
 950                 reg = <0x0 0x70019000 0x0 0x1000>;
 951                 clocks = <&tegra_car TEGRA210_CLK_MC>;
 952                 clock-names = "mc";
 953
 954                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 955
 956                 #iommu-cells = <1>;
 957                 #reset-cells = <1>;
 958         };
 959
 960         emc: external-memory-controller@7001b000 {
 961                 compatible = "nvidia,tegra210-emc";
 962                 reg = <0x0 0x7001b000 0x0 0x1000>,
 963                       <0x0 0x7001e000 0x0 0x1000>,
 964                       <0x0 0x7001f000 0x0 0x1000>;
 965                 clocks = <&tegra_car TEGRA210_CLK_EMC>;
 966                 clock-names = "emc";
 967                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 968                 nvidia,memory-controller = <&mc>;
 969                 #cooling-cells = <2>;
 970         };
 971
 972         sata@70020000 {
 973                 compatible = "nvidia,tegra210-ahci";
 974                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 975                       <0x0 0x70020000 0x0 0x7000>, /* SATA */
 976                       <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
 977                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 978                 clocks = <&tegra_car TEGRA210_CLK_SATA>,
 979                          <&tegra_car TEGRA210_CLK_SATA_OOB>;
 980                 clock-names = "sata", "sata-oob";
 981                 resets = <&tegra_car 124>,
 982                          <&tegra_car 129>,
 983                          <&tegra_car 123>;
 984                 reset-names = "sata", "sata-cold", "sata-oob";
 985                 status = "disabled";
 986         };
 987
 988         hda@70030000 {
 989                 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
 990                 reg = <0x0 0x70030000 0x0 0x10000>;
 991                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 992                 clocks = <&tegra_car TEGRA210_CLK_HDA>,
 993                          <&tegra_car TEGRA210_CLK_HDA2HDMI>,
 994                          <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
 995                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 996                 resets = <&tegra_car 125>, /* hda */
 997                          <&tegra_car 128>, /* hda2hdmi */
 998                          <&tegra_car 111>; /* hda2codec_2x */
 999                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1000                 power-domains = <&pd_sor>;
1001                 status = "disabled";
1002         };
1003
1004         usb@70090000 {
1005                 compatible = "nvidia,tegra210-xusb";
1006                 reg = <0x0 0x70090000 0x0 0x8000>,
1007                       <0x0 0x70098000 0x0 0x1000>,
1008                       <0x0 0x70099000 0x0 0x1000>;
1009                 reg-names = "hcd", "fpci", "ipfs";
1010
1011                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1012                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1013
1014                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1015                          <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1016                          <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1017                          <&tegra_car TEGRA210_CLK_XUSB_SS>,
1018                          <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1019                          <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1020                          <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1021                          <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1022                          <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1023                          <&tegra_car TEGRA210_CLK_CLK_M>,
1024                          <&tegra_car TEGRA210_CLK_PLL_E>;
1025                 clock-names = "xusb_host", "xusb_host_src",
1026                               "xusb_falcon_src", "xusb_ss",
1027                               "xusb_ss_src", "xusb_ss_div2",
1028                               "xusb_hs_src", "xusb_fs_src",
1029                               "pll_u_480m", "clk_m", "pll_e";
1030                 resets = <&tegra_car 89>, <&tegra_car 156>,
1031                          <&tegra_car 143>;
1032                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1033                 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1034                 power-domain-names = "xusb_host", "xusb_ss";
1035
1036                 nvidia,xusb-padctl = <&padctl>;
1037
1038                 status = "disabled";
1039         };
1040
1041         padctl: padctl@7009f000 {
1042                 compatible = "nvidia,tegra210-xusb-padctl";
1043                 reg = <0x0 0x7009f000 0x0 0x1000>;
1044                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1045                 resets = <&tegra_car 142>;
1046                 reset-names = "padctl";
1047                 nvidia,pmc =  <&tegra_pmc>;
1048
1049                 status = "disabled";
1050
1051                 pads {
1052                         usb2 {
1053                                 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1054                                 clock-names = "trk";
1055                                 status = "disabled";
1056
1057                                 lanes {
1058                                         usb2-0 {
1059                                                 status = "disabled";
1060                                                 #phy-cells = <0>;
1061                                         };
1062
1063                                         usb2-1 {
1064                                                 status = "disabled";
1065                                                 #phy-cells = <0>;
1066                                         };
1067
1068                                         usb2-2 {
1069                                                 status = "disabled";
1070                                                 #phy-cells = <0>;
1071                                         };
1072
1073                                         usb2-3 {
1074                                                 status = "disabled";
1075                                                 #phy-cells = <0>;
1076                                         };
1077                                 };
1078                         };
1079
1080                         hsic {
1081                                 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1082                                 clock-names = "trk";
1083                                 status = "disabled";
1084
1085                                 lanes {
1086                                         hsic-0 {
1087                                                 status = "disabled";
1088                                                 #phy-cells = <0>;
1089                                         };
1090
1091                                         hsic-1 {
1092                                                 status = "disabled";
1093                                                 #phy-cells = <0>;
1094                                         };
1095                                 };
1096                         };
1097
1098                         pcie {
1099                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1100                                 clock-names = "pll";
1101                                 resets = <&tegra_car 205>;
1102                                 reset-names = "phy";
1103                                 status = "disabled";
1104
1105                                 lanes {
1106                                         pcie-0 {
1107                                                 status = "disabled";
1108                                                 #phy-cells = <0>;
1109                                         };
1110
1111                                         pcie-1 {
1112                                                 status = "disabled";
1113                                                 #phy-cells = <0>;
1114                                         };
1115
1116                                         pcie-2 {
1117                                                 status = "disabled";
1118                                                 #phy-cells = <0>;
1119                                         };
1120
1121                                         pcie-3 {
1122                                                 status = "disabled";
1123                                                 #phy-cells = <0>;
1124                                         };
1125
1126                                         pcie-4 {
1127                                                 status = "disabled";
1128                                                 #phy-cells = <0>;
1129                                         };
1130
1131                                         pcie-5 {
1132                                                 status = "disabled";
1133                                                 #phy-cells = <0>;
1134                                         };
1135
1136                                         pcie-6 {
1137                                                 status = "disabled";
1138                                                 #phy-cells = <0>;
1139                                         };
1140                                 };
1141                         };
1142
1143                         sata {
1144                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1145                                 clock-names = "pll";
1146                                 resets = <&tegra_car 204>;
1147                                 reset-names = "phy";
1148                                 status = "disabled";
1149
1150                                 lanes {
1151                                         sata-0 {
1152                                                 status = "disabled";
1153                                                 #phy-cells = <0>;
1154                                         };
1155                                 };
1156                         };
1157                 };
1158
1159                 ports {
1160                         usb2-0 {
1161                                 status = "disabled";
1162                         };
1163
1164                         usb2-1 {
1165                                 status = "disabled";
1166                         };
1167
1168                         usb2-2 {
1169                                 status = "disabled";
1170                         };
1171
1172                         usb2-3 {
1173                                 status = "disabled";
1174                         };
1175
1176                         hsic-0 {
1177                                 status = "disabled";
1178                         };
1179
1180                         usb3-0 {
1181                                 status = "disabled";
1182                         };
1183
1184                         usb3-1 {
1185                                 status = "disabled";
1186                         };
1187
1188                         usb3-2 {
1189                                 status = "disabled";
1190                         };
1191
1192                         usb3-3 {
1193                                 status = "disabled";
1194                         };
1195                 };
1196         };
1197
1198         mmc@700b0000 {
1199                 compatible = "nvidia,tegra210-sdhci";
1200                 reg = <0x0 0x700b0000 0x0 0x200>;
1201                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1202                 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1203                          <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1204                 clock-names = "sdhci", "tmclk";
1205                 resets = <&tegra_car 14>;
1206                 reset-names = "sdhci";
1207                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1208                                 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1209                 pinctrl-0 = <&sdmmc1_3v3>;
1210                 pinctrl-1 = <&sdmmc1_1v8>;
1211                 pinctrl-2 = <&sdmmc1_3v3_drv>;
1212                 pinctrl-3 = <&sdmmc1_1v8_drv>;
1213                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1214                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1215                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1216                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1217                 nvidia,default-tap = <0x2>;
1218                 nvidia,default-trim = <0x4>;
1219                 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1220                                   <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1221                                   <&tegra_car TEGRA210_CLK_PLL_C4>;
1222                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1223                 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1224                 status = "disabled";
1225         };
1226
1227         mmc@700b0200 {
1228                 compatible = "nvidia,tegra210-sdhci";
1229                 reg = <0x0 0x700b0200 0x0 0x200>;
1230                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1231                 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1232                          <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1233                 clock-names = "sdhci", "tmclk";
1234                 resets = <&tegra_car 9>;
1235                 reset-names = "sdhci";
1236                 pinctrl-names = "sdmmc-1v8-drv";
1237                 pinctrl-0 = <&sdmmc2_1v8_drv>;
1238                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1239                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1240                 nvidia,default-tap = <0x8>;
1241                 nvidia,default-trim = <0x0>;
1242                 status = "disabled";
1243         };
1244
1245         mmc@700b0400 {
1246                 compatible = "nvidia,tegra210-sdhci";
1247                 reg = <0x0 0x700b0400 0x0 0x200>;
1248                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1249                 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1250                          <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1251                 clock-names = "sdhci", "tmclk";
1252                 resets = <&tegra_car 69>;
1253                 reset-names = "sdhci";
1254                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1255                                 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1256                 pinctrl-0 = <&sdmmc3_3v3>;
1257                 pinctrl-1 = <&sdmmc3_1v8>;
1258                 pinctrl-2 = <&sdmmc3_3v3_drv>;
1259                 pinctrl-3 = <&sdmmc3_1v8_drv>;
1260                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1261                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1262                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1263                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1264                 nvidia,default-tap = <0x3>;
1265                 nvidia,default-trim = <0x3>;
1266                 status = "disabled";
1267         };
1268
1269         mmc@700b0600 {
1270                 compatible = "nvidia,tegra210-sdhci";
1271                 reg = <0x0 0x700b0600 0x0 0x200>;
1272                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1273                 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1274                          <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1275                 clock-names = "sdhci", "tmclk";
1276                 resets = <&tegra_car 15>;
1277                 reset-names = "sdhci";
1278                 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1279                 pinctrl-0 = <&sdmmc4_1v8_drv>;
1280                 pinctrl-1 = <&sdmmc4_1v8_drv>;
1281                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1282                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1283                 nvidia,default-tap = <0x8>;
1284                 nvidia,default-trim = <0x0>;
1285                 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1286                                   <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1287                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1288                 nvidia,dqs-trim = <40>;
1289                 mmc-hs400-1_8v;
1290                 status = "disabled";
1291         };
1292
1293         usb@700d0000 {
1294                 compatible = "nvidia,tegra210-xudc";
1295                 reg = <0x0 0x700d0000 0x0 0x8000>,
1296                       <0x0 0x700d8000 0x0 0x1000>,
1297                       <0x0 0x700d9000 0x0 0x1000>;
1298                 reg-names = "base", "fpci", "ipfs";
1299                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1300                 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1301                          <&tegra_car TEGRA210_CLK_XUSB_SS>,
1302                          <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1303                          <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1304                          <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1305                 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1306                 power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1307                 power-domain-names = "dev", "ss";
1308                 nvidia,xusb-padctl = <&padctl>;
1309                 status = "disabled";
1310         };
1311
1312         soctherm: thermal-sensor@700e2000 {
1313                 compatible = "nvidia,tegra210-soctherm";
1314                 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1315                       <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1316                 reg-names = "soctherm-reg", "car-reg";
1317                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1318                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1319                 interrupt-names = "thermal", "edp";
1320                 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1321                         <&tegra_car TEGRA210_CLK_SOC_THERM>;
1322                 clock-names = "tsensor", "soctherm";
1323                 resets = <&tegra_car 78>;
1324                 reset-names = "soctherm";
1325                 #thermal-sensor-cells = <1>;
1326
1327                 throttle-cfgs {
1328                         throttle_heavy: heavy {
1329                                 nvidia,priority = <100>;
1330                                 nvidia,cpu-throt-percent = <85>;
1331                                 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
1332
1333                                 #cooling-cells = <2>;
1334                         };
1335                 };
1336         };
1337
1338         mipi: mipi@700e3000 {
1339                 compatible = "nvidia,tegra210-mipi";
1340                 reg = <0x0 0x700e3000 0x0 0x100>;
1341                 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1342                 clock-names = "mipi-cal";
1343                 power-domains = <&pd_sor>;
1344                 #nvidia,mipi-calibrate-cells = <1>;
1345         };
1346
1347         dfll: clock@70110000 {
1348                 compatible = "nvidia,tegra210-dfll";
1349                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1350                       <0 0x70110000 0 0x100>, /* I2C output control */
1351                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1352                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
1353                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1354                 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1355                          <&tegra_car TEGRA210_CLK_DFLL_REF>,
1356                          <&tegra_car TEGRA210_CLK_I2C5>;
1357                 clock-names = "soc", "ref", "i2c";
1358                 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1359                 reset-names = "dvco";
1360                 #clock-cells = <0>;
1361                 clock-output-names = "dfllCPU_out";
1362                 status = "disabled";
1363         };
1364
1365         aconnect@702c0000 {
1366                 compatible = "nvidia,tegra210-aconnect";
1367                 clocks = <&tegra_car TEGRA210_CLK_APE>,
1368                          <&tegra_car TEGRA210_CLK_APB2APE>;
1369                 clock-names = "ape", "apb2ape";
1370                 power-domains = <&pd_audio>;
1371                 #address-cells = <1>;
1372                 #size-cells = <1>;
1373                 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1374                 status = "disabled";
1375
1376                 adma: dma-controller@702e2000 {
1377                         compatible = "nvidia,tegra210-adma";
1378                         reg = <0x702e2000 0x2000>;
1379                         interrupt-parent = <&agic>;
1380                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1381                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1382                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1383                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1384                                      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1385                                      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1386                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1387                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1388                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1389                                      <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1390                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1391                                      <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1392                                      <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1393                                      <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1394                                      <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1395                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1396                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1397                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1398                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1399                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1400                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1401                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1402                         #dma-cells = <1>;
1403                         clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1404                         clock-names = "d_audio";
1405                         status = "disabled";
1406                 };
1407
1408                 agic: interrupt-controller@702f9000 {
1409                         compatible = "nvidia,tegra210-agic";
1410                         #interrupt-cells = <3>;
1411                         interrupt-controller;
1412                         reg = <0x702f9000 0x1000>,
1413                               <0x702fa000 0x2000>;
1414                         interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1415                         clocks = <&tegra_car TEGRA210_CLK_APE>;
1416                         clock-names = "clk";
1417                         status = "disabled";
1418                 };
1419
1420                 tegra_ahub: ahub@702d0800 {
1421                         compatible = "nvidia,tegra210-ahub";
1422                         reg = <0x702d0800 0x800>;
1423                         clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1424                         clock-names = "ahub";
1425                         assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1426                         assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1427                         #address-cells = <1>;
1428                         #size-cells = <1>;
1429                         ranges = <0x702d0000 0x702d0000 0x0000e400>;
1430                         status = "disabled";
1431
1432                         tegra_admaif: admaif@702d0000 {
1433                                 compatible = "nvidia,tegra210-admaif";
1434                                 reg = <0x702d0000 0x800>;
1435                                 dmas = <&adma 1>,  <&adma 1>,
1436                                        <&adma 2>,  <&adma 2>,
1437                                        <&adma 3>,  <&adma 3>,
1438                                        <&adma 4>,  <&adma 4>,
1439                                        <&adma 5>,  <&adma 5>,
1440                                        <&adma 6>,  <&adma 6>,
1441                                        <&adma 7>,  <&adma 7>,
1442                                        <&adma 8>,  <&adma 8>,
1443                                        <&adma 9>,  <&adma 9>,
1444                                        <&adma 10>, <&adma 10>;
1445                                 dma-names = "rx1",  "tx1",
1446                                             "rx2",  "tx2",
1447                                             "rx3",  "tx3",
1448                                             "rx4",  "tx4",
1449                                             "rx5",  "tx5",
1450                                             "rx6",  "tx6",
1451                                             "rx7",  "tx7",
1452                                             "rx8",  "tx8",
1453                                             "rx9",  "tx9",
1454                                             "rx10", "tx10";
1455                                 status = "disabled";
1456
1457                                 ports {
1458                                         #address-cells = <1>;
1459                                         #size-cells = <0>;
1460
1461                                         admaif1_port: port@0 {
1462                                                 reg = <0>;
1463
1464                                                 admaif1_ep: endpoint {
1465                                                         remote-endpoint = <&xbar_admaif1_ep>;
1466                                                 };
1467                                         };
1468
1469                                         admaif2_port: port@1 {
1470                                                 reg = <1>;
1471
1472                                                 admaif2_ep: endpoint {
1473                                                         remote-endpoint = <&xbar_admaif2_ep>;
1474                                                 };
1475                                         };
1476
1477                                         admaif3_port: port@2 {
1478                                                 reg = <2>;
1479
1480                                                 admaif3_ep: endpoint {
1481                                                         remote-endpoint = <&xbar_admaif3_ep>;
1482                                                 };
1483                                         };
1484
1485                                         admaif4_port: port@3 {
1486                                                 reg = <3>;
1487
1488                                                 admaif4_ep: endpoint {
1489                                                         remote-endpoint = <&xbar_admaif4_ep>;
1490                                                 };
1491                                         };
1492
1493                                         admaif5_port: port@4 {
1494                                                 reg = <4>;
1495
1496                                                 admaif5_ep: endpoint {
1497                                                         remote-endpoint = <&xbar_admaif5_ep>;
1498                                                 };
1499                                         };
1500
1501                                         admaif6_port: port@5 {
1502                                                 reg = <5>;
1503
1504                                                 admaif6_ep: endpoint {
1505                                                         remote-endpoint = <&xbar_admaif6_ep>;
1506                                                 };
1507                                         };
1508
1509                                         admaif7_port: port@6 {
1510                                                 reg = <6>;
1511
1512                                                 admaif7_ep: endpoint {
1513                                                         remote-endpoint = <&xbar_admaif7_ep>;
1514                                                 };
1515                                         };
1516
1517                                         admaif8_port: port@7 {
1518                                                 reg = <7>;
1519
1520                                                 admaif8_ep: endpoint {
1521                                                         remote-endpoint = <&xbar_admaif8_ep>;
1522                                                 };
1523                                         };
1524
1525                                         admaif9_port: port@8 {
1526                                                 reg = <8>;
1527
1528                                                 admaif9_ep: endpoint {
1529                                                         remote-endpoint = <&xbar_admaif9_ep>;
1530                                                 };
1531                                         };
1532
1533                                         admaif10_port: port@9 {
1534                                                 reg = <9>;
1535
1536                                                 admaif10_ep: endpoint {
1537                                                         remote-endpoint = <&xbar_admaif10_ep>;
1538                                                 };
1539                                         };
1540                                 };
1541                         };
1542
1543                         tegra_i2s1: i2s@702d1000 {
1544                                 compatible = "nvidia,tegra210-i2s";
1545                                 reg = <0x702d1000 0x100>;
1546                                 clocks = <&tegra_car TEGRA210_CLK_I2S0>,
1547                                          <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
1548                                 clock-names = "i2s", "sync_input";
1549                                 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
1550                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1551                                 assigned-clock-rates = <1536000>;
1552                                 sound-name-prefix = "I2S1";
1553                                 status = "disabled";
1554                         };
1555
1556                         tegra_i2s2: i2s@702d1100 {
1557                                 compatible = "nvidia,tegra210-i2s";
1558                                 reg = <0x702d1100 0x100>;
1559                                 clocks = <&tegra_car TEGRA210_CLK_I2S1>,
1560                                          <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
1561                                 clock-names = "i2s", "sync_input";
1562                                 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
1563                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1564                                 assigned-clock-rates = <1536000>;
1565                                 sound-name-prefix = "I2S2";
1566                                 status = "disabled";
1567                         };
1568
1569                         tegra_i2s3: i2s@702d1200 {
1570                                 compatible = "nvidia,tegra210-i2s";
1571                                 reg = <0x702d1200 0x100>;
1572                                 clocks = <&tegra_car TEGRA210_CLK_I2S2>,
1573                                          <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
1574                                 clock-names = "i2s", "sync_input";
1575                                 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
1576                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1577                                 assigned-clock-rates = <1536000>;
1578                                 sound-name-prefix = "I2S3";
1579                                 status = "disabled";
1580                         };
1581
1582                         tegra_i2s4: i2s@702d1300 {
1583                                 compatible = "nvidia,tegra210-i2s";
1584                                 reg = <0x702d1300 0x100>;
1585                                 clocks = <&tegra_car TEGRA210_CLK_I2S3>,
1586                                          <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
1587                                 clock-names = "i2s", "sync_input";
1588                                 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
1589                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1590                                 assigned-clock-rates = <1536000>;
1591                                 sound-name-prefix = "I2S4";
1592                                 status = "disabled";
1593                         };
1594
1595                         tegra_i2s5: i2s@702d1400 {
1596                                 compatible = "nvidia,tegra210-i2s";
1597                                 reg = <0x702d1400 0x100>;
1598                                 clocks = <&tegra_car TEGRA210_CLK_I2S4>,
1599                                          <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
1600                                 clock-names = "i2s", "sync_input";
1601                                 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
1602                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1603                                 assigned-clock-rates = <1536000>;
1604                                 sound-name-prefix = "I2S5";
1605                                 status = "disabled";
1606                         };
1607
1608                         tegra_dmic1: dmic@702d4000 {
1609                                 compatible = "nvidia,tegra210-dmic";
1610                                 reg = <0x702d4000 0x100>;
1611                                 clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1612                                 clock-names = "dmic";
1613                                 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1614                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1615                                 assigned-clock-rates = <3072000>;
1616                                 sound-name-prefix = "DMIC1";
1617                                 status = "disabled";
1618                         };
1619
1620                         tegra_dmic2: dmic@702d4100 {
1621                                 compatible = "nvidia,tegra210-dmic";
1622                                 reg = <0x702d4100 0x100>;
1623                                 clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1624                                 clock-names = "dmic";
1625                                 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1626                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1627                                 assigned-clock-rates = <3072000>;
1628                                 sound-name-prefix = "DMIC2";
1629                                 status = "disabled";
1630                         };
1631
1632                         tegra_dmic3: dmic@702d4200 {
1633                                 compatible = "nvidia,tegra210-dmic";
1634                                 reg = <0x702d4200 0x100>;
1635                                 clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1636                                 clock-names = "dmic";
1637                                 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1638                                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1639                                 assigned-clock-rates = <3072000>;
1640                                 sound-name-prefix = "DMIC3";
1641                                 status = "disabled";
1642                         };
1643
1644                         ports {
1645                                 #address-cells = <1>;
1646                                 #size-cells = <0>;
1647
1648                                 port@0 {
1649                                         reg = <0x0>;
1650
1651                                         xbar_admaif1_ep: endpoint {
1652                                                 remote-endpoint = <&admaif1_ep>;
1653                                         };
1654                                 };
1655
1656                                 port@1 {
1657                                         reg = <0x1>;
1658
1659                                         xbar_admaif2_ep: endpoint {
1660                                                 remote-endpoint = <&admaif2_ep>;
1661                                         };
1662                                 };
1663
1664                                 port@2 {
1665                                         reg = <0x2>;
1666
1667                                         xbar_admaif3_ep: endpoint {
1668                                                 remote-endpoint = <&admaif3_ep>;
1669                                         };
1670                                 };
1671
1672                                 port@3 {
1673                                         reg = <0x3>;
1674
1675                                         xbar_admaif4_ep: endpoint {
1676                                                 remote-endpoint = <&admaif4_ep>;
1677                                         };
1678                                 };
1679
1680                                 port@4 {
1681                                         reg = <0x4>;
1682                                         xbar_admaif5_ep: endpoint {
1683                                                 remote-endpoint = <&admaif5_ep>;
1684                                         };
1685                                 };
1686                                 port@5 {
1687                                         reg = <0x5>;
1688
1689                                         xbar_admaif6_ep: endpoint {
1690                                                 remote-endpoint = <&admaif6_ep>;
1691                                         };
1692                                 };
1693
1694                                 port@6 {
1695                                         reg = <0x6>;
1696
1697                                         xbar_admaif7_ep: endpoint {
1698                                                 remote-endpoint = <&admaif7_ep>;
1699                                         };
1700                                 };
1701
1702                                 port@7 {
1703                                         reg = <0x7>;
1704
1705                                         xbar_admaif8_ep: endpoint {
1706                                                 remote-endpoint = <&admaif8_ep>;
1707                                         };
1708                                 };
1709
1710                                 port@8 {
1711                                         reg = <0x8>;
1712
1713                                         xbar_admaif9_ep: endpoint {
1714                                                 remote-endpoint = <&admaif9_ep>;
1715                                         };
1716                                 };
1717
1718                                 port@9 {
1719                                         reg = <0x9>;
1720
1721                                         xbar_admaif10_ep: endpoint {
1722                                                 remote-endpoint = <&admaif10_ep>;
1723                                         };
1724                                 };
1725                         };
1726                 };
1727         };
1728
1729         spi@70410000 {
1730                 compatible = "nvidia,tegra210-qspi";
1731                 reg = <0x0 0x70410000 0x0 0x1000>;
1732                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1733                 #address-cells = <1>;
1734                 #size-cells = <0>;
1735                 clocks = <&tegra_car TEGRA210_CLK_QSPI>,
1736                          <&tegra_car TEGRA210_CLK_QSPI_PM>;
1737                 clock-names = "qspi", "qspi_out";
1738                 resets = <&tegra_car 211>;
1739                 reset-names = "qspi";
1740                 dmas = <&apbdma 5>, <&apbdma 5>;
1741                 dma-names = "rx", "tx";
1742                 status = "disabled";
1743         };
1744
1745         usb@7d000000 {
1746                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1747                 reg = <0x0 0x7d000000 0x0 0x4000>;
1748                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1749                 phy_type = "utmi";
1750                 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1751                 clock-names = "usb";
1752                 resets = <&tegra_car 22>;
1753                 reset-names = "usb";
1754                 nvidia,phy = <&phy1>;
1755                 status = "disabled";
1756         };
1757
1758         phy1: usb-phy@7d000000 {
1759                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1760                 reg = <0x0 0x7d000000 0x0 0x4000>,
1761                       <0x0 0x7d000000 0x0 0x4000>;
1762                 phy_type = "utmi";
1763                 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1764                          <&tegra_car TEGRA210_CLK_PLL_U>,
1765                          <&tegra_car TEGRA210_CLK_USBD>;
1766                 clock-names = "reg", "pll_u", "utmi-pads";
1767                 resets = <&tegra_car 22>, <&tegra_car 22>;
1768                 reset-names = "usb", "utmi-pads";
1769                 nvidia,hssync-start-delay = <0>;
1770                 nvidia,idle-wait-delay = <17>;
1771                 nvidia,elastic-limit = <16>;
1772                 nvidia,term-range-adj = <6>;
1773                 nvidia,xcvr-setup = <9>;
1774                 nvidia,xcvr-lsfslew = <0>;
1775                 nvidia,xcvr-lsrslew = <3>;
1776                 nvidia,hssquelch-level = <2>;
1777                 nvidia,hsdiscon-level = <5>;
1778                 nvidia,xcvr-hsslew = <12>;
1779                 nvidia,has-utmi-pad-registers;
1780                 status = "disabled";
1781         };
1782
1783         usb@7d004000 {
1784                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1785                 reg = <0x0 0x7d004000 0x0 0x4000>;
1786                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1787                 phy_type = "utmi";
1788                 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1789                 clock-names = "usb";
1790                 resets = <&tegra_car 58>;
1791                 reset-names = "usb";
1792                 nvidia,phy = <&phy2>;
1793                 status = "disabled";
1794         };
1795
1796         phy2: usb-phy@7d004000 {
1797                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1798                 reg = <0x0 0x7d004000 0x0 0x4000>,
1799                       <0x0 0x7d000000 0x0 0x4000>;
1800                 phy_type = "utmi";
1801                 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1802                          <&tegra_car TEGRA210_CLK_PLL_U>,
1803                          <&tegra_car TEGRA210_CLK_USBD>;
1804                 clock-names = "reg", "pll_u", "utmi-pads";
1805                 resets = <&tegra_car 58>, <&tegra_car 22>;
1806                 reset-names = "usb", "utmi-pads";
1807                 nvidia,hssync-start-delay = <0>;
1808                 nvidia,idle-wait-delay = <17>;
1809                 nvidia,elastic-limit = <16>;
1810                 nvidia,term-range-adj = <6>;
1811                 nvidia,xcvr-setup = <9>;
1812                 nvidia,xcvr-lsfslew = <0>;
1813                 nvidia,xcvr-lsrslew = <3>;
1814                 nvidia,hssquelch-level = <2>;
1815                 nvidia,hsdiscon-level = <5>;
1816                 nvidia,xcvr-hsslew = <12>;
1817                 status = "disabled";
1818         };
1819
1820         cpus {
1821                 #address-cells = <1>;
1822                 #size-cells = <0>;
1823
1824                 cpu@0 {
1825                         device_type = "cpu";
1826                         compatible = "arm,cortex-a57";
1827                         reg = <0>;
1828                         clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1829                                  <&tegra_car TEGRA210_CLK_PLL_X>,
1830                                  <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1831                                  <&dfll>;
1832                         clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1833                         clock-latency = <300000>;
1834                         cpu-idle-states = <&CPU_SLEEP>;
1835                         next-level-cache = <&L2>;
1836                 };
1837
1838                 cpu@1 {
1839                         device_type = "cpu";
1840                         compatible = "arm,cortex-a57";
1841                         reg = <1>;
1842                         cpu-idle-states = <&CPU_SLEEP>;
1843                         next-level-cache = <&L2>;
1844                 };
1845
1846                 cpu@2 {
1847                         device_type = "cpu";
1848                         compatible = "arm,cortex-a57";
1849                         reg = <2>;
1850                         cpu-idle-states = <&CPU_SLEEP>;
1851                         next-level-cache = <&L2>;
1852                 };
1853
1854                 cpu@3 {
1855                         device_type = "cpu";
1856                         compatible = "arm,cortex-a57";
1857                         reg = <3>;
1858                         cpu-idle-states = <&CPU_SLEEP>;
1859                         next-level-cache = <&L2>;
1860                 };
1861
1862                 idle-states {
1863                         entry-method = "psci";
1864
1865                         CPU_SLEEP: cpu-sleep {
1866                                 compatible = "arm,idle-state";
1867                                 arm,psci-suspend-param = <0x40000007>;
1868                                 entry-latency-us = <100>;
1869                                 exit-latency-us = <30>;
1870                                 min-residency-us = <1000>;
1871                                 wakeup-latency-us = <130>;
1872                                 idle-state-name = "cpu-sleep";
1873                                 status = "disabled";
1874                         };
1875                 };
1876
1877                 L2: l2-cache {
1878                         compatible = "cache";
1879                 };
1880         };
1881
1882         pmu {
1883                 compatible = "arm,armv8-pmuv3";
1884                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1885                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1886                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1887                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1888                 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
1889                                       &{/cpus/cpu@2} &{/cpus/cpu@3}>;
1890         };
1891
1892         sound {
1893                 status = "disabled";
1894
1895                 clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
1896                          <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1897                 clock-names = "pll_a", "plla_out0";
1898
1899                 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
1900                                   <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
1901                                   <&tegra_car TEGRA210_CLK_EXTERN1>;
1902                 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1903                 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
1904         };
1905
1906         thermal-zones {
1907                 cpu {
1908                         polling-delay-passive = <1000>;
1909                         polling-delay = <0>;
1910
1911                         thermal-sensors =
1912                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1913
1914                         trips {
1915                                 cpu-shutdown-trip {
1916                                         temperature = <102500>;
1917                                         hysteresis = <0>;
1918                                         type = "critical";
1919                                 };
1920
1921                                 cpu_throttle_trip: throttle-trip {
1922                                         temperature = <98500>;
1923                                         hysteresis = <1000>;
1924                                         type = "hot";
1925                                 };
1926                         };
1927
1928                         cooling-maps {
1929                                 map0 {
1930                                         trip = <&cpu_throttle_trip>;
1931                                         cooling-device = <&throttle_heavy 1 1>;
1932                                 };
1933                         };
1934                 };
1935
1936                 mem {
1937                         polling-delay-passive = <0>;
1938                         polling-delay = <0>;
1939
1940                         thermal-sensors =
1941                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1942
1943                         trips {
1944                                 dram_nominal: mem-nominal-trip {
1945                                         temperature = <50000>;
1946                                         hysteresis = <1000>;
1947                                         type = "passive";
1948                                 };
1949
1950                                 dram_throttle: mem-throttle-trip {
1951                                         temperature = <70000>;
1952                                         hysteresis = <1000>;
1953                                         type = "active";
1954                                 };
1955
1956                                 mem-hot-trip {
1957                                         temperature = <100000>;
1958                                         hysteresis = <1000>;
1959                                         type = "hot";
1960                                 };
1961
1962                                 mem-shutdown-trip {
1963                                         temperature = <103000>;
1964                                         hysteresis = <0>;
1965                                         type = "critical";
1966                                 };
1967                         };
1968
1969                         cooling-maps {
1970                                 dram-passive {
1971                                         cooling-device = <&emc 0 0>;
1972                                         trip = <&dram_nominal>;
1973                                 };
1974
1975                                 dram-active {
1976                                         cooling-device = <&emc 1 1>;
1977                                         trip = <&dram_throttle>;
1978                                 };
1979                         };
1980                 };
1981
1982                 gpu {
1983                         polling-delay-passive = <1000>;
1984                         polling-delay = <0>;
1985
1986                         thermal-sensors =
1987                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1988
1989                         trips {
1990                                 gpu-shutdown-trip {
1991                                         temperature = <103000>;
1992                                         hysteresis = <0>;
1993                                         type = "critical";
1994                                 };
1995
1996                                 gpu_throttle_trip: throttle-trip {
1997                                         temperature = <100000>;
1998                                         hysteresis = <1000>;
1999                                         type = "hot";
2000                                 };
2001                         };
2002
2003                         cooling-maps {
2004                                 map0 {
2005                                         trip = <&gpu_throttle_trip>;
2006                                         cooling-device = <&throttle_heavy 1 1>;
2007                                 };
2008                         };
2009                 };
2010
2011                 pllx {
2012                         polling-delay-passive = <0>;
2013                         polling-delay = <0>;
2014
2015                         thermal-sensors =
2016                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2017
2018                         trips {
2019                                 pllx-shutdown-trip {
2020                                         temperature = <103000>;
2021                                         hysteresis = <0>;
2022                                         type = "critical";
2023                                 };
2024
2025                                 pllx-throttle-trip {
2026                                         temperature = <100000>;
2027                                         hysteresis = <1000>;
2028                                         type = "hot";
2029                                 };
2030                         };
2031
2032                         cooling-maps {
2033                                 /*
2034                                  * There are currently no cooling maps,
2035                                  * because there are no cooling devices.
2036                                  */
2037                         };
2038                 };
2039         };
2040
2041         timer {
2042                 compatible = "arm,armv8-timer";
2043                 interrupts = <GIC_PPI 13
2044                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2045                              <GIC_PPI 14
2046                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2047                              <GIC_PPI 11
2048                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2049                              <GIC_PPI 10
2050                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2051                 interrupt-parent = <&gic>;
2052                 arm,no-tick-in-suspend;
2053         };
2054 };